diff options
| author | zwei4 <david.wei@intel.com> | 2017-03-06 10:38:49 +0800 |
|---|---|---|
| committer | Guo Mang <mang.guo@intel.com> | 2017-05-09 13:03:11 +0800 |
| commit | d4f2e18b8b39e3fb20001d1c47e19c4844162476 (patch) | |
| tree | d9d17f7099855df7b170437292adfab28625a0dc /Platform/BroxtonPlatformPkg/BuildBios.bat | |
| parent | d4949b48ee6164cbc24aef50cb7ef48e5d1135d1 (diff) | |
| download | edk2-platforms-d4f2e18b8b39e3fb20001d1c47e19c4844162476.tar.xz | |
Adjust FVs size and base.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
Diffstat (limited to 'Platform/BroxtonPlatformPkg/BuildBios.bat')
| -rw-r--r-- | Platform/BroxtonPlatformPkg/BuildBios.bat | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat b/Platform/BroxtonPlatformPkg/BuildBios.bat index 99a58cafd6..a326d3c640 100644 --- a/Platform/BroxtonPlatformPkg/BuildBios.bat +++ b/Platform/BroxtonPlatformPkg/BuildBios.bat @@ -404,8 +404,9 @@ copy /y/b %BUILD_PATH%\FV\FvOBBY.fv %Storage_Folder% >nul if /i "%FSP_WRAPPER%" == "TRUE" (
if %Stepping%==B (
+:: 0xFEF63000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE)
pushd %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin
- python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF65000 -o .\ -n FSP.fd
+ python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF63000 -o .\ -n FSP.fd
python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py split -f FSP.fd -o .\ -n FSP.Fv
popd
copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv
|