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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-08 17:01:38 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-16 13:02:38 +0200 |
| commit | 6d6591a29e52b1fcccea8bdd84c91a6ad4645f52 (patch) | |
| tree | 4ba7fb7ae84c47d20d797263d9799a9093fbe6c2 /Platform/Hisilicon/D03/D03.dsc | |
| parent | 709435c64b47ae84a1f7e6d0b6bda4190bf6e90f (diff) | |
| download | edk2-platforms-6d6591a29e52b1fcccea8bdd84c91a6ad4645f52.tar.xz | |
Silicon/AMD/Styx: add PPTT ACPI table
Add a ACPI PPTT table describing the cache topology of the Seattle SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Hisilicon/D03/D03.dsc')
0 files changed, 0 insertions, 0 deletions