diff options
| author | Ming Huang <huangming23@huawei.com> | 2017-03-29 10:28:00 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-10-05 13:53:16 +0100 |
| commit | bf5e51e477466d44d2d0fd39ea7f60c33a4cb202 (patch) | |
| tree | cb53d300b7769593ee6bbd3c2021a67bc351f29b /Platform/Hisilicon | |
| parent | f156dfa26364eb76b501599c0d030d4bcb4b16cb (diff) | |
| download | edk2-platforms-bf5e51e477466d44d2d0fd39ea7f60c33a4cb202.tar.xz | |
D05/PCIe: Modify PcieRegionBase of secondary chip
On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.
Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Hisilicon')
| -rw-r--r-- | Platform/Hisilicon/D05/D05.dsc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 01defe0dce..64101a7d01 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -329,12 +329,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
- gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000
+ gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
- gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000
+ gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000
gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
@@ -352,9 +352,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
- gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+ gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000
gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
- gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+ gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000
gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
|