Marvell/Drivers: Pp2Dxe: Rework PHY handling

Hitherto PHY handling in Pp2Dxe was not flexible. It allowed for using
only single MDIO controller, which may not be true on Armada 80x0 SoCs.
For this purpose introduce the MDIO description, using the new structures
and template in MvHwDescLib. This change enables addition of multiple
CP110 hardware blocks with MDIO controllers.

This change required different PHY handling and obtaining data over
desired MDIO bus. Now given Pp2 port is matched with the PHY via
its index in gMarvellTokenSpaceGuid.PcdPhyDeviceIds. The PHY itself
is mapped to the MDIO controller, using
gMarvellTokenSpaceGuid.PcdPhy2MdioController. Also obtaining
SMI addresses was moved to the PHY initialization routine.
All above allow for much cleaner and logical PHY description
in the .dsc file, which now uses macros for connection type
and speed.

Update PortingGuide documentation accordingly and Armada 70x0 DB
NIC/PHY description.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

2 files changed, 24 insertions, 4 deletions

diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Armada/Armada.dsc.inc
index 7d0dc3916f..72580172df 100644
--- a/Platform/Marvell/Armada/Armada.dsc.inc
+++ b/Platform/Marvell/Armada/Armada.dsc.inc
@@ -524,6 +524,24 @@
   DEFINE CP_RXAUI1          = 0x16

   DEFINE CP_SFI             = 0x17

 

+  #Network interface speed

+  DEFINE PHY_SPEED_10       = 0x1

+  DEFINE PHY_SPEED_100      = 0x2

+  DEFINE PHY_SPEED_1000     = 0x3

+  DEFINE PHY_SPEED_2500     = 0x4

+  DEFINE PHY_SPEED_10000    = 0x5

+

+  #Network PHY type

+  DEFINE PHY_RGMII          = 0x0

+  DEFINE PHY_RGMII_ID       = 0x1

+  DEFINE PHY_RGMII_TXID     = 0x2

+  DEFINE PHY_RGMII_RXID     = 0x3

+  DEFINE PHY_SGMII          = 0x4

+  DEFINE PHY_RTBI           = 0x5

+  DEFINE PHY_XAUI           = 0x6

+  DEFINE PHY_RXAUI          = 0x7

+  DEFINE PHY_SFI            = 0x8

+

   #UTMI PHY connection type

   DEFINE UTMI_USB_HOST0     = 0x0

   DEFINE UTMI_USB_HOST1     = 0x1

diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index b40766b9e9..430803c593 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -115,18 +115,20 @@
   gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }

 

   #MDIO

-  gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200

+  gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }

 

   #PHY

-  gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x8, 0x4, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }

   gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }

+  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }

   gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE

 

   #NET

-  gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }

   gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }

   gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }

-  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 }

+  gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }

+  gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SGMII), $(PHY_RGMII) }

+  gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }

   gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }

   gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }

   gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }