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author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-05-03 17:47:23 +0100 |
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committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-07-14 22:36:51 +0100 |
commit | 0189ff331b9bdd9353624bc7b509e53148976806 (patch) | |
tree | 481788a26d43fdad9f762256111ece2926b7835a /Platform/Marvell/Documentation/PortingGuide/Mpp.txt | |
parent | 8322634459ac602d9fbcca30e96b24ff098acb3c (diff) | |
download | edk2-platforms-devel-OpenPlatformPkg.tar.xz |
Platform: import Marvell Armada supportdevel-OpenPlatformPkg
Import Armada 70x0 suppport from OpenPlatformPkg,
together with its documentation and utilities.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Marvell/Documentation/PortingGuide/Mpp.txt')
-rw-r--r-- | Platform/Marvell/Documentation/PortingGuide/Mpp.txt | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/Platform/Marvell/Documentation/PortingGuide/Mpp.txt b/Platform/Marvell/Documentation/PortingGuide/Mpp.txt new file mode 100644 index 0000000000..68f0e9d179 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Mpp.txt @@ -0,0 +1,48 @@ +MPP configuration
+-----------------
+Multi-Purpose Ports (MPP) are configurable through platform PCDs.
+In order to set desired pin multiplexing, .dsc file needs to be modified.
+(Platform/Marvell/Armada/{platform_name}.dsc - please refer to
+Documentation/Build.txt for currently supported {platftorm_name} )
+Following PCDs are available:
+
+ gMarvellTokenSpaceGuid.PcdMppChipCount
+
+Indicates how many different chips are placed on board. So far up to 4 chips
+are supported.
+
+Every MPP PCD has <Num> part where
+ <Num> stands for chip ID (order is not important, but configuration will be
+ set for first PcdMppChipCount chips).
+
+Below is example for the first chip (Chip0).
+
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
+
+Indicates that register order is reversed. (Needs to be used only for AP806-Z1)
+
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
+
+This is base address for MPP configuration register.
+
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount
+
+Defines how many MPP pins are available.
+
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1
+ gMarvellTokenSpaceGuid.PcdChip0MppSel2
+
+This registers defines functions of 10 pins in ascending order.
+
+Examples
+--------
+#APN806-A0 MPP SET
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+Set pin 6 and 7 to 0xa function:
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
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