Drivers/Net/Pp2Dxe: Move registers' description to macros

Registers' offset are constant for each PP2 controller instance,
so use macros with relative addresses for their description.
This allowed to remove 5 PCD's and will ease enabling second
controller on Armada8k. Update PortingGuide accordingly.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

1 files changed, 0 insertions, 21 deletions

diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
index c1554a694e..3c2f4188f0 100644
--- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
+++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
@@ -34,26 +34,5 @@ PHY_SPEED (in Mbps) is defined as follows:
 Base address of shared register space of PP2:

   gMarvellTokenSpaceGuid.PcdPp2SharedAddress

 

-Spacing between consecutive GMAC register spaces:

-  gMarvellTokenSpaceGuid.PcdPp2GmacDevSize

-

-Base address of GMAC:

-  gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress

-

-Spacing between consecutive XLG register spaces:

-  gMarvellTokenSpaceGuid.PcdPp2XlgDevSize

-

-Base address of XLG:

-  gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress

-

-Base address of RFU1:

-  gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress

-

-Base address of SMI:

-  gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress

-

 TCLK frequency in Hz:

   gMarvellTokenSpaceGuid.PcdPp2ClockFrequency

-

-GMAC and XLG addresses are computed as follows:

-  address = base_address + dev_size * gop_index