diff options
| author | Joe Zhou <shjzhou@marvell.com> | 2017-09-01 13:17:56 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-09-01 13:06:47 +0100 |
| commit | 8f648bb3ab9721955baf5760d5c81f75bbe27658 (patch) | |
| tree | 20502a6d7b63926053a8c82c788947bcba72528f /Platform/Marvell/Drivers | |
| parent | 0d9c98ade555397adc2b0a13c0fddbb3fc092c2d (diff) | |
| download | edk2-platforms-8f648bb3ab9721955baf5760d5c81f75bbe27658.tar.xz | |
Drivers/Net/Pp2Dxe: Increase amount of ingress resources
Increase Rx ring and BM pool size for each port, which is
helpful when dealing with more intense incoming network
traffic.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Joe Zhou <shjzhou@marvell.com
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'Platform/Marvell/Drivers')
| -rw-r--r-- | Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 2 | ||||
| -rw-r--r-- | Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h index 52509b0b26..0ebf9367bb 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h @@ -965,7 +965,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
/* Max number of Rx descriptors */
-#define MVPP2_MAX_RXD 32
+#define MVPP2_MAX_RXD 64
/* Max number of Tx descriptors */
#define MVPP2_MAX_TXD 32
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h index b85cff760e..9e71ec9045 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -138,7 +138,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define MVPP2_BM_SWF_LONG_POOL(Port) ((Port > 2) ? 2 : Port)
#define MVPP2_BM_SWF_SHORT_POOL 3
#define MVPP2_BM_POOL 0
-#define MVPP2_BM_SIZE 32
+#define MVPP2_BM_SIZE 64
/*
* BM short pool packet Size
|