diff options
| author | Marcin Wojtas <mw@semihalf.com> | 2017-09-27 18:24:04 +0200 |
|---|---|---|
| committer | Leif Lindholm <leif@developerbox> | 2017-10-29 16:47:38 +0000 |
| commit | ed226a5d4ee8fb93f9e2a054e6905e99c70bf50c (patch) | |
| tree | 2970e3acc33532d25fd781c5fbb55fda721dbd6f /Platform/Marvell | |
| parent | 6e049d5b6dc76f56751ec122e8bdccd688772044 (diff) | |
| download | edk2-platforms-ed226a5d4ee8fb93f9e2a054e6905e99c70bf50c.tar.xz | |
Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting
This patch fixes incorrect settings for UHS mode in
SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which
the latter was missing. This field should be set to:
0x4 for DDR52
0x2 for SDR50
0x1 for SDR25
0x0 for others.
This way EmmcSwitchToHighSpeed function is on par with Linux
set_uhs_signaling routine in the Xenon driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Marvell')
| -rwxr-xr-x | Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194da7..4d4833fb58 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( if (IsDdr) {
HostCtrl2 = BIT2;
} else if (ClockFreq == 52) {
+ HostCtrl2 = BIT1;
+ } else if (ClockFreq == 26) {
HostCtrl2 = BIT0;
} else {
HostCtrl2 = 0;
|