diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-07 13:34:49 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-07 13:36:01 +0000 |
| commit | ce95ec196da05885844afb79bd2570c5cd9f6b27 (patch) | |
| tree | 7d1a2553bb54a57a7129a2576f343fe78e0d42c2 /Platform/Socionext/DeveloperBox/DeveloperBox.dsc | |
| parent | 23488946946f9cfb6296b4cf591ef6b86498921f (diff) | |
| download | edk2-platforms-ce95ec196da05885844afb79bd2570c5cd9f6b27.tar.xz | |
Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC
As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.
So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform/Socionext/DeveloperBox/DeveloperBox.dsc')
| -rw-r--r-- | Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 5d3dec8ba3..8fbd7b2d90 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -599,7 +599,7 @@ NetworkPkg/HttpBootDxe/HttpBootDxe.inf
Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf {
<LibraryClasses>
- DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+ DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf
}
#
|