diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-02-27 13:39:02 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-02-28 08:14:31 +0000 |
| commit | 8e55eaa4c69f28509f3e801cfdb1e8275a579ccf (patch) | |
| tree | 92421c54671b06267116d895223862b974636274 /Platform | |
| parent | f90743b8813518fd7111c272ea4a3483a94ed462 (diff) | |
| download | edk2-platforms-8e55eaa4c69f28509f3e801cfdb1e8275a579ccf.tar.xz | |
Silicon/SynQuacer: add stage 2 override translation tables for PCIe
The Designware PCIe IP in the SynQuacer SoC needs a little help to
appear sane to the OS. Not only does it lack a true root port, and
therefore does not perform any filtering whatsoever of type 0 config
TLPs that are not intended for the link peer, it also has trouble
issuing 64-bit wide MMIO accesses, which are often used on MMIO BARs
with memory semantics (e.g., frame buffers).
So let's create a stage 2 mapping covering the entire physical address
space, and remap some ECAM regions and demote write combine attributes
to device/strongly ordered. This is not a water tight fix, but it does
work around the issues in the majority of cases.
(Note that the ECAM remapping can also be addressed in the SMMU mapping
of the PCIe IP exposed to the CPU, but this is currently under
development, and it does not hurt to have it in two places)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Platform')
| -rw-r--r-- | Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 | ||||
| -rw-r--r-- | Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 190f8aa999..337d1524c6 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -578,6 +578,7 @@ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+ Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.inf
#
# eMMC support
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index 130572009f..bd1238a39e 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -50,9 +50,12 @@ NumBlocks = 0x28 #
################################################################################
-0x00000000|0x00080000
+0x00000000|0x00078000
FILE = Platform/Socionext/DeveloperBox/fip_all_arm_tf.bin
+0x00078000|0x00008000
+FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(ARCH)/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.bin
+
0x00080000|0x00200000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
|