Silicon/SynQuacerPciHostBridgeLib: stall for 150 ms during PERST#

Attempt to adhere more closely to the PCIe spec by ensuring that PERST#
remains asserted for at least 100 ms. Give it a good margin, and delay
for 150 ms; the additional boot time delay is not going to be noticeable
by anyone anyway.

Add some missing barriers as well, so that the reset takes effect right
when we think it does.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

0 files changed, 0 insertions, 0 deletions