QuarkPlatformPkg: Add new package for Galileo boards

Changes for V4 ============== 1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode from QuarkPlatformPkg commit to QuarkSocPkg commit 2) Fix incorrect license header in PlatformSecLibModStrs.uni Changes for V3 ============== 1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc This is required because QuarkMin.dsc uses the emulated variable driver that does not preserve any non-volatile UEFI variables across reset. If the condition is met where the memory type information variable needs to be updated, then the system will reset every time the UEFI Shell is run. By setting this PCD to FALSE, then reset action is disabled. 2) Move one binary file to QuarkSocBinPkg 3) Change RMU.bin FILE statements to INF statement in DSC FD region to be compatible with PACKAGES_PATH search for QuarkSocBinPkg Changes for V2 ============== 1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg 2) Configure PcdPciSerialParameters for PCI serial driver for Quark 3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM 4) Convert all UNI files to utf-8 5) Replace tabs with spaces and remove trailing spaces 6) Add License.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Acked-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524
author: Michael Kinney <michael.d.kinney@intel.com> 2015-12-15 19:23:57 +0000
committer: mdkinney <mdkinney@Edk2> 2015-12-15 19:23:57 +0000
commit: b303605e1b7e113b4311daf161c6c3289350447b (patch)
tree: 67bf068eb99ea84822f234b7194ee1084ee5455a /QuarkPlatformPkg/Include
parent: 9b6bbcdbfdf5e54c6d1ed538ea8076d0858fb164 (diff)
download: edk2-platforms-b303605e1b7e113b4311daf161c6c3289350447b.tar.xz
16 files changed, 1136 insertions, 0 deletions
diff --git a/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h b/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h
new file mode 100644
index 0000000000..6a60507e0e
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h
@@ -0,0 +1,29 @@
+/** @file
+Capsule on Data CD GUID.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+This is the contract between the recovery module and device recovery module
+in order to convey the name of a given recovery module type
+
+**/
+
+#ifndef _CAPSULE_ON_DATA_CD_H
+#define _CAPSULE_ON_DATA_CD_H
+
+#define PEI_CAPSULE_ON_DATA_CD_GUID \
+  { \
+  0x5cac0099, 0x0dc9, 0x48e5, {0x80, 0x68, 0xbb, 0x95, 0xf5, 0x40, 0x0a, 0x9f } \
+  };
+
+extern EFI_GUID gPeiCapsuleOnDataCDGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h b/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h
new file mode 100644
index 0000000000..b77841c18f
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h
@@ -0,0 +1,29 @@
+/** @file
+Capsule on Fat Floppy Disk GUID.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+This is the contract between the recovery module and device recovery module
+in order to convey the name of a given recovery module type
+
+**/
+
+#ifndef _CAPSULE_ON_FAT_FLOPPY_DISK_H
+#define _CAPSULE_ON_FAT_FLOPPY_DISK_H
+
+#define PEI_CAPSULE_ON_FAT_FLOPPY_DISK_GUID \
+  { \
+  0x2e3d2e75, 0x9b2e, 0x412d, {0xb4, 0xb1, 0x70, 0x41, 0x6b, 0x87, 0x0, 0xff }\
+  };
+
+extern EFI_GUID gPeiCapsuleOnFatFloppyDiskGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h b/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h
new file mode 100644
index 0000000000..7c128ac408
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h
@@ -0,0 +1,30 @@
+/** @file
+Capsule on Fat Ide Disk GUID.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+This is the contract between the recovery module and device recovery module
+in order to convey the name of a given recovery module type
+
+**/
+
+#ifndef _CAPSULE_ON_FAT_IDE_DISK_H
+#define _CAPSULE_ON_FAT_IDE_DISK_H
+
+#define PEI_CAPSULE_ON_FAT_IDE_DISK_GUID \
+  { \
+  0xb38573b6, 0x6200, 0x4ac5, {0xb5, 0x1d, 0x82, 0xe6, 0x59, 0x38, 0xd7, 0x83 }\
+  };
+
+extern EFI_GUID gPeiCapsuleOnFatIdeDiskGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h b/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h
new file mode 100644
index 0000000000..63eedb2533
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h
@@ -0,0 +1,30 @@
+/** @file
+Capsule on Fat Usb Disk GUID.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+This is the contract between the recovery module and device recovery module
+in order to convey the name of a given recovery module type
+
+**/
+
+#ifndef _PEI_CAPSULE_ON_FAT_USB_DISK_H
+#define _PEI_CAPSULE_ON_FAT_USB_DISK_H
+
+#define PEI_CAPSULE_ON_FAT_USB_DISK_GUID \
+  { \
+  0x0ffbce19, 0x324c, 0x4690, {0xa0, 0x09, 0x98, 0xc6, 0xae, 0x2e, 0xb1, 0x86 } \
+  };
+
+extern EFI_GUID gPeiCapsuleOnFatUsbDiskGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h b/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h
new file mode 100644
index 0000000000..62749ec406
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/MemoryConfigData.h
@@ -0,0 +1,29 @@
+/** @file
+Define a GUID name for GUID HOB which is used to pass Memory
+Configuration Data information to different modules.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEMORY_CONFIG_DATA_H_
+#define _MEMORY_CONFIG_DATA_H_
+
+#define EFI_MEMORY_CONFIG_DATA_GUID \
+  { \
+    0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } \
+  }
+
+#define EFI_MEMORY_CONFIG_DATA_NAME  L"MemoryConfig"
+
+extern EFI_GUID gEfiMemoryConfigDataGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h b/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h
new file mode 100644
index 0000000000..5770d12026
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h
@@ -0,0 +1,52 @@
+/** @file
+
+Capsule format guid for Quark capsule image.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _QUARK_CAPSULE_GUID_H_
+#define _QUARK_CAPSULE_GUID_H_
+
+#define QUARK_CAPSULE_GUID \
+  { 0xd400d1e4, 0xa314, 0x442b, { 0x89, 0xed, 0xa9, 0x2e, 0x4c, 0x81, 0x97, 0xcb } }
+
+#define SMI_INPUT_UPDATE_CAP 0x27
+#define SMI_INPUT_GET_CAP    0x28
+
+#define SMI_CAP_FUNCTION     0xEF
+
+#pragma pack(1)
+typedef struct {
+   UINT64  Address;
+   UINT32  BufferOffset;
+   UINT32  Size;
+   UINT32  Flags;
+   UINT32  Reserved;
+} CAPSULE_FRAGMENT;
+
+typedef struct {
+  UINTN         CapsuleLocation;  // Top of the capsule that point to structure CAPSULE_FRAGMENT
+  UINTN         CapsuleSize;    // Size of the capsule
+  EFI_STATUS   Status;      // Returned status
+} CAPSULE_INFO_PACKET;
+
+typedef struct {
+  UINTN           BlocksCompleted;  // # of blocks processed
+  UINTN           TotalBlocks;      // Total # of blocks to be processed
+  EFI_STATUS      Status;            // returned status
+} UPDATE_STATUS_PACKET;
+#pragma pack()
+
+extern EFI_GUID gEfiQuarkCapsuleGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h b/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h
new file mode 100644
index 0000000000..56e1b52956
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h
@@ -0,0 +1,29 @@
+/** @file
+
+Guid and variable name used to trigger quark lock of specific UEFI variables.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _QUARK_VARIABLE_LOCK_GUID_H_
+#define _QUARK_VARIABLE_LOCK_GUID_H_
+
+#define QUARK_VARIABLE_LOCK_GUID \
+  { \
+    0xeef749c2, 0xc047, 0x4d6e, { 0xb1, 0xbc, 0xd3, 0x6e, 0xb3, 0xa5, 0x55, 0x9c } \
+  }
+
+#define QUARK_VARIABLE_LOCK_NAME  L"QuarkVariableLock"
+
+extern EFI_GUID gQuarkVariableLockGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h b/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h
new file mode 100644
index 0000000000..694c45d1a7
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h
@@ -0,0 +1,35 @@
+/** @file
+GUIDs used for System Non Volatile HOB entries in the in the HOB list and FV Guids carrying
+the System specific information.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYSTEM_NV_DATA_HOB_GUID_H_
+#define _SYSTEM_NV_DATA_HOB_GUID_H_
+
+#define EFI_SYSTEM_NV_DATA_HOB_GUID \
+  {0xd6e5092d, 0xc7b2, 0x4872, {0xaf, 0x66, 0xfd, 0xc0, 0xe6, 0xf9, 0x5e, 0x78}}
+
+typedef struct {
+  EFI_GUID                  SystemNvDataHobGuid;
+  EFI_GUID                  SystemNvDataFvGuid;
+  EFI_LBA                   StartLba;
+  UINTN                     StartLbaOffset;
+  EFI_LBA                   EndLba;
+  UINTN                     EndLbaOffset;
+  UINT32                    DataTypeSignature;
+} NV_SYSTEM_DATA_GUID_TYPE;
+
+extern EFI_GUID gEfiSystemNvDataHobGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
new file mode 100644
index 0000000000..a6cc8633cb
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h
@@ -0,0 +1,322 @@
+/** @file
+PlatformHelperLib function prototype definitions.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_HELPER_LIB_H__
+#define __PLATFORM_HELPER_LIB_H__
+
+#include "Platform.h"
+
+//
+// Function prototypes for routines exported by this library.
+//
+
+/**
+  Find pointer to RAW data in Firmware volume file.
+
+  @param   FvNameGuid       Firmware volume to search. If == NULL search all.
+  @param   FileNameGuid     Firmware volume file to search for.
+  @param   SectionData      Pointer to RAW data section of found file.
+  @param   SectionDataSize  Pointer to UNITN to get size of RAW data.
+
+  @retval  EFI_SUCCESS            Raw Data found.
+  @retval  EFI_INVALID_PARAMETER  FileNameGuid == NULL.
+  @retval  EFI_NOT_FOUND          Firmware volume file not found.
+  @retval  EFI_UNSUPPORTED        Unsupported in current enviroment (PEI or DXE).
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFindFvFileRawDataSection (
+  IN CONST EFI_GUID                 *FvNameGuid OPTIONAL,
+  IN CONST EFI_GUID                 *FileNameGuid,
+  OUT VOID                          **SectionData,
+  OUT UINTN                         *SectionDataSize
+  );
+
+/**
+  Read 8bit character from debug stream.
+
+  Block until character is read.
+
+  @return 8bit character read from debug stream.
+
+**/
+CHAR8
+EFIAPI
+PlatformDebugPortGetChar8 (
+  VOID
+  );
+
+/**
+  Find free spi protect register and write to it to protect a flash region.
+
+  @param   DirectValue      Value to directly write to register.
+                            if DirectValue == 0 the use Base & Length below.
+  @param   BaseAddress      Base address of region in Flash Memory Map.
+  @param   Length           Length of region to protect.
+
+  @retval  EFI_SUCCESS      Free spi protect register found & written.
+  @retval  EFI_NOT_FOUND    Free Spi protect register not found.
+  @retval  EFI_DEVICE_ERROR Unable to write to spi protect register.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformWriteFirstFreeSpiProtect (
+  IN CONST UINT32                         DirectValue,
+  IN CONST UINT32                         BaseAddress,
+  IN CONST UINT32                         Length
+  );
+
+/**
+  Lock legacy SPI static configuration information.
+
+  Function will assert if unable to lock config.
+
+**/
+VOID
+EFIAPI
+PlatformFlashLockConfig (
+  VOID
+  );
+
+/**
+  Lock regions and config of SPI flash given the policy for this platform.
+
+  Function will assert if unable to lock regions or config.
+
+  @param   PreBootPolicy    If TRUE do Pre Boot Flash Lock Policy.
+
+**/
+VOID
+EFIAPI
+PlatformFlashLockPolicy (
+  IN CONST BOOLEAN                        PreBootPolicy
+  );
+
+/**
+  Erase and Write to platform flash.
+
+  Routine accesses one flash block at a time, each access consists
+  of an erase followed by a write of FLASH_BLOCK_SIZE. One or both
+  of DoErase & DoWrite params must be TRUE.
+
+  Limitations:-
+    CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.
+    DataSize must be a multiple of FLASH_BLOCK_SIZE.
+
+  @param   Smst                   If != NULL then InSmm and use to locate
+                                  SpiProtocol.
+  @param   CpuWriteAddress        Address in CPU memory map of flash region.
+  @param   Data                   The buffer containing the data to be written.
+  @param   DataSize               Amount of data to write.
+  @param   DoErase                Earse each block.
+  @param   DoWrite                Write to each block.
+
+  @retval  EFI_SUCCESS            Operation successful.
+  @retval  EFI_NOT_READY          Required resources not setup.
+  @retval  EFI_INVALID_PARAMETER  Invalid parameter.
+  @retval  Others                 Unexpected error happened.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFlashEraseWrite (
+  IN  VOID                              *Smst,
+  IN  UINTN                             CpuWriteAddress,
+  IN  UINT8                             *Data,
+  IN  UINTN                             DataSize,
+  IN  BOOLEAN                           DoErase,
+  IN  BOOLEAN                           DoWrite
+  );
+
+/** Check if System booted with recovery Boot Stage1 image.
+
+  @retval  TRUE    If system booted with recovery Boot Stage1 image.
+  @retval  FALSE   If system booted with normal stage1 image.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformIsBootWithRecoveryStage1 (
+  VOID
+  );
+
+/**
+  Clear SPI Protect registers.
+
+  @retval EFI_SUCESS         SPI protect registers cleared.
+  @retval EFI_ACCESS_DENIED  Unable to clear SPI protect registers.
+**/
+
+EFI_STATUS
+EFIAPI
+PlatformClearSpiProtect (
+  VOID
+  );
+
+/**
+  Determine if an SPI address range is protected.
+
+  @param  SpiBaseAddress  Base of SPI range.
+  @param  Length          Length of SPI range.
+
+  @retval TRUE       Range is protected.
+  @retval FALSE      Range is not protected.
+**/
+BOOLEAN
+EFIAPI
+PlatformIsSpiRangeProtected (
+  IN CONST UINT32                         SpiBaseAddress,
+  IN CONST UINT32                         Length
+  );
+
+/**
+  Set Legacy GPIO Level
+
+  @param  LevelRegOffset      GPIO level register Offset from GPIO Base Address.
+  @param  GpioNum             GPIO bit to change.
+  @param  HighLevel           If TRUE set GPIO High else Set GPIO low.
+
+**/
+VOID
+EFIAPI
+PlatformLegacyGpioSetLevel (
+  IN CONST UINT32       LevelRegOffset,
+  IN CONST UINT32       GpioNum,
+  IN CONST BOOLEAN      HighLevel
+  );
+
+/**
+  Get Legacy GPIO Level
+
+  @param  LevelRegOffset      GPIO level register Offset from GPIO Base Address.
+  @param  GpioNum             GPIO bit to check.
+
+  @retval TRUE       If bit is SET.
+  @retval FALSE      If bit is CLEAR.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformLegacyGpioGetLevel (
+  IN CONST UINT32       LevelRegOffset,
+  IN CONST UINT32       GpioNum
+  );
+
+/**
+  Set the direction of Pcal9555 IO Expander GPIO pin.
+
+  @param  Pcal9555SlaveAddr  I2c Slave address of Pcal9555 Io Expander.
+  @param  GpioNum            Gpio direction to configure - values 0-7 for Port0
+                             and 8-15 for Port1.
+  @param  CfgAsInput         If TRUE set pin direction as input else set as output.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetDir (
+  IN CONST UINT32                         Pcal9555SlaveAddr,
+  IN CONST UINT32                         GpioNum,
+  IN CONST BOOLEAN                        CfgAsInput
+  );
+
+/**
+  Set the level of Pcal9555 IO Expander GPIO high or low.
+
+  @param  Pcal9555SlaveAddr  I2c Slave address of Pcal9555 Io Expander.
+  @param  GpioNum            Gpio to change values 0-7 for Port0 and 8-15
+                             for Port1.
+  @param  HighLevel          If TRUE set pin high else set pin low.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetLevel (
+  IN CONST UINT32                         Pcal9555SlaveAddr,
+  IN CONST UINT32                         GpioNum,
+  IN CONST BOOLEAN                        HighLevel
+  );
+
+/**
+
+  Enable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+  @param  Pcal9555SlaveAddr  I2c Slave address of Pcal9555 Io Expander.
+  @param  GpioNum            Gpio to change values 0-7 for Port0 and 8-15
+                             for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioEnablePull (
+  IN CONST UINT32                         Pcal9555SlaveAddr,
+  IN CONST UINT32                         GpioNum
+  );
+
+/**
+
+  Disable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+  @param  Pcal9555SlaveAddr  I2c Slave address of Pcal9555 Io Expander.
+  @param  GpioNum            Gpio to change values 0-7 for Port0 and 8-15
+                             for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioDisablePull (
+  IN CONST UINT32                         Pcal9555SlaveAddr,
+  IN CONST UINT32                         GpioNum
+  );
+
+BOOLEAN
+EFIAPI
+PlatformPcal9555GpioGetState (
+  IN CONST UINT32                         Pcal9555SlaveAddr,
+  IN CONST UINT32                         GpioNum
+  );
+
+/**
+  Init platform LEDs into known state.
+
+  @param   PlatformType     Executing platform type.
+
+  @retval  EFI_SUCCESS      Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformLedInit (
+  IN CONST EFI_PLATFORM_TYPE              Type
+  );
+
+/**
+  Turn on or off platform flash update LED.
+
+  @param   PlatformType     Executing platform type.
+  @param   TurnOn           If TRUE turn on else turn off.
+
+  @retval  EFI_SUCCESS      Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFlashUpdateLed (
+  IN CONST EFI_PLATFORM_TYPE              Type,
+  IN CONST BOOLEAN                        TurnOn
+  );
+
+#endif // #ifndef __PLATFORM_HELPER_LIB_H__
diff --git a/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h b/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h
new file mode 100644
index 0000000000..308ebe8dde
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h
@@ -0,0 +1,62 @@
+/** @file
+PlatformPcieHelperLib function prototype definitions.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PLATFORM_PCIE_HELPER_LIB_H__
+#define __PLATFORM_PCIE_HELPER_LIB_H__
+
+#include "Platform.h"
+
+//
+// Function prototypes for routines exported by this library.
+//
+
+/**
+  Platform assert PCI express PERST# signal.
+
+  @param   PlatformType     See EFI_PLATFORM_TYPE enum definitions.
+
+**/
+VOID
+EFIAPI
+PlatformPERSTAssert (
+  IN CONST EFI_PLATFORM_TYPE              PlatformType
+  );
+
+/**
+  Platform de assert PCI express PERST# signal.
+
+  @param   PlatformType     See EFI_PLATFORM_TYPE enum definitions.
+
+**/
+VOID
+EFIAPI
+PlatformPERSTDeAssert (
+  IN CONST EFI_PLATFORM_TYPE              PlatformType
+  );
+
+/** Early initialisation of the PCIe controller.
+
+  @param   PlatformType     See EFI_PLATFORM_TYPE enum definitions.
+
+  @retval   EFI_SUCCESS               Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformPciExpressEarlyInit (
+  IN CONST EFI_PLATFORM_TYPE              PlatformType
+  );
+
+#endif // #ifndef __PLATFORM_PCIE_HELPER_LIB_H__
diff --git a/QuarkPlatformPkg/Include/Library/RecoveryOemHookLib.h b/QuarkPlatformPkg/Include/Library/RecoveryOemHookLib.h
new file mode 100644
index 0000000000..ea265adc83
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Library/RecoveryOemHookLib.h
@@ -0,0 +1,45 @@
+/** @file
+This library includes the recovery function that can be customized by OEM,
+including how to select the recovery capsule if more than one capsule found,
+and security check.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __RECOVERY_OEM_HOOK_LIB_H__
+#define __RECOVERY_OEM_HOOK_LIB_H__
+
+/**
+  This function allows the user to force a system recovery
+
+**/
+VOID
+EFIAPI
+OemInitiateRecovery (
+  VOID
+  );
+
+/**
+  This function allows the user to force a system recovery and deadloop.
+
+  Deadloop required since system should not execute beyond this point.
+  Deadloop should never happen since OemInitiateRecovery () called within
+  this routine should never return since it executes a Warm Reset.
+
+**/
+VOID
+EFIAPI
+OemInitiateRecoveryAndWait (
+  VOID
+  );
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Pcal9555.h b/QuarkPlatformPkg/Include/Pcal9555.h
new file mode 100644
index 0000000000..2b7efad00b
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Pcal9555.h
@@ -0,0 +1,30 @@
+/** @file
+Definition for Pcal9555 I2c IO Expander.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#ifndef __PCAL9555_H__
+#define __PCAL9555_H__
+
+#define PCAL9555_REG_IN_PORT0                        0x00
+#define PCAL9555_REG_IN_PORT1                        0x01
+#define PCAL9555_REG_OUT_PORT0                       0x02
+#define PCAL9555_REG_OUT_PORT1                       0x03
+#define PCAL9555_REG_CFG_PORT0                       0x06
+#define PCAL9555_REG_CFG_PORT1                       0x07
+
+#define PCAL9555_REG_PULL_EN_PORT0                   0x46
+#define PCAL9555_REG_PULL_EN_PORT1                   0x47
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Platform.h b/QuarkPlatformPkg/Include/Platform.h
new file mode 100644
index 0000000000..e6c71f1153
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Platform.h
@@ -0,0 +1,125 @@
+/** @file
+Quark platform specific information.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+#include "Uefi.h"
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+//
+// Constant definition
+//
+#define MAX_SMRAM_RANGES                    4
+#define MAX_NODE                            1
+
+#define QUARK_STAGE1_IMAGE_TYPE_MASK      0xF0
+#define QUARK_STAGE1_BOOT_IMAGE_TYPE      0x00  // Stage1 Boot images 0x00 -> 0x0F.
+#define QUARK_STAGE1_RECOVERY_IMAGE_TYPE  0x10  // Stage1 Recovery images 0x10 -> 0x1F.
+
+#define QUARK_BOOTROM_BASE_ADDRESS        0xFFFE0000  // Base address of Quark ROM in memory map.
+#define QUARK_BOOTROM_SIZE_BYTES          0x20000     // Quark ROM is 128KB.
+#define SMM_DEFAULT_SMBASE                  0x30000     // Default SMBASE address.
+#define SMM_DEFAULT_SMBASE_SIZE_BYTES       0x10000     // Size in bytes of default SMRAM.
+
+//
+// Gpio to be used to assert / deassert PCI express PERST# signal.
+//
+#define PCIEXP_PERST_RESUMEWELL_GPIO        3
+
+//
+// Minimum time in microseconds for assertion of PERST# signal.
+//
+#define PCIEXP_PERST_MIN_ASSERT_US          100
+
+//
+// Microsecond delay post issueing common lane reset.
+//
+#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1
+
+//
+// Microsecond delay to wait for PLL to lock.
+//
+#define PCIEXP_DELAY_US_WAIT_PLL_LOCK       80
+
+//
+// Microsecond delay post issueing sideband interface reset.
+//
+#define PCIEXP_DELAY_US_POST_SBI_RESET      20
+
+//
+// Microsecond delay post deasserting PERST#.
+//
+#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10
+
+//
+// Catastrophic Trip point in degrees Celsius for this platform.
+//
+#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS  105
+
+//
+// Platform flash update LED common definitions.
+//
+#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT   7
+#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA   (1000 * 1000)  // In Microseconds for EFI_STALL.
+
+//
+// This structure stores the base and size of the ACPI reserved memory used when
+// resuming from S3.  This region must be allocated by the platform code.
+//
+typedef struct {
+  UINT32  AcpiReservedMemoryBase;
+  UINT32  AcpiReservedMemorySize;
+  UINT32  SystemMemoryLength;
+} RESERVED_ACPI_S3_RANGE;
+
+#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))
+
+//
+// Define valid platform types.
+// First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition
+// and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.
+// Value shown for supported platforms to help sanity checking with build tools
+// and ACPI method usage.
+//
+typedef enum {
+  TypeUnknown = 0,      // !!! SHOULD BE THE FIRST ENTRY !!!
+  QuarkEmulation = 1,
+  ClantonPeakSVP = 2,
+  KipsBay = 3,
+  CrossHill = 4,
+  ClantonHill = 5,
+  Galileo = 6,
+  TypePlatformRsv7 = 7,
+  GalileoGen2 = 8,
+  TypePlatformMax       // !!! SHOULD BE THE LAST ENTRY !!!
+} EFI_PLATFORM_TYPE;
+
+#define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \
+  L"TypeUnknown",\
+  L"QuarkEmulation",\
+  L"ClantonPeakSVP",\
+  L"KipsBay",\
+  L"CrossHill",\
+  L"ClantonHill",\
+  L"Galileo",\
+  L"TypePlatformRsv7",\
+  L"GalileoGen2",\
+
+typedef struct {
+  UINT32  EntryOffset;
+  UINT8   ImageIndex;
+} QUARK_EDKII_STAGE1_HEADER;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/PlatformBoards.h b/QuarkPlatformPkg/Include/PlatformBoards.h
new file mode 100644
index 0000000000..efd8422c0e
--- /dev/null
+++ b/QuarkPlatformPkg/Include/PlatformBoards.h
@@ -0,0 +1,172 @@
+/** @file
+Board config definitions for each of the boards supported by this platform
+package.
+
+Copyright (c) 2013 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+#include "Platform.h"
+
+#ifndef __PLATFORM_BOARDS_H__
+#define __PLATFORM_BOARDS_H__
+
+//
+// Constant definition
+//
+
+//
+// Default resume well TPM reset.
+//
+#define PLATFORM_RESUMEWELL_TPM_RST_GPIO                5
+
+//
+// Basic Configs for GPIO table definitions.
+//
+#define NULL_LEGACY_GPIO_INITIALIZER                    {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
+#define ALL_INPUT_LEGACY_GPIO_INITIALIZER               {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}
+#define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER         ALL_INPUT_LEGACY_GPIO_INITIALIZER
+#define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER        {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}
+#define KIPS_BAY_LEGACY_GPIO_INITIALIZER                {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}
+#define CROSS_HILL_LEGACY_GPIO_INITIALIZER              {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}
+#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER            {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}
+#define GALILEO_LEGACY_GPIO_INITIALIZER                 {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}
+#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER            {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}
+
+#define NULL_GPIO_CONTROLLER_INITIALIZER                {0,0,0,0,0,0,0,0}
+#define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER           NULL_GPIO_CONTROLLER_INITIALIZER
+#define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER     NULL_GPIO_CONTROLLER_INITIALIZER
+#define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER    NULL_GPIO_CONTROLLER_INITIALIZER
+#define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER            {0x05,0x05,0,0,0,0,0,0}
+#define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER          {0x0D,0x2D,0,0,0,0,0,0}
+#define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER        {0x01,0x39,0,0,0,0,0,0}
+#define GALILEO_GPIO_CONTROLLER_INITIALIZER             {0x05,0x15,0,0,0,0,0,0}
+#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER        {0x05,0x05,0,0,0,0,0,0}
+
+//
+// Legacy Gpio to be used to assert / deassert PCI express PERST# signal
+// on Galileo Gen 2 platform.
+//
+#define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO       0
+
+//
+// Io expander slave address.
+//
+
+//
+// On Galileo value of Jumper J2 determines slave address of io expander.
+//
+#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO     5
+#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR              0x20
+#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR              0x21
+
+//
+// Three IO Expmanders at fixed addresses on Galileo Gen2.
+//
+#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR             0x25
+#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR             0x26
+#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR             0x27
+
+//
+// Led GPIOs for flash update / recovery.
+//
+#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO        1
+#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO   5
+
+//
+// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.
+//
+typedef struct {
+  UINT32  CoreWellEnable;               ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.
+  UINT32  CoreWellIoSelect;             ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.
+  UINT32  CoreWellLvlForInputOrOutput;  ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.
+  UINT32  CoreWellTriggerPositiveEdge;  ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.
+  UINT32  CoreWellTriggerNegativeEdge;  ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.
+  UINT32  CoreWellGPEEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.
+  UINT32  CoreWellSMIEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.
+  UINT32  CoreWellTriggerStatus;        ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.
+  UINT32  CoreWellNMIEnable;            ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.
+  UINT32  ResumeWellEnable;             ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.
+  UINT32  ResumeWellIoSelect;           ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.
+  UINT32  ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.
+  UINT32  ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.
+  UINT32  ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.
+  UINT32  ResumeWellGPEEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.
+  UINT32  ResumeWellSMIEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.
+  UINT32  ResumeWellTriggerStatus;      ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.
+  UINT32  ResumeWellNMIEnable;          ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.
+} BOARD_LEGACY_GPIO_CONFIG;
+
+//
+// GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.
+//
+typedef struct {
+  UINT32  PortADR;                      ///< Value for IOH REG GPIO_SWPORTA_DR.
+  UINT32  PortADir;                     ///< Value for IOH REG GPIO_SWPORTA_DDR.
+  UINT32  IntEn;                        ///< Value for IOH REG GPIO_INTEN.
+  UINT32  IntMask;                      ///< Value for IOH REG GPIO_INTMASK.
+  UINT32  IntType;                      ///< Value for IOH REG GPIO_INTTYPE_LEVEL.
+  UINT32  IntPolarity;                  ///< Value for IOH REG GPIO_INT_POLARITY.
+  UINT32  Debounce;                     ///< Value for IOH REG GPIO_DEBOUNCE.
+  UINT32  LsSync;                       ///< Value for IOH REG GPIO_LS_SYNC.
+} BOARD_GPIO_CONTROLLER_CONFIG;
+
+///
+/// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported
+/// by this platform package.
+/// Table indexed with EFI_PLATFORM_TYPE enum value.
+///
+#define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \
+  /* EFI_PLATFORM_TYPE - TypeUnknown*/\
+  NULL_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
+  QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
+  CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - KipsBay*/\
+  KIPS_BAY_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - CrossHill*/\
+  CROSS_HILL_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - ClantonHill*/\
+  CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - Galileo*/\
+  GALILEO_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\
+  NULL_LEGACY_GPIO_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - GalileoGen2*/\
+  GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\
+
+///
+/// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board
+/// supported by this platform package.
+/// Table indexed with EFI_PLATFORM_TYPE enum value.
+///
+#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \
+  /* EFI_PLATFORM_TYPE - TypeUnknown*/\
+  NULL_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - QuarkEmulation*/\
+  QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\
+  CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - KipsBay*/\
+  KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - CrossHill*/\
+  CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - ClantonHill*/\
+  CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - Galileo*/\
+  GALILEO_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\
+  NULL_GPIO_CONTROLLER_INITIALIZER,\
+  /* EFI_PLATFORM_TYPE - GalileoGen2*/\
+  GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h b/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644
index 0000000000..24b9ad9969
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,88 @@
+/** @file
+Definition of the global NVS area protocol.  This protocol
+publishes the address and format of a global ACPI NVS buffer
+used as a communications buffer between SMM code and ASL code.
+The format is derived from the ACPI reference code, version 0.95.
+Note:  Data structures defined in this protocol are not naturally aligned.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Forward reference for pure ANSI compatability
+//
+
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc} }
+
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Values
+  //
+  UINT32      OperatingSystemType;    // Os type indicator
+  UINT32      Cfgd;                   // System configuration description
+  UINT32      HpetEnable;
+
+  UINT32      Pm1blkIoBaseAddress;
+  UINT32      PmbaIoBaseAddress;
+  UINT32      Gpe0blkIoBaseAddress;
+  UINT32      GbaIoBaseAddress;
+
+  UINT32      SmbaIoBaseAddress;
+  UINT32      Reserved1;
+  UINT32      WdtbaIoBaseAddress;
+
+  UINT32      HpetBaseAddress;
+  UINT32      HpetSize;
+  UINT32      PciExpressBaseAddress;
+  UINT32      PciExpressSize;
+
+  UINT32      RcbaMmioBaseAddress;
+  UINT32      RcbaMmioSize;
+  UINT32      IoApicBaseAddress;
+  UINT32      IoApicSize;
+
+  UINT32      TpmPresent;
+  UINT32      DBG2Present;
+  UINT32      PlatformType;           // Set to one of EFI_PLATFORM_TYPE enums.
+  UINT32      AlternateSla;           // If TRUE use alternate I2C Slave addresses.
+
+  UINT8       Reserved[512 - 4 * 22]; // Total 512 Bytes
+} EFI_GLOBAL_NVS_AREA;
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA     *Area;
+};
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+#endif
diff --git a/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h b/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h
new file mode 100644
index 0000000000..00d775dddd
--- /dev/null
+++ b/QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h
@@ -0,0 +1,29 @@
+/** @file
+This protocol indicates that the platform SPI interface is ready for use.
+
+Copyright (c) 2013-2015 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+**/
+
+#ifndef _PLATFORM_SPI_READY_H_
+#define _PLATFORM_SPI_READY_H_
+
+// {7A5DBC75-5B2B-4e67-BDE1-D48EEE761562}
+#define EFI_SMM_SPI_READY_PROTOCOL_GUID  \
+  { 0x7a5dbc75, 0x5b2b, 0x4e67, 0xbd, 0xe1, 0xd4, 0x8e, 0xee, 0x76, 0x15, 0x62 }
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID                     gEfiSmmSpiReadyProtocolGuid;
+
+#endif
author	Michael Kinney <michael.d.kinney@intel.com>	2015-12-15 19:23:57 +0000
committer	mdkinney <mdkinney@Edk2>	2015-12-15 19:23:57 +0000
commit	b303605e1b7e113b4311daf161c6c3289350447b (patch)
tree	67bf068eb99ea84822f234b7194ee1084ee5455a /QuarkPlatformPkg/Include
parent	9b6bbcdbfdf5e54c6d1ed538ea8076d0858fb164 (diff)
download	edk2-platforms-b303605e1b7e113b4311daf161c6c3289350447b.tar.xz