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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-27 14:20:35 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-01-25 13:08:45 +0000 |
| commit | 59e41cf53d885bc62f29b6ddef99a3b6893a8d60 (patch) | |
| tree | ae8924b4b06416bf7bffbdfa25b6088cdc597e8a /Silicon/AMD/Styx | |
| parent | 1f956add945fc59b92ae4a418ada2923b6df6526 (diff) | |
| download | edk2-platforms-59e41cf53d885bc62f29b6ddef99a3b6893a8d60.tar.xz | |
Silicon/SynQuacer/DeviceTree: align uart DT nodes
Align the UART DT nodes:
- use 'uart' not 'fuart' as node name for the second serial port
- create an alias 'serial1' for the second serial port
- use UART clock reference instead of hardcoded frequency
- split 'clocks' property into 1 cell per phandle
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/AMD/Styx')
0 files changed, 0 insertions, 0 deletions