diff options
author | Guo Mang <mang.guo@intel.com> | 2016-12-23 10:44:35 +0800 |
---|---|---|
committer | Guo Mang <mang.guo@intel.com> | 2017-05-09 13:02:52 +0800 |
commit | ce4fba76a8084dcf46f5d5d2478ceb4025e54697 (patch) | |
tree | 09ecae884f6d09f4968ee01483d07002c5fb806b /Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl | |
parent | 1a701f1cc996c01a18b5aafc4742067028a62299 (diff) | |
download | edk2-platforms-ce4fba76a8084dcf46f5d5d2478ceb4025e54697.tar.xz |
BroxtonSiPkg: Add Cpu/AcpiTables
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Diffstat (limited to 'Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl')
-rw-r--r-- | Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl new file mode 100644 index 0000000000..1c3fb15689 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/AcpiTables/CpuSsdt/ApIst.asl @@ -0,0 +1,105 @@ +/** @file
+ Intel Processor Power Management IST ACPI Code.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "APIST.aml",
+ "SSDT",
+ 2,
+ "PmRef",
+ "ApIst",
+ 0x3000
+ )
+{
+ External(\_PR.CPU0._PSS, MethodObj)
+ External(\_PR.CPU0._PCT, MethodObj)
+ External(\_PR.CPU0._PPC, IntObj)
+ External(\_PR.CPU0._PSD, MethodObj)
+ External(\_PR.CPU1, DeviceObj)
+ External(\_PR.CPU2, DeviceObj)
+ External(\_PR.CPU3, DeviceObj)
+ External(\_PR.CFGD, IntObj)
+ External (PDC0)
+
+ Scope(\_PR.CPU1)
+ {
+ Method(_PPC,0)
+ {
+ Return(\_PR.CPU0._PPC) // Return P0 _PPC value.
+ }
+
+ Method(_PCT,0)
+ {
+ Return(\_PR.CPU0._PCT) // Return P0 _PCT.
+ }
+
+ Method(_PSS,0)
+ {
+ //Return the same table as CPU0 for CMP cases.
+ Return(\_PR.CPU0._PSS)
+ }
+ Method(_PSD,0)
+ {
+ Return(\_PR.CPU0._PSD) // Return P0 _PSD.
+ }
+ }
+
+ Scope(\_PR.CPU2)
+ {
+ Method(_PPC,0)
+ {
+ Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value.
+ }
+
+ Method(_PCT,0)
+ {
+ Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value.
+ }
+
+ Method(_PSS,0)
+ {
+ Return(\_PR.CPU0._PSS) // Return CPU0 _PSS.
+ }
+
+ Method(_PSD,0)
+ {
+ Return(\_PR.CPU0._PSD) // Return P0 _PSD.
+ }
+ }
+
+ Scope(\_PR.CPU3)
+ {
+ Method(_PPC,0)
+ {
+ Return(\_PR.CPU0._PPC) // Return CPU0 _PPC value.
+ }
+
+ Method(_PCT,0)
+ {
+ Return(\_PR.CPU0._PCT) // Return CPU0 _PCT value.
+ }
+
+ Method(_PSS,0)
+ {
+ Return(\_PR.CPU0._PSS) // Return CPU0 _PSS.
+ }
+
+ Method(_PSD,0)
+ {
+ Return(\_PR.CPU0._PSD) // Return P0 _PSD.
+ }
+ }
+
+} // End of Definition Block
+
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