diff options
author | Leif Lindholm <leif.lindholm@linaro.org> | 2017-08-03 12:24:30 +0100 |
---|---|---|
committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-08-03 12:24:30 +0100 |
commit | 600081b52debde8d06585fdaf09fac16d323670f (patch) | |
tree | fef3287095bb56eba411c0b31c525283978b71fb /Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt | |
parent | f4d38e50c0f24eb78eb003a94f583025621c63db (diff) | |
download | edk2-platforms-600081b52debde8d06585fdaf09fac16d323670f.tar.xz |
Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt')
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl | 88 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 38 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl | 38 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl | 29 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl | 956 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl | 86 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl | 181 | ||||
-rw-r--r-- | Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl | 136 |
8 files changed, 1552 insertions, 0 deletions
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl new file mode 100644 index 0000000000..e995295747 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/CPU.asl @@ -0,0 +1,88 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ //
+ // A57x16 Processor declaration
+ //
+ Device(CPU0) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ Device(CPU1) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ }
+ Device(CPU2) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ }
+ Device(CPU3) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ }
+ Device(CPU4) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 4)
+ }
+ Device(CPU5) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 5)
+ }
+ Device(CPU6) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 6)
+ }
+ Device(CPU7) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 7)
+ }
+ Device(CPU8) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 8)
+ }
+ Device(CPU9) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 9)
+ }
+ Device(CP10) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 10)
+ }
+ Device(CP11) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 11)
+ }
+ Device(CP12) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 12)
+ }
+ Device(CP13) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 13)
+ }
+ Device(CP14) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 14)
+ }
+ Device(CP15) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 15)
+ }
+}
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl new file mode 100644 index 0000000000..e3fc0d3565 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl @@ -0,0 +1,38 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+ Device(COM0) {
+ Name(_HID, "HISI0031") //it is not 16550 compatible
+ Name(_CID, "8250dw")
+ Name(_UID, Zero)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x80300000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 349 }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-frequency", 200000000},
+ Package () {"reg-io-width", 4},
+ Package () {"reg-shift", 2},
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl new file mode 100644 index 0000000000..5188060732 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Ctl.asl @@ -0,0 +1,38 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ // sysctl dsa
+ Device(CTL0) {
+ Name(_HID, "HISI0061")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xC0000000, 0x10000)
+ })
+ }
+ // sysctl pcie
+ Device(CTL1) {
+ Name(_HID, "HISI0061")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xB0000000, 0x10000)
+ })
+ }
+ // sysctl peri_c
+ Device(CTL2) {
+ Name(_HID, "HISI0061")
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x80000000, 0x10000)
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl new file mode 100644 index 0000000000..c0cc6d2e93 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Dsdt.asl @@ -0,0 +1,29 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Pv660Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 1, "HISI ", "HIP05 ", EFI_ACPI_ARM_OEM_REVISION) {
+ include ("Mbig.asl")
+ include ("CPU.asl")
+ include ("Com.asl")
+ include ("Usb.asl")
+ include ("Ctl.asl")
+ include ("Hns.asl")
+ include ("Pci.asl")
+}
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl new file mode 100644 index 0000000000..881aa1477e --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Hns.asl @@ -0,0 +1,956 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ Device (MDIO)
+ {
+ OperationRegion(CLKR, SystemMemory, 0x80000338, 8)
+ Field(CLKR, DWordAcc, NoLock, Preserve) {
+ CLKE, 1, // clock enable
+ , 31,
+ CLKD, 1, // clode disable
+ , 31,
+ }
+ OperationRegion(RSTR, SystemMemory, 0x80000A38, 8)
+ Field(RSTR, DWordAcc, NoLock, Preserve) {
+ RSTE, 1, // reset
+ , 31,
+ RSTD, 1, // de-reset
+ , 31,
+ }
+
+ Name(_HID, "HISI0141")
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0x803c0000 , 0x10000)
+ })
+
+ Method(_RST, 0, Serialized) {
+ Store (0x1, RSTE)
+ Sleep (10)
+ Store (0x1, CLKD)
+ Sleep (10)
+ Store (0x1, RSTD)
+ Sleep (10)
+ Store (0x1, CLKE)
+ Sleep (10)
+ }
+ }
+
+ Device (DSF0)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+ OperationRegion(H4SR, SystemMemory, 0xC0000190, 4)
+ Field(H4SR, DWordAcc, NoLock, Preserve) {
+ H4ST, 1,
+ , 31, //RESERVED
+ }
+ // DSAF RESET
+ OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+ Field(DRER, DWordAcc, NoLock, Preserve) {
+ DRTE, 1,
+ , 31, //RESERVED
+ DRTD, 1,
+ , 31, //RESERVED
+ }
+ // NT RESET
+ OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+ Field(NRER, DWordAcc, NoLock, Preserve) {
+ NRTE, 1,
+ , 31, //RESERVED
+ NRTD, 1,
+ , 31, //RESERVED
+ }
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // RCB PPE COM RESET
+ OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+ Field(RRTR, DWordAcc, NoLock, Preserve) {
+ RRTE, 1,
+ , 31, //RESERVED
+ RRTD, 1,
+ , 31, //RESERVED
+ }
+
+ // ROCE
+
+ // CPLD LED
+
+ // Serdes
+ OperationRegion(H4LR, SystemMemory, 0xC2288100, 0x1000)
+ Field(H4LR, DWordAcc, NoLock, Preserve) {
+ H4L0, 16, // port0
+ H4R0, 16, //RESERVED
+ Offset (0x400),
+ H4L1, 16, // port1
+ H4R1, 16, //RESERVED
+ Offset (0x800),
+ H4L2, 16, // port2
+ H4R2, 16, //RESERVED
+ Offset (0xc00),
+ H4L3, 16, // port3
+ H4R3, 16, //RESERVED
+ }
+ OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L2, 16, // port4
+ , 16, //RESERVED
+ Offset (0x400),
+ H3L3, 16, // port5
+ , 16, //RESERVED
+ }
+ Name (_HID, "HISI00B1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+ Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
+ {
+ 149,150,151,152,153,154,26,27,155,156,157,158,159,160, //[14] ge fifo err 8 / xge 6
+ 6,7,8,9,16,17,18,19,22,23,24,25, //[12] rcb com 4*3
+ 0,1,2,3,4,5,12,13, //[8] ppe tnl 0-7
+ 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, //[21] dsaf event int 3+18
+ 161,162,163,164,
+ }
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 384, 385, 386, 387, 388, 389, 390, 391, 392, 393, 394, 395, 396, 397, 398, 399, //[256] sevice rcb 2*128
+ 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415,
+ 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431,
+ 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447,
+ 448, 449, 450, 451, 452, 453, 454, 455, 456, 457, 458, 459, 460, 461, 462, 463,
+ 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479,
+ 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495,
+ 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511,
+ 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 527,
+ 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543,
+ 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559,
+ 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "6port-16rss"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+ }
+ })
+
+ //reset XGE port
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XRST, 2, Serialized) {
+ ShiftLeft (0x2082082, Arg0, Local0)
+ Or (Local0, 0x1, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset XGE core
+ //Arg0 : XGE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(XCRT, 2, Serialized) {
+ ShiftLeft (0x2080, Arg0, Local0)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, XRTE)
+ } Else {
+ Store(Local0, XRTD)
+ }
+ }
+
+ //reset GE port
+ //Arg0 : GE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(GRST, 2, Serialized) {
+ If (LLessEqual (Arg0, 5)) {
+ //Service port
+ ShiftLeft (0x1041041, Arg0, Local0)
+ ShiftLeft (0x1, Arg0, Local1)
+
+ If (LEqual (Arg1, 0)) {
+ Store(Local1, GR1E)
+ Store(Local0, GR0E)
+ } Else {
+ Store(Local0, GR0D)
+ Store(Local1, GR1D)
+ }
+ }
+ }
+
+ //reset PPE port
+ //Arg0 : PPE port index in dsaf
+ //Arg1 : 0 reset, 1 cancle reset
+ Method(PRST, 2, Serialized) {
+ ShiftLeft (0x1, Arg0, Local0)
+ If (LEqual (Arg1, 0)) {
+ Store(Local0, PRTE)
+ } Else {
+ Store(Local0, PRTD)
+ }
+ }
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 2, Serialized) {
+ ShiftLeft (Arg1, 10, Local0)
+ Switch (ToInteger(Arg0))
+ {
+ case (0x0){
+ Store (H4L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L0)
+ }
+ case (0x1){
+ Store (H4L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L1)
+ }
+ case (0x2){
+ Store (H4L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L2)
+ }
+ case (0x3){
+ Store (H4L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H4L3)
+ }
+ case (0x4){
+ Store (H3L2, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L2)
+ }
+ case (0x5){
+ Store (H3L3, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local0, H3L3)
+ }
+ }
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
+ //Arg1 : port
+ //Arg2 : 0 disable, 1 enable
+ Method(DRST, 3, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ Store (Arg2, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Store (0x1, DRTE)
+ Store (0x1, NRTE)
+ Sleep (10)
+ Store (0x1, RRTE)
+ }
+ Else
+ {
+ Store (0x1, DRTD)
+ Store (0x1, NRTD)
+ Sleep (10)
+ Store (0x1, RRTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ PRST (Local0, Local1)
+ }
+
+ //Reset XGE core
+ case (0x3)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XCRT (Local0, Local1)
+ }
+ //Reset XGE port
+ case (0x4)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ XRST (Local0, Local1)
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ Store (Arg1, Local0)
+ Store (Arg2, Local1)
+ GRST (Local0, Local1)
+ }
+ }
+ }
+
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
+ // Arg3[1] : port index in dsaf
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : port
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : port
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : port index in dsaf
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : port index in dsaf
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local1, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 1)), Local1)
+ SRLP (Local0, Local1)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (0, Local1)
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ If (LLessEqual (Local0, 3))
+ {
+ Store (H4ST, Local1)
+ }
+ ElseIf (LLessEqual (Local0, 5))
+ {
+ Store (H3ST, Local1)
+ }
+
+ Return (Local1)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT1)
+ {
+ Name (_ADR, 0x1)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 1},
+ Package () {"media-type", "fiber"},
+ }
+ })
+ }
+ Device (PRT4)
+ {
+ Name (_ADR, 0x4)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 4},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 0},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ Package () {"media-type", "copper"},
+ }
+ })
+ }
+ Device (PRT5)
+ {
+ Name (_ADR, 0x5)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 5},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 1},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ Package () {"media-type", "copper"},
+ }
+ })
+ }
+ }
+/*
+ Device (DSF1)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // ROCE
+
+ // CPLD LED
+
+ // Serdes
+ OperationRegion(H3LR, SystemMemory, 0xC2208100, 0x4)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L0, 16, // debug port0
+ , 16, //RESERVED
+ }
+ Name(_HID, "HISI00B1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc2000000 , 0x890000)
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 14, 15,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "single-port"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+ }
+ })
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 1, Serialized) {
+ ShiftLeft (Arg0, 10, Local0)
+ Store (H3L0, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H3L0)
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
+ //Arg1 : 0 disable, 1 enable
+ Method(DRST, 2, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store (0x100, PRTE)
+ } Else {
+ Store (0x100, PRTD)
+ }
+ }
+ //Reset PPE port
+ case (0x2)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x40, PRTE)
+ } Else {
+ Store(0x40, PRTD)
+ }
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x15540, GR1E)
+ Store(0x100, PRTE)
+ } Else {
+ Store(0x15540, GR1D)
+ Store(0x100, PRTD)
+ }
+ }
+ }
+ }
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset Sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
+ // Arg3[1] : reserved
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : reserved
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : reserved
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : reserved
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : reserved
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 2)), Local0)
+ SRLP (Local0)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (H3ST, Local0)
+ Return (Local0)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 0},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ }
+ })
+ }
+ }
+ Device (DSF2)
+ {
+ OperationRegion(H3SR, SystemMemory, 0xC0000180, 4)
+ Field(H3SR, DWordAcc, NoLock, Preserve) {
+ H3ST, 1,
+ , 31, //RESERVED
+ }
+
+ // XGE RESET
+ OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+ Field(XRER, DWordAcc, NoLock, Preserve) {
+ XRTE, 31,
+ , 1, //RESERVED
+ XRTD, 31,
+ , 1, //RESERVED
+ }
+
+ // GE RESET
+ OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+ Field(GRTR, DWordAcc, NoLock, Preserve) {
+ GR0E, 30,
+ , 2, //RESERVED
+ GR0D, 30,
+ , 2, //RESERVED
+ GR1E, 18,
+ , 14, //RESERVED
+ GR1D, 18,
+ , 14, //RESERVED
+ }
+
+ // PPE RESET
+ OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+ Field(PRTR, DWordAcc, NoLock, Preserve) {
+ PRTE, 10,
+ , 22, //RESERVED
+ PRTD, 10,
+ , 22, //RESERVED
+ }
+
+ // ROCE
+
+ // CPLD LED
+
+ // Serdes
+ OperationRegion(H3LR, SystemMemory, 0xC2208500, 0x4)
+ Field(H3LR, DWordAcc, NoLock, Preserve) {
+ H3L1, 16, // debug port1
+ , 16, //RESERVED
+ }
+ Name(_HID, "HISI00B1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xc2100000 , 0x890000)
+
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+ {
+ 20, 21,
+ }
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"mode", "single-port"},
+ Package () {"buf-size", 4096},
+ Package () {"desc-num", 1024},
+ Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+ }
+ })
+
+ // Set Serdes Loopback
+ //Arg0 : port
+ //Arg1 : 0 disable, 1 enable
+ Method(SRLP, 1, Serialized) {
+ ShiftLeft (Arg0, 10, Local0)
+ Store (H3L1, Local1)
+ And (Local1, 0xfffffbff, Local1)
+ Or (Local0, Local1, Local0)
+ Store (Local1, H3L1)
+ }
+
+ //Reset
+ //Arg0 : reset type (1: dsaf; 2: ppe; 3:reserved; 4:reserved; 5:G3)
+ //Arg1 : 0 disable, 1 enable
+ Method(DRST, 2, Serialized)
+ {
+ Switch (ToInteger(Arg0))
+ {
+ //DSAF reset
+ case (0x1)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store (0x200, PRTE)
+ } Else {
+ Store (0x2200, PRTD)
+ }
+ }
+
+ //Reset PPE port
+ case (0x2)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x80, PRTE)
+ } Else {
+ Store(0x80, PRTD)
+ }
+ }
+
+ //Reset GE port
+ case (0x5)
+ {
+ If (LEqual (Arg1, 0)) {
+ Store(0x2aa80, GR1E)
+ Store(0x200, PRTE)
+ } Else {
+ Store(0x2aa80, GR1D)
+ Store(0x200, PRTD)
+ }
+ }
+ }
+ }
+ // _DSM Device Specific Method
+ //
+ // Arg0: UUID Unique function identifier
+ // Arg1: Integer Revision Level
+ // Arg2: Integer Function Index
+ // 0 : Return Supported Functions bit mask
+ // 1 : Reset sequence
+ // Arg3[0] : reset type (1:dsaf; 2:ppe; 3:reserved; 4:reserved; 5: ge)
+ // Arg3[1] : reserved
+ // Arg3[2] : 0 reset, 1 cancle reset
+ // 2 : Set Serdes Loopback
+ // Arg3[0] : reserved
+ // Arg3[1] : 0 disable, 1 enable
+ // 3 : LED op set
+ // Arg3[0] : op type
+ // Arg3[1] : reserved
+ // Arg3[2] : para
+ // 4 : Get port type (GE or XGE)
+ // Arg3[0] : reserved
+ // Return : 0 GE, 1 XGE
+ // 5 : Get sfp status
+ // Arg3[0] : reserved
+ // Return : 0 no sfp, 1 have sfp
+ // Arg3: Package Parameters
+ Method (_DSM, 4, Serialized)
+ {
+ If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+ {
+ If (LEqual (Arg1, 0x00))
+ {
+ Switch (ToInteger(Arg2))
+ {
+ case (0x0)
+ {
+ Return (Buffer () {0x3F})
+ }
+
+ //Reset Sequence
+ case (0x1)
+ {
+ Store (DeRefOf (Index (Arg3, 0)), Local0)
+ Store (DeRefOf (Index (Arg3, 2)), Local2)
+ DRST (Local0, Local2)
+ }
+
+ //Set Serdes Loopback
+ case (0x2)
+ {
+ Store (DeRefOf (Index (Arg3, 2)), Local0)
+ SRLP (Local0)
+ }
+
+ //LED op set
+ case (0x3)
+ {
+
+ }
+
+ // Get port type (GE or XGE)
+ case (0x4)
+ {
+ Store (H3ST, Local0)
+ Return (Local0)
+ }
+
+ //Get sfp status
+ case (0x5)
+ {
+
+ }
+ }
+ }
+ }
+ Return (Buffer() {0x00})
+ }
+
+ Device (PRT0)
+ {
+ Name (_ADR, 0x0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"reg", 0},
+ Package () {"phy-mode", "sgmii"},
+ Package () {"phy-addr", 1},
+ Package () {"mdio-node", Package (){\_SB.MDIO}},
+ }
+ })
+ }
+ }
+*/
+ Device (ETH5) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 5},
+ }
+ })
+ }
+ Device (ETH4) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 4},
+ }
+ })
+ }
+ Device (ETH0) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 0},
+ }
+ })
+ }
+ Device (ETH1) {
+ Name(_HID, "HISI00C1")
+ Name (_CCA, 1) // Cache-coherent controller
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+ Package () {"ae-handle", Package (){\_SB.DSF0}},
+ Package () {"port-idx-in-ae", 1},
+ }
+ })
+ }
+
+}
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl new file mode 100644 index 0000000000..e7d3f72510 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Mbig.asl @@ -0,0 +1,86 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+ // Mbi-gen totem
+ Device(MBI0) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 0)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x8c030000, 0x10000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 256}
+ }
+ })
+ }
+
+ // mbi-gen dsa
+ Device(MBI1) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xc6030000, 0x10000)
+ })
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 640}
+ }
+ })
+ }
+
+ // mbi-gen m3
+ Device(MBI2) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 2)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xa3030000, 0x10000)
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 256}
+ }
+ })
+ }
+
+ // mbi-gen pcie
+ Device(MBI3) {
+ Name(_HID, "HISI0151")
+ Name(_CID, "MBIGen")
+ Name(_UID, 3)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xb7030000, 0x10000)
+ })
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"num-pins", 640}
+ }
+ })
+ }
+}
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl new file mode 100644 index 0000000000..244ff9375d --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Pci.asl @@ -0,0 +1,181 @@ +/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+Scope(_SB)
+{
+ // PCIe Root bus
+ Device (PCI1)
+ {
+ Name (_HID, "HISI0080") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 1) // Segment of this Root complex
+ Name(_BBN, 64) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 64, // AddressMinimum - Minimum Bus Number
+ 127, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 64 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000000b0000000, // Min Base Address pci address
+ 0x00000000b7feffff, // Max Base Address
+ 0x0000021f58000000, // Translate
+ 0x0000000007ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Min Base Address
+ 0x000000000000ffff, // Max Base Address
+ 0x000002200fff0000, // Translate
+ 0x0000000000010000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES1)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xb0080000 , 0x10000)
+ })
+ }
+
+ OperationRegion(SCTR, SystemMemory, 0xb0006918, 4)
+ Field(SCTR, AnyAcc, NoLock, Preserve) {
+ LSTA, 32,
+ }
+ Method(_DSM, 0x4, Serialized) {
+ If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) {
+
+ switch(ToInteger(Arg2))
+ {
+ // Function 0: Return LinkStatus
+ case(0) {
+ Store (0, Local0)
+ Store (LSTA, Local0)
+ Return (Local0)
+ }
+ default {
+ }
+ }
+ }
+ // If not one of the function identifiers we recognize, then return a buffer
+ // with bit 0 set to 0 indicating no functions supported.
+ return(Buffer(){0})
+ }
+ } // Device(PCI1)
+
+ // PCIe Root bus
+ Device (PCI2)
+ {
+ Name (_HID, "HISI0080") // PCI Express Root Bridge
+ Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+ Name(_SEG, 2) // Segment of this Root complex
+ Name(_BBN, 128) // Base Bus Number
+ Name(_CCA, 1)
+ Method (_CRS, 0, Serialized) { // Root complex resources
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 128, // AddressMinimum - Minimum Bus Number
+ 191, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 64 // RangeLength - Number of Busses
+ )
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000000c0000000, // Min Base Address
+ 0x00000000c3feffff, // Max Base Address
+ 0x0000023f4c000000, // Translate
+ 0x0000000003ff0000 // Length
+ )
+ QWordIO (
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Min Base Address
+ 0x000000000000ffff, // Max Base Address
+ 0x000002400fff0000, // Translate
+ 0x0000000000010000 // Length
+ )
+ }) // Name(RBUF)
+ Return (RBUF)
+ } // Method(_CRS)
+
+ Device (RES2)
+ {
+ Name (_HID, "HISI0081") // HiSi PCIe RC config base address
+ Name (_CRS, ResourceTemplate (){
+ Memory32Fixed (ReadWrite, 0xb0090000 , 0x10000)
+ })
+ }
+
+ OperationRegion(SCTR, SystemMemory, 0xb0006a18, 4)
+ Field(SCTR, AnyAcc, NoLock, Preserve) {
+ LSTA, 32,
+ }
+ Method(_DSM, 0x4, Serialized) {
+ If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949")))
+ {
+ switch(ToInteger(Arg2))
+ {
+ // Function 0: Return LinkStatus
+ case(0) {
+ Store (0, Local0)
+ Store (LSTA, Local0)
+ Return (Local0)
+ }
+ default {
+ }
+ }
+ }
+ // If not one of the function identifiers we recognize, then return a buffer
+ // with bit 0 set to 0 indicating no functions supported.
+ return(Buffer(){0})
+ }
+ } // Device(PCI2)
+}
+
diff --git a/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl new file mode 100644 index 0000000000..a0082af096 --- /dev/null +++ b/Silicon/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Usb.asl @@ -0,0 +1,136 @@ +/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+ Device (USB0)
+ {
+ Name (_HID, "PNP0D20") // _HID: Hardware ID
+ Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */) // _CID: Compatible ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xA1000000, // Address Base
+ 0x00010000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+ }
+
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () {"interrupt-parent",Package() {\_SB.MBI2}}
+ }
+ })
+
+ Device (RHUB)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Device (PRT1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ 0xFF,
+ Zero,
+ Zero,
+ Zero
+ })
+ Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
+ {
+ ToPLD (
+ PLD_Revision = 0x1,
+ PLD_IgnoreColor = 0x1,
+ PLD_Red = 0x0,
+ PLD_Green = 0x0,
+ PLD_Blue = 0x0,
+ PLD_Width = 0x0,
+ PLD_Height = 0x0,
+ PLD_UserVisible = 0x1,
+ PLD_Dock = 0x0,
+ PLD_Lid = 0x0,
+ PLD_Panel = "UNKNOWN",
+ PLD_VerticalPosition = "UPPER",
+ PLD_HorizontalPosition = "LEFT",
+ PLD_Shape = "UNKNOWN",
+ PLD_GroupOrientation = 0x0,
+ PLD_GroupToken = 0x0,
+ PLD_GroupPosition = 0x0,
+ PLD_Bay = 0x0,
+ PLD_Ejectable = 0x0,
+ PLD_EjectRequired = 0x0,
+ PLD_CabinetNumber = 0x0,
+ PLD_CardCageNumber = 0x0,
+ PLD_Reference = 0x0,
+ PLD_Rotation = 0x0,
+ PLD_Order = 0x0,
+ PLD_VerticalOffset = 0x0,
+ PLD_HorizontalOffset = 0x0)
+
+ })
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT3)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x04) // _ADR: Address
+ Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
+ {
+ Zero,
+ 0xFF,
+ Zero,
+ Zero
+ })
+ }
+ }
+ }
+}
+
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