diff options
| author | Ming Huang <huangming23@huawei.com> | 2017-03-29 10:28:00 +0800 |
|---|---|---|
| committer | Leif Lindholm <leif.lindholm@linaro.org> | 2017-10-05 13:53:16 +0100 |
| commit | bf5e51e477466d44d2d0fd39ea7f60c33a4cb202 (patch) | |
| tree | cb53d300b7769593ee6bbd3c2021a67bc351f29b /Silicon/Hisilicon | |
| parent | f156dfa26364eb76b501599c0d030d4bcb4b16cb (diff) | |
| download | edk2-platforms-bf5e51e477466d44d2d0fd39ea7f60c33a4cb202.tar.xz | |
D05/PCIe: Modify PcieRegionBase of secondary chip
On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.
Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Hisilicon')
| -rw-r--r-- | Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5db8..55c7f50825 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable,
ReadWrite,
0x0, // Granularity
- 0x20000000, // Min Base Address
+ 0x40000000, // Min Base Address
0xefffffff, // Max Base Address
0x65000000000, // Translate
- 0xd0000000 // Length
+ 0xb0000000 // Length
)
QWordIO (
ResourceProducer,
@@ -766,10 +766,10 @@ Scope(_SB) Cacheable,
ReadWrite,
0x0, // Granularity
- 0x30000000, // Min Base Address
+ 0x40000000, // Min Base Address
0xefffffff, // Max Base Address
0x75000000000, // Translate
- 0xc0000000 // Length
+ 0xb0000000 // Length
)
QWordIO (
ResourceProducer,
|