diff options
| author | Chasel, Chiu <chasel.chiu@intel.com> | 2017-11-30 22:37:57 +0800 |
|---|---|---|
| committer | Chasel, Chiu <chasel.chiu@intel.com> | 2017-12-06 13:10:42 +0800 |
| commit | 41a8bba3b198c7a11692e4d9404a86f5684efebd (patch) | |
| tree | e2157f92d0f84be987f1a6b3c088a352acf843db /Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c | |
| parent | 0791f3e77863e3d5bceb3da1b444f80fa6095a37 (diff) | |
| download | edk2-platforms-41a8bba3b198c7a11692e4d9404a86f5684efebd.tar.xz | |
edk2-platforms: Pre-allocate UPD buffer before FspWrapper
Customers request to initialize/update UPD buffer outside IntelFsp2Wrapper
for better code sharing and maintenance. Use MinPlatform SiliconPolicPei
to initialize UPD buffer and pass to FspWrapper by PCD. A new library
instance introduced to add dependency to FspWrapper to ensure
dispatching ordering.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c')
| -rw-r--r-- | Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c | 72 |
1 files changed, 63 insertions, 9 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c index d15e3f9083..4e82a0cc31 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiFspPolicyInitLib.c @@ -13,7 +13,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/
#include <PeiFspPolicyInitLib.h>
-
+#include <Library/FspWrapperApiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
/**
Performs silicon pre-mem policy initialization.
@@ -43,9 +45,35 @@ SiliconPolicyInitPreMem ( {
FSPM_UPD *FspmUpdDataPtr;
EFI_STATUS Status;
-
- FspmUpdDataPtr = FspmUpd;
-
+ UINTN *SourceData;
+ FSP_INFO_HEADER *FspmHeaderPtr;
+
+ if (FspmUpd == NULL) {
+ //
+ // Allocate and initialize UPD buffer, copy default FSP-M UPD data
+ //
+ FspmHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 (PcdFspmBaseAddress));
+ ASSERT (FspmHeaderPtr != NULL);
+ if (FspmHeaderPtr != NULL) {
+ DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr));
+ FspmUpdDataPtr = (FSPM_UPD *) AllocateZeroPool ((UINTN) FspmHeaderPtr->CfgRegionSize);
+ ASSERT (FspmUpdDataPtr != NULL);
+ if (FspmUpdDataPtr != NULL) {
+ SourceData = (UINTN *) ((UINTN) FspmHeaderPtr->ImageBase + (UINTN) FspmHeaderPtr->CfgRegionOffset);
+ CopyMem (FspmUpdDataPtr, SourceData, (UINTN) FspmHeaderPtr->CfgRegionSize);
+ PcdSet32S (PcdFspmUpdDataAddress, (UINT32) FspmUpdDataPtr);
+ }
+ }
+ } else {
+ FspmUpdDataPtr = FspmUpd;
+ }
+ //
+ // Return NULL pointer as error occurried and do not continue rest of the steps.
+ //
+ if (FspmUpdDataPtr == NULL) {
+ return NULL;
+ }
+ DEBUG ((DEBUG_INFO, "FspmUpdDataPtr - 0x%x\n", FspmUpdDataPtr));
//
// Initialize Intel PEI Platform Policy
//
@@ -97,7 +125,7 @@ SiliconPolicyInitPreMem ( //
Status = PeiFspMiscUpdInitPreMem (FspmUpdDataPtr);
- return FspmUpd;
+ return FspmUpdDataPtr;
}
/*
@@ -148,9 +176,35 @@ SiliconPolicyInitPostMem ( {
FSPS_UPD *FspsUpdDataPtr;
EFI_STATUS Status;
-
- FspsUpdDataPtr = FspsUpd;
-
+ FSP_INFO_HEADER *FspsHeaderPtr;
+ UINTN *SourceData;
+
+ if (FspsUpd == NULL) {
+ //
+ // Allocate and initialize UPD buffer, copy default FSP-S UPD data
+ //
+ FspsHeaderPtr = (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 (PcdFspsBaseAddress));
+ ASSERT (FspsHeaderPtr != NULL);
+ if (FspsHeaderPtr != NULL) {
+ DEBUG ((DEBUG_INFO, "FspsHeaderPtr - 0x%x\n", FspsHeaderPtr));
+ FspsUpdDataPtr = (FSPS_UPD *) AllocateZeroPool ((UINTN) FspsHeaderPtr->CfgRegionSize);
+ ASSERT (FspsUpdDataPtr != NULL);
+ if (FspsUpdDataPtr != NULL) {
+ SourceData = (UINTN *) ((UINTN) FspsHeaderPtr->ImageBase + (UINTN) FspsHeaderPtr->CfgRegionOffset);
+ CopyMem (FspsUpdDataPtr, SourceData, (UINTN) FspsHeaderPtr->CfgRegionSize);
+ PcdSet32S (PcdFspsUpdDataAddress, (UINT32) FspsUpdDataPtr);
+ }
+ }
+ } else {
+ FspsUpdDataPtr = FspsUpd;
+ }
+ //
+ // Return NULL pointer as error occurried and do not continue rest of the steps.
+ //
+ if (FspsUpdDataPtr == NULL) {
+ return NULL;
+ }
+ DEBUG ((DEBUG_INFO, "FspsUpdDataPtr - 0x%x\n", FspsUpdDataPtr));
//
// Initialize Intel PEI Platform Policy
//
@@ -189,7 +243,7 @@ SiliconPolicyInitPostMem ( DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy Initialization fail, Status = %r\n", Status));
}
- return FspsUpd;
+ return FspsUpdDataPtr;
}
/*
|