diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-06-19 10:55:06 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-06-20 15:12:29 +0800 |
| commit | 646b243c0e3ef49b98071ca2c3fec15299b4d72f (patch) | |
| tree | 00d62812fcedd3d1bf49692b863bb48a826f3ab0 /Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library | |
| parent | f98787b719524d7ba9f2cefac0e8c8b8698cb02c (diff) | |
| download | edk2-platforms-646b243c0e3ef49b98071ca2c3fec15299b4d72f.tar.xz | |
Add KabylakeSiliconPkg
reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com>
reviewed-by: Amy Chan <amy.chan@intel.com>
reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library')
23 files changed, 3483 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h new file mode 100644 index 0000000000..5362beeea3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioLib.h @@ -0,0 +1,707 @@ +/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
+ attempt to access these GPIO Pads registers, registers value
+ returned in this case will be 0xFF.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <GpioConfig.h>
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Some GpioPads are configured and switched to native mode by RC, those include:
+ SerialIo pins, ISH pins, ClkReq Pins
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+//
+// Functions for setting/getting multiple GpioPad settings
+//
+
+/**
+ This procedure will read multiple GPIO settings
+
+ @param[in] GpioPad GPIO Pad
+ @param[out] GpioData GPIO data structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadConfig (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_CONFIG *GpioData
+ );
+
+/**
+ This procedure will configure multiple GPIO settings
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioData GPIO data structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_CONFIG *GpioData
+ );
+
+//
+// Functions for setting/getting single GpioPad properties
+//
+
+/**
+ This procedure will set GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetOutputValue (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] OutputVal GPIO Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetOutputValue (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *OutputVal
+ );
+
+/**
+ This procedure will get GPIO input level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InputVal GPIO Input value
+ 0: InputLow, 1: InputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetInputValue (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+/**
+ This procedure will get GPIO IOxAPIC interrupt number
+
+ @param[in] GpioPad GPIO pad
+ @param[out] IrqNum IRQ number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadIoApicIrqNumber (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *IrqNum
+ );
+
+/**
+ This procedure will configure GPIO input inversion
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value for GPIO input inversion
+ 0: No input inversion, 1: Invert input
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetInputInversion (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO pad input inversion value
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InvertState GPIO inversion state
+ 0: No input inversion, 1: Inverted input
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetInputInversion (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InvertState
+ );
+
+/**
+ This procedure will set GPIO interrupt settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of Level/Edge
+ use GPIO_INT_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadInterruptConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_INT_CONFIG Value
+ );
+
+/**
+ This procedure will set GPIO electrical settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of termination
+ use GPIO_ELECTRICAL_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadElectricalConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_ELECTRICAL_CONFIG Value
+ );
+
+/**
+ This procedure will set GPIO Reset settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value for Pad Reset Configuration
+ use GPIO_RESET_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadResetConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_RESET_CONFIG Value
+ );
+
+/**
+ This procedure will get GPIO Reset settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of Pad Reset Configuration
+ based on GPIO_RESET_CONFIG
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadResetConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_RESET_CONFIG *Value
+ );
+
+/**
+ This procedure will get GPIO Host Software Pad Ownership for certain group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Host Ownership register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] HostSwRegVal Value of Host Software Pad Ownership register
+ Bit position - PadNumber
+ Bit value - 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetHostSwOwnershipForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *HostSwRegVal
+ );
+
+/**
+ This procedure will get GPIO Host Software Pad Ownership for certain group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Host Ownership register number for current group
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] HostSwRegVal Value of Host Software Pad Ownership register
+ Bit position - PadNumber
+ Bit value - 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioSetHostSwOwnershipForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 HostSwRegVal
+ );
+
+/**
+ This procedure will get Gpio Pad Host Software Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadHostSwOwn Value of Host Software Pad Owner
+ 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetHostSwOwnershipForPad (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadHostSwOwn
+ );
+
+/**
+ This procedure will set Gpio Pad Host Software Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[in] PadHostSwOwn Pad Host Software Owner
+ 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetHostSwOwnershipForPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 PadHostSwOwn
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for selected pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadCfgLock PadCfgLock for selected pad
+ 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadCfgLock (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadCfgLock
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for selected pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadCfgLock PadCfgLockTx for selected pad
+ 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadCfgLockTx (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadCfgLockTx
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pad.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioUnlockPadCfg (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioLockPadCfg (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pad.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioUnlockPadCfgTx (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLockTx Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLockTx
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioLockPadCfgTx (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get Group to GPE mapping.
+ Refer to BWG and EDS for GPIO GPE information.
+
+ @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetGroupToGpeDwX (
+ IN GPIO_GROUP *GroupToGpeDw0,
+ IN GPIO_GROUP *GroupToGpeDw1,
+ IN GPIO_GROUP *GroupToGpeDw2
+ );
+
+/**
+ This procedure will set Group to GPE mapping.
+ Refer to BWG and EDS for GPIO GPE information.
+
+ @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioSetGroupToGpeDwX (
+ IN GPIO_GROUP GroupToGpeDw0,
+ IN GPIO_GROUP GroupToGpeDw1,
+ IN GPIO_GROUP GroupToGpeDw2
+ );
+
+/**
+ This procedure will get GPE number for provided GpioPad.
+ PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX())
+ what results in the fact that certain Pad can cause different General Purpose Event. Only three
+ GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common
+ event (GPE_111 for 2-tier).
+
+ 1-tier:
+ Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used
+ to determine what _LXX ACPI method would be called on event on selected GPIO pad
+
+ 2-tier:
+ Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE
+ will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine
+ what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN
+ registers for all GPIO groups not mapped to 1-tier GPE.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpeNumber GPE number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpeNumber (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *GpeNumber
+ );
+
+/**
+ This procedure is used to clear SMI STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioClearGpiSmiSts (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used by Smi Dispatcher and will clear
+ all GPI SMI Status bits
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+GpioClearAllGpiSmiSts (
+ VOID
+ );
+
+/**
+ This procedure is used to disable all GPI SMI
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+GpioDisableAllGpiSmi (
+ VOID
+ );
+
+/**
+ This procedure is used to register GPI SMI dispatch function.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpiNum GPI number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiSmiNum (
+ IN GPIO_PAD GpioPad,
+ OUT UINTN *GpiNum
+ );
+
+/**
+ This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture
+
+ @param[in] GpioPad GPIO pad
+
+ @retval Data 0 means 1-tier, 1 means 2-tier
+**/
+BOOLEAN
+GpioCheckFor2Tier (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used to clear GPE STS for a specified GpioPad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioClearGpiGpeSts (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used to read GPE STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] Data GPE STS data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiGpeSts (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32* Data
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h new file mode 100644 index 0000000000..5f2c57fd34 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h @@ -0,0 +1,225 @@ +/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT8
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+/**
+ This procedure will return GpioPad from GroupIndex and PadNumber
+
+ @param[in] GroupIndex GPIO GroupIndex
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupIndexAndPadNumber (
+ IN UINT32 GroupIndex,
+ IN UINT32 PadNumber
+ );
+
+/**
+ This function sets SerialIo I2C controller pins into native mode
+
+ @param[in] SerialIoI2cControllerNumber I2C controller
+
+ @retval Status
+**/
+EFI_STATUS
+GpioSetSerialIoI2cPinsIntoNativeMode (
+ IN UINT32 SerialIoI2cControllerNumber
+ );
+
+/**
+ This function sets SerialIo I2C controller pins tolerance
+
+ @param[in] SerialIoI2CControllerNumber I2C controller
+ @param[in] Pad1v8Tolerance TRUE: Enable 1v8 Pad tolerance
+ FALSE: Disable 1v8 Pad tolerance
+
+ @retval Status
+**/
+EFI_STATUS
+GpioSetSerialIoI2CPinsTolerance (
+ IN UINT32 SerialIoI2CControllerNumber,
+ IN BOOLEAN Pad1v8Tolerance
+ );
+
+/**
+ This function sets SerialIo UART controller pins into native mode
+
+ @param[in] SerialIoI2CControllerNumber UART controller
+ @param[in] HardwareFlowControl Hardware Flow control
+
+ @retval Status
+**/
+EFI_STATUS
+GpioSetSerialIoUartPinsIntoNativeMode (
+ IN UINT32 SerialIoUartControllerNumber,
+ IN BOOLEAN HardwareFlowControl
+ );
+
+/**
+ This function sets SerialIo SPI controller pins into native mode
+
+ @param[in] SerialIoI2CControllerNumber SPI controller
+
+ @retval Status
+**/
+EFI_STATUS
+GpioSetSerialIoSpiPinsIntoNativeMode (
+ IN UINT32 SerialIoUartControllerNumber
+ );
+
+/**
+ This function checks if GPIO pin for SATA reset port is in GPIO MODE
+
+ @param[in] SataPort SATA port number
+
+ @retval TRUE Pin is in GPIO mode
+ FALSE Pin is in native mode
+**/
+BOOLEAN
+GpioIsSataResetPortInGpioMode (
+ IN UINTN SataPort
+ );
+
+/**
+ This function checks if SataDevSlp pin is in native mode
+
+ @param[in] SataPort SATA port
+ @param[out] DevSlpPad DevSlpPad
+
+ @retval TRUE DevSlp is in native mode
+ FALSE DevSlp is not in native mode
+**/
+BOOLEAN
+GpioIsSataDevSlpPinEnabled (
+ IN UINTN SataPort,
+ OUT GPIO_PAD *DevSlpPad
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h new file mode 100644 index 0000000000..9f5da64dff --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/OcWdtLib.h @@ -0,0 +1,37 @@ +/** @file
+ Header file for OC WDT Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _OC_WDT_LIB_H_
+#define _OC_WDT_LIB_H_
+
+/**
+ Check for unexpected reset.
+ If there was an unexpected reset, enforces WDT expiration.
+**/
+VOID
+OcWdtResetCheck (
+ VOID
+ );
+
+/**
+ This function install WDT PPI
+
+ @retval EFI_STATUS Results of the installation of the WDT PPI
+**/
+EFI_STATUS
+EFIAPI
+OcWdtInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h new file mode 100644 index 0000000000..30ad2713b5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h @@ -0,0 +1,345 @@ +/** @file
+ Header file for PchCycleDecodingLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_CYCLE_DECODING_LIB_H_
+#define _PCH_CYCLE_DECODING_LIB_H_
+
+/**
+ Set PCH ACPI base address.
+ The Address should not be 0 and should be 256 bytes alignment, and it is IO space, so must not exceed 0xFFFF.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. clear PMC PCI offset 44h [7] to diable ACPI base address first before changing base address.
+ 2. program PMC PCI offset 40h [15:2] to ACPI base address.
+ 3. set PMC PCI offset 44h [7] to enable ACPI base address.
+ 4. program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F, PMC PCI Offset 40h bit[15:2], 1].
+ 5. Program "ACPI Base Destination ID" PCR[DMI] + 27B8h[31:0] to [0x23A0].
+
+ @param[in] Address Address for ACPI base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+EFIAPI
+PchAcpiBaseSet (
+ IN UINT16 Address
+ );
+
+/**
+ Get PCH ACPI base address.
+
+ @param[out] Address Address of ACPI base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid pointer passed.
+**/
+EFI_STATUS
+EFIAPI
+PchAcpiBaseGet (
+ OUT UINT16 *Address
+ );
+
+/**
+ Set PCH PWRM base address.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. clear PMC PCI offset 44h [8] to diable PWRM base address first before changing PWRM base address.
+ 2. program PMC PCI offset 48h [31:16] to PM base address.
+ 3. set PMC PCI offset 44h [8] to enable PWRM base address.
+ 4. program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the PWRMBASE to be 64KB aligned.
+ program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the memory allocated to PWRMBASE to be 64KB in size.
+ 5. program "PM Base Control" PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0].
+
+ @param[in] Address Address for PWRM base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+EFIAPI
+PchPwrmBaseSet (
+ IN UINT32 Address
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @param[out] Address Address of PWRM base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid pointer passed.
+**/
+EFI_STATUS
+EFIAPI
+PchPwrmBaseGet (
+ OUT UINT32 *Address
+ );
+
+/**
+ Set PCH TCO base address.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. set Smbus PCI offset 54h [8] to enable TCO base address.
+ 2. program Smbus PCI offset 50h [15:5] to TCO base address.
+ 3. set Smbus PCI offset 54h [8] to enable TCO base address.
+ 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1].
+
+ @param[in] Address Address for TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+EFIAPI
+PchTcoBaseSet (
+ IN UINT16 Address
+ );
+
+/**
+ Get PCH TCO base address.
+
+ @param[out] Address Address of TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid pointer passed.
+**/
+EFI_STATUS
+EFIAPI
+PchTcoBaseGet (
+ OUT UINT16 *Address
+ );
+
+///
+/// structure of LPC general IO range register
+/// It contains base address, address mask, and enable status.
+///
+typedef struct {
+ UINT32 BaseAddr :16;
+ UINT32 Length :15;
+ UINT32 Enable : 1;
+} PCH_LPC_GEN_IO_RANGE;
+
+#define PCH_LPC_GEN_IO_RANGE_MAX 4
+///
+/// structure of LPC general IO range register list
+/// It lists all LPC general IO ran registers supported by PCH.
+///
+typedef struct {
+ PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];
+} PCH_LPC_GEN_IO_RANGE_LIST;
+
+/**
+ Set PCH LPC generic IO range.
+ For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
+ and less than or equal to 256. Moreover, the address must be length aligned.
+ This function basically checks the address and length, which should not overlap with all other generic ranges.
+ If no more generic range register available, it returns out of resource error.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ The IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
+ but all predefined and can't be changed. IO range below 0x100 will be skipped except 0x80-0x8F.
+ Steps of programming generic IO range:
+ 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
+ 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h.
+
+ @param[in] Address Address for generic IO range base address.
+ @param[in] Length Length of generic IO range.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+EFIAPI
+PchLpcGenIoRangeSet (
+ IN UINT16 Address,
+ IN UINTN Length
+ );
+
+/**
+ Get PCH LPC generic IO range list.
+ This function returns a list of base address, length, and enable for all LPC generic IO range regsiters.
+
+ @param[out] LpcGenIoRangeList Return all LPC generic IO range register status.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+EFIAPI
+PchLpcGenIoRangeGet (
+ OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList
+ );
+
+/**
+ Set PCH LPC memory range decoding.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. Program LPC/eSPI PCI 98h [0] to [0] to disable memory decoding first before changing base address.
+ 2. Program LPC/eSPI PCI 98h [31:16, 0] to [Address, 1].
+ 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h.
+
+ @param[in] Address Address for memory base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+**/
+EFI_STATUS
+EFIAPI
+PchLpcMemRangeSet (
+ IN UINT32 Address
+ );
+
+/**
+ Get PCH LPC memory range decoding address.
+
+ @param[out] Address Address of LPC memory decoding base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+EFIAPI
+PchLpcMemRangeGet (
+ OUT UINT32 *Address
+ );
+
+/**
+ Set PCH BIOS range deocding.
+ This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly.
+ Please check EDS for detail of BiosDecodeEnable bit definition.
+ bit 15: F8-FF Enable
+ bit 14: F0-F8 Enable
+ bit 13: E8-EF Enable
+ bit 12: E0-E8 Enable
+ bit 11: D8-DF Enable
+ bit 10: D0-D7 Enable
+ bit 9: C8-CF Enable
+ bit 8: C0-C7 Enable
+ bit 7: Legacy F Segment Enable
+ bit 6: Legacy E Segment Enable
+ bit 5: Reserved
+ bit 4: Reserved
+ bit 3: 70-7F Enable
+ bit 2: 60-6F Enable
+ bit 1: 50-5F Enable
+ bit 0: 40-4F Enable
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable.
+ if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
+ 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
+
+ @param[in] BiosDecodeEnable Bios decode enable setting.
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+EFIAPI
+PchBiosDecodeEnableSet (
+ IN UINT16 BiosDecodeEnable
+ );
+
+/**
+ Set PCH LPC IO decode ranges.
+ Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h.
+ Please check EDS for detail of Lpc IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+EFIAPI
+PchLpcIoDecodeRangesSet (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC IO enable decoding.
+ Setup LPC I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC offset 82h.
+ Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
+ in LPC 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
+ Please check EDS for detail of Lpc IO decode ranges bit definition.
+
+ @param[in] LpcIoEnableDecoding Lpc IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+EFIAPI
+PchLpcIoEnableDecodingSet (
+ IN UINT16 LpcIoEnableDecoding
+ );
+
+/**
+ Set PCH IO port 80h cycle decoding to PCIE root port.
+ System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that
+ the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12])
+ before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default
+ IO range values.
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP.
+ 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO.
+ 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding.
+
+ @param[in] RpPhyNumber PCIE root port physical number.
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+EFIAPI
+PchIoPort80DecodeSet (
+ IN UINTN RpPhyNumber
+ );
+
+/**
+ Get IO APIC regsiters base address.
+ It returns IO APIC INDEX, DATA, and EOI regsiter address once the parameter is not NULL.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[out] IoApicIndex Buffer of IO APIC INDEX regsiter address
+ @param[out] IoApicData Buffer of IO APIC DATA regsiter address
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PchIoApicBaseGet (
+ OPTIONAL OUT UINT32 *IoApicIndex,
+ OPTIONAL OUT UINT32 *IoApicData
+ );
+
+/**
+ Get HPET base address.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[out] HpetBase Buffer of HPET base address
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchHpetBaseGet (
+ OUT UINT32 *HpetBase
+ );
+
+#endif // _PCH_CYCLE_DECODING_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h new file mode 100644 index 0000000000..2096645375 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchEspiLib.h @@ -0,0 +1,102 @@ +/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_ESPI_LIB_H_
+#define _PCH_ESPI_LIB_H_
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+/**
+ Get configuration from eSPI slave
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] SlaveAddress Slave Configuration Register Address
+ @param[out] OutData Configuration data read
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed
+ @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveGetConfig (
+ IN UINT32 SlaveId,
+ IN UINT32 SlaveAddress,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Set eSPI slave configuration
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] SlaveAddress Slave Configuration Register Address
+ @param[in] InData Configuration data to write
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed
+ @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned
+ @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7FF has been locked
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveSetConfig (
+ IN UINT32 SlaveId,
+ IN UINT32 SlaveAddress,
+ IN UINT32 InData
+ );
+
+/**
+ Get status from eSPI slave
+
+ @param[in] SlaveId eSPI slave ID
+ @param[out] OutData Configuration data read
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveGetStatus (
+ IN UINT32 SlaveId,
+ OUT UINT16 *OutData
+ );
+
+/**
+ eSPI slave in-band reset
+
+ @param[in] SlaveId eSPI slave ID
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveInBandReset (
+ IN UINT32 SlaveId
+ );
+
+#endif // _PEI_DXE_SMM_PCH_ESPI_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h new file mode 100644 index 0000000000..5461286634 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchGbeLib.h @@ -0,0 +1,64 @@ +/** @file
+ Header file for PchGbeLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_GBE_LIB_H_
+#define _PCH_GBE_LIB_H_
+
+/**
+ Check whether GbE region is valid
+ Check SPI region directly since GBE might be disabled in SW.
+
+ @retval TRUE Gbe Region is valid
+ @retval FALSE Gbe Region is invalid
+**/
+BOOLEAN
+PchIsGbeRegionValid (
+ VOID
+ );
+
+/**
+ Returns GbE over PCIe port number based on a soft strap.
+
+ @return Root port number (1-based)
+ @retval 0 GbE over PCIe disabled
+**/
+UINT32
+PchGetGbePortNumber (
+ VOID
+ );
+
+/**
+ Check whether LAN controller is enabled in the platform.
+
+ @retval TRUE GbE is enabled
+ @retval FALSE GbE is disabled
+**/
+BOOLEAN
+PchIsGbePresent (
+ VOID
+ );
+
+/**
+ Check whether LAN controller is enabled in the platform.
+
+ @deprecated Use PchIsGbePresent instead.
+
+ @retval TRUE GbE is enabled
+ @retval FALSE GbE is disabled
+**/
+BOOLEAN
+PchIsGbeAvailable (
+ VOID
+ );
+
+#endif // _PCH_GBE_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h new file mode 100644 index 0000000000..65076800a9 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchHsioLib.h @@ -0,0 +1,114 @@ +/** @file
+ Header file for PchHsioLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_HSIO_LIB_H_
+#define _PCH_HSIO_LIB_H_
+
+/**
+ Represents HSIO lane
+**/
+typedef struct {
+ UINT8 Index; ///< Lane index
+ UINT8 Pid; ///< Sideband ID
+ UINT16 Base; ///< Sideband base address
+} HSIO_LANE;
+
+/**
+ The function returns the Port Id and lane owner for the specified lane
+
+ @param[in] PhyMode Phymode that needs to be checked
+ @param[out] Pid Common Lane End Point ID
+ @param[out] LaneOwner Lane Owner
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid lane number
+**/
+EFI_STATUS
+EFIAPI
+PchGetLaneInfo (
+ IN UINT32 LaneNum,
+ OUT UINT8 *PortId,
+ OUT UINT8 *LaneOwner
+ );
+
+/**
+ Get HSIO lane representation needed to perform any operation on the lane.
+
+ @param[in] LaneIndex Number of the HSIO lane
+ @param[out] HsioLane HSIO lane representation
+**/
+VOID
+HsioGetLane (
+ IN UINT8 LaneIndex,
+ OUT HSIO_LANE *HsioLane
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[in] PcieLaneIndex PCIE Root Port Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetPcieLaneNum (
+ UINT32 PcieLaneIndex,
+ UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[in] SataLaneIndex Sata Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetSataLaneNum (
+ UINT32 SataLaneIndex,
+ UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[in] Usb3LaneIndex USB3 Lane Index
+ @param[out] LaneNum Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetUsb3LaneNum (
+ UINT32 Usb3LaneIndex,
+ UINT8 *LaneNum
+ );
+
+/**
+ Determine the lane number of a specified port
+
+ @param[out] LaneNum GBE Lane Number
+
+ @retval EFI_SUCCESS Lane number valid.
+ @retval EFI_UNSUPPORTED Incorrect input device port
+**/
+EFI_STATUS
+PchGetGbeLaneNum (
+ UINT8 *LaneNum
+ );
+
+#endif // _PCH_HSIO_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..5902b92f18 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchInfoLib.h @@ -0,0 +1,260 @@ +/** @file
+ Header file for PchInfoLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_INFO_LIB_H_
+#define _PCH_INFO_LIB_H_
+
+#include <PchAccess.h>
+
+typedef enum {
+ PchH = 1,
+ PchLp,
+ PchUnknownSeries
+} PCH_SERIES;
+
+typedef enum {
+ SklPch = 1,
+ KblPch,
+ PchUnknownGeneration
+} PCH_GENERATION;
+
+typedef enum {
+ RstUnsupported = 0,
+ RstPremium,
+ RstOptane,
+ RstMaxMode
+} RST_MODE;
+
+typedef enum {
+ PchMobileSku = 0,
+ PchDesktopSku,
+ PchServerSku,
+ PchUnknownSku,
+ PchMaxSku
+} PCH_SKU_TYPE;
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+EFIAPI
+PchStepping (
+ VOID
+ );
+
+/**
+ Determine if PCH is supported
+
+ @retval TRUE PCH is supported
+ @retval FALSE PCH is not supported
+**/
+BOOLEAN
+IsPchSupported (
+ VOID
+ );
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+EFIAPI
+GetPchSeries (
+ VOID
+ );
+
+/**
+ Return Pch Generation
+
+ @retval PCH_GENERATION Pch Generation
+**/
+PCH_GENERATION
+EFIAPI
+GetPchGeneration (
+ VOID
+ );
+
+/**
+ Get PCH SKU type
+
+ @retval PCH_SKU_TYPE Type of PCH SKU
+**/
+PCH_SKU_TYPE
+GetPchSkuType (
+ VOID
+ );
+
+/**
+ Get Lpc Did
+
+ @retval UINT16 Lpc Did
+**/
+UINT16
+EFIAPI
+GetLpcDid (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+EFIAPI
+GetPchMaxPciePortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Sata Port Number
+
+ @retval Pch Maximum Sata Port Number
+**/
+UINT8
+EFIAPI
+GetPchMaxSataPortNum (
+ VOID
+ );
+
+/**
+ Get Pch Usb Maximum Physical Port Number
+
+ @retval Pch Usb Maximum Physical Port Number
+**/
+UINT8
+EFIAPI
+GetPchUsbMaxPhysicalPortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Usb2 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb2 Port Number of XHCI Controller
+**/
+UINT8
+EFIAPI
+GetPchXhciMaxUsb2PortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Usb3 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb3 Port Number of XHCI Controller
+**/
+UINT8
+EFIAPI
+GetPchXhciMaxUsb3PortNum (
+ VOID
+ );
+
+/**
+ Get PCH stepping ASCII string
+ The return string is zero terminated.
+
+ @param [in] PchStep Pch stepping
+ @param [out] Buffer Output buffer of string
+ @param [in,out] BufferSize Size of input buffer,
+ and return required string size when buffer is too small.
+
+ @retval EFI_SUCCESS String copy successfully
+ @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL
+ @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
+**/
+EFI_STATUS
+PchGetSteppingStr (
+ IN PCH_STEPPING PchStep,
+ OUT CHAR8 *Buffer,
+ IN OUT UINT32 *BufferSize
+ );
+
+/**
+ Get PCH series ASCII string
+ The return string is zero terminated.
+
+ @param [in] PchSeries Pch series
+ @param [out] Buffer Output buffer of string
+ @param [in,out] BufferSize Size of input buffer,
+ and return required string size when buffer is too small.
+
+ @retval EFI_SUCCESS String copy successfully
+ @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL
+ @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
+**/
+EFI_STATUS
+PchGetSeriesStr (
+ IN PCH_SERIES PchSeries,
+ OUT CHAR8 *Buffer,
+ IN OUT UINT32 *BufferSize
+ );
+
+/**
+ Get PCH Sku ASCII string
+ The return string is zero terminated.
+
+ @param [in] LpcDid LPC device id
+ @param [out] Buffer Output buffer of string
+ @param [in,out] BufferSize Size of input buffer,
+ and return required string size when buffer is too small.
+
+ @retval EFI_SUCCESS String copy successfully
+ @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL
+ @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
+**/
+EFI_STATUS
+PchGetSkuStr (
+ IN UINT16 LpcDid,
+ OUT CHAR8 *Buffer,
+ IN OUT UINT32 *BufferSize
+ );
+
+/**
+ Get RST mode supported by the silicon
+
+ @retval RST_MODE RST mode supported by silicon
+**/
+RST_MODE
+EFIAPI
+GetSupportedRstMode (
+ VOID
+ );
+
+/**
+ Check if current SKU supports Optane mode
+
+ @retval TRUE This SKU supports Optane mode
+ @retval FALSE This SKU doesn't support Optane mode
+**/
+BOOLEAN
+EFIAPI
+IsOptaneModeSupported (
+ VOID
+ );
+
+/**
+ Check if current SKU supports RAID feature
+
+ @retval TRUE This SKU supports RAID
+ @retval FALSE This SKU doesn't support RAID
+**/
+BOOLEAN
+EFIAPI
+IsPchRaidSupported (
+ VOID
+ );
+#endif // _PCH_INFO_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h new file mode 100644 index 0000000000..8083ac4efd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchP2sbLib.h @@ -0,0 +1,160 @@ +/** @file
+ Header file for PchP2sbLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_P2SB_LIB_H_
+#define _PCH_P2SB_LIB_H_
+
+/**
+ Get P2SB pci configuration register.
+ It returns register at Offset of P2SB controller and size in 4bytes.
+ The Offset should not exceed 255 and must be aligned with size.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[in] Offset Register offset of P2SB controller.
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchP2sbCfgGet32 (
+ IN UINTN Offset,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Get P2SB pci configuration register.
+ It returns register at Offset of P2SB controller and size in 2bytes.
+ The Offset should not exceed 255 and must be aligned with size.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[in] Offset Register offset of P2SB controller.
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchP2sbCfgGet16 (
+ IN UINTN Offset,
+ OUT UINT16 *OutData
+ );
+
+/**
+ Get P2SB pci configuration register.
+ It returns register at Offset of P2SB controller and size in 1byte.
+ The Offset should not exceed 255 and must be aligned with size.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[in] Offset Register offset of P2SB controller.
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchP2sbCfgGet8 (
+ IN UINTN Offset,
+ OUT UINT8 *OutData
+ );
+
+/**
+ Set P2SB pci configuration register.
+ It programs register at Offset of P2SB controller and size in 4bytes.
+ The Offset should not exceed 255 and must be aligned with size.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[in] Offset Register offset of P2SB controller.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchP2sbCfgSet32 (
+ IN UINTN Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Set P2SB pci configuration register.
+ It programs register at Offset of P2SB controller and size in 2bytes.
+ The Offset should not exceed 255 and must be aligned with size.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[in] Offset Register offset of P2SB controller.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchP2sbCfgSet16 (
+ IN UINTN Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Set P2SB pci configuration register.
+ It programs register at Offset of P2SB controller and size in 1bytes.
+ The Offset should not exceed 255 and must be aligned with size.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[in] Offset Register offset of P2SB controller.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchP2sbCfgSet8 (
+ IN UINTN Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Hide P2SB device.
+
+ @param[in] P2sbBase Pci base address of P2SB controller.
+
+ @retval EFI_SUCCESS Always return success.
+**/
+EFI_STATUS
+PchHideP2sb (
+ IN UINTN P2sbBase
+ );
+
+/**
+ Reveal P2SB device.
+ Also return the original P2SB status which is for Hidding P2SB or not after.
+ If OrgStatus is not NULL, then TRUE means P2SB is unhidden,
+ and FALSE means P2SB is hidden originally.
+
+ @param[in] P2sbBase Pci base address of P2SB controller.
+ @param[out] OrgStatus Original P2SB hidding/unhidden status
+
+ @retval EFI_SUCCESS Always return success.
+**/
+EFI_STATUS
+PchRevealP2sb (
+ IN UINTN P2sbBase,
+ OUT BOOLEAN *OrgStatus
+ );
+
+#endif // _PCH_P2SB_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h new file mode 100644 index 0000000000..d5084772dd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h @@ -0,0 +1,110 @@ +/** @file
+ Header file for PchPcieRpLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#define RST_PCIE_STORAGE_CR_1 0
+#define RST_PCIE_STORAGE_CR_2 1
+#define RST_PCIE_STORAGE_CR_3 2
+#define RST_PCIE_STORAGE_CR_INVALID 99
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Get Root Port physical Number by Pch Pcie Root Port Device and Function Number
+
+ @param[in] RpDev Root port device number.
+ @param[in] RpFun Root port function number.
+ @param[out] RpNumber Return corresponding physical Root Port index (0-based)
+
+ @retval EFI_SUCCESS Physical root port is retrieved
+ @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid
+ @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpNumber (
+ IN UINTN RpDev,
+ IN UINTN RpFun,
+ OUT UINTN *RpNumber
+ );
+
+/**
+ Gets base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINTN
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+/**
+ Determines whether L0s is supported on current stepping.
+
+ @return TRUE if L0s is supported, FALSE otherwise
+**/
+BOOLEAN
+PchIsPcieL0sSupported (
+ VOID
+ );
+
+/**
+ Some early SKL PCH steppings require Native ASPM to be disabled due to hardware issues:
+ - RxL0s exit causes recovery
+ - Disabling PCIe L0s capability disables L1
+ Use this function to determine affected steppings.
+
+ @return TRUE if Native ASPM is supported, FALSE otherwise
+**/
+BOOLEAN
+PchIsPcieNativeAspmSupported (
+ VOID
+ );
+
+/**
+ Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type
+
+ @param[in] RootPortNum Root Port Number
+
+ @retval UINT32 The RST PCIe Storage Cycle Router Number
+**/
+UINT32
+RstGetCycleRouterNumber (
+ IN UINT32 RootPortNum
+ );
+
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h new file mode 100644 index 0000000000..149168993f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPcrLib.h @@ -0,0 +1,196 @@ +/** @file
+ Header file for PchPcrLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchAccess.h>
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT16 *OutData
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+ @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ OUT UINT8 *OutData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] InData Input Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT16 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h new file mode 100644 index 0000000000..61a955802a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPmcLib.h @@ -0,0 +1,50 @@ +/** @file
+ Header file for PchPmcLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_PMC_LIB_H_
+#define _PCH_PMC_LIB_H_
+
+typedef enum {
+ WarmBoot = 1,
+ ColdBoot,
+ PwrFlr,
+ PwrFlrSys,
+ PwrFlrPch,
+ PchPmStatusMax
+} PCH_PM_STATUS;
+
+/**
+ Query PCH to determine the Pm Status
+
+ @param[in] PmStatus - The Pch Pm Status to be probed
+
+ @retval Status TRUE if Status querried is Valid or FALSE if otherwise
+**/
+BOOLEAN
+GetPchPmStatus (
+ PCH_PM_STATUS PmStatus
+ );
+
+/**
+ Funtion to check if Battery lost or CMOS cleared.
+
+ @reval TRUE Battery is always present.
+ @reval FALSE CMOS is cleared.
+**/
+BOOLEAN
+EFIAPI
+PchIsRtcBatteryGood (
+ VOID
+ );
+
+#endif // _PCH_PMC_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h new file mode 100644 index 0000000000..f4e3659960 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h @@ -0,0 +1,113 @@ +/** @file
+ Prototype of the PeiPchPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_PCH_POLICY_LIB_H_
+#define _PEI_PCH_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ Print whole PCH_PREMEM_POLICY_PPI and serial out.
+
+ @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
+**/
+VOID
+EFIAPI
+PchPreMemPrintPolicyPpi (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ Print whole SI_POLICY_PPI and serial out.
+
+ @param[in] SiPolicyPpi The RC Policy PPI instance
+**/
+VOID
+EFIAPI
+PchPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ Get PCH PREMEM config block table total size.
+
+ @retval Size of PCH PREMEM config block table
+**/
+UINT16
+EFIAPI
+PchGetPreMemConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ Get PCH config block table total size.
+
+ @retval Size of PCH config block table
+**/
+UINT16
+EFIAPI
+PchGetConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ PchAddPreMemConfigBlocks add all PCH config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+PchAddPreMemConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+/**
+ PchAddConfigBlocks add all PCH config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+PchAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+/*
+ Apply sample board PCH specific default settings
+
+ @param[in] SiPreMemPolicy The pointer to SI PREMEM Policy PPI instance
+*/
+VOID
+EFIAPI
+PchLoadSamplePreMemPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/*
+ Apply sample board PCH specific default settings
+
+ @param[in] SiPolicyPpi The pointer to SI Policy PPI instance
+*/
+VOID
+EFIAPI
+PchLoadSamplePolicy (
+ IN SI_POLICY_PPI *SiPolicy
+ );
+
+#endif // _PEI_PCH_POLICY_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h new file mode 100644 index 0000000000..4a2924f8f6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchPsfLib.h @@ -0,0 +1,170 @@ +/** @file
+ Header file for PchPsfLib.
+ This is helper library of RC for PSF register programming.
+ It's not expected to be used in platform code.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_PSF_LIB_H_
+#define _PCH_PSF_LIB_H_
+
+#include <Library/PchSerialIoLib.h>
+
+/**
+ This procedure will enable SerialIO device BAR1 at PSF level
+
+ @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2)
+
+ @retval None
+**/
+VOID
+PsfEnableSerialIoDeviceBar1 (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice
+ );
+
+/**
+ This procedure will disable SerialIO device BAR1 at PSF level
+
+ @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2)
+
+ @retval None
+**/
+VOID
+PsfDisableSerialIoDeviceBar1 (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice
+ );
+
+/**
+ This procedure will disable SerailIO device at PSF level
+
+ @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2)
+
+ @retval None
+**/
+VOID
+PsfDisableSerialIoDevice (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice
+ );
+
+/**
+ This procedure will hide SerialIo device PciCfgSpace at PSF level
+
+ @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2)
+
+ @retval None
+**/
+VOID
+PsfHideSerialIoDevice (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice
+ );
+
+/**
+ This procedure will reveal SerialIo device PciCfgSpace at PSF level
+
+ @param[in] SerialIoDevice SERIAL IO device (I2C0-5, SPI0-1, UART0-2)
+
+ @retval None
+**/
+VOID
+PsfRevealSerialIoDevice (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice
+ );
+
+/**
+ This procedure will set BARx value for TraceHub ACPI device at PSF level
+
+ @param[in] BarNum BAR Number (0:BAR0, 1:BAR1)
+ @param[in] BarValue 32bit BAR value
+
+ @retval None
+**/
+VOID
+PsfSetTraceHubAcpiDeviceBarValue (
+ IN UINT8 BarNum,
+ IN UINT32 BarValue
+ );
+
+/**
+ This procedure will enable MSE for TraceHub ACPI device at PSF level
+
+ @param[in] None
+
+ @retval None
+**/
+VOID
+PsfEnableTraceHubAcpiDeviceMemorySpace (
+ VOID
+ );
+
+/**
+ Enable HECI device at PSF level
+
+ @param[in] HeciDevice HECIx Device (HECI1-3)
+
+ @retval None
+**/
+VOID
+PsfEnableHeciDevice (
+ IN UINT8 HeciDevice
+ );
+
+/**
+ Disable HECI device at PSF level
+
+ @param[in] HeciDevice HECIx Device (HECI1-3)
+
+ @retval None
+**/
+VOID
+PsfDisableHeciDevice (
+ IN UINT8 HeciDevice
+ );
+
+/**
+ Enable IDER device at PSF level
+
+ @retval None
+**/
+VOID
+PsfEnableIderDevice (
+ VOID
+ );
+
+/**
+ Disable IDER device at PSF level
+
+ @retval None
+**/
+VOID
+PsfDisableIderDevice (
+ VOID
+ );
+
+/**
+ Enable SOL device at PSF level
+
+ @retval None
+**/
+VOID
+PsfEnableSolDevice (
+ VOID
+ );
+
+/**
+ Disable SOL device at PSF level
+
+ @retval None
+**/
+VOID
+PsfDisableSolDevice (
+ VOID
+ );
+#endif // _PCH_PSF_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h new file mode 100644 index 0000000000..448cd21f50 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchResetLib.h @@ -0,0 +1,30 @@ +/** @file
+ Header file for PCH RESET Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_RESET_LIB_H_
+#define _PCH_RESET_LIB_H_
+
+
+/**
+ Initialize PCH Reset APIs
+
+ @retval EFI_SUCCESS APIs are installed successfully
+ @retval EFI_OUT_OF_RESOURCES Can't allocate pool
+**/
+EFI_STATUS
+EFIAPI
+PchInitializeReset (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h new file mode 100644 index 0000000000..87d3318260 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h @@ -0,0 +1,162 @@ +/** @file
+ Header file for PchSbiAccessLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_SBI_ACCESS_LIB_H_
+#define _PCH_SBI_ACCESS_LIB_H_
+
+/**
+ PCH SBI Register structure
+**/
+typedef struct {
+ UINT32 SbiAddr;
+ UINT32 SbiExtAddr;
+ UINT32 SbiData;
+ UINT16 SbiStat;
+ UINT16 SbiRid;
+} PCH_SBI_REGISTER_STRUCT;
+
+/**
+ PCH SBI opcode definitions
+**/
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} PCH_SBI_OPCODE;
+
+/**
+ PCH SBI response status definitions
+**/
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} PCH_SBI_RESPONSE;
+
+/**
+ Execute PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+**/
+EFI_STATUS
+EFIAPI
+PchSbiExecution (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+**/
+EFI_STATUS
+EFIAPI
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+/**
+ This function saves all PCH SBI registers.
+ The save and restore operations must be done while using the PchSbiExecution inside SMM.
+ It prevents the racing condition of PchSbiExecution re-entry between POST and SMI.
+ Before using this function, make sure the P2SB is not hidden.
+
+ @param[in, out] PchSbiRegister Structure for saving the registers
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Device is hidden.
+**/
+EFI_STATUS
+EFIAPI
+PchSbiRegisterSave (
+ IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister
+ );
+
+/**
+ This function restores all PCH SBI registers
+ The save and restore operations must be done while using the PchSbiExecution inside SMM.
+ It prevents the racing condition of PchSbiExecution re-entry between POST and SMI.
+ Before using this function, make sure the P2SB is not hidden.
+
+ @param[in] PchSbiRegister Structure for restoring the registers
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Device is hidden.
+**/
+EFI_STATUS
+EFIAPI
+PchSbiRegisterRestore (
+ IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister
+ );
+
+#endif // _PCH_SBI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h new file mode 100644 index 0000000000..4ee5a9713e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h @@ -0,0 +1,219 @@ +/** @file
+ Header file for PCH Serial IO Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_SERIAL_IO_LIB_H_
+#define _PCH_SERIAL_IO_LIB_H_
+
+typedef enum {
+ PchSerialIoIndexI2C0,
+ PchSerialIoIndexI2C1,
+ PchSerialIoIndexI2C2,
+ PchSerialIoIndexI2C3,
+ PchSerialIoIndexI2C4,
+ PchSerialIoIndexI2C5,
+ PchSerialIoIndexSpi0,
+ PchSerialIoIndexSpi1,
+ PchSerialIoIndexUart0,
+ PchSerialIoIndexUart1,
+ PchSerialIoIndexUart2,
+ PchSerialIoIndexMax
+} PCH_SERIAL_IO_CONTROLLER;
+
+typedef enum {
+ PchSerialIoDisabled,
+ PchSerialIoAcpi,
+ PchSerialIoPci,
+ PchSerialIoAcpiHidden,
+ PchSerialIoLegacyUart,
+ PchSerialIoSkipInit
+} PCH_SERIAL_IO_MODE;
+
+enum PCH_LP_SERIAL_IO_VOLTAGE_SEL {
+ PchSerialIoIs33V = 0,
+ PchSerialIoIs18V
+};
+enum PCH_LP_SERIAL_IO_CS_POLARITY {
+ PchSerialIoCsActiveLow = 0,
+ PchSerialIoCsActiveHigh = 1
+};
+enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL {
+ PchSerialIoHwFlowCtrlDisabled = 0,
+ PchSerialIoHwFlowControlEnabled = 1
+};
+
+#define SERIALIO_HID_LENGTH 8 // including null terminator
+#define SERIALIO_UID_LENGTH 1
+#define SERIALIO_CID_LENGTH 1
+#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+SERIALIO_CID_LENGTH
+
+/**
+ Returns index of the last i2c controller
+
+ @param[in] Number Number of SerialIo controller
+
+ @retval Index of I2C controller
+**/
+PCH_SERIAL_IO_CONTROLLER
+GetMaxI2cNumber (
+ VOID
+ );
+
+/**
+ Returns string with AcpiHID assigned to selected SerialIo controller
+
+ @param[in] Number Number of SerialIo controller
+
+ @retval pointer to 8-byte string
+**/
+CHAR8*
+GetSerialIoAcpiHID (
+ IN PCH_SERIAL_IO_CONTROLLER Number
+ );
+
+/**
+ Checks if Device with given PciDeviceId is one of SerialIo controllers
+ If yes, its number is returned through Number parameter, otherwise Number is not updated
+
+ @param[in] PciDevId Device ID
+ @param[out] Number Number of SerialIo controller
+
+ @retval TRUE Yes it is a SerialIo controller
+ @retval FALSE No it isn't a SerialIo controller
+**/
+BOOLEAN
+IsSerialIoPciDevId (
+ IN UINT16 PciDevId,
+ OUT PCH_SERIAL_IO_CONTROLLER *Number
+ );
+
+/**
+ Checks if Device with given AcpiHID string is one of SerialIo controllers
+ If yes, its number is returned through Number parameter, otherwise Number is not updated
+
+ @param[in] AcpiHid String
+ @param[out] Number Number of SerialIo controller
+
+ @retval TRUE yes it is a SerialIo controller
+ @retval FALSE no it isn't a SerialIo controller
+**/
+BOOLEAN
+IsSerialIoAcpiHid (
+ IN CHAR8 *AcpiHid,
+ OUT PCH_SERIAL_IO_CONTROLLER *Number
+ );
+
+/**
+ Configures Serial IO Controller
+
+ @param[in] Controller
+ @param[in] DeviceMode
+
+ @retval None
+**/
+VOID
+ConfigureSerialIoController (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode
+ );
+
+/**
+ Initializes GPIO pins used by SerialIo I2C devices
+
+ @param[in] Controller
+ @param[in] DeviceMode
+ @param[in] I2cVoltage
+
+ @retval None
+**/
+VOID
+SerialIoI2cGpioInit (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN UINT32 I2cVoltage
+ );
+
+/**
+ Initializes GPIO pins used by SerialIo SPI devices
+
+ @param[in] Controller
+ @param[in] DeviceMode
+ @param[in] SpiCsPolarity
+
+ @retval None
+**/
+VOID
+SerialIoSpiGpioInit (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN UINT32 SpiCsPolarity
+ );
+
+/**
+ Initializes GPIO pins used by SerialIo devices
+
+ @param[in] Controller
+ @param[in] DeviceMode
+ @param[in] HardwareFlowControl
+
+ @retval None
+**/
+VOID
+SerialIoUartGpioInit (
+ IN PCH_SERIAL_IO_CONTROLLER Controller,
+ IN PCH_SERIAL_IO_MODE DeviceMode,
+ IN BOOLEAN HardwareFlowControl
+ );
+
+/**
+ Finds PCI Device Number of SerialIo devices.
+ SerialIo devices' BDF is configurable
+
+ @param[in] SerialIoNumber 0=I2C0, ..., 11=UART2
+
+ @retval SerialIo device number
+**/
+UINT8
+GetSerialIoDeviceNumber (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Finds PCI Function Number of SerialIo devices.
+ SerialIo devices' BDF is configurable
+
+ @param[in] SerialIoNumber 0=I2C0, ..., 11=UART2
+
+ @retval SerialIo funciton number
+**/
+UINT8
+GetSerialIoFunctionNumber (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber
+ );
+
+/**
+ Finds BAR values of SerialIo devices.
+ SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work.
+
+ @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2
+ @param[in] BarNumber 0=BAR0, 1=BAR1
+
+ @retval SerialIo Bar value
+**/
+UINTN
+FindSerialIoBar (
+ IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice,
+ IN UINT8 BarNumber
+ );
+
+
+#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h new file mode 100644 index 0000000000..66c5945a7b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.h @@ -0,0 +1,98 @@ +/** @file
+ Header file for PCH Serial IO UART Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_SERIAL_IO_UART_LIB_H_
+#define _PCH_SERIAL_IO_UART_LIB_H_
+
+/**
+ Initialize selected SerialIo UART.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[in] FifoEnable When TRUE, enables 64-byte FIFOs.
+ @param[in] BaudRate Baud rate.
+ @param[in] LineControl Data length, parity, stop bits.
+ @param[in] HardwareFlowControl Automated hardware flow control. If TRUE, hardware automatically checks CTS when sending data, and sets RTS when receiving data.
+**/
+VOID
+EFIAPI
+PchSerialIoUartInit (
+ IN UINT8 UartNumber,
+ IN BOOLEAN FifoEnable,
+ IN UINT32 BaudRate,
+ IN UINT8 LineControl,
+ IN BOOLEAN HardwareFlowControl
+ );
+
+
+/**
+ Write data to serial device.
+
+ If the buffer is NULL, then return 0;
+ if NumberOfBytes is zero, then return 0.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[in] Buffer Point of data buffer which need to be writed.
+ @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval Actual number of bytes writed to serial device.
+**/
+UINTN
+EFIAPI
+PchSerialIoUartOut (
+ IN UINT8 UartNumber,
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+);
+
+/*
+ Read data from serial device and save the datas in buffer.
+
+ If the buffer is NULL, then return 0;
+ if NumberOfBytes is zero, then return 0.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+ @param[out] Buffer Point of data buffer which need to be writed.
+ @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
+ @param[in] WaitUntilBufferFull When TRUE, function waits until whole buffer is filled. When FALSE, function returns as soon as no new characters are available.
+
+ @retval Actual number of bytes raed from serial device.
+
+**/
+UINTN
+EFIAPI
+PchSerialIoUartIn (
+ IN UINT8 UartNumber,
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes,
+ IN BOOLEAN WaitUntilBufferFull
+);
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @param[in] UartNumber Selects Serial IO UART device (0-2)
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+PchSerialIoUartPoll (
+ IN UINT8 UartNumber
+ );
+
+
+#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_UART_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h new file mode 100644 index 0000000000..cdeeae5e6d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h @@ -0,0 +1,28 @@ +/** @file
+ Header file for SMM Control PEI Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_SMM_CONTROL_LIB_H_
+#define _PCH_SMM_CONTROL_LIB_H_
+
+/**
+ This function install PEI SMM Control PPI
+
+ @retval EFI_STATUS Results of the installation of the SMM Control PPI
+**/
+EFI_STATUS
+EFIAPI
+PchSmmControlInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h new file mode 100644 index 0000000000..f89e42a546 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h @@ -0,0 +1,113 @@ +/** @file
+ Library that contains common parts of WdtPei and WdtDxe. Not a standalone module.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_WDT_COMMON_LIB_H_
+#define _PCH_WDT_COMMON_LIB_H_
+
+extern UINT8 mAllowExpectedReset;
+
+/**
+ Reads LPC bridge to get Watchdog Timer address
+
+
+ @retval UINT32 Watchdog's address
+**/
+UINT32
+WdtGetAddress (
+ VOID
+ );
+
+/**
+ Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+ causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+ function was called too.
+
+ @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+ @retval EFI_SUCCESS if everything's OK
+ @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
+**/
+EFI_STATUS
+EFIAPI
+WdtReloadAndStart (
+ IN UINT32 TimeoutValue
+ );
+
+/**
+ Disables WDT timer.
+
+
+**/
+VOID
+EFIAPI
+WdtDisable (
+ VOID
+ );
+
+/**
+ Returns WDT failure status.
+
+
+ @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
+ @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
+**/
+UINT8
+EFIAPI
+WdtCheckStatus (
+ VOID
+ );
+
+/**
+ Normally, each reboot performed while watchdog runs is considered a failure.
+ This function allows platform to perform expected reboots with WDT running,
+ without being interpreted as failures.
+ In DXE phase, it is enough to call this function any time before reset.
+ In PEI phase, between calling this function and performing reset, ReloadAndStart()
+ must not be called.
+
+
+**/
+VOID
+EFIAPI
+WdtAllowKnownReset (
+ VOID
+ );
+
+/**
+ Returns information if WDT coverage for the duration of BIOS execution
+ was requested by an OS application
+
+
+ @retval TRUE if WDT was requested
+ @retval FALSE if WDT was not requested
+**/
+UINT8
+EFIAPI
+IsWdtRequired (
+ VOID
+ );
+
+/**
+ Returns WDT enabled/disabled status.
+
+
+ @retval TRUE if WDT is enabled
+ @retval FALSE if WDT is disabled
+**/
+UINT8
+EFIAPI
+IsWdtEnabled (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h new file mode 100644 index 0000000000..ba9586a7a2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SecPchLib.h @@ -0,0 +1,27 @@ +/** @file
+ Header file for SEC PCH Lib.
+ All function in this library is available for SEC
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SEC_PCH_LIB_H_
+#define _SEC_PCH_LIB_H_
+
+/**
+ This function do the PCH cycle decoding initialization.
+**/
+VOID
+EFIAPI
+EarlyCycleDecoding (
+ VOID
+ );
+
+#endif // _SEC_PCH_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h new file mode 100644 index 0000000000..12dfaeb440 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h @@ -0,0 +1,104 @@ +/** @file
+ The header file includes the common header files, defines
+ internal structure and functions used by SpiFlashCommonLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SPI_FLASH_COMMON_LIB_H__
+#define __SPI_FLASH_COMMON_LIB_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h new file mode 100644 index 0000000000..23cb544d67 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/TraceHubInitLib.h @@ -0,0 +1,49 @@ +/** @file
+ Header file for TraceHub Init Lib.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _TRACE_HUB_INIT_LIB_H_
+#define _TRACE_HUB_INIT_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <PchAccess.h>
+
+///
+/// The PCH_TRACE_HUB_ENABLE_MODE describes the desired TraceHub mode of operation
+///
+typedef enum {
+ TraceHubModeDisabled = 0, ///< Pch TraceHub Disabled
+ TraceHubModeHostDebugger = 2, ///< Pch TraceHub External Debugger Present
+ TraceHubModeMax
+} TRACE_HUB_ENABLE_MODE;
+
+/**
+ This function performs basic initialization for TraceHub
+ This routine will consume address range 0xFE0C0000 - 0xFE3FFFFF for BARs usage.
+ Although controller allows access to a 64bit address resource, PEI phase is a 32bit env,
+ addresses greater than 4G is not allowed by CPU address space.
+ So, the addresses must be limited to below 4G and UBARs should be set to 0.
+ If this routine is called by platform code, it is expected EnableMode is passed in as PchTraceHubModeDisabled,
+ relying on the Intel TH debugger to enable it through the "cratchpad0 bit [24]".
+ By this practice, it gives the validation team the capability to use single debug BIOS
+ to validate the early trace functionality and code path that enable/disable Intel TH using BIOS policy.
+
+ @param[in] EnableMode Trace Hub Enable Mode
+**/
+VOID
+TraceHubInitialize (
+ IN UINT8 EnableMode
+ );
+
+#endif // _TRACE_HUB_INIT_LIB_H_
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