diff options
| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-06-19 10:55:06 +0800 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-06-20 15:12:29 +0800 |
| commit | 646b243c0e3ef49b98071ca2c3fec15299b4d72f (patch) | |
| tree | 00d62812fcedd3d1bf49692b863bb48a826f3ab0 /Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c | |
| parent | f98787b719524d7ba9f2cefac0e8c8b8698cb02c (diff) | |
| download | edk2-platforms-646b243c0e3ef49b98071ca2c3fec15299b4d72f.tar.xz | |
Add KabylakeSiliconPkg
reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com>
reviewed-by: Amy Chan <amy.chan@intel.com>
reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c')
| -rw-r--r-- | Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c new file mode 100644 index 0000000000..277923bdcc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c @@ -0,0 +1,146 @@ +/** @file
+ PCH Gbe Library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MmPciLib.h>
+#include <PchAccess.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchCycleDecodingLib.h>
+
+/**
+ Check whether GbE region is valid
+ Check SPI region directly since GbE might be disabled in SW.
+
+ @retval TRUE Gbe Region is valid
+ @retval FALSE Gbe Region is invalid
+**/
+BOOLEAN
+PchIsGbeRegionValid (
+ VOID
+ )
+{
+ UINT32 SpiBar;
+ SpiBar = MmioRead32 (MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SPI,
+ PCI_FUNCTION_NUMBER_PCH_SPI)
+ + R_PCH_SPI_BAR0) & ~B_PCH_SPI_BAR0_MASK;
+ ASSERT (SpiBar != 0);
+ if (MmioRead32 (SpiBar + R_PCH_SPI_FREG3_GBE) != B_PCH_SPI_FREGX_BASE_MASK) {
+ return TRUE;
+ }
+ return FALSE;
+}
+
+/**
+ Returns GbE over PCIe port number based on a soft strap.
+
+ @return Root port number (1-based)
+ @retval 0 GbE over PCIe disabled
+**/
+UINT32
+PchGetGbePortNumber (
+ VOID
+ )
+{
+ UINT32 GbePortSel;
+ UINT32 PcieStrapFuse;
+
+ PchPcrRead32 (PID_FIA, R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE, &PcieStrapFuse);
+ if ((PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN) == 0) {
+ return 0; // GbE disabled
+ }
+ GbePortSel = (PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL) >> N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL;
+ if (GetPchSeries () == PchLp) {
+ switch (GbePortSel) {
+ case 0: return 3;
+ case 1: return 4;
+ case 2: return 5;
+ case 3: return 9;
+ case 4: return 10;
+ }
+ } else {
+ switch (GbePortSel) {
+ case 0: return 4;
+ case 1: return 5;
+ case 2: return 9;
+ case 3: return 12;
+ case 4: return 13;
+ }
+ }
+ DEBUG ((DEBUG_ERROR, "Invalid GbE port\n"));
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Check whether LAN controller is enabled in the platform.
+
+ @retval TRUE GbE is enabled
+ @retval FALSE GbE is disabled
+**/
+BOOLEAN
+PchIsGbePresent (
+ VOID
+ )
+{
+ UINT32 PwrmBase;
+ UINT32 FuseDis2State;
+ //
+ // Check PMC strap/fuse
+ //
+ PchPwrmBaseGet (&PwrmBase);
+ FuseDis2State = MmioRead32 (PwrmBase + R_PCH_PWRM_FUSE_DIS_RD_2);
+ if (FuseDis2State & B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS) {
+ return FALSE;
+ }
+ //
+ // Check FIA strap/fuse
+ //
+ if (PchGetGbePortNumber () == 0) {
+ return FALSE;
+ }
+ //
+ // Check GbE NVM
+ //
+ if (PchIsGbeRegionValid () == FALSE) {
+ return FALSE;
+ }
+ return TRUE;
+}
+
+/**
+ Check whether LAN controller is enabled in the platform.
+
+ @deprecated Use PchIsGbePresent instead.
+
+ @retval TRUE GbE is enabled
+ @retval FALSE GbE is disabled
+**/
+BOOLEAN
+PchIsGbeAvailable (
+ VOID
+ )
+{
+ return PchIsGbePresent ();
+}
+
+
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