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author | Jiewen Yao <jiewen.yao@intel.com> | 2018-03-17 07:40:05 +0800 |
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committer | Jiewen Yao <jiewen.yao@intel.com> | 2018-03-17 07:40:05 +0800 |
commit | 0c4229f0c041ae2f5990b9fce1bbf8e1bb842845 (patch) | |
tree | 7bf159632a596abf8a11c5b2fbffb1ffea3b36f6 /Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h | |
parent | 923863e826faf98bf5755be50c533b2ea80f4a38 (diff) | |
download | edk2-platforms-0c4229f0c041ae2f5990b9fce1bbf8e1bb842845.tar.xz |
LewisBurgPkg: Initial version.
Cc: Isaac W Oram <isaac.w.oram@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
Diffstat (limited to 'Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h')
-rw-r--r-- | Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h new file mode 100644 index 0000000000..a3dd6ed148 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h @@ -0,0 +1,30 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// +#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register +#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock +#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable +#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control +#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register +#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable +#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable +#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable +#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable + +#endif |