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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-08 15:13:24 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-15 20:32:18 +0000 |
| commit | ca11ac71980cdb4c1bd3b4c2c6549b90fc47b4cc (patch) | |
| tree | 73dce23ff2357d079ffd4600254aca0c8f18738c /Silicon/Marvell | |
| parent | f8acbb73fae68638ae57afd776802728b99a5901 (diff) | |
| download | edk2-platforms-ca11ac71980cdb4c1bd3b4c2c6549b90fc47b4cc.tar.xz | |
Silicon/SynQuacer: add cache topology information to device tree
Add a DT description of the size and geometry of the various levels
of caches that are present in the SynQuacer SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Marvell')
0 files changed, 0 insertions, 0 deletions