diff options
| author | Masahisa KOJIMA <kojima.masahisa@socionext.com> | 2017-12-11 18:27:57 +0900 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-12 18:36:31 +0000 |
| commit | 676116c33577bde05d8141983e60af5dca682d1a (patch) | |
| tree | 86a2a99f1ddc78aebe1d5d061c16c30a0ce8ffff /Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | |
| parent | ace0059c18862e7fd2d02e48db38ab23edfd5342 (diff) | |
| download | edk2-platforms-676116c33577bde05d8141983e60af5dca682d1a.tar.xz | |
Silicon/Socionext/SynQuacer: add UART #0 node to DT
In order to be able to use UART #0 on the DeveloperBox's 96boards low
speed connector, expose it to the OS by adding a node to the device
tree. This requires a CM3 firmware build that makes the SCP detach
from the serial port after boot.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Masahisa KOJIMA <kojima.masahisa@socionext.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index c9fee5d1f3..37a3981f03 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -440,6 +440,15 @@ clock-names = "uartclk", "apb_pclk";
};
+ fuart: fuart@51040000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x51040000 0x0 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ };
+
clk_netsec: refclk125mhz {
compatible = "fixed-clock";
clock-frequency = <125000000>;
|