diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-16 12:57:04 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-26 19:05:05 +0200 |
| commit | 6c816b0e41758c4a75d0367afa7324bddf8151df (patch) | |
| tree | 18e72f2a8fb7bd9908f553aebf55c81ce847be02 /Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | |
| parent | ed9be80fa9521edc2ef959d493904d4800e64ca1 (diff) | |
| download | edk2-platforms-6c816b0e41758c4a75d0367afa7324bddf8151df.tar.xz | |
Silicon/Socionext/SynQuacer: update PHY reference clock rate
As reported by Kojima-san, the PHY reference clock value we use in our
ACPI and DT descriptions is out of sync with the hardware. Replace
125 MHz with 250 MHz throughout.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 6e93c6ae16..f6887329f6 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -420,9 +420,9 @@ reg-shift = <2>;
};
- clk_netsec: refclk125mhz {
+ clk_netsec: refclk250mhz {
compatible = "fixed-clock";
- clock-frequency = <125000000>;
+ clock-frequency = <250000000>;
#clock-cells = <0>;
};
|