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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2018-01-27 17:40:46 +0000
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2018-01-29 16:06:53 +0000
commit265bb85cdfb8d9f43fa9a112bfb549bb6ad68123 (patch)
treeddd5bbe8ffe5cba5d9c4f31dc9f39bd6508e0fc2 /Silicon/Socionext/SynQuacer/Drivers
parente26d421e1108a80d772e00b0c27b4a516982fb0e (diff)
downloadedk2-platforms-265bb85cdfb8d9f43fa9a112bfb549bb6ad68123.tar.xz
Silicon/SynQuacer: set CNTFRQ field of MMIO timer frame
Even though the ARM ARM quite clearly states that the CNTFRQ field of each MMIO timer frame should be a read-only alias of the CNTFRQ field of the base frame, the SynQuacer SoC implements it as a register that is programmable separately. So let's program it from the hardware rather than overriding the frequency using a DT property. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Drivers')
-rw-r--r--Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c18
-rw-r--r--Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h1
-rw-r--r--Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf2
3 files changed, 21 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
index b60607d058..b9394aa19f 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
@@ -174,6 +174,23 @@ SmmuEnableCoherentDma (
SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB);
}
+#define MMIO_TIMER_CNTFRQ_OFFSET 0x10
+
+STATIC
+VOID
+SetMmioTimerFrequency (
+ VOID
+ )
+{
+ //
+ // Initialize the CNTFRQ field of the first non-secure MMIO timer frame.
+ // This field should be a read-only alias of the global frequency register
+ // but in reality, it is a separate field that needs to be set explicitly.
+ //
+ MmioWrite32 (SYNQUACER_MMIO_TIMER_CNT_BASE0 + MMIO_TIMER_CNTFRQ_OFFSET,
+ ArmGenericTimerGetTimerFreq ());
+}
+
STATIC
EFI_STATUS
InstallHiiPages (
@@ -297,6 +314,7 @@ PlatformDxeEntryPoint (
ASSERT_EFI_ERROR (Status);
SmmuEnableCoherentDma ();
+ SetMmioTimerFrequency ();
Status = RegisterPcieNotifier ();
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h
index 53898b5828..5fb1437757 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h
@@ -18,6 +18,7 @@
#include <PiDxe.h>
#include <Guid/SynQuacerPlatformFormSet.h>
#include <IndustryStandard/Pci.h>
+#include <Library/ArmGenericTimerCounterLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
index de21ba33df..40e42a4d18 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf
@@ -29,6 +29,7 @@
PlatformDxeHii.vfr
[Packages]
+ ArmPkg/ArmPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
@@ -37,6 +38,7 @@
Silicon/Socionext/SynQuacer/SynQuacer.dec
[LibraryClasses]
+ ArmGenericTimerCounterLib
BaseMemoryLib
DebugLib
DevicePathLib