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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-08-24 15:37:47 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-16 17:30:57 +0000 |
| commit | 1f47a73e184b4514cbc5c099fec1bd564e394db4 (patch) | |
| tree | 465ae5b0af3e8f883a8571148f767fcb83cbe04d /Silicon/Socionext/SynQuacer/Include | |
| parent | bf109f8b87077a8f8215c9f0af8c9639d50cc64c (diff) | |
| download | edk2-platforms-1f47a73e184b4514cbc5c099fec1bd564e394db4.tar.xz | |
Silicon/SynQuacer: add package with platform headers
Add a package .DEC description for SynQuacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Include')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 60 | ||||
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 63 |
2 files changed, 123 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h new file mode 100644 index 0000000000..f29a35809b --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -0,0 +1,60 @@ +/** @file
+ Physical memory map for SynQuacer
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_MEMORYMAP_H_
+#define _SYNQUACER_PLATFORM_MEMORYMAP_H_
+
+// Memory mapped SPI NOR
+#define SYNQUACER_SPI_NOR_BASE 0x08000000
+#define SYNQUACER_SPI_NOR_SIZE SIZE_128MB
+
+// On-Chip non-secure ROM
+#define SYNQUACER_NON_SECURE_ROM_BASE 0x1F000000
+#define SYNQUACER_NON_SECURE_ROM_SZ SIZE_512KB
+
+// On-Chip Peripherals
+#define SYNQUACER_PERIPHERALS_BASE 0x20000000
+#define SYNQUACER_PERIPHERALS_SZ 0x0E000000
+
+// On-Chip non-secure SRAM
+#define SYNQUACER_NON_SECURE_SRAM_BASE 0x2E000000
+#define SYNQUACER_NON_SECURE_SRAM_SZ SIZE_64KB
+
+// GIC-500
+#define SYNQUACER_GIC500_DIST_BASE FixedPcdGet64 (PcdGicDistributorBase)
+#define SYNQUACER_GIC500_DIST_SIZE SIZE_256KB
+#define SYNQUACER_GIC500_RDIST_BASE FixedPcdGet64 (PcdGicRedistributorsBase)
+#define SYNQUACER_GIC500_RDIST_SIZE SIZE_8MB
+
+// GPIO block
+#define SYNQUACER_GPIO_BASE 0x51000000
+#define SYNQUACER_GPIO_SIZE SIZE_4KB
+
+// eMMC(SDH30)
+#define SYNQUACER_EMMC_BASE 0x52300000
+#define SYNQUACER_EMMC_BASE_SZ SIZE_4KB
+
+#define SYNQUACER_EEPROM_BASE 0x10000000
+#define SYNQUACER_EEPROM_BASE_SZ SIZE_64KB
+
+// NETSEC
+#define SYNQUACER_NETSEC1_BASE 0x522D0000
+#define SYNQUACER_NETSEC1_BASE_SZ SIZE_64KB
+
+// PCI
+#define SYNQUACER_PCIE_BASE 0x58200000
+#define SYNQUACER_PCIE_SIZE 0x00200000
+
+#endif
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h new file mode 100644 index 0000000000..d2a3f9acbf --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -0,0 +1,63 @@ +/** @file
+ PCI memory configuration for SynQuacer
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SYNQUACER_PLATFORM_PCI_H_
+#define _SYNQUACER_PLATFORM_PCI_H_
+
+#define SYNQUACER_PCI_SEG0_CONFIG_BASE 0x60000000
+#define SYNQUACER_PCI_SEG0_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG0_DBI_BASE 0x583d0000
+#define SYNQUACER_PCI_SEG0_EXS_BASE 0x58390000
+
+#define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0
+#define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e
+
+#define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0
+#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff
+#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000
+#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000
+#define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff
+#define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000
+
+#define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000
+#define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff
+#define SYNQUACER_PCI_SEG0_MMIO64_SIZE 0x100000000
+
+#define SYNQUACER_PCI_SEG1_CONFIG_BASE 0x70000000
+#define SYNQUACER_PCI_SEG1_CONFIG_SIZE 0x07f00000
+#define SYNQUACER_PCI_SEG1_DBI_BASE 0x583c0000
+#define SYNQUACER_PCI_SEG1_EXS_BASE 0x58380000
+
+#define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0
+#define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e
+
+#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000
+#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff
+#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000
+#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE
+
+#define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000
+#define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff
+#define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000
+
+#define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000
+#define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff
+#define SYNQUACER_PCI_SEG1_MMIO64_SIZE 0x100000000
+
+#endif
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