diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-04 14:17:51 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-17 17:46:06 +0000 |
| commit | f8f11924f454b0ee519de05d92d0c7881a478bbe (patch) | |
| tree | 5d10d82cb0077f6568c35491898c5c767f7fb51d /Silicon/Socionext/SynQuacer/Library | |
| parent | fca178afd6a44ce0a8c2c7f2e4a2bded78ce6134 (diff) | |
| download | edk2-platforms-f8f11924f454b0ee519de05d92d0c7881a478bbe.tar.xz | |
Silicon/SynQuacerPciHostBridgeLib: add workaround to support 32-bit only cards
Implement workaround suggested by Socionext to get legacy endpoints
with 32-bit BARs working. This fixes the issue on Developer Box with
the onboard ASM1061 SATA controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Library')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index b5bfea8e0e..1bbef5b6cf 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -32,10 +32,13 @@ #define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH BIT12
#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_CFG_SHIFT_MODE BIT28
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT 0xF
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_64BIT 0xFF
#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
@@ -297,8 +300,9 @@ PciInitController ( RootBridge->Mem.Base,
RootBridge->Mem.Base,
RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
- IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
- 0);
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT);
// Region 1: Type 0 config space
ConfigureWindow (DbiBase, 1,
|