diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-29 18:36:21 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-30 17:38:34 +0000 |
| commit | b490ebc08f2a8c3b95b5fd22f142badc72925358 (patch) | |
| tree | b10ab4622f8e46b6f211e309bf519ad88a90a819 /Silicon/Socionext/SynQuacer | |
| parent | 7a74db8e88ca6926599a7bf60cd8ef92f260388e (diff) | |
| download | edk2-platforms-b490ebc08f2a8c3b95b5fd22f142badc72925358.tar.xz | |
Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed
As it turns out, getting the PCIe controllers to switch to Gen2 speed
is surprisingly easy. It only involves setting the 'speed change' bit
in the controller at initialization time, after which the hardware
will automatically attempt to switch to Gen2 speed after training at
Gen1 speed has completed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 6b42d3e298..e63b3a4bb2 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -113,6 +113,9 @@ #define PROGRAM_INTERFACE 0x0000FF00
#define PROGRAM_INTERFACE_VALUE 0x00
+#define GEN2_CONTROL_OFF 0x80c
+#define DIRECT_SPEED_CHANGE BIT17
+
#define MISC_CONTROL_1_OFF 0x8BC
#define DBI_RO_WR_EN BIT0
@@ -295,6 +298,9 @@ PciInitController ( EFI_PCI_COMMAND_MEMORY_SPACE |
EFI_PCI_COMMAND_BUS_MASTER);
+ // Force link speed change to Gen2 at link up
+ MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
+
// Region 0: MMIO32 range
ConfigureWindow (DbiBase, 0,
RootBridge->Mem.Base,
|