diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-27 21:24:34 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-17 18:48:12 +0000 |
| commit | 0cac7372c16c7d6755060a6264257f856f7fcf09 (patch) | |
| tree | 6ecb9c433418ffe026cd07fa66cf629a2b6a0822 /Silicon/Socionext | |
| parent | 92093e026f61bc45bddc612c14ceaede404cfdbf (diff) | |
| download | edk2-platforms-0cac7372c16c7d6755060a6264257f856f7fcf09.tar.xz | |
Silicon/SynQuacer: add description of GPIO block to device tree
Add a description of the SoCs GPIO controller as well as a description
of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
evaluation board as well as the Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext')
3 files changed, 34 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 9e0acd5933..6ae7d5f300 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -19,3 +19,14 @@ model = "Socionext Developer Box";
compatible = "socionext,developer-box", "socionext,synquacer";
};
+
+&gpio {
+ gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4",
+ "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8",
+ "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B",
+ "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT",
+ "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F",
+ "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
+ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27",
+ "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31";
+};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index f89e722219..966952b9a2 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -21,6 +21,9 @@ #define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -511,4 +514,13 @@ msi-map = <0x0 &its 0x10000 0x7f00>;
dma-coherent;
};
+
+ gpio: gpio@51000000 {
+ compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
+ reg = <0x0 0x51000000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clk_apb>;
+ base = <0>;
+ };
};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index cda72fdf2f..7de7db182b 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -19,3 +19,14 @@ model = "SynQuacer Evaluation Board";
compatible = "socionext,synquacer-eval-board", "socionext,synquacer";
};
+
+&gpio {
+ gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4",
+ "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8",
+ "PEC-PD8", "PEC-PD9", "PEC-PD10", "PEC-PD11",
+ "NC", "NC", "PCIE1EXTINT", "PCIE0EXTINT",
+ "PHY_P2_2", "PHY_P1_2", "NC", "NC",
+ "NC", "NC", "NC", "NC",
+ "NC", "NC", "PEC-PD26", "PEC-PD27",
+ "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31";
+};
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