diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-01 13:23:01 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-11-25 22:25:11 +0000 |
| commit | 71096fc4a8a98d555ff709d628dcbbd9c99c5d96 (patch) | |
| tree | c0bcebacb03f0f4fca7f2b8d1dc98861bfd69998 /Silicon/Socionext | |
| parent | 563c2efbfa0580f4a1efee368cfc77d27bf33a1f (diff) | |
| download | edk2-platforms-71096fc4a8a98d555ff709d628dcbbd9c99c5d96.tar.xz | |
Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch
Ordinary computers typically have a physical switch or jumper on the
board that allows non-volatile settings to be cleared. Let's implement
the same using DIP switch #1 on block #3, and clear the EFI variable
store if it is set to ON at boot time.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext')
3 files changed, 38 insertions, 1 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c index 358dd5a91f..e4aec8b091 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c @@ -21,8 +21,11 @@ #include <Library/PeiServicesLib.h>
#include <Platform/DramInfo.h>
#include <Ppi/DramInfo.h>
+#include <Ppi/EmbeddedGpio.h>
#include <Ppi/MemoryDiscovered.h>
+#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED MAX_UINT8
+
STATIC
CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase);
@@ -103,10 +106,35 @@ PlatformPeim ( VOID
)
{
- EFI_STATUS Status;
+ EMBEDDED_GPIO_PPI *Gpio;
+ EFI_STATUS Status;
+ UINTN Value;
+ UINT8 Pin;
ASSERT (mDramInfo->NumRegions > 0);
+ Pin = FixedPcdGet8 (PcdClearSettingsGpioPin);
+ if (Pin != CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) {
+ Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL,
+ (VOID **)&Gpio);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n",
+ __FUNCTION__, Status));
+ } else {
+ Status = Gpio->Get (Gpio, Pin, &Value);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n",
+ __FUNCTION__, Status));
+ } else if (Value > 0) {
+ DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__));
+ PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS);
+ }
+ }
+ }
+
//
// Record the first region into PcdSystemMemoryBase and PcdSystemMemorySize.
// This is the region we will use for UEFI itself.
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf index 70eb715d44..a6501fb205 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf @@ -25,6 +25,7 @@ [Packages]
ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Socionext/SynQuacer/SynQuacer.dec
@@ -40,11 +41,16 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
+ gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin
gSynQuacerTokenSpaceGuid.PcdDramInfoBase
[Ppis]
+ gEdkiiEmbeddedGpioPpiGuid ## CONSUMES
gSynQuacerDramInfoPpiGuid ## PRODUCES
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
+
+[Depex]
+ gEdkiiEmbeddedGpioPpiGuid
diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 1a683b8152..4e5ccea6a4 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -30,3 +30,6 @@ gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase|0|UINT32|0x00000002
gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress|0|UINT8|0x00000003
+
+ # GPIO pin index [0 .. 31] or MAX_UINT8 for not implemented
+ gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004
|