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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2017-12-07 13:34:49 +0000
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2017-12-07 13:36:01 +0000
commitce95ec196da05885844afb79bd2570c5cd9f6b27 (patch)
tree7d1a2553bb54a57a7129a2576f343fe78e0d42c2 /Silicon/Socionext
parent23488946946f9cfb6296b4cf591ef6b86498921f (diff)
downloadedk2-platforms-ce95ec196da05885844afb79bd2570c5cd9f6b27.tar.xz
Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC
As it turns out, it is surprisingly easy to configure both the NETSEC and eMMC devices as cache coherent for DMA, given that they are both behind the same SMMU which is already configured in passthrough mode by the firmware running on the SCP. So update the static SMMU configuration to make memory accesses performed by these devices inner shareable inner/outer writeback cacheable, which makes them cache coherent with the CPUs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext')
-rw-r--r--Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi2
-rw-r--r--Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c23
-rw-r--r--Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h4
-rw-r--r--Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c3
4 files changed, 32 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 5e663c59ef..ec784c70af 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -456,6 +456,7 @@
max-speed = <1000>;
max-frame-size = <9000>;
phy-handle = <&ethphy0>;
+ dma-coherent;
#address-cells = <1>;
#size-cells = <0>;
@@ -557,6 +558,7 @@
fujitsu,cmd-dat-delay-select;
clocks = <&clk_alw_c_0 &clk_alw_b_0>;
clock-names = "core", "iface";
+ dma-coherent;
status = "disabled";
};
};
diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
index 070e6be92e..6432891312 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
+++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c
@@ -130,6 +130,27 @@ FreeDevice:
return Status;
}
+#define SMMU_SCR0 0x0
+#define SMMU_SCR0_SHCFG_INNER (0x2 << 22)
+#define SMMU_SCR0_MTCFG (0x1 << 20)
+#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16)
+
+STATIC
+VOID
+SmmuEnableCoherentDma (
+ VOID
+ )
+{
+ //
+ // The SCB SMMU (MMU-500) is shared between the NETSEC and eMMC devices, and
+ // is configured in passthrough mode by default. Let's set the global memory
+ // type override as well, so that all memory accesses by these devices are
+ // inner shareable inner/outer writeback cacheable.
+ //
+ MmioOr32 (SYNQUACER_SCB_SMMU_BASE + SMMU_SCR0,
+ SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB);
+}
+
EFI_STATUS
EFIAPI
PlatformDxeEntryPoint (
@@ -178,5 +199,7 @@ PlatformDxeEntryPoint (
&Handle);
ASSERT_EFI_ERROR (Status);
+ SmmuEnableCoherentDma ();
+
return EFI_SUCCESS;
}
diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
index 3c7bd58866..f43adcc860 100644
--- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
+++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h
@@ -65,4 +65,8 @@
#define SYNQUACER_PCIE_BASE 0x58200000
#define SYNQUACER_PCIE_SIZE 0x00200000
+// SCB SMMU
+#define SYNQUACER_SCB_SMMU_BASE 0x52E00000
+#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB
+
#endif
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index a640b3e0c0..1402ecafce 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -115,6 +115,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)),
ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase),
FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)),
+
+ // NETSEC/eMMC SMMU
+ ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE),
};
STATIC