diff options
| author | gongchengya <gongchengya1@huawei.com> | 2018-03-07 14:55:46 +0800 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-07 16:04:47 +0000 |
| commit | f1f2f212550c79f2e3fb615da183d570b016abfa (patch) | |
| tree | b2065f92db841695d83bb6ee305db94b987d137f /Silicon | |
| parent | 09a7b9d58bd2132f59f7f4ab1c54616e5826981f (diff) | |
| download | edk2-platforms-f1f2f212550c79f2e3fb615da183d570b016abfa.tar.xz | |
Hisilicon: disable GICv3 legacy mode
Hi1616 GIC does not fully support GICv2 legacy mode, and SBSA watchdog
interrupts 400 and 496 cannot be signaled to CPU, so we switch to pure
GICv3 mode.
For other Hisilicon platforms, we suppose they don't need V2 legacy
mode either if they have GICv3. D03 also works for this patch. If the
platforms only have GICv2, this change will have no impact on them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: gongchengya <gongchengya1@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'Silicon')
| -rw-r--r-- | Silicon/Hisilicon/Hisilicon.dsc.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc index b196322a20..f8d5f0b270 100644 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc @@ -249,7 +249,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
- gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|TRUE
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
[PcdsFixedAtBuild.common]
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44
|