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| author | Yao, Jiewen <jiewen.yao@intel.com> | 2015-11-30 19:57:40 +0000 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2016-02-25 09:13:23 +0800 |
| commit | cd5e29959f602cddd8e4b42b207f2101b6e92e89 (patch) | |
| tree | 090c2ab6c4b3438828354d518dc863a646c599c0 /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | |
| parent | b2c7f09d779b252b6cd4fa48cd42aea203522bf4 (diff) | |
| download | edk2-platforms-cd5e29959f602cddd8e4b42b207f2101b6e92e89.tar.xz | |
UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default
So that we can use write-protection for code later.
This is REPOST.
It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>:
Title: fix generation of 32-bit PAE page tables
"Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table
Entries (PDPTEs); see Table 4-8 in the SDM. With VMX extended page
tables, the processor notices and fails the VM entry as soon as CR0.PG
is set to 1."
And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit 881520ea6778953c57d975ca2a9cf3f2114f99c4)
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c')
0 files changed, 0 insertions, 0 deletions