diff options
| author | Jeff Fan <jeff.fan@intel.com> | 2016-07-29 21:13:34 +0800 |
|---|---|---|
| committer | Jeff Fan <jeff.fan@intel.com> | 2016-08-17 19:58:48 +0800 |
| commit | 5c66d125eaae51945c0a14ef6d5d3fa2ce7d7a66 (patch) | |
| tree | 9f4f0a5a3c55f86a09c38db14985ae74f345c89a /UefiCpuPkg | |
| parent | 8396e2dd30bf6f9057d3cd5fa1d26f023341f0a0 (diff) | |
| download | edk2-platforms-5c66d125eaae51945c0a14ef6d5d3fa2ce7d7a66.tar.xz | |
UefiCpuPkg/MpInitLib: Add EnableExecuteDisable in MP_CPU_EXCHANGE_INFO
EnableExecuteDisable in MP_CPU_EXCHANGE_INFO is used to tell AP reset vector if
enable execute disable feature on APs. This feature should be enabled before CR3
is written.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm | 30 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 4 | ||||
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 13 |
5 files changed, 49 insertions, 1 deletions
diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc b/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc index 015396af80..60add860d1 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc @@ -36,4 +36,6 @@ ModeOffsetLocation equ LockLocation + 20h NumApsExecutingLocation equ LockLocation + 24h
CodeSegmentLocation equ LockLocation + 28h
DataSegmentLocation equ LockLocation + 2Ch
+EnableExecuteDisableLocation equ LockLocation + 30h
+Cr3Location equ LockLocation + 3Ch
diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm index 7050413c5a..8bacb42836 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -85,6 +85,36 @@ Flat32Start: ; protected mode entry point mov ss, dx
mov esi, ebx
+
+ mov edi, esi
+ add edi, EnableExecuteDisableLocation
+ cmp byte [edi], 0
+ jz SkipEnableExecuteDisable
+
+ ;
+ ; Enable IA32 PAE execute disable
+ ;
+
+ mov ecx, 0xc0000080
+ rdmsr
+ bts eax, 11
+ wrmsr
+
+ mov edi, esi
+ add edi, Cr3Location
+ mov eax, dword [edi]
+ mov cr3, eax
+
+ mov eax, cr4
+ bts eax, 5
+ mov cr4, eax
+
+ mov eax, cr0
+ bts eax, 31
+ mov cr0, eax
+
+SkipEnableExecuteDisable:
+
mov edi, esi
add edi, LockLocation
mov eax, NotVacantFlag
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 92d1dd9f6a..28a3cd4b82 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -55,6 +55,7 @@ typedef struct { UINTN NumApsExecuting;
UINTN CodeSegment;
UINTN DataSegment;
+ UINTN EnableExecuteDisable;
UINTN Cr3;
} MP_CPU_EXCHANGE_INFO;
diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc index 5aac212449..d533741f0e 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc @@ -36,6 +36,8 @@ ModeOffsetLocation equ LockLocation + 3Ch NumApsExecutingLocation equ LockLocation + 44h
CodeSegmentLocation equ LockLocation + 4Ch
DataSegmentLocation equ LockLocation + 54h
-Cr3Location equ LockLocation + 5Ch
+EnableExecuteDisableLocation equ LockLocation + 5Ch
+Cr3Location equ LockLocation + 64h
+
;-------------------------------------------------------------------------------
diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm index 848992ca44..3c55ffaafe 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -69,6 +69,19 @@ o32 lgdt [cs:si] mov si, IdtrLocation
o32 lidt [cs:si]
+ mov si, EnableExecuteDisableLocation
+ cmp byte [si], 0
+ jz SkipEnableExecuteDisableBit
+
+ ;
+ ; Enable execute disable bit
+ ;
+ mov ecx, 0c0000080h ; EFER MSR number
+ rdmsr ; Read EFER
+ bts eax, 11 ; Enable Execute Disable Bit
+ wrmsr ; Write EFER
+
+SkipEnableExecuteDisableBit:
mov di, DataSegmentLocation
mov edi, [di] ; Save long mode DS in edi
|