diff options
| author | vanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-08-23 01:42:01 +0000 |
|---|---|---|
| committer | vanjeff <vanjeff@6f19259b-4bc3-4df7-8a09-765794883524> | 2012-08-23 01:42:01 +0000 |
| commit | a66e0c7da759ce41b2615529f9d69627e23e5b08 (patch) | |
| tree | 67518f23ede088e7c223a6de7b980c8b18303e98 /UefiCpuPkg | |
| parent | abef469fc1969f1142bf8add4275d573b4793e94 (diff) | |
| download | edk2-platforms-a66e0c7da759ce41b2615529f9d69627e23e5b08.tar.xz | |
1. Added SetLocalApicBaseAdress() and GetLocalApicBaseAddress() APIs in Local APIC library.
2. Updated Local APIC library instances to get Local APIC base Address by invoking GetLocalApicBaseAddress() instead of by PCD PcdCpuLocalApicBaseAddress.
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com>
Reviewed-by: Rui Sun <rui.sun@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13668 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg')
5 files changed, 132 insertions, 20 deletions
diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h index 52914fa9bd..ed847b9579 100644 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -4,7 +4,7 @@ Local APIC library assumes local APIC is enabled. It does not
handles cases where local APIC is disabled.
- Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -22,6 +22,32 @@ #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
/**
+ Retrieve the base address of local APIC.
+
+ @return The base address of local APIC.
+
+**/
+UINTN
+EFIAPI
+GetLocalApicBaseAddress (
+ VOID
+ );
+
+/**
+ Set the base address of local APIC.
+
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
+
+ @param[in] BaseAddress Local APIC base address to be set.
+
+**/
+VOID
+EFIAPI
+SetLocalApicBaseAddress (
+ IN UINTN BaseAddress
+ );
+
+/**
Get the current local APIC mode.
If local APIC is disabled, then ASSERT.
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c index 77c24deed0..53c1610810 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -3,7 +3,7 @@ This local APIC library instance supports xAPIC mode only.
- Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -21,13 +21,58 @@ #include <Library/LocalApicLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
-#include <Library/PcdLib.h>
//
// Library internal functions
//
/**
+ Retrieve the base address of local APIC.
+
+ @return The base address of local APIC.
+
+**/
+UINTN
+EFIAPI
+GetLocalApicBaseAddress (
+ VOID
+ )
+{
+ MSR_IA32_APIC_BASE ApicBaseMsr;
+
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
+}
+
+/**
+ Set the base address of local APIC.
+
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
+
+ @param[in] BaseAddress Local APIC base address to be set.
+
+**/
+VOID
+EFIAPI
+SetLocalApicBaseAddress (
+ IN UINTN BaseAddress
+ )
+{
+ MSR_IA32_APIC_BASE ApicBaseMsr;
+
+ ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
+
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+
+ ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+}
+
+/**
Read from a local APIC register.
This function reads from a local APIC register either in xAPIC or x2APIC mode.
@@ -49,7 +94,7 @@ ReadLocalApicReg ( ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
- return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
+ return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
}
/**
@@ -76,7 +121,7 @@ WriteLocalApicReg ( ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
+ MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
}
/**
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf index 470e02971d..5f0f0be1bb 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf @@ -3,7 +3,7 @@ #
# This library instance supports xAPIC mode only.
#
-# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -41,6 +41,3 @@ TimerLib
IoLib
-[Pcd]
- gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
-
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 62201cd240..48468e8bc9 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports x2APIC capable processors
which have xAPIC and x2APIC modes.
- Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -22,13 +22,58 @@ #include <Library/LocalApicLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
-#include <Library/PcdLib.h>
//
// Library internal functions
//
/**
+ Retrieve the base address of local APIC.
+
+ @return The base address of local APIC.
+
+**/
+UINTN
+EFIAPI
+GetLocalApicBaseAddress (
+ VOID
+ )
+{
+ MSR_IA32_APIC_BASE ApicBaseMsr;
+
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
+}
+
+/**
+ Set the base address of local APIC.
+
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
+
+ @param[in] BaseAddress Local APIC base address to be set.
+
+**/
+VOID
+EFIAPI
+SetLocalApicBaseAddress (
+ IN UINTN BaseAddress
+ )
+{
+ MSR_IA32_APIC_BASE ApicBaseMsr;
+
+ ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
+
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
+
+ ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
+}
+
+/**
Read from a local APIC register.
This function reads from a local APIC register either in xAPIC or x2APIC mode.
@@ -52,7 +97,7 @@ ReadLocalApicReg ( ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
- return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);
+ return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
} else {
//
// DFR is not supported in x2APIC mode.
@@ -95,7 +140,7 @@ WriteLocalApicReg ( ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);
+ MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
} else {
//
// DFR is not supported in x2APIC mode.
@@ -134,6 +179,7 @@ SendIpi ( {
UINT64 MsrValue;
LOCAL_APIC_ICR_LOW IcrLowReg;
+ UINTN LocalApciBaseAddress;
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
ASSERT (ApicId <= 0xff);
@@ -141,10 +187,11 @@ SendIpi ( //
// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
//
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET, IcrLow);
+ LocalApciBaseAddress = GetLocalApicBaseAddress();
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);
do {
- IcrLowReg.Uint32 = MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET);
+ IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);
} while (IcrLowReg.Bits.DeliveryStatus != 0);
} else {
//
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf index df2769c9ff..baece39a43 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf @@ -4,7 +4,7 @@ # This library instance supports x2APIC capable processors
# which have xAPIC and x2APIC modes.
#
-# Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -42,6 +42,3 @@ TimerLib
IoLib
-[Pcd]
- gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
-
|