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-rw-r--r--ArmPkg/Include/Chipset/AArch64Mmu.h6
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c3
2 files changed, 6 insertions, 3 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 2398ba2539..22e492d61d 100644
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -75,12 +75,14 @@
#define TT_AF BIT10
#define TT_PXN_MASK BIT53
-#define TT_UXN_MASK BIT54
+#define TT_UXN_MASK BIT54 // EL1&0
+#define TT_XN_MASK BIT54 // EL2 / EL3
#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
#define TT_TABLE_PXN BIT59
-#define TT_TABLE_XN BIT60
+#define TT_TABLE_UXN BIT60 // EL1&0
+#define TT_TABLE_XN BIT60 // EL2 / EL3
#define TT_TABLE_NS BIT63
#define TT_TABLE_AP_MASK (BIT62 | BIT61)
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index 3765d61ccd..d82c82c202 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -335,7 +335,8 @@ GetBlockEntryListFromAddress (
if (Attributes & TT_PXN_MASK) {
TableAttributes = TT_TABLE_PXN;
}
- if (Attributes & TT_UXN_MASK) {
+ // XN maps to UXN in the EL1&0 translation regime
+ if (Attributes & TT_XN_MASK) {
TableAttributes = TT_TABLE_XN;
}
if (Attributes & TT_NS) {