diff options
8 files changed, 53 insertions, 36 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c index 59246f80bc..ce1c6ce09a 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c @@ -1,7 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+ Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -131,11 +131,12 @@ InitializeExceptions ( FiqEnabled = ArmGetFiqState ();
ArmDisableFiq ();
- // AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
- //DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
- //ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ // The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure 'Align=4K'
+ // is defined into your FDF for this module.
+ ASSERT (((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
- // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
+ // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector
+ // Base Address to point into CpuDxe code.
ArmWriteVBar ((UINTN)ExceptionHandlersStart);
if (FiqEnabled) {
diff --git a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c index 6da648d990..9fbaeaf430 100644 --- a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c +++ b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c @@ -1,7 +1,7 @@ /** @file
* Main file supporting the SEC Phase for Versatile Express
*
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -283,9 +283,10 @@ InitializeDebugAgent ( EFI_FFS_FILE_HEADER *FfsHeader;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
- // Now we've got UART, make the check:
- // - The Vector table must be 32-byte aligned
- //Need to fix basetools ASSERT(((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ // Now we've got UART, check the Debug Agent Vector Table
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
+ // 'Align=4K' is defined into your FDF for this module.
+ ASSERT (((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)DebugAgentVectorTable);
// We use InitFlag to know if DebugAgent has been intialized from
diff --git a/ArmPlatformPkg/ArmPlatformPkg-2ndstage.fdf b/ArmPlatformPkg/ArmPlatformPkg-2ndstage.fdf index afc2fff48f..de6ad0bed3 100644 --- a/ArmPlatformPkg/ArmPlatformPkg-2ndstage.fdf +++ b/ArmPlatformPkg/ArmPlatformPkg-2ndstage.fdf @@ -1,13 +1,13 @@ #
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
@@ -184,11 +184,18 @@ READ_LOCK_STATUS = TRUE #
############################################################################
-[Rule.Common.SEC]
+[Rule.ARM.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
+# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
+# It is the reason 4K is used instead of 2K for the module alignment.
+[Rule.AARCH64.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
diff --git a/ArmPlatformPkg/ArmPlatformPkg.fdf b/ArmPlatformPkg/ArmPlatformPkg.fdf index d7355d7dca..0eda603ecd 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.fdf +++ b/ArmPlatformPkg/ArmPlatformPkg.fdf @@ -1,13 +1,13 @@ #
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
@@ -241,11 +241,18 @@ READ_LOCK_STATUS = TRUE #
############################################################################
-[Rule.Common.SEC]
+[Rule.ARM.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
+# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
+# It is the reason 4K is used instead of 2K for the module alignment.
+[Rule.AARCH64.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf index 97a7766483..a0316f73f8 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf @@ -1,5 +1,5 @@ #
-# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -267,7 +267,7 @@ READ_LOCK_STATUS = TRUE [Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf index 4e1c5a2aee..647f9b6bbe 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf @@ -1,5 +1,5 @@ #
-# Copyright (c) 2011, 2013, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -240,7 +240,7 @@ READ_LOCK_STATUS = TRUE [Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf index 83ceec4f63..b495a1b947 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf @@ -1,5 +1,5 @@ #
-# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -251,7 +251,7 @@ READ_LOCK_STATUS = TRUE [Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 1abefaefd2..f33f376cf1 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -1,7 +1,7 @@ /** @file
* Main file supporting the transition to PEI Core in Normal World for Versatile Express
*
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -86,8 +86,9 @@ CEntryPoint ( //
// Write VBAR - The Exception Vector table must be aligned to its requirement
- //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64
- //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
+ // 'Align=4K' is defined into your FDF for this module.
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)PeiVectorTable);
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
|