3 files changed, 122 insertions, 9 deletions
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index a54abc0772..5e143d3779 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -489,7 +489,8 @@
   Ipf/Synchronization.c
   Ipf/InterlockedCompareExchange64.s
   Ipf/InterlockedCompareExchange32.s
-  Ipf/CpuBreakpoint.c
+  Ipf/CpuBreakpoint.c    | INTEL
+  Ipf/CpuBreakpointMsc.c | MSFT
   Ipf/Unaligned.c
   Ipf/SwitchStack.s
   Ipf/longjmp.s
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
index 3dcbecf29d..59c7e40818 100644
--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
+++ b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
@@ -17,14 +17,6 @@
 //
 #include <BaseLibInternals.h>
 
-//void __mfa (void);
-
-#pragma intrinsic (_enable)
-#pragma intrinsic (_disable)
-#pragma intrinsic (__break)
-#pragma intrinsic (__mfa)
-
-
 /**
   Generates a breakpoint on the CPU.
 
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
new file mode 100644
index 0000000000..ed53e42b7b
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
@@ -0,0 +1,120 @@
+/** @file
+  Base Library CPU functions for Itanium
+
+  Copyright (c) 2006, Intel Corporation<BR>
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// Include common header file for this module.
+//
+#include <BaseLibInternals.h>
+
+#pragma intrinsic (_enable)
+#pragma intrinsic (_disable)
+#pragma intrinsic (__break)
+#pragma intrinsic (__mfa)
+
+/**
+  Generates a breakpoint on the CPU.
+
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such
+  that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+  VOID
+  )
+{
+  __break (0);
+}
+
+/**
+  Used to serialize load and store operations.
+
+  All loads and stores that proceed calls to this function are guaranteed to be
+  globally visible when this function returns.
+
+**/
+VOID
+EFIAPI
+MemoryFence (
+  VOID
+  )
+{
+  __mfa ();
+}
+
+/**
+  Disables CPU interrupts.
+
+  Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+  VOID
+  )
+{
+  _disable ();
+}
+
+/**
+  Enables CPU interrupts.
+
+  Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+  VOID
+  )
+{
+  _enable ();
+}
+
+/**
+  Enables CPU interrupts for the smallest window required to capture any
+  pending interrupts.
+
+  Enables CPU interrupts for the smallest window required to capture any
+  pending interrupts.
+
+**/
+VOID
+EFIAPI
+EnableDisableInterrupts (
+  VOID
+  )
+{
+  EnableInterrupts ();
+  DisableInterrupts ();
+}
+
+/**
+  Places the CPU in a sleep state until an interrupt is received.
+
+  Places the CPU in a sleep state until an interrupt is received. If interrupts
+  are disabled prior to calling this function, then the CPU will be placed in a
+  sleep state indefinitely.
+
+**/
+VOID
+EFIAPI
+CpuSleep (
+  VOID
+  )
+{
+  PalCallStatic (NULL, 29, 0, 0, 0);
+}