diff options
Diffstat (limited to 'ArmPkg/Drivers/CpuDxe')
-rw-r--r-- | ArmPkg/Drivers/CpuDxe/CpuDxe.h | 4 | ||||
-rw-r--r-- | ArmPkg/Drivers/CpuDxe/Mmu.c | 16 |
2 files changed, 10 insertions, 10 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index af2cdc60a5..e11d5d6bf4 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -111,8 +111,8 @@ CpuSetMemoryAttributes ( EFI_STATUS
InitializeExceptions (
- IN EFI_CPU_ARCH_PROTOCOL *Cpu
- );
+\s\sIN EFI_CPU_ARCH_PROTOCOL *Cpu
+\s\s);
EFI_STATUS
SyncCacheConfig (
diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c index d7ea0eb551..0b86b8bc98 100644 --- a/ArmPkg/Drivers/CpuDxe/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Mmu.c @@ -338,11 +338,11 @@ UpdatePageEntries ( // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
- // map to strongly ordered
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+\s\s\s\s // map to strongly ordered
+\s\s\s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- // map to normal non-cachable
- EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ \s\s // map to normal non-cachable
+ \s\s EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
@@ -486,11 +486,11 @@ UpdateSectionEntries ( // modify cacheability attributes
EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
if (FeaturePcdGet(PcdEfiUncachedMemoryToStronglyOrdered)) {
- // map to strongly ordered
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
+\s\s\s\s // map to strongly ordered
+\s\s\s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
} else {
- // map to normal non-cachable
- EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
+ \s\s // map to normal non-cachable
+ \s\s EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
}
break;
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