summaryrefslogtreecommitdiff
path: root/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
diff options
context:
space:
mode:
Diffstat (limited to 'ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c')
-rw-r--r--ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
index 6b94c41862..0f89801525 100644
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11LibMem.c
@@ -2,7 +2,7 @@
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
-
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -29,7 +29,7 @@ FillTranslationTable (
UINTN Index;
UINT32 Attributes;
UINT32 PhysicalBase = MemoryRegion->PhysicalBase;
-
+
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
@@ -53,10 +53,10 @@ FillTranslationTable (
Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
break;
}
-
+
Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
-
+
for (Index = 0; Index < Sections; Index++)
{
*Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
@@ -84,7 +84,7 @@ ArmConfigureMmu (
if (TranslationTableBase != NULL) {
*TranslationTableBase = TranslationTable;
}
-
+
if (TranslationTableBase != NULL) {
*TranslationTableSize = TRANSLATION_TABLE_SIZE;
}
@@ -109,7 +109,7 @@ ArmConfigureMmu (
}
ArmSetTTBR0(TranslationTable);
-
+
ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
DOMAIN_ACCESS_CONTROL_NONE(14) |
DOMAIN_ACCESS_CONTROL_NONE(13) |
@@ -126,7 +126,7 @@ ArmConfigureMmu (
DOMAIN_ACCESS_CONTROL_NONE( 2) |
DOMAIN_ACCESS_CONTROL_NONE( 1) |
DOMAIN_ACCESS_CONTROL_MANAGER(0));
-
+
ArmEnableInstructionCache();
ArmEnableDataCache();
ArmEnableMmu();