diff options
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm | 22 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S | 2 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm | 2 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 12 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 12 |
5 files changed, 25 insertions, 25 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm index 7099ced8f4..831532f4d2 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm @@ -70,17 +70,17 @@ ArmDisableAsynchronousAbort ArmEnableIrq cpsie i isb - bx LR +\s\sbx LR ArmDisableIrq cpsid i isb - bx LR +\s\sbx LR ArmEnableFiq cpsie f isb - bx LR +\s\sbx LR ArmDisableFiq cpsid f @@ -99,17 +99,17 @@ ArmDisableInterrupts ArmGetInterruptState mrs R0,CPSR - tst R0,#0x80 ;Check if IRQ is enabled. + tst R0,#0x80\s\s ;Check if IRQ is enabled. moveq R0,#1 movne R0,#0 - bx LR +\s\sbx LR ArmGetFiqState - mrs R0,CPSR - tst R0,#0x40 ;Check if FIQ is enabled. - moveq R0,#1 - movne R0,#0 - bx LR +\s\smrs R0,CPSR +\s\stst R0,#0x40\s\s ;Check if FIQ is enabled. +\s\smoveq R0,#1 +\s\smovne R0,#0 +\s\sbx LR ArmInvalidateTlb mov r0,#0 @@ -126,7 +126,7 @@ ArmSetTTBR0 ArmGetTTBR0BaseAddress mrc p15,0,r0,c2,c0,0 - ldr r1, = 0xFFFFC000 + ldr\s\s r1, = 0xFFFFC000 and r0, r0, r1 isb bx lr diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S index 0636897b87..9d7b31efdc 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.S @@ -31,7 +31,7 @@ ASM_PFX(ArmGetScuBaseAddress): # the Configuration BAR as a stack is not necessary setup. The SCU is at the
# offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
- bx lr
+ bx\s\slr
# IN None
# OUT r1 = SCU enabled (boolean)
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm index 08528fc4ec..e87d231356 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreHelper.asm @@ -31,7 +31,7 @@ ArmGetScuBaseAddress // the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
- bx lr
+ bx\s\slr
// IN None
// OUT r1 = SCU enabled (boolean)
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index cfbb8f545c..00704164f9 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -80,21 +80,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line + mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line\s\s\s\s dsb isb bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line + mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line\s\s\s\s dsb isb bx lr ASM_PFX(ArmCleanDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c10, 2 @ Clean this line + mcr p15, 0, r0, c7, c10, 2 @ Clean this line\s\s\s\s dsb isb bx lr @@ -119,7 +119,7 @@ ASM_PFX(ArmDisableMmu): bic R0,R0,#1 mcr p15,0,R0,c1,c0,0 @Disable MMU - mcr p15,0,R0,c8,c7,0 @Invalidate TLB +\s\smcr \s\s\s\sp15,0,R0,c8,c7,0 @Invalidate TLB mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array dsb isb @@ -309,7 +309,7 @@ ASM_PFX(ArmCallWFI): //Note: Return 0 in Uniprocessor implementation ASM_PFX(ArmReadCbar): - mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register + mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register bx lr ASM_PFX(ArmInvalidateInstructionAndDataTlb): @@ -318,7 +318,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb): bx lr ASM_PFX(ArmReadMpidr): - mrc p15, 0, r0, c0, c0, 5 @ read MPIDR + mrc p15, 0, r0, c0, c0, 5\s\s @ read MPIDR bx lr ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index 7b4ca425bd..4cd78d8a23 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -82,21 +82,21 @@ ArmCleanInvalidateDataCacheEntryByMVA ArmInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line + mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line\s\s\s\s dsb isb bx lr ArmCleanInvalidateDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line + mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line\s\s\s\s dsb isb bx lr ArmCleanDataCacheEntryBySetWay - mcr p15, 0, r0, c7, c10, 2 ; Clean this line + mcr p15, 0, r0, c7, c10, 2 ; Clean this line\s\s\s\s dsb isb bx lr @@ -125,7 +125,7 @@ ArmDisableMmu bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data) - mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB + mcr \s\s p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array dsb isb @@ -307,7 +307,7 @@ ArmCallWFI //Note: Return 0 in Uniprocessor implementation ArmReadCbar - mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register + mrc p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register bx lr ArmInvalidateInstructionAndDataTlb @@ -316,7 +316,7 @@ ArmInvalidateInstructionAndDataTlb bx lr ArmReadMpidr - mrc p15, 0, r0, c0, c0, 5 ; read MPIDR + mrc p15, 0, r0, c0, c0, 5\s\s\s\s; read MPIDR bx lr END |