diff options
Diffstat (limited to 'Core/MdePkg/Library/BaseCpuLib/Arm')
-rw-r--r-- | Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S | 36 | ||||
-rw-r--r-- | Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm | 37 | ||||
-rw-r--r-- | Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S | 43 | ||||
-rw-r--r-- | Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm | 44 |
4 files changed, 160 insertions, 0 deletions
diff --git a/Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S new file mode 100644 index 0000000000..960fd990a1 --- /dev/null +++ b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.S @@ -0,0 +1,36 @@ +#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for ARM
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuFlushTlb)
+
+#/**
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+# Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuFlushTlb (
+# VOID
+# )#
+#
+ASM_PFX(CpuFlushTlb):
+ mov r0,#0
+ mcr p15,0,r0,c8,c5,0 // Invalidate all the unlocked entried in TLB
+ bx LR
diff --git a/Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm new file mode 100644 index 0000000000..76313ab607 --- /dev/null +++ b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuFlushTlb.asm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------
+;
+; CpuFlushTlb() for ARM
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuFlushTlb
+ AREA cpu_flush_tlb, CODE, READONLY
+
+;/**
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuFlushTlb (
+; VOID
+; );
+;
+CpuFlushTlb
+ MOV r0,#0
+ MCR p15,0,r0,c8,c5,0 ;Invalidate all the unlocked entried in TLB
+ BX LR
+
+ END
diff --git a/Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S new file mode 100644 index 0000000000..2c859306db --- /dev/null +++ b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.S @@ -0,0 +1,43 @@ +#------------------------------------------------------------------------------
+#
+# CpuSleep() for ARMv7
+#
+# ARMv6 versions was:
+# MOV r0,#0
+# MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+#
+# But this is a no-op on ARMv7
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(CpuSleep)
+
+#/**
+# Places the CPU in a sleep state until an interrupt is received.
+#
+# Places the CPU in a sleep state until an interrupt is received. If interrupts
+# are disabled prior to calling this function, then the CPU will be placed in a
+# sleep state indefinitely.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuSleep (
+# VOID
+# );
+#
+ASM_PFX(CpuSleep):
+ wfi
+ bx lr
diff --git a/Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm new file mode 100644 index 0000000000..a51e2cd9dd --- /dev/null +++ b/Core/MdePkg/Library/BaseCpuLib/Arm/CpuSleep.asm @@ -0,0 +1,44 @@ +;------------------------------------------------------------------------------
+;
+; CpuSleep() for ARMv7
+;
+; ARMv6 versions was:
+; MOV r0,#0
+; MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
+;
+; But this is a no-op on ARMv7
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2011, Apple Inc. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+ EXPORT CpuSleep
+ AREA cpu_sleep, CODE, READONLY
+
+;/**
+; Places the CPU in a sleep state until an interrupt is received.
+;
+; Places the CPU in a sleep state until an interrupt is received. If interrupts
+; are disabled prior to calling this function, then the CPU will be placed in a
+; sleep state indefinitely.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuSleep (
+; VOID
+; );
+;
+CpuSleep
+ WFI
+ BX LR
+
+ END
|