diff options
Diffstat (limited to 'MdePkg/Include/Ipf')
| -rw-r--r-- | MdePkg/Include/Ipf/IpfDefines.h | 553 | ||||
| -rw-r--r-- | MdePkg/Include/Ipf/IpfMacro.i | 67 | ||||
| -rw-r--r-- | MdePkg/Include/Ipf/PalApi.h | 31 | ||||
| -rw-r--r-- | MdePkg/Include/Ipf/ProcessorBind.h | 219 | ||||
| -rw-r--r-- | MdePkg/Include/Ipf/SalApi.h | 721 |
5 files changed, 0 insertions, 1591 deletions
diff --git a/MdePkg/Include/Ipf/IpfDefines.h b/MdePkg/Include/Ipf/IpfDefines.h deleted file mode 100644 index 4b9c1adee0..0000000000 --- a/MdePkg/Include/Ipf/IpfDefines.h +++ /dev/null @@ -1,553 +0,0 @@ -///** @file
-// IPF Processor Defines for assembly code
-//
-// @note
-// This file is included by assembly files as well. The assmber can NOT deal
-// with /* */ commnets this is why this file is commented not following the
-// coding standard
-//
-//Copyright (c) 2006, Intel Corporation
-//All rights reserved. This program and the accompanying materials
-//are licensed and made available under the terms and conditions of the BSD License
-//which accompanies this distribution. The full text of the license may be found at
-//http://opensource.org/licenses/bsd-license.php
-//
-//THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//Module Name: IpfDefines.h
-//
-//**/
-
-#ifndef _IPFDEFINES_H
-#define _IPFDEFINES_H
-
-//
-// IPI DElivery Methods
-//
-#define IPI_INT_DELIVERY 0x0
-#define IPI_PMI_DELIVERY 0x2
-#define IPI_NMI_DELIVERY 0x4
-#define IPI_INIT_DELIVERY 0x5
-#define IPI_ExtINT_DELIVERY 0x7
-
-//
-// Define Itanium-based system registers.
-//
-// Define Itanium-based system register bit field offsets.
-//
-// Processor Status Register (PSR) Bit positions
-//
-// User / System mask
-//
-#define PSR_RV0 0
-#define PSR_BE 1
-#define PSR_UP 2
-#define PSR_AC 3
-#define PSR_MFL 4
-#define PSR_MFH 5
-
-//
-// PSR bits 6-12 reserved (must be zero)
-//
-#define PSR_MBZ0 6
-#define PSR_MBZ0_V 0x1ffUL L
-
-//
-// System only mask
-//
-#define PSR_IC 13
-#define PSR_IC_MASK (1 << 13)
-#define PSR_I 14
-#define PSR_PK 15
-#define PSR_MBZ1 16
-#define PSR_MBZ1_V 0x1UL L
-#define PSR_DT 17
-#define PSR_DFL 18
-#define PSR_DFH 19
-#define PSR_SP 20
-#define PSR_PP 21
-#define PSR_DI 22
-#define PSR_SI 23
-#define PSR_DB 24
-#define PSR_LP 25
-#define PSR_TB 26
-#define PSR_RT 27
-
-//
-// PSR bits 28-31 reserved (must be zero)
-//
-#define PSR_MBZ2 28
-#define PSR_MBZ2_V 0xfUL L
-
-//
-// Neither mask
-//
-#define PSR_CPL 32
-#define PSR_CPL_LEN 2
-#define PSR_IS 34
-#define PSR_MC 35
-#define PSR_IT 36
-#define PSR_IT_MASK 0x1000000000
-#define PSR_ID 37
-#define PSR_DA 38
-#define PSR_DD 39
-#define PSR_SS 40
-#define PSR_RI 41
-#define PSR_RI_LEN 2
-#define PSR_ED 43
-#define PSR_BN 44
-
-//
-// PSR bits 45-63 reserved (must be zero)
-//
-#define PSR_MBZ3 45
-#define PSR_MBZ3_V 0xfffffUL L
-
-//
-// Floating Point Status Register (FPSR) Bit positions
-//
-//
-// Traps
-//
-#define FPSR_VD 0
-#define FPSR_DD 1
-#define FPSR_ZD 2
-#define FPSR_OD 3
-#define FPSR_UD 4
-#define FPSR_ID 5
-
-//
-// Status Field 0 - Controls
-//
-#define FPSR0_FTZ0 6
-#define FPSR0_WRE0 7
-#define FPSR0_PC0 8
-#define FPSR0_RC0 10
-#define FPSR0_TD0 12
-
-//
-// Status Field 0 - Flags
-//
-#define FPSR0_V0 13
-#define FPSR0_D0 14
-#define FPSR0_Z0 15
-#define FPSR0_O0 16
-#define FPSR0_U0 17
-#define FPSR0_I0 18
-
-//
-// Status Field 1 - Controls
-//
-#define FPSR1_FTZ0 19
-#define FPSR1_WRE0 20
-#define FPSR1_PC0 21
-#define FPSR1_RC0 23
-#define FPSR1_TD0 25
-
-//
-// Status Field 1 - Flags
-//
-#define FPSR1_V0 26
-#define FPSR1_D0 27
-#define FPSR1_Z0 28
-#define FPSR1_O0 29
-#define FPSR1_U0 30
-#define FPSR1_I0 31
-
-//
-// Status Field 2 - Controls
-//
-#define FPSR2_FTZ0 32
-#define FPSR2_WRE0 33
-#define FPSR2_PC0 34
-#define FPSR2_RC0 36
-#define FPSR2_TD0 38
-
-//
-// Status Field 2 - Flags
-//
-#define FPSR2_V0 39
-#define FPSR2_D0 40
-#define FPSR2_Z0 41
-#define FPSR2_O0 42
-#define FPSR2_U0 43
-#define FPSR2_I0 44
-
-//
-// Status Field 3 - Controls
-//
-#define FPSR3_FTZ0 45
-#define FPSR3_WRE0 46
-#define FPSR3_PC0 47
-#define FPSR3_RC0 49
-#define FPSR3_TD0 51
-
-//
-// Status Field 0 - Flags
-//
-#define FPSR3_V0 52
-#define FPSR3_D0 53
-#define FPSR3_Z0 54
-#define FPSR3_O0 55
-#define FPSR3_U0 56
-#define FPSR3_I0 57
-
-//
-// FPSR bits 58-63 Reserved -- Must be zero
-//
-#define FPSR_MBZ0 58
-#define FPSR_MBZ0_V 0x3fUL L
-
-//
-// For setting up FPSR on kernel entry
-// All traps are disabled.
-//
-#define FPSR_FOR_KERNEL 0x3f
-
-#define FP_REG_SIZE 16 // 16 byte spill size
-#define HIGHFP_REGS_LENGTH (96 * 16)
-
-//
-// Define hardware Task Priority Register (TPR)
-//
-//
-// TPR bit positions
-//
-#define TPR_MIC 4 // Bits 0 - 3 ignored
-#define TPR_MIC_LEN 4
-#define TPR_MMI 16 // Mask Maskable Interrupt
-//
-// Define hardware Interrupt Status Register (ISR)
-//
-//
-// ISR bit positions
-//
-#define ISR_CODE 0
-#define ISR_CODE_LEN 16
-#define ISR_CODE_MASK 0xFFFF
-#define ISR_IA_VECTOR 16
-#define ISR_IA_VECTOR_LEN 8
-#define ISR_MBZ0 24
-#define ISR_MBZ0_V 0xff
-#define ISR_X 32
-#define ISR_W 33
-#define ISR_R 34
-#define ISR_NA 35
-#define ISR_SP 36
-#define ISR_RS 37
-#define ISR_IR 38
-#define ISR_NI 39
-#define ISR_MBZ1 40
-#define ISR_EI 41
-#define ISR_ED 43
-#define ISR_MBZ2 44
-#define ISR_MBZ2_V 0xfffff
-
-//
-// ISR codes
-//
-// For General exceptions: ISR{3:0}
-//
-#define ISR_ILLEGAL_OP 0 // Illegal operation fault
-#define ISR_PRIV_OP 1 // Privileged operation fault
-#define ISR_PRIV_REG 2 // Privileged register fauls
-#define ISR_RESVD_REG 3 // Reserved register/field flt
-#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
-//
-// Define hardware Default Control Register (DCR)
-//
-//
-// DCR bit positions
-//
-#define DCR_PP 0
-#define DCR_BE 1
-#define DCR_LC 2
-#define DCR_MBZ0 4
-#define DCR_MBZ0_V 0xf
-#define DCR_DM 8
-#define DCR_DP 9
-#define DCR_DK 10
-#define DCR_DX 11
-#define DCR_DR 12
-#define DCR_DA 13
-#define DCR_DD 14
-#define DCR_DEFER_ALL 0x7f00
-#define DCR_MBZ1 2
-#define DCR_MBZ1_V 0xffffffffffffUL L
-
-//
-// Define hardware RSE Configuration Register
-//
-// RS Configuration (RSC) bit field positions
-//
-#define RSC_MODE 0
-#define RSC_PL 2
-#define RSC_BE 4
-#define RSC_MBZ0 5
-#define RSC_MBZ0_V 0x3ff
-#define RSC_LOADRS 16
-#define RSC_LOADRS_LEN 14
-#define RSC_MBZ1 30
-#define RSC_MBZ1_V 0x3ffffffffUL L
-
-//
-// RSC modes
-//
-#define RSC_MODE_LY (0x0) // Lazy
-#define RSC_MODE_SI (0x1) // Store intensive
-#define RSC_MODE_LI (0x2) // Load intensive
-#define RSC_MODE_EA (0x3) // Eager
-//
-// RSC Endian bit values
-//
-#define RSC_BE_LITTLE 0
-#define RSC_BE_BIG 1
-
-//
-// Define Interruption Function State (IFS) Register
-//
-// IFS bit field positions
-//
-#define IFS_IFM 0
-#define IFS_IFM_LEN 38
-#define IFS_MBZ0 38
-#define IFS_MBZ0_V 0x1ffffff
-#define IFS_V 63
-#define IFS_V_LEN 1
-
-//
-// IFS is valid when IFS_V = IFS_VALID
-//
-#define IFS_VALID 1
-
-//
-// Define Page Table Address (PTA)
-//
-#define PTA_VE 0
-#define PTA_VF 8
-#define PTA_SIZE 2
-#define PTA_SIZE_LEN 6
-#define PTA_BASE 15
-
-//
-// Define Region Register (RR)
-//
-//
-// RR bit field positions
-//
-#define RR_VE 0
-#define RR_MBZ0 1
-#define RR_PS 2
-#define RR_PS_LEN 6
-#define RR_RID 8
-#define RR_RID_LEN 24
-#define RR_MBZ1 32
-
-//
-// SAL uses region register 0 and RID of 1000
-//
-#define SAL_RID 0x1000
-#define SAL_RR_REG 0x0
-#define SAL_TR 0x0
-
-//
-// Total number of region registers
-//
-#define RR_SIZE 8
-
-//
-// Define Protection Key Register (PKR)
-//
-// PKR bit field positions
-//
-#define PKR_V 0
-#define PKR_WD 1
-#define PKR_RD 2
-#define PKR_XD 3
-#define PKR_MBZ0 4
-#define PKR_KEY 8
-#define PKR_KEY_LEN 24
-#define PKR_MBZ1 32
-
-#define PKR_VALID (1 << PKR_V)
-
-//
-// Number of protection key registers
-//
-#define PKRNUM 8
-
-//
-// Define Interruption TLB Insertion register (ITIR)
-//
-//
-// Define Translation Insertion Format (TR)
-//
-// PTE0 bit field positions
-//
-#define PTE0_P 0
-#define PTE0_MBZ0 1
-#define PTE0_MA 2
-#define PTE0_A 5
-#define PTE0_D 6
-#define PTE0_PL 7
-#define PTE0_AR 9
-#define PTE0_PPN 12
-#define PTE0_MBZ1 48
-#define PTE0_ED 52
-#define PTE0_IGN0 53
-
-//
-// ITIR bit field positions
-//
-#define ITIR_MBZ0 0
-#define ITIR_PS 2
-#define ITIR_PS_LEN 6
-#define ITIR_KEY 8
-#define ITIR_KEY_LEN 24
-#define ITIR_MBZ1 32
-#define ITIR_MBZ1_LEN 16
-#define ITIR_PPN 48
-#define ITIR_PPN_LEN 15
-#define ITIR_MBZ2 63
-
-#define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
-#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
-// Dirty (bit 6=1), Accessed (bit 5=1),
-// MA WB (bits 4-2=000), Present (bit 0=1)
-//
-// Memory access rights
-//
-#define AR_UR_KR 0x0 // user/kernel read
-#define AR_URX_KRX 0x1 // user/kernel read and execute
-#define AR_URW_KRW 0x2 // user/kernel read & write
-#define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
-#define AR_UR_KRW 0x4 // user read/kernel read,write
-#define AR_URX_KRWX 0x5 // user read/execute, kernel all
-#define AR_URWX_KRW 0x6 // user all, kernel read & write
-#define AR_UX_KRX 0x7 // user execute only, kernel read and execute
-//
-// Memory attribute values
-//
-//
-// The next 4 are all cached, non-sequential & speculative, coherent
-//
-#define MA_WBU 0x0 // Write back, unordered
-//
-// The next 3 are all non-cached, sequential & non-speculative
-//
-#define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
-#define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
-// & fetchadd exported
-//
-#define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
-#define MA_NAT 0xf // NaT page
-//
-// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
-// base of IVA (Interruption Vector Address)
-//
-#define IVT_SIZE 0x8000
-#define EXTRA_ALIGNMENT 0x1000
-
-#define OFF_VHPTFLT 0x0000 // VHPT Translation fault
-#define OFF_ITLBFLT 0x0400 // Instruction TLB fault
-#define OFF_DTLBFLT 0x0800 // Data TLB fault
-#define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
-#define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
-#define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
-#define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
-#define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
-#define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
-#define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
-#define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
-#define OFF_BREAKFLT 0x2C00 // Break Inst fault
-#define OFF_EXTINT 0x3000 // External Interrupt
-//
-// Offset 0x3400 to 0x0x4C00 are reserved
-//
-#define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
-#define OFF_KEYPERMFLT 0x5100 // Key Permission fault
-#define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
-#define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
-#define OFF_GPFLT 0x5400 // General Exception fault
-#define OFF_FPDISFLT 0x5500 // Disable-FP fault
-#define OFF_NATFLT 0x5600 // NAT Consumption fault
-#define OFF_SPECLNFLT 0x5700 // Speculation fault
-#define OFF_DBGFLT 0x5900 // Debug fault
-#define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
-#define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
-#define OFF_FPFLT 0x5C00 // Floating Point fault
-#define OFF_FPTRAP 0x5D00 // Floating Point Trap
-#define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
-#define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
-#define OFF_SSTEPTRAP 0x6000 // Single Step Trap
-//
-// Offset 0x6100 to 0x6800 are reserved
-//
-#define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
-#define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
-#define OFF_IA32INT 0x6B00 // iA32 Interrupt
-#define NUMBER_OF_VECTORS 0x100
-//
-// Privilege levels
-//
-#define PL_KERNEL 0
-#define PL_USER 3
-
-//
-// Instruction set (IS) bits
-//
-#define IS_IA64 0
-#define IS_IA 1
-
-//
-// RSC while in kernel: enabled, little endian, PL = 0, eager mode
-//
-#define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
-
-//
-// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
-//
-#define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
-
-//
-// RSE disabled: disabled, PL = 0, little endian, eager mode
-//
-#define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
-
-#define NAT_BITS_PER_RNAT_REG 63
-
-//
-// Macros for generating PTE0 and PTE1 value
-//
-#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
- ( ( ed << PTE0_ED ) | \
- ( ppn12_47 << PTE0_PPN ) | \
- ( ar << PTE0_AR ) | \
- ( pl << PTE0_PL ) | \
- ( d << PTE0_D ) | \
- ( a << PTE0_A ) | \
- ( ma << PTE0_MA ) | \
- ( p << PTE0_P ) \
- )
-
-#define ITIR(ppn48_63, key, ps) \
- ( ( ps << ITIR_PS ) | \
- ( key << ITIR_KEY ) | \
- ( ppn48_63 << ITIR_PPN ) \
- )
-
-//
-// Macro to generate mask value from bit position. The result is a
-// 64-bit.
-//
-#define BITMASK(bp, value) (value << bp)
-
-#define BUNDLE_SIZE 16
-#define SPURIOUS_INT 0xF
-
-#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
-
-#define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;
-
-#endif
diff --git a/MdePkg/Include/Ipf/IpfMacro.i b/MdePkg/Include/Ipf/IpfMacro.i deleted file mode 100644 index 86fd3c1a8e..0000000000 --- a/MdePkg/Include/Ipf/IpfMacro.i +++ /dev/null @@ -1,67 +0,0 @@ -//++
-// Copyright (c) 2006, Intel Corporation
-// All rights reserved. This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-// Module Name:
-// IpfMacro.i
-//
-// Abstract:
-// Contains the macros needed for calling procedures in Itanium-based assembly code.
-//
-//
-// Revision History:
-//
-//--
-
-#ifndef __IA64PROC_I__
-#define __IA64PROC_I__
-
-
-#define PROCEDURE_ENTRY(name) .##text; \
- .##type name, @function; \
- .##proc name; \
-name::
-
-#define PROCEDURE_EXIT(name) .##endp name
-
-// Note: use of NESTED_SETUP requires number of locals (l) >= 3
-
-#define NESTED_SETUP(i,l,o,r) \
- alloc loc1=ar##.##pfs,i,l,o,r ;\
- mov loc0=b0
-
-#define NESTED_RETURN \
- mov b0=loc0 ;\
- mov ar##.##pfs=loc1 ;;\
- br##.##ret##.##dpnt b0;;
-
-#define GLOBAL_FUNCTION(Function) \
- .##type Function, @function; \
- .##global Function
-
-#define INTERRUPT_HANDLER_BEGIN(name) \
-PROCEDURE_ENTRY(name##HandlerBegin) \
-;; \
-PROCEDURE_EXIT(name##HandlerBegin)
-
-#define INTERRUPT_HANDLER_END(name) \
-PROCEDURE_ENTRY(name##HandlerEnd) \
-;; \
-PROCEDURE_EXIT(name##HandlerEnd)
-
-
-#define INTERRUPT_HANDLER_BLOCK_BEGIN \
-INTERRUPT_HANDLER_BEGIN(First)
-
-#define INTERRUPT_HANDLER_BLOCK_END \
-INTERRUPT_HANDLER_END(Last)
-
-
-
-#endif
diff --git a/MdePkg/Include/Ipf/PalApi.h b/MdePkg/Include/Ipf/PalApi.h deleted file mode 100644 index 0afa3d361f..0000000000 --- a/MdePkg/Include/Ipf/PalApi.h +++ /dev/null @@ -1,31 +0,0 @@ -/** @file
- Main PAL API's defined in IPF PAL Spec.
-
- Copyright (c) 2006 - 2007, Intel Corporation
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Module Name: PalApi.h
-
-**/
-
-#ifndef __PAL_API_H__
-#define __PAL_API_H__
-
-//
-// IPF Specific Functions
-//
-
-typedef struct {
- UINT64 Status;
- UINT64 r9;
- UINT64 r10;
- UINT64 r11;
-} PAL_CALL_RETURN;
-
-#endif
diff --git a/MdePkg/Include/Ipf/ProcessorBind.h b/MdePkg/Include/Ipf/ProcessorBind.h deleted file mode 100644 index 119b5913c4..0000000000 --- a/MdePkg/Include/Ipf/ProcessorBind.h +++ /dev/null @@ -1,219 +0,0 @@ -/** @file
- Processor or Compiler specific defines and types for Intel Itanium(TM).
-
- Copyright (c) 2006, Intel Corporation
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Module Name: ProcessorBind.h
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-
-//
-// Define the processor type so other code can make processor based choices
-//
-#define MDE_CPU_IPF
-
-
-//
-// Make sure we are useing the correct packing rules per EFI specification
-//
-#pragma pack()
-
-
-#if _MSC_EXTENSIONS
-
-//
-// Disable warning that make it impossible to compile at /W4
-// This only works for Microsoft tools. Copied from the
-// IA-32 version of efibind.h
-//
-
-//
-// Disabling bitfield type checking warnings.
-//
-#pragma warning ( disable : 4214 )
-
-
-// Disabling the unreferenced formal parameter warnings.
-//
-#pragma warning ( disable : 4100 )
-
-//
-// Disable slightly different base types warning as CHAR8 * can not be set
-// to a constant string.
-//
-#pragma warning ( disable : 4057 )
-
-//
-// Disable warning on conversion from function pointer to a data pointer
-//
-#pragma warning ( disable : 4054 )
-
-//
-// ASSERT(FALSE) or while (TRUE) are legal constructes so supress this warning
-//
-#pragma warning ( disable : 4127 )
-
-//
-// Can not cast a function pointer to a data pointer. We need to do this on
-// IPF to get access to the PLABEL.
-//
-#pragma warning ( disable : 4514 )
-
-//
-// This warning is caused by functions defined but not used. For precompiled header only.
-//
-#pragma warning ( disable : 4505 )
-
-//
-// This warning is caused by empty (after preprocessing) souce file. For precompiled header only.
-//
-#pragma warning ( disable : 4206 )
-
-#endif
-
-
-#if (__STDC_VERSION__ < 199901L)
- //
- // No ANSI C 2000 stdint.h integer width declarations, so define equivalents
- //
-
- #if _MSC_EXTENSIONS
-
-
- //
- // use Microsoft C complier dependent interger width types
- //
- typedef unsigned __int64 UINT64;
- typedef __int64 INT64;
- typedef unsigned __int32 UINT32;
- typedef __int32 INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #else
- #ifdef _EFI_P64
- //
- // P64 - is Intel Itanium(TM) speak for pointers being 64-bit and longs and ints
- // are 32-bits
- //
- typedef unsigned long long UINT64;
- typedef long long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short CHAR16;
- typedef unsigned short UINT16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #else
- //
- // Assume LP64 - longs and pointers are 64-bit. Ints are 32-bit.
- //
- typedef unsigned long UINT64;
- typedef long INT64;
- typedef unsigned int UINT32;
- typedef int INT32;
- typedef unsigned short UINT16;
- typedef unsigned short CHAR16;
- typedef short INT16;
- typedef unsigned char BOOLEAN;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef char INT8;
- #endif
- #endif
-
- #define UINT8_MAX 0xff
-
-#else
- //
- // Use ANSI C 2000 stdint.h integer width declarations
- //
- #include <stdint.h>
- typedef uint8_t BOOLEAN;
- typedef int8_t INT8;
- typedef uint8_t UINT8;
- typedef int16_t INT16;
- typedef uint16_t UINT16;
- typedef int32_t INT32;
- typedef uint32_t UINT32;
- typedef int64_t INT64;
- typedef uint64_t UINT64;
- typedef char CHAR8;
- typedef uint16_t CHAR16;
-
-#endif
-
-typedef UINT64 UINTN;
-typedef INT64 INTN;
-
-
-//
-// Processor specific defines
-//
-#define MAX_BIT 0x8000000000000000ULL
-#define MAX_2_BITS 0xC000000000000000ULL
-
-//
-// Maximum legal Itanium-based address
-//
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
-
-//
-// Per the Itanium Software Conventions and Runtime Architecture Guide,
-// section 3.3.4, IPF stack must always be 16-byte aligned.
-//
-#define CPU_STACK_ALIGNMENT 16
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify thier member functions with EFIAPI.
-//
-#if _MSC_EXTENSIONS
- //
- // Microsoft* compiler requires _EFIAPI useage, __cdecl is Microsoft* specific C.
- //
- #define EFIAPI __cdecl
-#else
- #define EFIAPI
-#endif
-
-//
-// The Microsoft* C compiler can removed references to unreferenced data items
-// if the /OPT:REF linker option is used. We defined a macro as this is a
-// a non standard extension
-//
-#if _MSC_EXTENSIONS
- #define GLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany)
-#else
- #define GLOBAL_REMOVE_IF_UNREFERENCED
-#endif
-
-//
-// A pointer to a function in IPF points to a plabel.
-//
-typedef struct {
- UINT64 EntryPoint;
- UINT64 GP;
-} EFI_PLABEL;
-
-#endif
-
diff --git a/MdePkg/Include/Ipf/SalApi.h b/MdePkg/Include/Ipf/SalApi.h deleted file mode 100644 index 1d62705d56..0000000000 --- a/MdePkg/Include/Ipf/SalApi.h +++ /dev/null @@ -1,721 +0,0 @@ -/** @file
- Main SAL API's defined in SAL 3.0 specification.
-
- Copyright (c) 2006, Intel Corporation
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
- Module Name: SalApi.h
-
-**/
-
-#ifndef __SAL_API_H__
-#define __SAL_API_H__
-
-//
-// FIT Types
-// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
-//
-#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
-#define EFI_SAL_FIT_PAL_B_TYPE 0x01
-//
-// type from 0x02 to 0x0E is reserved.
-//
-#define EFI_SAL_FIT_PAL_A_TYPE 0x0F
-//
-// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
-//
-#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
-#define EFI_SAL_FIT_UNUSED_TYPE 0x7F
-
-//
-// EFI_SAL_STATUS
-//
-typedef UINTN EFI_SAL_STATUS;
-
-#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
-#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
-#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
-#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
-#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
-#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
-#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
-#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
-
-//
-// Return values from SAL
-//
-typedef struct {
- EFI_SAL_STATUS Status; // register r8
- UINTN r9;
- UINTN r10;
- UINTN r11;
-} SAL_RETURN_REGS;
-
-//
-// Delivery Mode of IPF CPU.
-//
-typedef enum {
- EFI_DELIVERY_MODE_INT,
- EFI_DELIVERY_MODE_MPreserved1,
- EFI_DELIVERY_MODE_PMI,
- EFI_DELIVERY_MODE_MPreserved2,
- EFI_DELIVERY_MODE_NMI,
- EFI_DELIVERY_MODE_INIT,
- EFI_DELIVERY_MODE_MPreserved3,
- EFI_DELIVERY_MODE_ExtINT
-} EFI_DELIVERY_MODE;
-
-typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
- (
- IN UINT64 FunctionId,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4,
- IN UINT64 Arg5,
- IN UINT64 Arg6,
- IN UINT64 Arg7,
- IN UINT64 Arg8
- );
-
-//
-// SAL Procedure FunctionId definition
-//
-#define EFI_SAL_SET_VECTORS 0x01000000
-#define EFI_SAL_GET_STATE_INFO 0x01000001
-#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
-#define EFI_SAL_CLEAR_STATE_INFO 0x01000003
-#define EFI_SAL_MC_RENDEZ 0x01000004
-#define EFI_SAL_MC_SET_PARAMS 0x01000005
-#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
-#define EFI_SAL_CACHE_FLUSH 0x01000008
-#define EFI_SAL_CACHE_INIT 0x01000009
-#define EFI_SAL_PCI_CONFIG_READ 0x01000010
-#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
-#define EFI_SAL_FREQ_BASE 0x01000012
-#define EFI_SAL_UPDATE_PAL 0x01000020
-
-#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
-#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
-
-//
-// SAL Procedure parameter definitions
-// Not much point in using typedefs or enums because all params
-// are UINT64 and the entry point is common
-//
-// EFI_SAL_SET_VECTORS
-//
-#define EFI_SAL_SET_MCA_VECTOR 0x0
-#define EFI_SAL_SET_INIT_VECTOR 0x1
-#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
-
-typedef struct {
- UINT64 Length : 32;
- UINT64 ChecksumValid : 1;
- UINT64 Reserved1 : 7;
- UINT64 ByteChecksum : 8;
- UINT64 Reserved2 : 16;
-} SAL_SET_VECTORS_CS_N;
-
-//
-// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
-// EFI_SAL_CLEAR_STATE_INFO
-//
-#define EFI_SAL_MCA_STATE_INFO 0x0
-#define EFI_SAL_INIT_STATE_INFO 0x1
-#define EFI_SAL_CMC_STATE_INFO 0x2
-#define EFI_SAL_CP_STATE_INFO 0x3
-
-//
-// EFI_SAL_MC_SET_PARAMS
-//
-#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
-#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
-#define EFI_SAL_MC_SET_CPE_PARAM 0x3
-
-#define EFI_SAL_MC_SET_INTR_PARAM 0x1
-#define EFI_SAL_MC_SET_MEM_PARAM 0x2
-
-//
-// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
-//
-#define EFI_SAL_REGISTER_PAL_ADDR 0x0
-
-//
-// EFI_SAL_CACHE_FLUSH
-//
-#define EFI_SAL_FLUSH_I_CACHE 0x01
-#define EFI_SAL_FLUSH_D_CACHE 0x02
-#define EFI_SAL_FLUSH_BOTH_CACHE 0x03
-#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
-
-//
-// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
-//
-#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
-#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
-#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
-
-typedef struct {
- UINT64 Register : 8;
- UINT64 Function : 3;
- UINT64 Device : 5;
- UINT64 Bus : 8;
- UINT64 Segment : 8;
- UINT64 Reserved : 32;
-} SAL_PCI_ADDRESS;
-
-//
-// EFI_SAL_FREQ_BASE
-//
-#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
-#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
-#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
-
-//
-// EFI_SAL_UPDATE_PAL
-//
-#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
-#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
-#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
-#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
-#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
-#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
-#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
-#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
-
-typedef struct {
- UINT32 Size;
- UINT32 MmddyyyyDate;
- UINT16 Version;
- UINT8 Type;
- UINT8 Reserved[5];
- UINT64 FwVendorId;
-} SAL_UPDATE_PAL_DATA_BLOCK;
-
-typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
- struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
- struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;
- UINT8 StoreChecksum;
- UINT8 Reserved[15];
-} SAL_UPDATE_PAL_INFO_BLOCK;
-
-//
-// SAL System Table Definitions
-//
-#pragma pack(1)
-typedef struct {
- UINT32 Signature;
- UINT32 Length;
- UINT16 SalRevision;
- UINT16 EntryCount;
- UINT8 CheckSum;
- UINT8 Reserved[7];
- UINT16 SalAVersion;
- UINT16 SalBVersion;
- UINT8 OemId[32];
- UINT8 ProductId[32];
- UINT8 Reserved2[8];
-} SAL_SYSTEM_TABLE_HEADER;
-#pragma pack()
-
-#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
-#define EFI_SAL_REVISION 0x0300
-//
-// SAL System Types
-//
-#define EFI_SAL_ST_ENTRY_POINT 0
-#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
-#define EFI_SAL_ST_PLATFORM_FEATURES 2
-#define EFI_SAL_ST_TR_USAGE 3
-#define EFI_SAL_ST_PTC 4
-#define EFI_SAL_ST_AP_WAKEUP 5
-
-#pragma pack(1)
-typedef struct {
- UINT8 Type; // Type == 0
- UINT8 Reserved[7];
- UINT64 PalProcEntry;
- UINT64 SalProcEntry;
- UINT64 SalGlobalDataPointer;
- UINT64 Reserved2[2];
-} SAL_ST_ENTRY_POINT_DESCRIPTOR;
-
-//
-// Not needed for Itanium-based OS boot
-//
-typedef struct {
- UINT8 Type; // Type == 1
- UINT8 NeedVirtualRegistration;
- UINT8 MemoryAttributes;
- UINT8 PageAccessRights;
- UINT8 SupportedAttributes;
- UINT8 Reserved;
- UINT8 MemoryType;
- UINT8 MemoryUsage;
- UINT64 PhysicalMemoryAddress;
- UINT32 Length;
- UINT32 Reserved1;
- UINT64 OemReserved;
-} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;
-
-#pragma pack()
-//
-// Memory Attributes
-//
-#define SAL_MDT_ATTRIB_WB 0x00
-//
-// #define SAL_MDT_ATTRIB_UC 0x02
-//
-#define SAL_MDT_ATTRIB_UC 0x04
-#define SAL_MDT_ATTRIB_UCE 0x05
-#define SAL_MDT_ATTRIB_WC 0x06
-
-//
-// Supported memory Attributes
-//
-#define SAL_MDT_SUPPORT_WB 0x1
-#define SAL_MDT_SUPPORT_UC 0x2
-#define SAL_MDT_SUPPORT_UCE 0x4
-#define SAL_MDT_SUPPORT_WC 0x8
-
-//
-// Virtual address registration
-//
-#define SAL_MDT_NO_VA 0x00
-#define SAL_MDT_NEED_VA 0x01
-//
-// MemoryType info
-//
-#define SAL_REGULAR_MEMORY 0x0000
-#define SAL_MMIO_MAPPING 0x0001
-#define SAL_SAPIC_IPI_BLOCK 0x0002
-#define SAL_IO_PORT_MAPPING 0x0003
-#define SAL_FIRMWARE_MEMORY 0x0004
-#define SAL_BLACK_HOLE 0x000A
-//
-// Memory Usage info
-//
-#define SAL_MDT_USAGE_UNSPECIFIED 0x00
-#define SAL_PAL_CODE 0x01
-#define SAL_BOOTSERVICE_CODE 0x02
-#define SAL_BOOTSERVICE_DATA 0x03
-#define SAL_RUNTIMESERVICE_CODE 0x04
-#define SAL_RUNTIMESERVICE_DATA 0x05
-#define SAL_IA32_OPTIONROM 0x06
-#define SAL_IA32_SYSTEMROM 0x07
-#define SAL_PMI_CODE 0x0a
-#define SAL_PMI_DATA 0x0b
-
-#pragma pack(1)
-typedef struct {
- UINT8 Type; // Type == 2
- UINT8 PlatformFeatures;
- UINT8 Reserved[14];
-} SAL_ST_PLATFORM_FEATURES;
-#pragma pack()
-
-#define SAL_PLAT_FEAT_BUS_LOCK 0x01
-#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
-#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
-
-#pragma pack(1)
-typedef struct {
- UINT8 Type; // Type == 3
- UINT8 TRType;
- UINT8 TRNumber;
- UINT8 Reserved[5];
- UINT64 VirtualAddress;
- UINT64 EncodedPageSize;
- UINT64 Reserved1;
-} SAL_ST_TR_DECRIPTOR;
-#pragma pack()
-
-#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
-#define EFI_SAL_ST_TR_USAGE_DATA 01
-
-#pragma pack(1)
-typedef struct {
- UINT64 NumberOfProcessors;
- UINT64 LocalIDRegister;
-} SAL_COHERENCE_DOMAIN_INFO;
-#pragma pack()
-
-#pragma pack(1)
-typedef struct {
- UINT8 Type; // Type == 4
- UINT8 Reserved[3];
- UINT32 NumberOfDomains;
- SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
-} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
-#pragma pack()
-
-#pragma pack(1)
-typedef struct {
- UINT8 Type; // Type == 5
- UINT8 WakeUpType;
- UINT8 Reserved[6];
- UINT64 ExternalInterruptVector;
-} SAL_ST_AP_WAKEUP_DECRIPTOR;
-#pragma pack()
-//
-// FIT Entry
-//
-#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
-#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
-#define EFI_SAL_FIT_PALB_TYPE 01
-
-typedef struct {
- UINT64 Address;
- UINT8 Size[3];
- UINT8 Reserved;
- UINT16 Revision;
- UINT8 Type : 7;
- UINT8 CheckSumValid : 1;
- UINT8 CheckSum;
-} EFI_SAL_FIT_ENTRY;
-
-//
-// SAL Common Record Header
-//
-typedef struct {
- UINT16 Length;
- UINT8 Data[1024];
-} SAL_OEM_DATA;
-
-typedef struct {
- UINT8 Seconds;
- UINT8 Minutes;
- UINT8 Hours;
- UINT8 Reserved;
- UINT8 Day;
- UINT8 Month;
- UINT8 Year;
- UINT8 Century;
-} SAL_TIME_STAMP;
-
-typedef struct {
- UINT64 RecordId;
- UINT16 Revision;
- UINT8 ErrorSeverity;
- UINT8 ValidationBits;
- UINT32 RecordLength;
- SAL_TIME_STAMP TimeStamp;
- UINT8 OemPlatformId[16];
-} SAL_RECORD_HEADER;
-
-typedef struct {
- EFI_GUID Guid;
- UINT16 Revision;
- UINT8 ErrorRecoveryInfo;
- UINT8 Reserved;
- UINT32 SectionLength;
-} SAL_SEC_HEADER;
-
-//
-// SAL Processor Record
-//
-#define SAL_PROCESSOR_ERROR_RECORD_INFO \
- { \
- 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define CHECK_INFO_VALID_BIT_MASK 0x1
-#define REQUESTOR_ID_VALID_BIT_MASK 0x2
-#define RESPONDER_ID_VALID_BIT_MASK 0x4
-#define TARGER_ID_VALID_BIT_MASK 0x8
-#define PRECISE_IP_VALID_BIT_MASK 0x10
-
-typedef struct {
- UINT64 InfoValid : 1;
- UINT64 ReqValid : 1;
- UINT64 RespValid : 1;
- UINT64 TargetValid : 1;
- UINT64 IpValid : 1;
- UINT64 Reserved : 59;
- UINT64 Info;
- UINT64 Req;
- UINT64 Resp;
- UINT64 Target;
- UINT64 Ip;
-} MOD_ERROR_INFO;
-
-typedef struct {
- UINT8 CpuidInfo[40];
- UINT8 Reserved;
-} CPUID_INFO;
-
-typedef struct {
- UINT64 FrLow;
- UINT64 FrHigh;
-} FR_STRUCT;
-
-#define MIN_STATE_VALID_BIT_MASK 0x1
-#define BR_VALID_BIT_MASK 0x2
-#define CR_VALID_BIT_MASK 0x4
-#define AR_VALID_BIT_MASK 0x8
-#define RR_VALID_BIT_MASK 0x10
-#define FR_VALID_BIT_MASK 0x20
-
-typedef struct {
- UINT64 ValidFieldBits;
- UINT8 MinStateInfo[1024];
- UINT64 Br[8];
- UINT64 Cr[128];
- UINT64 Ar[128];
- UINT64 Rr[8];
- FR_STRUCT Fr[128];
-} PSI_STATIC_STRUCT;
-
-#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
-#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
-#define PROC_CR_LID_VALID_BIT_MASK 0x4
-#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
-#define CPU_INFO_VALID_BIT_MASK 0x1000000
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT64 ProcErrorMap;
- UINT64 ProcStateParameter;
- UINT64 ProcCrLid;
- MOD_ERROR_INFO CacheError[15];
- MOD_ERROR_INFO TlbError[15];
- MOD_ERROR_INFO BusError[15];
- MOD_ERROR_INFO RegFileCheck[15];
- MOD_ERROR_INFO MsCheck[15];
- CPUID_INFO CpuInfo;
- PSI_STATIC_STRUCT PsiValidData;
-} SAL_PROCESSOR_ERROR_RECORD;
-
-//
-// Sal Platform memory Error Record
-//
-#define SAL_MEMORY_ERROR_RECORD_INFO \
- { \
- 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
-#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
-#define MEMORY_ADDR_BIT_MASK 0x4
-#define MEMORY_NODE_VALID_BIT_MASK 0x8
-#define MEMORY_CARD_VALID_BIT_MASK 0x10
-#define MEMORY_MODULE_VALID_BIT_MASK 0x20
-#define MEMORY_BANK_VALID_BIT_MASK 0x40
-#define MEMORY_DEVICE_VALID_BIT_MASK 0x80
-#define MEMORY_ROW_VALID_BIT_MASK 0x100
-#define MEMORY_COLUMN_VALID_BIT_MASK 0x200
-#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
-#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
-#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
-#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
-#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
-#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
-#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT64 MemErrorStatus;
- UINT64 MemPhysicalAddress;
- UINT64 MemPhysicalAddressMask;
- UINT16 MemNode;
- UINT16 MemCard;
- UINT16 MemModule;
- UINT16 MemBank;
- UINT16 MemDevice;
- UINT16 MemRow;
- UINT16 MemColumn;
- UINT16 MemBitPosition;
- UINT64 ModRequestorId;
- UINT64 ModResponderId;
- UINT64 ModTargetId;
- UINT64 BusSpecificData;
- UINT8 MemPlatformOemId[16];
-} SAL_MEMORY_ERROR_RECORD;
-
-//
-// PCI BUS Errors
-//
-#define SAL_PCI_BUS_ERROR_RECORD_INFO \
- { \
- 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
-#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
-#define PCI_BUS_ID_VALID_BIT_MASK 0x4
-#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
-#define PCI_BUS_DATA_VALID_BIT_MASK 0x10
-#define PCI_BUS_CMD_VALID_BIT_MASK 0x20
-#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
-#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
-#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
-#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
-#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
-
-typedef struct {
- UINT8 BusNumber;
- UINT8 SegmentNumber;
-} PCI_BUS_ID;
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT64 PciBusErrorStatus;
- UINT16 PciBusErrorType;
- PCI_BUS_ID PciBusId;
- UINT32 Reserved;
- UINT64 PciBusAddress;
- UINT64 PciBusData;
- UINT64 PciBusCommand;
- UINT64 PciBusRequestorId;
- UINT64 PciBusResponderId;
- UINT64 PciBusTargetId;
- UINT8 PciBusOemId[16];
-} SAL_PCI_BUS_ERROR_RECORD;
-
-//
-// PCI Component Errors
-//
-#define SAL_PCI_COMP_ERROR_RECORD_INFO \
- { \
- 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
-#define PCI_COMP_INFO_VALID_BIT_MASK 0x2
-#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
-#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
-#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
-#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
-
-typedef struct {
- UINT16 VendorId;
- UINT16 DeviceId;
- UINT8 ClassCode[3];
- UINT8 FunctionNumber;
- UINT8 DeviceNumber;
- UINT8 BusNumber;
- UINT8 SegmentNumber;
- UINT8 Reserved[5];
-} PCI_COMP_INFO;
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT64 PciComponentErrorStatus;
- PCI_COMP_INFO PciComponentInfo;
- UINT32 PciComponentMemNum;
- UINT32 PciComponentIoNum;
- UINT8 PciBusOemId[16];
-} SAL_PCI_COMPONENT_ERROR_RECORD;
-
-//
-// Sal Device Errors Info.
-//
-#define SAL_DEVICE_ERROR_RECORD_INFO \
- { \
- 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
-#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
-#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
-#define SEL_EVM_REV_VALID_BIT_MASK 0x8;
-#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
-#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
-#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
-#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
-#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
-#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT16 SelRecordId;
- UINT8 SelRecordType;
- UINT32 TimeStamp;
- UINT16 GeneratorId;
- UINT8 EvmRevision;
- UINT8 SensorType;
- UINT8 SensorNum;
- UINT8 EventDirType;
- UINT8 Data1;
- UINT8 Data2;
- UINT8 Data3;
-} SAL_DEVICE_ERROR_RECORD;
-
-//
-// Sal SMBIOS Device Errors Info.
-//
-#define SAL_SMBIOS_ERROR_RECORD_INFO \
- { \
- 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
-#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
-#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
-#define SMBIOS_DATA_VALID_BIT_MASK 0x8
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT8 SmbiosEventType;
- UINT8 SmbiosLength;
- UINT8 SmbiosBcdTimeStamp[6];
-} SAL_SMBIOS_DEVICE_ERROR_RECORD;
-
-//
-// Sal Platform Specific Errors Info.
-//
-#define SAL_PLATFORM_ERROR_RECORD_INFO \
- { \
- 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
- }
-
-#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
-#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
-#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
-#define PLATFORM_TARGET_VALID_BIT_MASK 0x8
-#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
-#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
-#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
-#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
-
-typedef struct {
- SAL_SEC_HEADER SectionHeader;
- UINT64 ValidationBits;
- UINT64 PlatformErrorStatus;
- UINT64 PlatformRequestorId;
- UINT64 PlatformResponderId;
- UINT64 PlatformTargetId;
- UINT64 PlatformBusSpecificData;
- UINT8 OemComponentId[16];
-} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
-
-//
-// Union of all the possible Sal Record Types
-//
-typedef union {
- SAL_RECORD_HEADER *RecordHeader;
- SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;
- SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;
- SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;
- SAL_DEVICE_ERROR_RECORD *ImpiRecord;
- SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;
- SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;
- SAL_MEMORY_ERROR_RECORD *MemoryRecord;
- UINT8 *Raw;
-} SAL_ERROR_RECORDS_POINTERS;
-
-#pragma pack()
-
-#endif
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