diff options
Diffstat (limited to 'OvmfPkg/Library/AcpiTimerLib')
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c | 8 | ||||
| -rw-r--r-- | OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c | 8 |
2 files changed, 14 insertions, 2 deletions
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c index 652545d864..a839495e67 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -37,6 +37,8 @@ AcpiTimerLibConstructor ( {
UINT16 HostBridgeDevId;
UINTN Pmba;
+ UINT32 PmbaAndVal;
+ UINT32 PmbaOrVal;
UINTN AcpiCtlReg;
UINT8 AcpiEnBit;
@@ -47,11 +49,15 @@ AcpiTimerLibConstructor ( switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
+ PmbaOrVal = PIIX4_PMBA_VALUE;
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+ PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
+ PmbaOrVal = ICH9_PMBASE_VALUE;
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
@@ -70,7 +76,7 @@ AcpiTimerLibConstructor ( // If the Power Management Base Address is not programmed,
// then program it now.
//
- PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
+ PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
//
// Enable PMBA I/O port decodes
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c index 735dfd2e4b..dbbecc93c1 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -35,6 +35,8 @@ AcpiTimerLibConstructor ( {
UINT16 HostBridgeDevId;
UINTN Pmba;
+ UINT32 PmbaAndVal;
+ UINT32 PmbaOrVal;
UINTN AcpiCtlReg;
UINT8 AcpiEnBit;
@@ -45,11 +47,15 @@ AcpiTimerLibConstructor ( switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;
+ PmbaOrVal = PIIX4_PMBA_VALUE;
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break;
case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+ PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;
+ PmbaOrVal = ICH9_PMBASE_VALUE;
AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
break;
@@ -68,7 +74,7 @@ AcpiTimerLibConstructor ( // If the Power Management Base Address is not programmed,
// then program it now.
//
- PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
+ PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);
//
// Enable PMBA I/O port decodes
|