diff options
Diffstat (limited to 'Platform/Marvell/Documentation/PortingGuide')
11 files changed, 336 insertions, 0 deletions
diff --git a/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt b/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt new file mode 100644 index 0000000000..a96015e152 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt @@ -0,0 +1,45 @@ +COMPHY configuration
+---------------------------
+In order to configure ComPhy library, following PCDs are available:
+
+ gMarvellTokenSpaceGuid.PcdComPhyDevices
+
+This array indicates, which ones of the ComPhy chips defined in
+MVHW_COMPHY_DESC template will be configured.
+
+Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not
+important, but configuration will be set for first PcdComPhyChipCount chips).
+
+Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes
+settings for this chip. Their format is unicode string, containing settings
+for up to 10 lanes. Setting for each one is separated with semicolon.
+These PCDs together describe outputs of PHY integrated in simple cihp.
+Below is example for the first chip (Chip0).
+
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes
+
+Unicode string indicating PHY types. Currently supported are:
+
+{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3",
+L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0",
+L"SGMII1", L"SGMII2", L"SGMII3",
+L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE",
+L"RXAUI0", L"RXAUI1", L"SFI" }
+
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds
+
+Indicates PHY speeds in MHz. Currently supported are:
+
+{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 10310 }
+
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags
+
+Indicates lane polarity invert.
+
+Example
+-------
+ #ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2"
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000"
+
diff --git a/Platform/Marvell/Documentation/PortingGuide/I2c.txt b/Platform/Marvell/Documentation/PortingGuide/I2c.txt new file mode 100644 index 0000000000..020ffb4f1b --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/I2c.txt @@ -0,0 +1,20 @@ +1. Porting I2C driver to a new SOC
+----------------------------------
+In order to enable driver on a new platform, following steps need to be taken:
+ - add following line to .dsc file:
+ Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+ - add following line to .fdf file:
+ INF Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf
+ - add PCDs with relevant values to .dsc file:
+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 }
+ (addresses of I2C slave devices on bus)
+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 }
+ (buses to which accoring slaves are attached)
+ gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+ (number of SoC's I2C buses)
+ gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100"
+ (base addresses of I2C controller buses)
+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000
+ (I2C host controller clock frequency)
+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+ (baud rate used in I2C transmission)
diff --git a/Platform/Marvell/Documentation/PortingGuide/Mdio.txt b/Platform/Marvell/Documentation/PortingGuide/Mdio.txt new file mode 100644 index 0000000000..c341d9e8d0 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Mdio.txt @@ -0,0 +1,7 @@ +MDIO driver configuration
+-------------------------
+MDIO driver provides access to network PHYs' registers via MARVELL_MDIO_READ and
+MARVELL_MDIO_WRITE functions (MARVELL_MDIO_PROTOCOL). Following PCD is required:
+
+ gMarvellTokenSpaceGuid.PcdMdioBaseAddress
+ (base address of SMI management register)
diff --git a/Platform/Marvell/Documentation/PortingGuide/Mpp.txt b/Platform/Marvell/Documentation/PortingGuide/Mpp.txt new file mode 100644 index 0000000000..68f0e9d179 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Mpp.txt @@ -0,0 +1,48 @@ +MPP configuration
+-----------------
+Multi-Purpose Ports (MPP) are configurable through platform PCDs.
+In order to set desired pin multiplexing, .dsc file needs to be modified.
+(Platform/Marvell/Armada/{platform_name}.dsc - please refer to
+Documentation/Build.txt for currently supported {platftorm_name} )
+Following PCDs are available:
+
+ gMarvellTokenSpaceGuid.PcdMppChipCount
+
+Indicates how many different chips are placed on board. So far up to 4 chips
+are supported.
+
+Every MPP PCD has <Num> part where
+ <Num> stands for chip ID (order is not important, but configuration will be
+ set for first PcdMppChipCount chips).
+
+Below is example for the first chip (Chip0).
+
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag
+
+Indicates that register order is reversed. (Needs to be used only for AP806-Z1)
+
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress
+
+This is base address for MPP configuration register.
+
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount
+
+Defines how many MPP pins are available.
+
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1
+ gMarvellTokenSpaceGuid.PcdChip0MppSel2
+
+This registers defines functions of 10 pins in ascending order.
+
+Examples
+--------
+#APN806-A0 MPP SET
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+Set pin 6 and 7 to 0xa function:
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 }
diff --git a/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt b/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt new file mode 100644 index 0000000000..ec1afbc7bf --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt @@ -0,0 +1,31 @@ +PciEmulation configuration
+--------------------------
+Installation of various NonDiscoverable devices via PciEmulation driver is performed
+via set of PCDs. Following are available:
+
+ gMarvellTokenSpaceGuid.PcdPciEXhci
+
+Indicates, which Xhci devices are used.
+
+ gMarvellTokenSpaceGuid.PcdPciEAhci
+
+Indicates, which Ahci devices are used.
+
+ gMarvellTokenSpaceGuid.PcdPciESdhci
+
+Indicates, which Sdhci devices are used.
+
+All above PCD's correspond to hardware description in a dedicated structure:
+
+STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate
+
+in Platforms/Marvell/PciEmulation/PciEmulation.c file. It comprises device
+count, base addresses, register region size and DMA-coherency type.
+
+Examples
+--------
+Assuming we want to enable second XHCI port and one SDHCI port on Armada
+70x0 board, following needs to be declared:
+
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }
diff --git a/Platform/Marvell/Documentation/PortingGuide/Phy.txt b/Platform/Marvell/Documentation/PortingGuide/Phy.txt new file mode 100644 index 0000000000..69dae02a3e --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Phy.txt @@ -0,0 +1,45 @@ +PHY driver configuration
+------------------------
+MvPhyDxe provides basic initialization and status routines for Marvell PHYs.
+Currently only 1512 series PHYs are supported. Following PCDs are required:
+
+ gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
+ (list of values corresponding to PHY_CONNECTION enum)
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg
+ (boolean - if true, driver waits for autonegotiation on startup)
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds
+ (list of values corresponding to MV_PHY_DEVICE_ID enum)
+
+PHY_CONNECTION enum type is defined as follows:
+
+ typedef enum {
+0 PHY_CONNECTION_RGMII,
+1 PHY_CONNECTION_RGMII_ID,
+2 PHY_CONNECTION_RGMII_TXID,
+3 PHY_CONNECTION_RGMII_RXID,
+4 PHY_CONNECTION_SGMII,
+5 PHY_CONNECTION_RTBI,
+6 PHY_CONNECTION_XAUI,
+7 PHY_CONNECTION_RXAUI
+ } PHY_CONNECTION;
+
+MV_PHY_DEVICE_ID:
+
+ typedef enum {
+0 MV_PHY_DEVICE_1512,
+ } MV_PHY_DEVICE_ID;
+
+It should be extended when adding support for other PHY
+models.
+
+Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be:
+
+ gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 }
+
+with disabled autonegotiation:
+
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+assuming, that PHY models are 1512:
+
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt new file mode 100644 index 0000000000..c1554a694e --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt @@ -0,0 +1,59 @@ +Pp2Dxe porting guide
+--------------------
+Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs
+are required to operate:
+
+Number of ports/network interfaces:
+ gMarvellTokenSpaceGuid.PcdPp2NumPorts
+
+Addresses of PHY devices:
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses
+
+Identificators of PP2 ports:
+ gMarvellTokenSpaceGuid.PcdPp2PortIds
+
+Indexes used in GOP operation:
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes
+
+Set to 0x1 for always-up interface, 0x0 otherwise:
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
+
+Values corresponding to PHY_SPEED enum:
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
+
+PHY_SPEED (in Mbps) is defined as follows:
+ typedef enum {
+ 0 NO_SPEED,
+ 1 SPEED_10,
+ 2 SPEED_100,
+ 3 SPEED_1000,
+ 4 SPEED_2500,
+ 5 SPEED_10000
+ } PHY_SPEED;
+
+Base address of shared register space of PP2:
+ gMarvellTokenSpaceGuid.PcdPp2SharedAddress
+
+Spacing between consecutive GMAC register spaces:
+ gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
+
+Base address of GMAC:
+ gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
+
+Spacing between consecutive XLG register spaces:
+ gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
+
+Base address of XLG:
+ gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
+
+Base address of RFU1:
+ gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
+
+Base address of SMI:
+ gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
+
+TCLK frequency in Hz:
+ gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
+
+GMAC and XLG addresses are computed as follows:
+ address = base_address + dev_size * gop_index
diff --git a/Platform/Marvell/Documentation/PortingGuide/Reset.txt b/Platform/Marvell/Documentation/PortingGuide/Reset.txt new file mode 100644 index 0000000000..30dec8612b --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Reset.txt @@ -0,0 +1,7 @@ +MarvellResetSystemLib configuration
+-----------------------------------
+This simple library allows to mask given bits in given reg at UEFI 'reset'
+command call. These variables are configurable through PCDs:
+
+ gMarvellTokenSpaceGuid.PcdResetRegAddress
+ gMarvellTokenSpaceGuid.PcdResetRegMask
diff --git a/Platform/Marvell/Documentation/PortingGuide/Spi.txt b/Platform/Marvell/Documentation/PortingGuide/Spi.txt new file mode 100644 index 0000000000..be498a66a6 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Spi.txt @@ -0,0 +1,16 @@ +Spi driver configuration
+------------------------
+Following PCDs are available for configuration of spi driver:
+
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency
+
+Frequency (in Hz) of SPI clock
+
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency
+
+Max SCLK line frequency (in Hz) (max transfer frequency)
+
+ gMarvellTokenSpaceGuid.PcdSpiDefaultMode
+
+default SCLK mode (see SPI_MODE enum in file
+Platform/Marvell/Drivers/Spi/MvSpi.h)
diff --git a/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt b/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt new file mode 100644 index 0000000000..226db4001e --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt @@ -0,0 +1,23 @@ +SpiFlash driver configuration
+-----------------------------
+Folowing PCDs for spi flash driver configuration must be set properly:
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles
+
+Size of SPI flash address in bytes (3 or 4)
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize
+
+Size of minimal erase block in bytes
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashPageSize
+
+Size of SPI flash page
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashId
+
+Id of SPI flash
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd
+
+Spi flash polling flag
diff --git a/Platform/Marvell/Documentation/PortingGuide/Utmi.txt b/Platform/Marvell/Documentation/PortingGuide/Utmi.txt new file mode 100644 index 0000000000..cff4843da2 --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide/Utmi.txt @@ -0,0 +1,35 @@ +UTMI PHY configuration
+----------------------
+In order to configure UTMI, following PCDs are available:
+
+ gMarvellTokenSpaceGuid.PcdUtmiPhyCount
+
+Indicates how many UTMI PHYs are available on platform.
+
+Next four PCDs are in unicode string format containing settings for all devices
+separated with semicolon.
+
+ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit
+
+Indicates base address of the UTMI unit.
+
+ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg
+
+Indicates address of USB Configuration register.
+
+ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg
+
+Indicates address of external UTMI configuration.
+
+ gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort
+
+Indicates type of the connected USB port.
+
+Example
+-------
+#UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2
+ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000"
+ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420"
+ gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444"
+ gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"
|