diff options
Diffstat (limited to 'Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c')
| -rw-r--r-- | Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 165 |
1 files changed, 165 insertions, 0 deletions
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c index cdd0979450..27ae6b889d 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c @@ -4116,6 +4116,21 @@ MvGop110PortInit ( /* MAC unreset */
MvGop110GmacReset (Port, UNRESET);
break;
+ case MV_MODE_SFI:
+ /* Configure PCS */
+ MvGopXpcsModeCfg (Port, MVPP2_SFI_LANE_COUNT);
+
+ MvGopMpcsModeCfg (Port);
+
+ /* Configure MAC */
+ MvGopXlgMacModeCfg (Port);
+
+ /* PCS unreset */
+ MvGopXpcsUnreset (Port);
+
+ /* MAC unreset */
+ MvGopXlgMacUnreset (Port);
+ break;
default:
return -1;
}
@@ -4512,6 +4527,104 @@ Mvpp2SmiPhyAddrCfg ( return 0;
}
+/* Set the internal mux's to the required PCS */
+EFI_STATUS
+MvGopXpcsModeCfg (
+ IN PP2DXE_PORT *Port,
+ IN INT32 NumOfLanes
+ )
+{
+ UINT8 LaneCoeff;
+
+ switch (NumOfLanes) {
+ case 1:
+ case 2:
+ case 4:
+ LaneCoeff = NumOfLanes >> 1;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ /* Configure XG MAC mode */
+ MmioAndThenOr32 (Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG,
+ ~(MVPP22_XPCS_PCSMODE_MASK | MVPP22_XPCS_LANEACTIVE_MASK),
+ LaneCoeff << MVPP22_XPCS_LANEACTIVE_OFFS);
+
+ return EFI_SUCCESS;
+}
+
+VOID
+MvGopMpcsModeCfg (
+ IN PP2DXE_PORT *Port
+ )
+{
+ /* Configure MPCS40G COMMON CONTROL */
+ MmioAnd32 (Port->Priv->MpcsBase + MVPP22_MPCS40G_COMMON_CONTROL,
+ ~MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK);
+
+ /* Configure MPCS CLOCK RESET */
+ MmioAndThenOr32 (Port->Priv->MpcsBase + MVPP22_MPCS_CLOCK_RESET,
+ ~(MVPP22_MPCS_CLK_DIVISION_RATIO_MASK | MVPP22_MPCS_CLK_DIV_PHASE_SET_MASK),
+ MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT | MVPP22_MPCS_MAC_CLK_RESET_MASK |
+ MVPP22_MPCS_RX_SD_CLK_RESET_MASK | MVPP22_MPCS_TX_SD_CLK_RESET_MASK);
+}
+
+/* Set the internal mux's to the required MAC in the GOP */
+VOID
+MvGopXlgMacModeCfg (
+ IN PP2DXE_PORT *Port
+ )
+{
+ /* Configure 10G MAC mode */
+ MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_RXFCEN_MASK);
+
+ MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL3_REG,
+ ~MV_XLG_MAC_CTRL3_MACMODESELECT_MASK,
+ MV_XLG_MAC_CTRL3_MACMODESELECT_10G);
+
+ MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL4_REG,
+ ~(MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK | MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK),
+ MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_MASK | MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_MASK);
+
+ /* Configure frame size limit */
+ MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL1_REG,
+ ~MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK,
+ MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT);
+
+ /* Mask all port's external interrupts */
+ MvGop110XlgPortLinkEventMask (Port);
+
+ /* Unmask link change interrupt - enable automatic status update */
+ MmioOr32 (Port->XlgBase + MV_XLG_INTERRUPT_MASK_REG,
+ MV_XLG_INTERRUPT_LINK_CHANGE_MASK | MV_XLG_SUMMARY_INTERRUPT_MASK);
+}
+
+/* Set PCS to exit from reset */
+VOID
+MvGopXpcsUnreset (
+ IN PP2DXE_PORT *Port
+ )
+{
+ MmioOr32 (Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG, MVPP22_XPCS_PCSRESET);
+}
+
+/* Set the MAC to exit from reset */
+VOID
+MvGopXlgMacUnreset (
+ IN PP2DXE_PORT *Port
+ )
+{
+ MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_MACRESETN_MASK);
+}
+
+BOOLEAN
+MvGop110XlgLinkStatusGet (
+ IN PP2DXE_PORT *Port
+ )
+{
+ return MmioRead32 (Port->XlgBase + MV_XLG_MAC_PORT_STATUS_REG) & MV_XLG_MAC_PORT_STATUS_LINKSTATUS_MASK;
+}
+
BOOLEAN
MvGop110PortIsLinkUp (
IN PP2DXE_PORT *Port
@@ -4522,6 +4635,8 @@ MvGop110PortIsLinkUp ( case MV_MODE_SGMII:
case MV_MODE_QSGMII:
return MvGop110GmacLinkStatusGet (Port);
+ case MV_MODE_SFI:
+ return MvGop110XlgLinkStatusGet (Port);
case MV_MODE_XAUI:
case MV_MODE_RXAUI:
return FALSE;
@@ -4546,6 +4661,30 @@ MvGop110GmacLinkStatusGet ( return (Val & 1) ? TRUE : FALSE;
}
+STATIC
+VOID
+MvGop110XlgPortEnable (
+ IN PP2DXE_PORT *Port
+ )
+{
+ /* Enable port and MIB counters update */
+ MmioAndThenOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG,
+ ~MV_XLG_MAC_CTRL0_MIBCNTDIS_MASK,
+ MV_XLG_MAC_CTRL0_PORTEN_MASK);
+}
+
+STATIC
+VOID
+MvGop110XlgPortDisable (
+ IN PP2DXE_PORT *Port
+ )
+{
+ /* Mask all port's external interrupts */
+ MvGop110XlgPortLinkEventMask (Port);
+
+ MmioAnd32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, ~MV_XLG_MAC_CTRL0_PORTEN_MASK);
+}
+
VOID
MvGop110PortDisable (
IN PP2DXE_PORT *Port
@@ -4557,6 +4696,11 @@ MvGop110PortDisable ( case MV_MODE_QSGMII:
MvGop110GmacPortDisable (Port);
break;
+ case MV_MODE_XAUI:
+ case MV_MODE_RXAUI:
+ case MV_MODE_SFI:
+ MvGop110XlgPortDisable (Port);
+ break;
default:
return;
}
@@ -4573,6 +4717,11 @@ MvGop110PortEnable ( case MV_MODE_QSGMII:
MvGop110GmacPortEnable (Port);
break;
+ case MV_MODE_XAUI:
+ case MV_MODE_RXAUI:
+ case MV_MODE_SFI:
+ MvGop110XlgPortEnable (Port);
+ break;
default:
return;
}
@@ -4622,6 +4771,15 @@ MvGop110GmacPortLinkEventMask ( MvGop110GmacWrite (Port, MV_GMAC_INTERRUPT_SUM_MASK_REG, RegVal);
}
+VOID
+MvGop110XlgPortLinkEventMask (
+ IN PP2DXE_PORT *Port
+ )
+{
+ MmioAnd32 (Port->XlgBase + MV_XLG_EXTERNAL_INTERRUPT_MASK_REG,
+ ~MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_MASK);
+}
+
INT32
MvGop110PortEventsMask (
IN PP2DXE_PORT *Port
@@ -4634,6 +4792,11 @@ MvGop110PortEventsMask ( case MV_MODE_QSGMII:
MvGop110GmacPortLinkEventMask (Port);
break;
+ case MV_MODE_XAUI:
+ case MV_MODE_RXAUI:
+ case MV_MODE_SFI:
+ MvGop110XlgPortLinkEventMask (Port);
+ break;
default:
return -1;
}
@@ -4655,6 +4818,7 @@ MvGop110FlCfg ( break;
case MV_MODE_XAUI:
case MV_MODE_RXAUI:
+ case MV_MODE_SFI:
return 0;
default:
return -1;
@@ -4679,6 +4843,7 @@ MvGop110SpeedDuplexSet ( break;
case MV_MODE_XAUI:
case MV_MODE_RXAUI:
+ case MV_MODE_SFI:
break;
default:
return -1;
|