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-rw-r--r--Platform/Marvell/Armada/Armada70x0.dsc6
-rw-r--r--Platform/Marvell/Documentation/PortingGuide/Pp2.txt21
-rw-r--r--Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h10
-rw-r--r--Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c12
-rw-r--r--Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf6
-rw-r--r--Platform/Marvell/Marvell.dec6
6 files changed, 16 insertions, 45 deletions
diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Armada/Armada70x0.dsc
index 3440038ff2..d86567b9bd 100644
--- a/Platform/Marvell/Armada/Armada70x0.dsc
+++ b/Platform/Marvell/Armada/Armada70x0.dsc
@@ -119,18 +119,12 @@
#NET
gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 }
gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333
- gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00
- gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000
gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 }
gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 }
gMarvellTokenSpaceGuid.PcdPp2NumPorts|3
gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
- gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000
gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000
- gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200
- gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00
- gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000
#PciEmulation
gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 }
diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
index c1554a694e..3c2f4188f0 100644
--- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
+++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt
@@ -34,26 +34,5 @@ PHY_SPEED (in Mbps) is defined as follows:
Base address of shared register space of PP2:
gMarvellTokenSpaceGuid.PcdPp2SharedAddress
-Spacing between consecutive GMAC register spaces:
- gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
-
-Base address of GMAC:
- gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
-
-Spacing between consecutive XLG register spaces:
- gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
-
-Base address of XLG:
- gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
-
-Base address of RFU1:
- gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
-
-Base address of SMI:
- gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
-
TCLK frequency in Hz:
gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
-
-GMAC and XLG addresses are computed as follows:
- address = base_address + dev_size * gop_index
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
index f283db2d49..868be53031 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
@@ -39,6 +39,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#define BIT(nr) (1 << (nr))
#endif
+/* PP2v2 registers offsets */
+#define MVPP22_SMI_OFFSET 0x12a200
+#define MVPP22_MPCS_OFFSET 0x130000
+#define MVPP22_XPCS_OFFSET 0x130400
+#define MVPP22_GMAC_OFFSET 0x130e00
+#define MVPP22_GMAC_REG_SIZE 0x1000
+#define MVPP22_XLG_OFFSET 0x130f00
+#define MVPP22_XLG_REG_SIZE 0x1000
+#define MVPP22_RFU1_OFFSET 0x441000
+
/* RX Fifo Registers */
#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
index 1e2ccd0dbe..d53f3b7398 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
@@ -1141,10 +1141,6 @@ Pp2DxeParsePortPcd (
Pp2Context->Port.PhyInterface = PhyConnectionTypes[Pp2Context->Instance];
Pp2Context->Port.AlwaysUp = AlwaysUp[Pp2Context->Instance];
Pp2Context->Port.Speed = Speed[Pp2Context->Instance];
- Pp2Context->Port.GmacBase = PcdGet64 (PcdPp2GmacBaseAddress) +
- PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->Port.GopIndex;
- Pp2Context->Port.XlgBase = PcdGet64 (PcdPp2XlgBaseAddress) +
- PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Port.GopIndex;
}
EFI_STATUS
@@ -1174,8 +1170,8 @@ Pp2DxeInitialise (
}
Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
- Mvpp2Shared->Rfu1Base = PcdGet64 (PcdPp2Rfu1BaseAddress);
- Mvpp2Shared->SmiBase = PcdGet64 (PcdPp2SmiBaseAddress);
+ Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
+ Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
/* Prepare buffers */
@@ -1259,6 +1255,10 @@ Pp2DxeInitialise (
Pp2Context->Port.TxpNum = 1;
Pp2Context->Port.Priv = Mvpp2Shared;
Pp2Context->Port.FirstRxq = 4 * Pp2Context->Instance;
+ Pp2Context->Port.GmacBase = Mvpp2Shared->Base + MVPP22_GMAC_OFFSET +
+ MVPP22_GMAC_REG_SIZE * Pp2Context->Port.GopIndex;
+ Pp2Context->Port.XlgBase = Mvpp2Shared->Base + MVPP22_XLG_OFFSET +
+ MVPP22_XLG_REG_SIZE * Pp2Context->Port.GopIndex;
/* Gather accumulated configuration data of all ports' MAC's */
NetCompConfig |= MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port);
diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
index 9052fe27b7..ecd82b618d 100644
--- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
+++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf
@@ -74,18 +74,12 @@
gMarvellTokenSpaceGuid.PcdPhyConnectionTypes
gMarvellTokenSpaceGuid.PcdPhySmiAddresses
gMarvellTokenSpaceGuid.PcdPp2ClockFrequency
- gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress
- gMarvellTokenSpaceGuid.PcdPp2GmacDevSize
gMarvellTokenSpaceGuid.PcdPp2GopIndexes
gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp
gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed
gMarvellTokenSpaceGuid.PcdPp2NumPorts
gMarvellTokenSpaceGuid.PcdPp2PortIds
- gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress
gMarvellTokenSpaceGuid.PcdPp2SharedAddress
- gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress
- gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress
- gMarvellTokenSpaceGuid.PcdPp2XlgDevSize
[Depex]
TRUE
diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec
index 5cbf0c389f..9e2f7067aa 100644
--- a/Platform/Marvell/Marvell.dec
+++ b/Platform/Marvell/Marvell.dec
@@ -170,18 +170,12 @@
#NET
gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024
gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026
- gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0|UINT64|0x3000027
- gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0|UINT32|0x3000028
gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029
gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A
gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B
gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D
gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C
- gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0|UINT64|0x300002E
gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F
- gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0|UINT64|0x3000030
- gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0|UINT64|0x3000031
- gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0|UINT32|0x3000032
#PciEmulation
gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-18 20:32:25 +0000