diff options
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Include')
14 files changed, 1390 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/ConfigBlock.h b/Silicon/Intel/KabylakeSiliconPkg/Include/ConfigBlock.h new file mode 100644 index 0000000000..246582e9ee --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/ConfigBlock.h @@ -0,0 +1,59 @@ +/** @file
+ Header file for Config Block Lib implementation
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
+ UINT8 Revision; ///< Offset 24 Revision of this config block
+ UINT8 Attributes; ///< Offset 25 The main revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
+ UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/HstiFeatureBit.h b/Silicon/Intel/KabylakeSiliconPkg/Include/HstiFeatureBit.h new file mode 100644 index 0000000000..cdbe75ae18 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/HstiFeatureBit.h @@ -0,0 +1,183 @@ +/** @file
+ This file contains various definitions for IHV HSTI implementation
+ including error string definitions
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __HSTI_FEATURE_BIT_H__
+#define __HSTI_FEATURE_BIT_H__
+
+#define HSTI_SECURITY_FEATURE_SIZE 3
+
+#define HSTI_ERROR L"Error "
+#define HSTI_PLATFORM_SECURITY_SPECIFICATION L" Platform Security Specification"
+#define HSTI_BOOTGUARD_CONFIGURATION L" - Boot Guard Configuration - "
+#define HSTI_SPI_FLASH_CONFIGURATION L" - SPI Flash Configuration - "
+#define HSTI_PCH_SECURITY_CONFIGURATION L" - PCH Security Configuration - "
+#define HSTI_BIOS_GUARD_SECURITY_CONFIGURATION L" - BIOS Guard Security Configuration - "
+#define HSTI_MEASURED_BOOT_CONFIGURATION L" - Measured Boot Configuration - "
+#define HSTI_INTEGRATED_DEVICE_DMA_PROTECTION L" - Integrated Device DMA Protection - "
+#define HSTI_CPU_SECURITY_CONFIGURATION L" - CPU Security Configuration - "
+#define HSTI_SYSTEM_AGENT_SECURITY_CONFIGURATION L" - Secure System Agent Security Configuration - "
+#define HSTI_MEMORY_MAP_SECURITY_CONFIGURATION L" - Memory Map Security Configuration - "
+#define HSTI_PROCESSOR_GRAPHICS_SECURITY_CONFIGURATION L" - Processor Graphics Security Configuration - "
+#define HSTI_PROCESSOR_SPD_SECURITY_CONFIGURATION L" - SPD Security Configuration - "
+
+
+#define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY BIT0
+#define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_ERROR_CODE_1 L"0x00000001"
+#define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_ERROR_STRING_1 L"Boot Guard configured without Verified Boot\r\n"
+#define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_ERROR_CODE_2 L"0x00000002"
+#define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_ERROR_STRING_2 L"Boot Guard disabled\r\n"
+
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION BIT1
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_1 L"0x00010001"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_1 L"SPI Flash not write protected\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_2 L"0x00010002"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_2 L"SPI Flash descriptor overridden\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_3 L"0x00010003"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_3 L"SPI Controller configuration unlocked\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_4 L"0x00010004"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_4 L"SPI Controller BIOS Interface unlocked\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_5 L"0x00010005"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_5 L"Top Swap enabled\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_6 L"0x00010006"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_6 L"SPI Vendor Specific Component Capabilities unlocked\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_7 L"0x00010007"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_7 L"SPI Controller GbE Interface unlocked\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_8 L"0x00010008"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_8 L"ME FW not in Normal Working State\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_9 L"0x00010009"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_9 L"Flash Descriptor Invalid\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_A L"0x0001000A"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_A L"SPI Region Access Rights Invalid\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_B L"0x0001000B"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_B L"SPI SW Sequencing OPCODEs insufficiently restrained\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_C L"0x0001000C"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_C L"Allowed SPI SW Sequencing OPCODE configuration incorrect\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_D L"0x0001000D"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_D L"Global SMI not enabled and locked\r\n"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_CODE_E L"0x0001000E"
+#define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_ERROR_STRING_E L"TCO SMI not enabled and locked\r\n"
+
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE BIT2
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_ERROR_CODE_1 L"0x00020001"
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_ERROR_STRING_1 L"BIOS Guard unsupported\r\n"
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_ERROR_CODE_2 L"0x00020002"
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_ERROR_STRING_2 L"BIOS Guard configuration unlocked\r\n"
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_ERROR_CODE_3 L"0x00020001"
+#define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_ERROR_STRING_3 L"BIOS Guard disabled\r\n"
+
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT BIT3
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_CODE_1 L"0x00030001"
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_STRING_1 L"Chipset supports FW TPM, however no TPM enabled\r\n"
+
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_CODE_2 L"0x00030002"
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_STRING_2 L"PCR[7] is not initialized\r\n"
+
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_CODE_3 L"0x00030003"
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_STRING_3 L"Event Log is not published or invalid\r\n"
+
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_CODE_4 L"0x00030004"
+#define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_ERROR_STRING_4 L"Platform Auth accessible via 0x00000000\r\n"
+
+
+#define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION BIT4
+#define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_ERROR_CODE_1 L"0x00040001"
+#define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_ERROR_STRING_1 L"Bus Mastering Enabled for non-boot, integrated device\r\n"
+
+#define HSTI_BYTE0_DEBUG_MODE_DISABLED_VERIFICATION BIT5
+#define HSTI_BYTE0_DEBUG_MODE_DISABLED_VERIFICATION_ERROR_CODE_1 L"0x00050001"
+#define HSTI_BYTE0_DEBUG_MODE_DISABLED_VERIFICATION_ERROR_STRING_1 L"Debug MSR enabled\r\n"
+
+#define HSTI_BYTE0_DEBUG_MODE_DISABLED_VERIFICATION_ERROR_CODE_2 L"0x00050002"
+#define HSTI_BYTE0_DEBUG_MODE_DISABLED_VERIFICATION_ERROR_STRING_2 L"Debug interface unlocked\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION BIT6
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_1 L"0x00060001"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_1 L" Minimum uCode patch revision not met\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_2 L"0x00060002"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_2 L" Pre-production silicon in use\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_3 L"0x00060003"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_3 L"VMX & Senter feature configuration unlocked\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_4 L"0x00060004"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_4 L" SMM Code Fetch feature configuration unlocked\r\n"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_4A L" SMM Code Fetch outside SMRAM detection feature is disabled\r\n"
+
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_5 L"0x00060005"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_5 L" AES-NI Feature configuration unlocked\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_6 L"0x00060006"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_6 L" FIT table not present\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_7 L"0x00060007"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_7 L" MicrocodeRangeRegisters improperly configured or unlocked\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_8 L"0x00060008"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_8 L" SMM COnfiguration Unlocked\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_9 L"0x00060009"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_9 L" TSEG not naturally aligned\r\n"
+
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_CODE_A L"0x0006000A"
+#define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_ERROR_STRING_A L" Improper SMRR configuration\r\n"
+
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION BIT7
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_CODE_1 L"0x00070001"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_STRING_1 L"Intel TXT configuration unlocked\r\n"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_CODE_2 L"0x00070002"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_STRING_2 L"Memory Controller configuration unlocked\r\n"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_CODE_3 L"0x00070003"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_STRING_3 L"System Agent configuration unlocked\r\n"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_CODE_4 L"0x00070004"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_STRING_4 L"Graphics memory configuration unlocked\r\n"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_CODE_5 L"0x00070005"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_STRING_5 L"VT-d configuration unlocked\r\n"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_CODE_6 L"0x00070006"
+#define HSTI_BYTE0_SECURE_SYSTEM_AGENT_CONFIGURATION_ERROR_STRING_6 L"Power Plane 0 Current Config unlocked\r\n"
+
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION BIT0
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_CODE_1 L"0x00080001"
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_STRING_1 L" Memory BAR configuration unlocked\r\n"
+
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_CODE_2 L"0x00080002"
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_STRING_2 L" Fixed MMIO regions overlap\r\n"
+
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_CODE_3 L"0x00080003"
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_STRING_3 L" Non lockable MMIO ranges overlap other critical regions\r\n"
+
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_CODE_4 L"0x00080004"
+#define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_ERROR_STRING_4 L" SPD not write protected\r\n"
+
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION BIT1
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_ERROR_CODE_1 L"0x00090001"
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_ERROR_STRING_1 L" Graphics configuration unlocked\r\n"
+
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_ERROR_CODE_2 L"0x00090002"
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_ERROR_STRING_2 L"Invalid Graphics Memory Alignment\r\n"
+
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_ERROR_CODE_3 L"0x00090003"
+#define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_ERROR_STRING_3 L" Reserved Check failed\r\n"
+
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION BIT2
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_1 L"0x000A0001"
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_1 L" Thermal Configuration unlocked\r\n"
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_2 L"0x000A0002"
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_2 L"BAR's unlocked\r\n"
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_CODE_3 L"0x000A0003"
+#define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_ERROR_STRING_3 L" Reserved Check failure\r\n"
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/AslUpdateLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/AslUpdateLib.h new file mode 100644 index 0000000000..dc76e33557 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/AslUpdateLib.h @@ -0,0 +1,146 @@ +/** @file
+ ASL dynamic update library definitions.
+ This library provides dymanic update to various ASL structures.
+ There may be different libraries for different environments (PEI, BS, RT, SMM).
+ Make sure you meet the requirements for the library (protocol dependencies, use
+ restrictions, etc).
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ASL_UPDATE_LIB_H_
+#define _ASL_UPDATE_LIB_H_
+
+//
+// Include files
+//
+#include <IndustryStandard/Acpi.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+
+//
+// AML parsing definitions
+//
+#define AML_RESRC_TEMP_END_TAG 0x0079
+
+//
+// ASL PSS package structure layout
+//
+#pragma pack (1)
+typedef struct {
+ UINT8 NameOp; // 12h ;First opcode is a NameOp.
+ UINT8 PackageLead; // 20h ;First opcode is a NameOp.
+ UINT8 NumEntries; // 06h ;First opcode is a NameOp.
+ UINT8 DwordPrefix1; // 0Ch
+ UINT32 CoreFrequency; // 00h
+ UINT8 DwordPrefix2; // 0Ch
+ UINT32 Power; // 00h
+ UINT8 DwordPrefix3; // 0Ch
+ UINT32 TransLatency; // 00h
+ UINT8 DwordPrefix4; // 0Ch
+ UINT32 BmLatency; // 00h
+ UINT8 DwordPrefix5; // 0Ch
+ UINT32 Control; // 00h
+ UINT8 DwordPrefix6; // 0Ch
+ UINT32 Status; // 00h
+} PSS_PACKAGE_LAYOUT;
+#pragma pack()
+
+/**
+ Initialize the ASL update library state.
+ This must be called prior to invoking other library functions.
+
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+InitializeAslUpdateLib (
+ VOID
+ );
+
+/**
+ This procedure will update immediate value assigned to a Name
+
+ @param[in] AslSignature The signature of Operation Region that we want to update.
+ @param[in] Buffer source of data to be written over original aml
+ @param[in] Length length of data to be overwritten
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+UpdateNameAslCode(
+ IN UINT32 AslSignature,
+ IN VOID *Buffer,
+ IN UINTN Length
+ );
+
+/**
+ This function uses the ACPI support protocol to locate an ACPI table using the .
+ It is really only useful for finding tables that only have a single instance,
+ e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc.
+ Matches are determined by finding the table with ACPI table that has
+ a matching signature and version.
+
+ @param[in] Signature Pointer to an ASCII string containing the Signature to match
+ @param[in, out] Table Updated with a pointer to the table
+ @param[in, out] Handle AcpiSupport protocol table handle for the table found
+ @param[in, out] Version On input, the version of the table desired,
+ on output, the versions the table belongs to
+ @see AcpiSupport protocol for details
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+LocateAcpiTableBySignature (
+ IN UINT32 Signature,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ );
+
+/**
+ This function uses the ACPI support protocol to locate an ACPI SSDT table.
+ The table is located by searching for a matching OEM Table ID field.
+ Partial match searches are supported via the TableIdSize parameter.
+
+ @param[in] TableId Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in] TableIdSize Length of the TableId to match. Table ID are 8 bytes long, this function
+ will consider it a match if the first TableIdSize bytes match
+ @param[in, out] Table Updated with a pointer to the table
+ @param[in, out] Handle AcpiSupport protocol table handle for the table found
+ @param[in, out] Version See AcpiSupport protocol, GetAcpiTable function for use
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+LocateAcpiTableByOemTableId (
+ IN UINT8 *TableId,
+ IN UINT8 TableIdSize,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ );
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum
+ @param[in] Size Number of bytes to checksum
+ @param[in] ChecksumOffset Offset to place the checksum result in
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AcpiChecksum (
+ IN VOID *Buffer,
+ IN UINTN Size,
+ IN UINTN ChecksumOffset
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 0000000000..cc437b93bf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,70 @@ +/** @file
+ Header file for Config Block Lib implementation
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ );
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/MmPciLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/MmPciLib.h new file mode 100644 index 0000000000..b4f8b41e1b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/MmPciLib.h @@ -0,0 +1,34 @@ +/** @file
+ Get Pci Express address library implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+);
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h new file mode 100644 index 0000000000..184b04f5de --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h @@ -0,0 +1,143 @@ +/** @file
+ Header file for PEI SiPolicyUpdate Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
+#define _PEI_SI_POLICY_UPDATE_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs Silicon PEI Policy initialization.
+
+ @param[in, out] SiPolicy The Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicy
+ );
+
+/**
+ This function performs CPU PEI Policy initialization in Post-memory.
+
+ @param[in, out] SiPolicyPpi The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ This function performs SI PEI Policy initialization.
+
+ @param[in, out] SiPolicyPpi The SA Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+This function performs SA PEI Policy initialization for PreMem.
+
+@param[in, out] SiPreMemPolicyPpi The SI PreMem Policy PPI instance
+
+@retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+);
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicy
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @param[in, out] SiPreMemPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/**
+ Update the ME Policy Library
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+UpdatePeiMePolicy (
+ IN OUT SI_POLICY_PPI *SiPolicy
+ );
+
+/**
+ Update the ME Policy Library
+
+ @param[in, out] SiPreMemPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+UpdatePeiMePolicyPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/**
+ Install the Active Management Policy Ppi Library
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+UpdatePeiAmtPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicy
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiConfigBlockLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiConfigBlockLib.h new file mode 100644 index 0000000000..56527478b4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiConfigBlockLib.h @@ -0,0 +1,64 @@ +/** @file
+ Prototype of the SiConfigBlockLib library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_CONFIG_BLOCK_LIB_H_
+#define _SI_CONFIG_BLOCK_LIB_H_
+
+
+typedef
+VOID
+(*LOAD_DEFAULT_FUNCTION) (
+ IN VOID *ConfigBlockPointer
+ );
+
+typedef struct {
+ EFI_GUID *Guid;
+ UINT16 Size;
+ UINT8 Revision;
+ LOAD_DEFAULT_FUNCTION LoadDefault;
+} COMPONENT_BLOCK_ENTRY;
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+#endif // _SI_CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h new file mode 100644 index 0000000000..98d3ad25e0 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiPolicyLib.h @@ -0,0 +1,114 @@ +/** @file
+ Prototype of the SiPolicyLib library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_LIB_H_
+#define _SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ Print whole SI_PREMEM_POLICY_PPI and serial out.
+
+ @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
+**/
+VOID
+EFIAPI
+SiPreMemPrintPolicyPpi (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ Print whole SI_POLICY_PPI and serial out.
+
+ @param[in] SiPolicyPpi The RC Policy PPI instance
+**/
+VOID
+EFIAPI
+SiPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SiPreMemPolicyPpi The pointer to get Silicon PREMEM Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiCreatePreMemConfigBlocks (
+ OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi
+ );
+
+/**
+ SiCreateConfigBlocks creates the config blocksg of Silicon Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiCreateConfigBlocks (
+ OUT SI_POLICY_PPI **SiPolicyPpi
+ );
+
+/**
+ SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyPpi (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ );
+
+/**
+ SiInstallPolicyPpi installs SiPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ Print out all silicon policy information.
+
+ @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
+
+**/
+VOID
+DumpSiPolicy (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+#endif // _SI_PREMEM_POLICY_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiliconInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiliconInitLib.h new file mode 100644 index 0000000000..d10e7cf0b8 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Library/SiliconInitLib.h @@ -0,0 +1,34 @@ +/** @file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SILICON_INIT_LIB_H_
+#define _SILICON_INIT_LIB_H_
+
+///@todo it should be moved to Si Pkg.
+
+VOID
+EarlySiliconInit (
+ VOID
+ );
+
+VOID
+SiliconInit (
+ VOID
+ );
+
+VOID
+LateSiliconInit (
+ VOID
+ );
+
+#endif
\ No newline at end of file diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/PcieRegs.h b/Silicon/Intel/KabylakeSiliconPkg/Include/PcieRegs.h new file mode 100644 index 0000000000..3a3b22fd83 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/PcieRegs.h @@ -0,0 +1,309 @@ +/** @file
+ Register names for PCIE standard register
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCIE_REGS_H_
+#define _PCIE_REGS_H_
+
+#include <IndustryStandard/Pci30.h>
+
+//
+// PCI type 0 Header
+//
+#define R_PCI_PI_OFFSET 0x09
+#define R_PCI_SCC_OFFSET 0x0A
+#define R_PCI_BCC_OFFSET 0x0B
+
+//
+// PCI type 1 Header
+//
+#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register
+#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate Bus Number
+#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary Bus Number
+#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary Bus Number
+#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN | B_PCI_BRIDGE_BNUM_SCBN)
+
+#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and Limit Register
+
+#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base and Limit Register
+#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory Limit
+#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory Base
+
+#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable Memory Base and Limit Register
+#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetchable Memory Limit
+#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit Indicator
+#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetchable Memory Base
+#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit Indicator
+
+#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable Memory Base Upper 32-Bit Register
+#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF
+
+#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable Memory Limit Upper 32-Bit Register
+#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF
+
+//
+// PCIE capabilities register
+//
+#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID
+#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capability Capability ID Pointer
+
+//
+// PCI Express Capability List Register (CAPID:10h)
+//
+#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Capabilities Register (Offset 02h)
+#define S_PCIE_XCAP 2
+#define B_PCIE_XCAP_SI BIT8 ///< Slot Implemented
+#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
+#define N_PCIE_XCAP_DT 4
+
+#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities Register (Offset 04h)
+#define S_PCIE_DCAP 4
+#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency
+#define N_PCIE_DCAP_E1AL 9
+#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency
+#define N_PCIE_DCAP_E0AL 6
+#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Supported
+
+#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control Register (Offset 08h)
+#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
+#define N_PCIE_DCTL_MPS 5
+#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable
+#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable
+#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Error Reporting Enable
+#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Error Reporting Enable
+
+#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status Register (Offset 0Ah)
+#define B_PCIE_DSTS_TDP BIT5 ///< Transactions Pending
+#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected
+#define B_PCIE_DSTS_URD BIT3 ///< Unsupported Request Detected
+#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected
+#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Error Detected
+#define B_PCIE_DSTS_CED BIT0 ///< Correctable Error Detected
+
+#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities Register (Offset 0Ch)
+#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optionality Compliance
+#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power Management
+#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency
+#define N_PCIE_LCAP_EL1 15
+#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s Exit Latency
+#define N_PCIE_LCAP_EL0 12
+#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Management (ASPM) Support
+#define B_PCIE_LCAP_APMS_L0S BIT10
+#define B_PCIE_LCAP_APMS_L1 BIT11
+#define N_PCIE_LCAP_APMS 10
+#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum Link Width
+#define N_PCIE_LCAP_MLW 4
+#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed
+#define V_PCIE_LCAP_MLS_GEN3 3
+
+#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control Register (Offset 10h)
+#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power Management
+#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch
+#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
+#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link
+#define B_PCIE_LCTL_LD BIT4 ///< Link Disable
+#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State Power Management (ASPM) Control
+#define V_PCIE_LCTL_ASPM_L0S 1
+#define V_PCIE_LCTL_ASPM_L1 2
+#define V_PCIE_LCTL_ASPM_L0S_L1 3
+
+#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register (Offset 12h)
+#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link Active
+#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Configuration
+#define B_PCIE_LSTS_LT BIT11 ///< Link Training
+#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link Width
+#define N_PCIE_LSTS_NLW 4
+#define V_PCIE_LSTS_NLW_1 0x0010
+#define V_PCIE_LSTS_NLW_2 0x0020
+#define V_PCIE_LSTS_NLW_4 0x0040
+#define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed
+#define V_PCIE_LSTS_CLS_GEN1 1
+#define V_PCIE_LSTS_CLS_GEN2 2
+#define V_PCIE_LSTS_CLS_GEN3 3
+
+#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities Register (Offset 14h)
+#define S_PCIE_SLCAP 4
+#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical Slot Number
+#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Power Limit Scale
+#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Power Limit Value
+#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
+#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surprise
+
+#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control Register (Offset 18h)
+#define S_PCIE_SLCTL 2
+#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Interrupt Enable
+#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable
+
+#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register (Offset 1Ah)
+#define S_PCIE_SLSTS 2
+#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
+#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed
+
+#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control Register (Offset 1Ch)
+#define S_PCIE_RCTL 2
+#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable
+#define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable
+#define B_PCIE_RCTL_SNE BIT1 ///< System Error on Non-Fatal Error Enable
+#define B_PCIE_RCTL_SCE BIT0 ///< System Error on Correctable Error Enable
+
+#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Register (Offset 20h)
+#define S_PCIE_RSTS 4
+
+#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities 2 Register (Offset 24h)
+#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBFF Supported
+#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
+
+#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2 Register (Offset 28h)
+#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBFF Enable
+#define N_PCIE_DCTL2_OBFFEN 13
+#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled
+#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAKE# signaling
+#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism Enable
+#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable
+#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeout Value
+#define V_PCIE_DCTL2_CTV_DEFAULT 0x0
+#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5
+#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6
+#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9
+#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA
+
+#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2 Register (Offset 30h)
+#define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-emphasis (0 = -6dB, 1 = -3.5dB)
+#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed
+#define V_PCIE_LCTL2_TLS_GEN1 1
+#define V_PCIE_LCTL2_TLS_GEN2 2
+#define V_PCIE_LCTL2_TLS_GEN3 3
+
+#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 Register (Offset 32h)
+#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalization Request
+#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3 Successful
+#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2 Successful
+#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1 Successful
+#define B_PCIE_LSTS2_EC BIT1 ///< Equalization Complete
+#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emphasis Level
+
+//
+// PCI Power Management Capability (CAPID:01h)
+//
+#define R_PCIE_PMC_OFFSET 0x02 ///< Power Management Capabilities Register
+#define S_PCIE_PMC 2
+#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME Support
+#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock
+
+#define R_PCIE_PMCS_OFFST 0x04 ///< Power Management Status/Control Register
+#define S_PCIE_PMCS 4
+#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clock Control Enable
+#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support
+#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status
+#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable
+#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset
+#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power State
+#define V_PCIE_PMCS_PS_D0 0
+#define V_PCIE_PMCS_PS_D3H 3
+
+//
+// PCIE Extension Capability Register
+//
+#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Capability Offset
+#define N_PCIE_EXCAP_NCO 20
+#define V_PCIE_EXCAP_NCO_LISTEND 0
+#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capability Version
+#define N_PCIE_EXCAP_CV 16
+#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capability ID
+
+//
+// Advanced Error Reporting Capability (CAPID:0001h)
+//
+#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID
+#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable Error Mask Register
+#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Timeout Mask
+#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Completion
+
+//
+// ACS Extended Capability (CAPID:000Dh)
+//
+#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID
+#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability Register
+//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control Register (NOTE: register size in PCIE spce is not match the PCH register size)
+
+//
+// Secondary PCI Express Extended Capability Header (CAPID:0019h)
+//
+#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID
+#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3 Register
+#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equalization
+#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Status
+#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan 1 Equalization Control Register (Offset 0Ch)
+#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream Port Lane 1 Transmitter Preset
+#define N_PCIE_EX_L01EC_UPL1TP 24
+#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstream Port Lane 1 Transmitter Preset
+#define N_PCIE_EX_L01EC_DPL1TP 16
+#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream Port Transmitter Preset
+#define N_PCIE_EX_L01EC_UPL0TP 8
+#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstream Port Transmitter Preset
+#define N_PCIE_EX_L01EC_DPL0TP 0
+
+#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lane 3 Equalization Control Register (Offset 10h)
+#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream Port Lane 3 Transmitter Preset
+#define N_PCIE_EX_L23EC_UPL3TP 24
+#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstream Port Lane 3 Transmitter Preset
+#define N_PCIE_EX_L23EC_DPL3TP 16
+#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream Port Lane 2 Transmitter Preset
+#define N_PCIE_EX_L23EC_UPL2TP 8
+#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstream Port Lane 2 Transmitter Preset
+#define N_PCIE_EX_L23EC_DPL2TP 0
+
+
+//
+// L1 Sub-States Extended Capability Register (CAPID:001Eh)
+//
+#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID
+#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States Capabilities
+#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpower_on value
+#define N_PCIE_EX_L1SCAP_PTV 19
+#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpower_on scale
+#define N_PCIE_EX_L1SCAP_PTPOS 16
+#define V_PCIE_EX_L1SCAP_PTPOS_2us 0
+#define V_PCIE_EX_L1SCAP_PTPOS_10us 1
+#define V_PCIE_EX_L1SCAP_PTPOS_100us 2
+#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported
+#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supported
+#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported
+#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 supported
+#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 supported
+#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States Control 1
+#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States Control 2
+#define N_PCIE_EX_L1SCTL2_POWT 3
+
+//
+// Base Address Offset
+//
+#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address Register 0
+#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address Register 1
+#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address Register 2
+#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address Register 3
+#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address Register 4
+#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address Register 5
+#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
+#define B_PCI_BAR_MEMORY_TYPE_64 BIT2
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/SiInitPpi.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/SiInitPpi.h new file mode 100644 index 0000000000..6d2b857ac6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/SiInitPpi.h @@ -0,0 +1,22 @@ +/** @file
+ Silicon Initializtion PPI is used to export End of Silicon
+ init
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_INIT_PPI_H_
+#define _SI_INIT_PPI_H_
+
+extern EFI_GUID gEndOfSiInitPpiGuid;
+
+#endif // _SI_INIT_PPI_H_
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/SiPolicy.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/SiPolicy.h new file mode 100644 index 0000000000..044dadc022 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Ppi/SiPolicy.h @@ -0,0 +1,36 @@ +/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicyStruct.h>
+#include <PchAccess.h>
+#include <PchPolicyCommon.h>
+#include <PchPreMemPolicyCommon.h>
+#include <MePolicyCommon.h>
+#include <SaPolicyCommon.h>
+#include <CpuPolicyCommon.h>
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid;
+extern EFI_GUID gSiPolicyPpiGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;
+typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h b/Silicon/Intel/KabylakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h new file mode 100644 index 0000000000..91fcad80a0 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h @@ -0,0 +1,66 @@ +/** @file
+ Protocol used for specifying platform related Silicon information and policy setting.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_PROTOCOL_H_
+#define _SI_POLICY_PROTOCOL_H_
+
+#include <IndustryStandard/Hsti.h>
+
+//
+// DXE_SI_POLICY_PROTOCOL revisions
+//
+#define DXE_SI_POLICY_PROTOCOL_REVISION 2
+
+extern EFI_GUID gDxeSiPolicyProtocolGuid;
+
+#pragma pack (push,1)
+
+/**
+ The protocol allows the platform code to publish a set of configuration information that the
+ Silicon drivers will use to configure the processor in the DXE phase.
+ This Policy Protocol needs to be initialized for Silicon configuration.
+ @note The Protocol has to be published before processor DXE drivers are dispatched.
+**/
+typedef struct {
+ /**
+ This member specifies the revision of the Si Policy protocol. This field is used to indicate backward
+ compatible changes to the protocol. Any such changes to this protocol will result in an update in the revision number.
+
+ <b>Revision 1</b>:
+ - Initial version
+ <b>Revision 2</b>:
+ - Added SmbiosOemTypeFirmwareVersionInfo to determines the SMBIOS OEM type
+ **/
+ UINT8 Revision;
+ /**
+ SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,
+ values 0-0x7F will be treated as disable FVI reporting.
+ FVI structure uses it as SMBIOS OEM type to provide version information.
+ **/
+ UINT8 SmbiosOemTypeFirmwareVersionInfo;
+ UINT8 ReservedByte[6]; ///< Reserved bytes, align to multiple 8.
+ /**
+ This member describes a pointer to Hsti results from previous boot. In order to mitigate the large performance cost
+ of performing all of the platform security tests on each boot, we can save the results across boots and retrieve
+ and point this policy to them prior to the launch of HstiSiliconDxe. Logic should be implemented to not populate this
+ upon major platform changes (i.e changes to setup option or platform hw)to ensure that results accurately reflect the
+ configuration of the platform.
+ **/
+ ADAPTER_INFO_PLATFORM_SECURITY *Hsti; ///< This is a pointer to Hsti results from previous boot
+ UINTN HstiSize; ///< Size of results, if setting Hsti policy to point to previous results
+} DXE_SI_POLICY_PROTOCOL;
+
+#pragma pack (pop)
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Include/SiPolicyStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Include/SiPolicyStruct.h new file mode 100644 index 0000000000..f1facc4300 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Include/SiPolicyStruct.h @@ -0,0 +1,110 @@ +/** @file
+ Intel reference code configuration policies.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+
+/**
+ Silicon Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ This member specifies the revision of the Silicon Policy. This field is used to indicate change
+ to the policy structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_POLICY_REVISION 1
+#define SI_CONFIG_REVISION 1
+
+/**
+ Silicon pre-memory Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION 1
+
+extern EFI_GUID gSiConfigGuid;
+
+/**
+ The Silicon Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ //
+ // Platform specific common policies that used by several silicon components.
+ //
+ ///
+ /// Offset 28 The minimum temporary bus number available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempPciBusMin;
+ ///
+ /// Offset 29 The maximum temporary bus number available to be assigned to each root port and its downstream
+ /// devices for initialization of these devices before PCI Bus enumeration.
+ ///
+ UINT8 TempPciBusMax;
+ UINT8 Rsvd0[2]; ///< Offset 30 - 31 Reserved bytes, align to multiple 4.
+ ///
+ /// Offset 32 Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers.
+ /// Minimum size is 2MB bytes
+ ///
+ UINT32 TempMemBaseAddr;
+ ///
+ /// Offset 36 Size of allocated temp MMIO space
+ ///
+ UINT32 TempMemSize;
+ ///
+ /// Offset 40 Temporary IO Base Address for PCI devices to be used to initialize IO registers.
+ ///
+ UINT16 TempIoBaseAddr;
+ UINT16 TempIoSize; ///< Offset 42 Size of temporary IO space
+ UINT32 CsmFlag :1; ///< Offset 44 BIT0: CSM status flag.
+ UINT32 RsvdBits :31; ///< Reserved
+} SI_CONFIG;
+
+/**
+ SI Policy PPI in Pre-Mem\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader;
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+/**
+ SI Policy PPI\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader;
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+#endif
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