diff options
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Library')
32 files changed, 4505 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c new file mode 100644 index 0000000000..a411547ccb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.c @@ -0,0 +1,151 @@ +/** @file
+ Library functions for Config Block management.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <ConfigBlock.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ )
+{
+ CONFIG_BLOCK_TABLE_HEADER *ConfigBlkTblAddrPtr;
+ UINT32 ConfigBlkTblHdrSize;
+
+ ConfigBlkTblHdrSize = (UINT32)(sizeof (CONFIG_BLOCK_TABLE_HEADER));
+
+ if (TotalSize <= (ConfigBlkTblHdrSize + sizeof (CONFIG_BLOCK_HEADER))) {
+ DEBUG ((DEBUG_ERROR, "Invalid Parameter\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ConfigBlkTblAddrPtr = (CONFIG_BLOCK_TABLE_HEADER *)AllocateZeroPool (TotalSize);
+ if (ConfigBlkTblAddrPtr == NULL) {
+ DEBUG ((DEBUG_ERROR, "Could not allocate memory.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+ ConfigBlkTblAddrPtr->NumberOfBlocks = 0;
+ ConfigBlkTblAddrPtr->Header.GuidHob.Header.HobLength = TotalSize;
+ ConfigBlkTblAddrPtr->AvailableSize = TotalSize - ConfigBlkTblHdrSize;
+
+ *ConfigBlockTableAddress = (VOID *)ConfigBlkTblAddrPtr;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ )
+{
+ CONFIG_BLOCK *TempConfigBlk;
+ CONFIG_BLOCK_TABLE_HEADER *ConfigBlkTblAddrPtr;
+ CONFIG_BLOCK *ConfigBlkAddrPtr;
+ UINT16 ConfigBlkSize;
+
+ ConfigBlkTblAddrPtr = (CONFIG_BLOCK_TABLE_HEADER *)ConfigBlockTableAddress;
+ ConfigBlkAddrPtr = (CONFIG_BLOCK *)(*ConfigBlockAddress);
+ ConfigBlkSize = ConfigBlkAddrPtr->Header.GuidHob.Header.HobLength;
+ DEBUG ((DEBUG_INFO, "Config Block GUID: %g / Config Block Size: 0x%x bytes\n", &(ConfigBlkAddrPtr->Header.GuidHob.Name), ConfigBlkSize));
+ if ((ConfigBlkSize % 4) != 0) {
+ DEBUG ((DEBUG_ERROR, "Config Block must be multiples of 4 bytes\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ if (ConfigBlkTblAddrPtr->AvailableSize < ConfigBlkSize) {
+ DEBUG ((DEBUG_ERROR, "Config Block Table is full and cannot add new Config Block.\n"));
+ DEBUG ((DEBUG_ERROR, "Available Config Block Size: 0x%x bytes / Requested Config Block Size: 0x%x bytes\n", ConfigBlkTblAddrPtr->AvailableSize, ConfigBlkSize));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ TempConfigBlk = (CONFIG_BLOCK *)((UINTN)ConfigBlkTblAddrPtr + (UINTN)(ConfigBlkTblAddrPtr->Header.GuidHob.Header.HobLength - ConfigBlkTblAddrPtr->AvailableSize));
+ CopyMem (&TempConfigBlk->Header, &ConfigBlkAddrPtr->Header, sizeof(CONFIG_BLOCK_HEADER));
+
+ ConfigBlkTblAddrPtr->NumberOfBlocks++;
+ ConfigBlkTblAddrPtr->AvailableSize = ConfigBlkTblAddrPtr->AvailableSize - ConfigBlkSize;
+
+ *ConfigBlockAddress = (VOID *) TempConfigBlk;
+ DEBUG ((DEBUG_INFO, "Config Block Address: 0x%x / Available Config Block Size: 0x%x bytes\n", (UINT32)(UINTN)*ConfigBlockAddress, ConfigBlkTblAddrPtr->AvailableSize));
+ return EFI_SUCCESS;
+}
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ )
+{
+ UINT16 OffsetIndex;
+ CONFIG_BLOCK *TempConfigBlk;
+ CONFIG_BLOCK_TABLE_HEADER *ConfigBlkTblAddrPtr;
+ UINT32 ConfigBlkTblHdrSize;
+ UINT32 ConfigBlkOffset;
+ UINT16 NumOfBlocks;
+
+ ConfigBlkTblHdrSize = (UINT32)(sizeof (CONFIG_BLOCK_TABLE_HEADER));
+ ConfigBlkTblAddrPtr = (CONFIG_BLOCK_TABLE_HEADER *)ConfigBlockTableAddress;
+ NumOfBlocks = ConfigBlkTblAddrPtr->NumberOfBlocks;
+
+ ConfigBlkOffset = 0;
+ for (OffsetIndex = 0; OffsetIndex < NumOfBlocks; OffsetIndex++) {
+ if ((ConfigBlkTblHdrSize + ConfigBlkOffset) > (ConfigBlkTblAddrPtr->Header.GuidHob.Header.HobLength)) {
+ break;
+ }
+ TempConfigBlk = (CONFIG_BLOCK *)((UINTN)ConfigBlkTblAddrPtr + (UINTN)ConfigBlkTblHdrSize + (UINTN)ConfigBlkOffset);
+ if (CompareGuid (&(TempConfigBlk->Header.GuidHob.Name), ConfigBlockGuid)) {
+ *ConfigBlockAddress = (VOID *)TempConfigBlk;
+ return EFI_SUCCESS;
+ }
+ ConfigBlkOffset = ConfigBlkOffset + TempConfigBlk->Header.GuidHob.Header.HobLength;
+ }
+ DEBUG ((DEBUG_ERROR, "Could not find the config block.\n"));
+ return EFI_NOT_FOUND;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf new file mode 100644 index 0000000000..f544c75a6c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf @@ -0,0 +1,35 @@ +## @file
+# Component INF file for the BaseConfigBlock library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseConfigBlockLib
+FILE_GUID = 1EC07EA8-7808-4e06-9D79-309AE331D2D5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseConfigBlockLib.c
+
+[LibraryClasses]
+DebugLib
+BaseMemoryLib
+MemoryAllocationLib
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c new file mode 100644 index 0000000000..98ff9e3410 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.c @@ -0,0 +1,93 @@ +/** @file
+ This file is BaseSiConfigBlockLib library is used to add config blocks
+ to config block header.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <ConfigBlock.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/SiConfigBlockLib.h>
+
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ )
+{
+ UINT16 TotalBlockSize;
+ UINT16 BlockCount;
+
+ TotalBlockSize = 0;
+ for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
+ TotalBlockSize += (UINT32) ComponentBlocks[BlockCount].Size;
+ DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize));
+ }
+
+ return TotalBlockSize;
+}
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ )
+{
+ UINT16 BlockCount;
+ VOID *ConfigBlockPointer;
+ CONFIG_BLOCK ConfigBlockBuf;
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Initialize ConfigBlockPointer to NULL
+ //
+ ConfigBlockPointer = NULL;
+ //
+ // Loop to identify each config block from ComponentBlocks[] Table and add each of them
+ //
+ for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
+ ZeroMem (&ConfigBlockBuf,sizeof(CONFIG_BLOCK));
+ CopyMem (&(ConfigBlockBuf.Header.GuidHob.Name), ComponentBlocks[BlockCount].Guid, sizeof (EFI_GUID));
+ ConfigBlockBuf.Header.GuidHob.Header.HobLength = ComponentBlocks[BlockCount].Size;
+ ConfigBlockBuf.Header.Revision = ComponentBlocks[BlockCount].Revision;
+ ConfigBlockPointer = (VOID *)&ConfigBlockBuf;
+ Status = AddConfigBlock ((VOID *)ConfigBlockTableAddress, (VOID *)&ConfigBlockPointer);
+ ASSERT_EFI_ERROR (Status);
+ ComponentBlocks[BlockCount].LoadDefault (ConfigBlockPointer);
+ }
+ return Status;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf new file mode 100644 index 0000000000..5961b1a6b2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf @@ -0,0 +1,40 @@ +## @file
+# Component description file for the BaseSiConfigBlockLib library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseSiConfigBlockLib
+FILE_GUID = 6C068D0F-F48E-48CB-B369-433E507AF4A2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SiConfigBlockLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseSiConfigBlockLib.c
+
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.c new file mode 100644 index 0000000000..ea85be4a11 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.c @@ -0,0 +1,314 @@ +/** @file
+ Boot service DXE ASL update library implementation.
+
+ These functions in this file can be called during DXE and cannot be called during runtime
+ or in SMM which should use a RT or SMM library.
+
+ This library uses the ACPI Support protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Library/AslUpdateLib.h>
+
+//
+// Function implemenations
+//
+static EFI_ACPI_SDT_PROTOCOL *mAcpiSdt = NULL;
+static EFI_ACPI_TABLE_PROTOCOL *mAcpiTable = NULL;
+
+/**
+ Initialize the ASL update library state.
+ This must be called prior to invoking other library functions.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+InitializeAslUpdateLib (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Locate ACPI tables
+ ///
+ Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **) &mAcpiSdt);
+ ASSERT_EFI_ERROR (Status);
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &mAcpiTable);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
+
+/**
+ This procedure will update immediate value assigned to a Name
+
+ @param[in] AslSignature - The signature of Operation Region that we want to update.
+ @param[in] Buffer - source of data to be written over original aml
+ @param[in] Length - length of data to be overwritten
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateNameAslCode (
+ IN UINT32 AslSignature,
+ IN VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_DESCRIPTION_HEADER *Table;
+ UINT8 *CurrPtr;
+ UINT32 *Signature;
+ UINT8 *DsdtPointer;
+ UINTN Handle;
+ UINT8 DataSize;
+
+ if (mAcpiTable == NULL) {
+ InitializeAslUpdateLib ();
+ if (mAcpiTable == NULL) {
+ return EFI_NOT_READY;
+ }
+ }
+
+ ///
+ /// Locate table with matching ID
+ ///
+ Handle = 0;
+ Status = LocateAcpiTableBySignature (
+ EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ (EFI_ACPI_DESCRIPTION_HEADER **) &Table,
+ &Handle
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ ///
+ /// Point to the beginning of the DSDT table
+ ///
+ CurrPtr = (UINT8 *) Table;
+
+ ///
+ /// Loop through the ASL looking for values that we must fix up.
+ ///
+ for (DsdtPointer = CurrPtr; DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); DsdtPointer++) {
+ ///
+ /// Get a pointer to compare for signature
+ ///
+ Signature = (UINT32 *) DsdtPointer;
+ ///
+ /// Check if this is the Device Object signature we are looking for
+ ///
+ if ((*Signature) == AslSignature) {
+ ///
+ /// Look for Name Encoding
+ ///
+ if (*(DsdtPointer-1) == AML_NAME_OP) {
+ ///
+ /// Check if size of new and old data is the same
+ ///
+ DataSize = *(DsdtPointer+4);
+ if ((Length == 1 && DataSize == 0xA) ||
+ (Length == 2 && DataSize == 0xB) ||
+ (Length == 4 && DataSize == 0xC)) {
+ CopyMem (DsdtPointer+5, Buffer, Length);
+ } else if (Length == 1 && ((*(UINT8*) Buffer) == 0 || (*(UINT8*) Buffer) == 1) && (DataSize == 0 || DataSize == 1)) {
+ CopyMem (DsdtPointer+4, Buffer, Length);
+ } else {
+ FreePool (Table);
+ return EFI_BAD_BUFFER_SIZE;
+ }
+ Status = mAcpiTable->UninstallAcpiTable (
+ mAcpiTable,
+ Handle
+ );
+ Handle = 0;
+ Status = mAcpiTable->InstallAcpiTable (
+ mAcpiTable,
+ Table,
+ Table->Length,
+ &Handle
+ );
+ FreePool (Table);
+ return Status;
+ }
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+
+/**
+ This function uses the ACPI SDT protocol to locate an ACPI table.
+ It is really only useful for finding tables that only have a single instance,
+ e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc.
+
+ @param[in] Signature - Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in, out] Table - Updated with a pointer to the table
+ @param[in, out] Handle - AcpiSupport protocol table handle for the table found
+ @param[in, out] Version - The version of the table desired
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+LocateAcpiTableBySignature (
+ IN UINT32 Signature,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ )
+{
+ EFI_STATUS Status;
+ INTN Index;
+ EFI_ACPI_TABLE_VERSION Version;
+ EFI_ACPI_DESCRIPTION_HEADER *OrgTable;
+
+ if (mAcpiSdt == NULL) {
+ InitializeAslUpdateLib ();
+ if (mAcpiSdt == NULL) {
+ return EFI_NOT_READY;
+ }
+ }
+
+ ///
+ /// Locate table with matching ID
+ ///
+ Version = 0;
+ Index = 0;
+ do {
+ Status = mAcpiSdt->GetAcpiTable (Index, (EFI_ACPI_SDT_HEADER **)&OrgTable, &Version, Handle);
+ if (Status == EFI_NOT_FOUND) {
+ break;
+ }
+ ASSERT_EFI_ERROR (Status);
+ Index++;
+ } while (OrgTable->Signature != Signature);
+
+ if (Status != EFI_NOT_FOUND) {
+ *Table = AllocateCopyPool (OrgTable->Length, OrgTable);
+ ASSERT (*Table);
+ }
+
+ ///
+ /// If we found the table, there will be no error.
+ ///
+ return Status;
+}
+
+/**
+ This function uses the ACPI SDT protocol to locate an ACPI SSDT table.
+
+ @param[in] TableId - Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in] TableIdSize - Length of the TableId to match. Table ID are 8 bytes long, this function
+ will consider it a match if the first TableIdSize bytes match
+ @param[in, out] Table - Updated with a pointer to the table
+ @param[in, out] Handle - AcpiSupport protocol table handle for the table found
+ @param[in, out] Version - See AcpiSupport protocol, GetAcpiTable function for use
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+LocateAcpiTableByOemTableId (
+ IN UINT8 *TableId,
+ IN UINT8 TableIdSize,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ )
+{
+ EFI_STATUS Status;
+ INTN Index;
+ EFI_ACPI_TABLE_VERSION Version;
+ EFI_ACPI_DESCRIPTION_HEADER *OrgTable;
+
+ if (mAcpiSdt == NULL) {
+ InitializeAslUpdateLib ();
+ if (mAcpiSdt == NULL) {
+ return EFI_NOT_READY;
+ }
+ }
+ ///
+ /// Locate table with matching ID
+ ///
+ Version = 0;
+ Index = 0;
+ do {
+ Status = mAcpiSdt->GetAcpiTable (Index, (EFI_ACPI_SDT_HEADER **)&OrgTable, &Version, Handle);
+ if (Status == EFI_NOT_FOUND) {
+ break;
+ }
+ ASSERT_EFI_ERROR (Status);
+ Index++;
+ } while (CompareMem (&(OrgTable->OemTableId), TableId, TableIdSize));
+
+ if (Status != EFI_NOT_FOUND) {
+ *Table = AllocateCopyPool (OrgTable->Length, OrgTable);
+ ASSERT (*Table);
+ }
+
+ ///
+ /// If we found the table, there will be no error.
+ ///
+ return Status;
+}
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum
+ @param[in] Size Number of bytes to checksum
+ @param[in] ChecksumOffset Offset to place the checksum result in
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AcpiChecksum (
+ IN VOID *Buffer,
+ IN UINTN Size,
+ IN UINTN ChecksumOffset
+ )
+{
+ UINT8 Sum;
+ UINT8 *Ptr;
+
+ Sum = 0;
+ ///
+ /// Initialize pointer
+ ///
+ Ptr = Buffer;
+
+ ///
+ /// set checksum to 0 first
+ ///
+ Ptr[ChecksumOffset] = 0;
+
+ ///
+ /// add all content of buffer
+ ///
+ while (Size--) {
+ Sum = (UINT8) (Sum + (*Ptr++));
+ }
+ ///
+ /// set checksum
+ ///
+ Ptr = Buffer;
+ Ptr[ChecksumOffset] = (UINT8) (0xff - Sum + 1);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf new file mode 100644 index 0000000000..0b24bbe71e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf @@ -0,0 +1,47 @@ +## @file
+# Provides services to update ASL tables.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeAslUpdateLib
+FILE_GUID = 8621697D-4E3A-4bf2-ADB0-3E2FF06559CA
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = AslUpdateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PcdLib
+BaseMemoryLib
+UefiLib
+MemoryAllocationLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+DxeAslUpdateLib.c
+
+
+[Protocols]
+gEfiAcpiTableProtocolGuid ## CONSUMES
+gEfiAcpiSdtProtocolGuid ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.c b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.c new file mode 100644 index 0000000000..834315d236 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.c @@ -0,0 +1,131 @@ +/** @file
+ Boot service DXE ASL update library implementation.
+
+ These functions in this file can be called during DXE and cannot be called during runtime
+ or in SMM which should use a RT or SMM library.
+
+ This library uses the ACPI Support protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiSpec.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Library/AslUpdateLib.h>
+
+//
+// Function implemenations
+//
+
+/**
+ Initialize the ASL update library state.
+ This must be called prior to invoking other library functions.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+InitializeAslUpdateLib (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This procedure will update immediate value assigned to a Name
+
+ @param[in] AslSignature - The signature of Operation Region that we want to update.
+ @param[in] Buffer - source of data to be written over original aml
+ @param[in] Length - length of data to be overwritten
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateNameAslCode (
+ IN UINT32 AslSignature,
+ IN VOID *Buffer,
+ IN UINTN Length
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function uses the ACPI SDT protocol to locate an ACPI table.
+ It is really only useful for finding tables that only have a single instance,
+ e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc.
+
+ @param[in] Signature - Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in, out] Table - Updated with a pointer to the table
+ @param[in, out] Handle - AcpiSupport protocol table handle for the table found
+ @param[in, out] Version - The version of the table desired
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+LocateAcpiTableBySignature (
+ IN UINT32 Signature,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This function uses the ACPI SDT protocol to locate an ACPI SSDT table.
+
+ @param[in] TableId - Pointer to an ASCII string containing the OEM Table ID from the ACPI table header
+ @param[in] TableIdSize - Length of the TableId to match. Table ID are 8 bytes long, this function
+ will consider it a match if the first TableIdSize bytes match
+ @param[in, out] Table - Updated with a pointer to the table
+ @param[in, out] Handle - AcpiSupport protocol table handle for the table found
+ @param[in, out] Version - See AcpiSupport protocol, GetAcpiTable function for use
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+LocateAcpiTableByOemTableId (
+ IN UINT8 *TableId,
+ IN UINT8 TableIdSize,
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table,
+ IN OUT UINTN *Handle
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum
+ @param[in] Size Number of bytes to checksum
+ @param[in] ChecksumOffset Offset to place the checksum result in
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AcpiChecksum (
+ IN VOID *Buffer,
+ IN UINTN Size,
+ IN UINTN ChecksumOffset
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.inf new file mode 100644 index 0000000000..3805dbf1dd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdateLibNull.inf @@ -0,0 +1,37 @@ +## @file
+# Provides services to update ASL tables.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeAslUpdateLibNull
+FILE_GUID = C7A3725F-6146-4FAB-B2EF-B4CED222DA52
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = AslUpdateLib
+
+
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+DxeAslUpdateLibNull.c
+
+
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c new file mode 100644 index 0000000000..3688872019 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.c @@ -0,0 +1,37 @@ +/** @file
+ This file contains routines that get PCI Express Address
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+ )
+{
+ ASSERT ((Bus <= 0xFF) && (Device <= 0x1F) && (Function <= 0x7));
+
+ return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12));
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf new file mode 100644 index 0000000000..24cae56d04 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciLib.inf @@ -0,0 +1,47 @@ +## @file
+# Component description file for the PeiDxeSmmMmPciLib
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmMmPciLib
+FILE_GUID = D03D6670-A032-11E2-9E96-0800200C9A66
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = MmPciLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+PcdLib
+DebugLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+
+[Sources]
+PeiDxeSmmMmPciLib.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c new file mode 100644 index 0000000000..282f774831 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c @@ -0,0 +1,366 @@ +/** @file
+ Implementation of Fsp PCH Policy Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+
+#include <CpuAccess.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <FspEas.h>
+
+/**
+ Performs FSP CPU PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n"));
+
+ //
+ // Locate SiPreMemPolicyPpi
+ //
+ SiPreMemPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclockingPreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ ///
+ ///Test RC Policies
+ ///
+
+ ///
+ ///
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n"));
+
+ //
+ // Overclocking PreMem policies
+ //
+ FspmUpd->FspmConfig.OcSupport = (UINT8) CpuOverClockingPreMemConfig->OcSupport;
+ FspmUpd->FspmConfig.OcLock = (UINT8) CpuOverClockingPreMemConfig->OcLock;
+ FspmUpd->FspmConfig.CoreMaxOcRatio = (UINT8) CpuOverClockingPreMemConfig->CoreMaxOcRatio;
+ FspmUpd->FspmConfig.CoreVoltageMode = (UINT8) CpuOverClockingPreMemConfig->CoreVoltageMode;
+ FspmUpd->FspmConfig.RingMinOcRatio = (UINT8) CpuOverClockingPreMemConfig->RingMinOcRatio;
+ FspmUpd->FspmConfig.RingMaxOcRatio = (UINT8) CpuOverClockingPreMemConfig->RingMaxOcRatio;
+ FspmUpd->FspmConfig.CoreVoltageOverride = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOverride;
+ FspmUpd->FspmConfig.CoreVoltageAdaptive = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageAdaptive;
+ FspmUpd->FspmConfig.CoreVoltageOffset = (UINT16) CpuOverClockingPreMemConfig->CoreVoltageOffset;
+ FspmUpd->FspmConfig.CorePllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->CorePllVoltageOffset;
+ FspmUpd->FspmConfig.GtPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->GtPllVoltageOffset;
+ FspmUpd->FspmConfig.RingPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->RingPllVoltageOffset;
+ FspmUpd->FspmConfig.SaPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->SaPllVoltageOffset;
+ FspmUpd->FspmConfig.McPllVoltageOffset = (UINT8) CpuOverClockingPreMemConfig->McPllVoltageOffset;
+ FspmUpd->FspmConfig.Avx2RatioOffset = (UINT8) CpuOverClockingPreMemConfig->Avx2RatioOffset;
+ FspmUpd->FspmConfig.BclkAdaptiveVoltage = (UINT8) CpuOverClockingPreMemConfig->BclkAdaptiveVoltage;
+
+ //
+ // Cpu Config Lib policies
+ //
+ FspmUpd->FspmConfig.HyperThreading = (UINT8) CpuConfigLibPreMemConfig->HyperThreading;
+ FspmUpd->FspmConfig.BootFrequency = (UINT8) CpuConfigLibPreMemConfig->BootFrequency;
+ FspmUpd->FspmConfig.ActiveCoreCount = (UINT8) CpuConfigLibPreMemConfig->ActiveCoreCount;
+ FspmUpd->FspmConfig.JtagC10PowerGateDisable = (UINT8) CpuConfigLibPreMemConfig->JtagC10PowerGateDisable;
+ FspmUpd->FspmConfig.FClkFrequency = (UINT8) CpuConfigLibPreMemConfig->FClkFrequency;
+ FspmUpd->FspmConfig.BistOnReset = (UINT8) CpuConfigLibPreMemConfig->BistOnReset;
+ FspmUpd->FspmConfig.VmxEnable = (UINT8) CpuConfigLibPreMemConfig->VmxEnable;
+ FspmUpd->FspmConfig.CpuRatioOverride = (UINT8) CpuConfigLibPreMemConfig->CpuRatioOverride;
+ FspmUpd->FspmConfig.CpuRatio = (UINT8) CpuConfigLibPreMemConfig->CpuRatio;
+ FspmUpd->FspmConfig.PeciSxReset = (UINT8) CpuConfigLibPreMemConfig->PeciSxReset;
+ FspmUpd->FspmConfig.PeciC10Reset = (UINT8) CpuConfigLibPreMemConfig->PeciC10Reset;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine is used to search SMRAM and get SmramCpuData point.
+
+ @retval SmramCpuData - The pointer of CPU information in SMRAM.
+ @retval NULL - Unable to find the CPU information.
+ **/
+
+STATIC
+SMRAM_CPU_DATA *
+GetSmmCpuData(
+ VOID
+ )
+{
+ UINT32 Address;
+ SMRAM_CPU_DATA *SmramCpuData;
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_STATUS Status;
+ UINT32 TsegBase = 0;
+ UINT32 TsegSize = 0;
+
+ //
+ // Find TSEG Base using Fsp Resource Descriptor
+ //
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
+ if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED)
+ && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)
+ && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)
+ && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobTsegGuid))) {
+
+ TsegBase = (UINT32)Hob.ResourceDescriptor->PhysicalStart;
+ TsegSize = (UINT32)Hob.ResourceDescriptor->ResourceLength;
+ DEBUG((DEBUG_INFO, "Found gFspReservedMemoryResourceHobTsegGuid\n"));
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+
+ ///
+ /// Search SMRAM on page alignment for the SMMNVS signature
+ ///
+ if(TsegBase && TsegSize ){
+ for (Address = (TsegBase + TsegSize - EFI_PAGE_SIZE); Address >= TsegBase; Address -= EFI_PAGE_SIZE ) {
+ SmramCpuData = (SMRAM_CPU_DATA *) (UINTN) Address;
+ if (CompareGuid(&SmramCpuData->HeaderGuid, &gSmramCpuDataHeaderGuid)) {
+ return SmramCpuData;
+ }
+ }
+ }
+
+ DEBUG((DEBUG_WARN, "SmramCpuData not found\n"));
+ return NULL;
+}
+
+/**
+ Performs FSP CPU PEI Policy post memory initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+ CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
+ CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig;
+ CPU_TEST_CONFIG *CpuTestConfig;
+ CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig;
+ UINTN Index;
+ SMRAM_CPU_DATA *SmramCpuData;
+ UINT32 S3BspMtrrTablePointer;
+ UINT32 CpuS3ResumeDataPointer;
+ EFI_BOOT_MODE BootMode;
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n"));
+ //
+ // Locate gSiPolicyPpiGuid
+ //
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomConfigGuid, (VOID *) &CpuPowerMgmtCustomConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (VOID *) &CpuTestConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfigGuid, (VOID *) &CpuPowerMgmtTestConfig);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Production RC Policies
+ //
+
+ CopyMem ((VOID *)&(FspsUpd->FspsConfig.CpuConfig), (VOID *)&(((CPU_CONFIG_UNION *)CpuConfig)->CpuConfigFsp.Data), sizeof (UINT32));
+ FspsUpd->FspsConfig.MicrocodePatchAddress = CpuConfig->MicrocodePatchAddress;
+
+ FspsUpd->FspsConfig.TurboMode = (UINT8) CpuPowerMgmtBasicConfig->TurboMode;
+
+ ///
+ ///Test RC Policies
+ ///
+ FspsUpd->FspsTestConfig.MlcStreamerPrefetcher = (UINT8) CpuTestConfig->MlcStreamerPrefetcher;
+ FspsUpd->FspsTestConfig.MlcSpatialPrefetcher = (UINT8) CpuTestConfig->MlcSpatialPrefetcher;
+ FspsUpd->FspsTestConfig.MonitorMwaitEnable = (UINT8) CpuTestConfig->MonitorMwaitEnable;
+ FspsUpd->FspsTestConfig.DebugInterfaceEnable = (UINT8) CpuTestConfig->DebugInterfaceEnable;
+ FspsUpd->FspsTestConfig.DebugInterfaceLockEnable = (UINT8) CpuTestConfig->DebugInterfaceLockEnable;
+ FspsUpd->FspsTestConfig.ApIdleManner = (UINT8) CpuTestConfig->ApIdleManner;
+ FspsUpd->FspsTestConfig.ApHandoffManner = (UINT8) CpuTestConfig->ApHandoffManner;
+ FspsUpd->FspsTestConfig.ProcTraceOutputScheme = (UINT8) CpuTestConfig->ProcTraceOutputScheme;
+ FspsUpd->FspsTestConfig.ProcTraceEnable = (UINT8) CpuTestConfig->ProcTraceEnable;
+ FspsUpd->FspsTestConfig.ProcTraceMemSize = (UINT8) CpuTestConfig->ProcTraceMemSize;
+ FspsUpd->FspsTestConfig.VoltageOptimization = (UINT8) CpuTestConfig->VoltageOptimization;
+
+
+ FspsUpd->FspsTestConfig.OneCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->OneCoreRatioLimit;
+ FspsUpd->FspsTestConfig.TwoCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->TwoCoreRatioLimit;
+ FspsUpd->FspsTestConfig.ThreeCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit;
+ FspsUpd->FspsTestConfig.FourCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->FourCoreRatioLimit;
+ FspsUpd->FspsTestConfig.FiveCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->FiveCoreRatioLimit;
+ FspsUpd->FspsTestConfig.SixCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->SixCoreRatioLimit;
+ FspsUpd->FspsTestConfig.SevenCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->SevenCoreRatioLimit;
+ FspsUpd->FspsTestConfig.EightCoreRatioLimit = (UINT8) CpuPowerMgmtBasicConfig->EightCoreRatioLimit;
+ FspsUpd->FspsTestConfig.Hwp = (UINT8) CpuPowerMgmtBasicConfig->Hwp;
+ FspsUpd->FspsTestConfig.HdcControl = (UINT8) CpuPowerMgmtBasicConfig->HdcControl;
+ FspsUpd->FspsTestConfig.PowerLimit1Time = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit1Time;
+ FspsUpd->FspsTestConfig.PowerLimit2 = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit2;
+ FspsUpd->FspsTestConfig.TurboPowerLimitLock = (UINT8) CpuPowerMgmtBasicConfig->TurboPowerLimitLock;
+ FspsUpd->FspsTestConfig.PowerLimit3Time = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Time;
+ FspsUpd->FspsTestConfig.PowerLimit3DutyCycle = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle;
+ FspsUpd->FspsTestConfig.PowerLimit3Lock = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit3Lock;
+ FspsUpd->FspsTestConfig.PowerLimit4Lock = (UINT8) CpuPowerMgmtBasicConfig->PowerLimit4Lock;
+ FspsUpd->FspsTestConfig.TccActivationOffset = (UINT8) CpuPowerMgmtBasicConfig->TccActivationOffset;
+ FspsUpd->FspsTestConfig.TccOffsetClamp = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetClamp;
+ FspsUpd->FspsTestConfig.TccOffsetLock = (UINT8) CpuPowerMgmtBasicConfig->TccOffsetLock;
+ FspsUpd->FspsTestConfig.PowerLimit1 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.PowerLimit2Power = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit2Power * 125);
+ FspsUpd->FspsTestConfig.PowerLimit3 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit3 * 125);
+ FspsUpd->FspsTestConfig.PowerLimit4 = (UINT32) (CpuPowerMgmtBasicConfig->PowerLimit4 * 125);
+ FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl = (UINT32) CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl;
+
+ FspsUpd->FspsTestConfig.NumberOfEntries = (UINT8) CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries;
+ FspsUpd->FspsTestConfig.Custom1PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time;
+ FspsUpd->FspsTestConfig.Custom2PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time;
+ FspsUpd->FspsTestConfig.Custom3PowerLimit1Time = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time;
+ FspsUpd->FspsTestConfig.Custom1TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio;
+ FspsUpd->FspsTestConfig.Custom2TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio;
+ FspsUpd->FspsTestConfig.Custom3TurboActivationRatio = (UINT8) CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio;
+ FspsUpd->FspsTestConfig.ConfigTdpLock = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpLock;
+ FspsUpd->FspsTestConfig.ConfigTdpBios = (UINT8) CpuPowerMgmtCustomConfig->ConfigTdpBios;
+ FspsUpd->FspsTestConfig.MaxRatio = (UINT16) CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio;
+ for (Index = 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries; Index++) {
+ FspsUpd->FspsTestConfig.StateRatio[Index] = (UINT16) CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index];
+ }
+ FspsUpd->FspsTestConfig.Custom1PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.Custom1PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125);
+ FspsUpd->FspsTestConfig.Custom2PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.Custom2PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125);
+ FspsUpd->FspsTestConfig.Custom3PowerLimit1 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125);
+ FspsUpd->FspsTestConfig.Custom3PowerLimit2 = (UINT32) (CpuPowerMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125);
+
+ FspsUpd->FspsTestConfig.Eist = (UINT8) CpuPowerMgmtTestConfig->Eist;
+ FspsUpd->FspsTestConfig.EnergyEfficientPState = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientPState;
+ FspsUpd->FspsTestConfig.EnergyEfficientTurbo = (UINT8) CpuPowerMgmtTestConfig->EnergyEfficientTurbo;
+ FspsUpd->FspsTestConfig.TStates = (UINT8) CpuPowerMgmtTestConfig->TStates;
+ FspsUpd->FspsTestConfig.BiProcHot = (UINT8) CpuPowerMgmtTestConfig->BiProcHot;
+ FspsUpd->FspsTestConfig.DisableProcHotOut = (UINT8) CpuPowerMgmtTestConfig->DisableProcHotOut;
+ FspsUpd->FspsTestConfig.ProcHotResponse = (UINT8) CpuPowerMgmtTestConfig->ProcHotResponse;
+ FspsUpd->FspsTestConfig.DisableVrThermalAlert = (UINT8) CpuPowerMgmtTestConfig->DisableVrThermalAlert;
+ FspsUpd->FspsTestConfig.AutoThermalReporting = (UINT8) CpuPowerMgmtTestConfig->AutoThermalReporting;
+ FspsUpd->FspsTestConfig.ThermalMonitor = (UINT8) CpuPowerMgmtTestConfig->ThermalMonitor;
+ FspsUpd->FspsTestConfig.Cx = (UINT8) CpuPowerMgmtTestConfig->Cx;
+ FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock = (UINT8) CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock;
+ FspsUpd->FspsTestConfig.C1e = (UINT8) CpuPowerMgmtTestConfig->C1e;
+ FspsUpd->FspsTestConfig.PkgCStateDemotion = (UINT8) CpuPowerMgmtTestConfig->PkgCStateDemotion;
+ FspsUpd->FspsTestConfig.PkgCStateUnDemotion = (UINT8) CpuPowerMgmtTestConfig->PkgCStateUnDemotion;
+ FspsUpd->FspsTestConfig.CStatePreWake = (UINT8) CpuPowerMgmtTestConfig->CStatePreWake;
+ FspsUpd->FspsTestConfig.TimedMwait = (UINT8) CpuPowerMgmtTestConfig->TimedMwait;
+ FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection = (UINT8) CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection;
+ FspsUpd->FspsTestConfig.PkgCStateLimit = (UINT8) CpuPowerMgmtTestConfig->PkgCStateLimit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit;
+ FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit = (UINT8) CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit;
+ FspsUpd->FspsTestConfig.PpmIrmSetting = (UINT8) CpuPowerMgmtTestConfig->PpmIrmSetting;
+ FspsUpd->FspsTestConfig.ProcHotLock = (UINT8) CpuPowerMgmtTestConfig->ProcHotLock;
+ FspsUpd->FspsTestConfig.RaceToHalt = (UINT8) CpuPowerMgmtTestConfig->RaceToHalt;
+ FspsUpd->FspsTestConfig.ConfigTdpLevel = (UINT8) CpuPowerMgmtTestConfig->ConfigTdpLevel;
+ FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl;
+ FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl = (UINT16) CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl;
+
+ Status = PeiServicesGetBootMode(&BootMode);
+ if ((Status == EFI_SUCCESS) && (BootMode == BOOT_ON_S3_RESUME)) {
+ SmramCpuData = GetSmmCpuData();
+ if (SmramCpuData != NULL) {
+ S3BspMtrrTablePointer = (UINT32) AllocateZeroPool(SmramCpuData->S3BspMtrrTableSize); //Add Null terminator
+ FspsUpd->FspsConfig.CpuS3ResumeMtrrData = S3BspMtrrTablePointer;
+ FspsUpd->FspsConfig.CpuS3ResumeMtrrDataSize = (UINT16) SmramCpuData->S3BspMtrrTableSize;
+ //
+ // Copy BSP MTRR table to UPD.
+ //
+ CopyMem((VOID*) S3BspMtrrTablePointer,
+ (UINT8 *) SmramCpuData + SmramCpuData->S3BspMtrrTableOffset,
+ SmramCpuData->S3BspMtrrTableSize);
+
+ CpuS3ResumeDataPointer = (UINT32) AllocateZeroPool(SmramCpuData->CpuPrivateDataSize);
+ FspsUpd->FspsTestConfig.CpuS3ResumeData = CpuS3ResumeDataPointer;
+ FspsUpd->FspsTestConfig.CpuS3ResumeDataSize = (UINT16) SmramCpuData->CpuPrivateDataSize;
+ //
+ // Copy CPU_PRIVATE_DATA to UPD.
+ //
+ CopyMem((VOID*) CpuS3ResumeDataPointer,
+ (UINT8 *) SmramCpuData + SmramCpuData->CpuPrivateDataOffset,
+ SmramCpuData->CpuPrivateDataSize);
+ } else {
+ //@todo Check if an assert can be handled cleanly
+ DEBUG((DEBUG_WARN, "Unable to initialize S3 data\n"));
+ }
+
+ }
+ ///
+ ///
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c new file mode 100644 index 0000000000..d97bf8be57 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c @@ -0,0 +1,129 @@ +/** @file
+ Implementation of Fsp Me Policy Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ Performs FSP ME PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+ ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n"));
+
+ //
+ // Locate gSiPreMemPolicyPpi
+ //
+ SiPreMemPolicy = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ FspmUpd->FspmConfig.HeciTimeouts = (UINT8) MePeiPreMemConfig->HeciTimeouts;
+
+ //
+ // Test policies
+ //
+ FspmUpd->FspmTestConfig.DidInitStat = (UINT8) MePeiPreMemConfig->DidInitStat;
+ FspmUpd->FspmTestConfig.DisableCpuReplacedPolling = (UINT8) MePeiPreMemConfig->DisableCpuReplacedPolling;
+ FspmUpd->FspmTestConfig.SendDidMsg = (UINT8) MePeiPreMemConfig->SendDidMsg;
+ FspmUpd->FspmTestConfig.DisableHeciRetry = (UINT8) MePeiPreMemConfig->DisableHeciRetry;
+ FspmUpd->FspmTestConfig.DisableMessageCheck = (UINT8) MePeiPreMemConfig->DisableMessageCheck;
+ FspmUpd->FspmTestConfig.SkipMbpHob = (UINT8) MePeiPreMemConfig->SkipMbpHob;
+
+ FspmUpd->FspmTestConfig.HeciCommunication2 = (UINT8) MePeiPreMemConfig->HeciCommunication2;
+ FspmUpd->FspmTestConfig.KtDeviceEnable = (UINT8) MePeiPreMemConfig->KtDeviceEnable;
+ FspmUpd->FspmTestConfig.IderDeviceEnable = (UINT8) MePeiPreMemConfig->IderDeviceEnable;
+
+
+ FspmUpd->FspmConfig.Heci1BarAddress = MePeiPreMemConfig->Heci1BarAddress;
+ FspmUpd->FspmConfig.Heci2BarAddress = MePeiPreMemConfig->Heci2BarAddress;
+ FspmUpd->FspmConfig.Heci3BarAddress = MePeiPreMemConfig->Heci3BarAddress;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP ME PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ ME_PEI_CONFIG *MePeiConfig;
+
+ DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n"));
+ //
+ // Locate gSiPolicyPpiGuid
+ //
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ FspsUpd->FspsConfig.Heci3Enabled = (UINT8) MePeiConfig->Heci3Enabled;
+ FspsUpd->FspsConfig.MeUnconfigOnRtcClear = (UINT8) MePeiConfig->MeUnconfigOnRtcClear;
+ FspsUpd->FspsConfig.MeUnconfigIsValid = (UINT8) MePeiConfig->MeUnconfigIsValid;
+
+ //
+ // Test policies
+ //
+ FspsUpd->FspsTestConfig.EndOfPostMessage = (UINT8) MePeiConfig->EndOfPostMessage;
+ FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci = (UINT8) MePeiConfig->DisableD0I3SettingForHeci;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c new file mode 100644 index 0000000000..b9329e4c8a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c @@ -0,0 +1,56 @@ +/** @file
+ Implementation of Fsp Misc UPD Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Locate system configuration variable
+ //
+ FspmUpd->FspmArchUpd.StackBase = (VOID *)(UINTN)(PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize) + PcdGet32(PcdFspReservedBufferSize)));
+ FspmUpd->FspmArchUpd.StackSize = PcdGet32(PcdFspTemporaryRamSize);
+
+ Status = PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode));
+ if (EFI_ERROR (Status)) {
+ FspmUpd->FspmArchUpd.BootMode = BOOT_WITH_FULL_CONFIGURATION;
+ }
+
+ FspmUpd->FspmArchUpd.BootLoaderTolumSize = 0x0;
+
+ //
+ // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
+ //
+ FspmUpd->FspmArchUpd.NvsBufferPtr = NULL;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c new file mode 100644 index 0000000000..3f7e297c0b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c @@ -0,0 +1,713 @@ +/** @file
+ Implementation of Fsp PCH Policy Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+ PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig;
+ PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
+ PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
+ PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;
+ PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
+ PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+ PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig;
+ PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
+ PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
+ PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig;
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n"));
+ //
+ // Locate PchPreMemPolicyPpi
+ //
+ SiPreMemPolicy = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gTraceHubPreMemConfigGuid, (VOID *) &TraceHubPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPreMemConfigGuid, (VOID *) &HsioPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Update PCIE RP policies
+ //
+ FspmUpd->FspmConfig.PcieRpEnableMask = PcieRpPreMemConfig->RpEnabledMask & ((1 << KBL_PCH_H_PCIE_MAX_ROOT_PORTS) - 1);
+
+ //
+ // Update TraceHub policies
+ //
+ FspmUpd->FspmConfig.EnableTraceHub = ((UINT8)TraceHubPreMemConfig->EnableMode == 0) ? 0 : 1;
+ FspmUpd->FspmConfig.TraceHubMemReg0Size = (UINT32)TraceHubPreMemConfig->MemReg0Size;
+ FspmUpd->FspmConfig.TraceHubMemReg1Size = (UINT32)TraceHubPreMemConfig->MemReg1Size;
+
+ //
+ // Update Smbus policies
+ //
+ FspmUpd->FspmConfig.SmbusEnable = (UINT8)SmbusPreMemConfig->Enable;
+ FspmUpd->FspmConfig.SmbusArpEnable = (UINT8)SmbusPreMemConfig->ArpEnable;
+ FspmUpd->FspmTestConfig.SmbusDynamicPowerGating = (UINT8)SmbusPreMemConfig->DynamicPowerGating;
+ FspmUpd->FspmTestConfig.SmbusSpdWriteDisable = (UINT8)SmbusPreMemConfig->SpdWriteDisable;
+ FspmUpd->FspmConfig.PchSmbusIoBase = (UINT16)SmbusPreMemConfig->SmbusIoBase;
+ FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses = (UINT8)SmbusPreMemConfig->NumRsvdSmbusAddresses;
+ FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr = (UINT32)SmbusPreMemConfig->RsvdSmbusAddressTable;
+
+ //
+ // Update Dci policies
+ //
+ FspmUpd->FspmTestConfig.PchDciEn = (UINT8)DciPreMemConfig->DciEn;
+
+ //
+ // Update HPET policies
+ //
+ FspmUpd->FspmConfig.PchHpetEnable = (UINT8)HpetPreMemConfig->Enable;
+ FspmUpd->FspmConfig.PchHpetBdfValid = (UINT8)HpetPreMemConfig->BdfValid;
+ FspmUpd->FspmConfig.PchHpetBusNumber = (UINT8)HpetPreMemConfig->BusNumber;
+ FspmUpd->FspmConfig.PchHpetDeviceNumber = (UINT8)HpetPreMemConfig->DeviceNumber;
+ FspmUpd->FspmConfig.PchHpetFunctionNumber = (UINT8)HpetPreMemConfig->FunctionNumber;
+ FspmUpd->FspmConfig.PchHpetBase = (UINT32)HpetPreMemConfig->Base;
+
+ //
+ // Update HSIO PCIE policies
+ //
+ FspmUpd->FspmConfig.PchPmPciePllSsc = (UINT8)HsioPciePreMemConfig->PciePllSsc;
+ for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) {
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable;
+ FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable;
+ FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] = (UINT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0;
+ }
+
+ //
+ // Update HSIO SATA policies
+ //
+ for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index ++) {
+ FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable;
+ FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag;
+ FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable;
+ FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag;
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable;
+ FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable;
+ FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] = (UINT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph;
+ }
+
+ //
+ // Update HSIO policies
+ //
+ FspmUpd->FspmTestConfig.ChipsetInitMessage = (UINT8)HsioPreMemConfig->ChipsetInitMessage;
+ FspmUpd->FspmTestConfig.BypassPhySyncReset = (UINT8)HsioPreMemConfig->BypassPhySyncReset;
+
+ //
+ // Update LPC policies
+ //
+ FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding = (UINT8)LpcPreMemConfig->EnhancePort8xhDecoding;
+
+ //
+ // Update Pch General Premem policies
+ //
+ FspmUpd->FspmConfig.PchAcpiBase = (UINT16)PchGeneralPreMemConfig->AcpiBase;
+ FspmUpd->FspmConfig.PchPort80Route = (UINT8)PchGeneralPreMemConfig->Port80Route;
+
+ //
+ // Update Wdt policies
+ //
+ FspmUpd->FspmTestConfig.WdtDisableAndLock = (UINT8)WdtPreMemConfig->DisableAndLock;
+
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ SI_POLICY_PPI *SiPolicy;
+ PCH_LAN_CONFIG *LanConfig;
+ PCH_HDAUDIO_CONFIG *HdAudioConfig;
+ PCH_SCS_CONFIG *ScsConfig;
+ PCH_ISH_CONFIG *IshConfig;
+ PCH_SPI_CONFIG *SpiConfig;
+ PCH_SATA_CONFIG *SataConfig;
+ PCH_USB_CONFIG *UsbConfig;
+ PCH_SERIAL_IO_CONFIG *SerialIoConfig;
+ PCH_INTERRUPT_CONFIG *InterruptConfig;
+ PCH_LOCK_DOWN_CONFIG *LockDownConfig;
+ PCH_CIO2_CONFIG *Cio2Config;
+ PCH_PCIE_CONFIG *PcieRpConfig;
+ PCH_DMI_CONFIG *DmiConfig;
+ PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
+ PCH_IOAPIC_CONFIG *IoApicConfig;
+ PCH_P2SB_CONFIG *P2sbConfig;
+ PCH_GENERAL_CONFIG *PchGeneralConfig;
+ PCH_PM_CONFIG *PmConfig;
+ PCH_PORT61H_SMM_CONFIG *Port61hConfig;
+ PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig;
+ PCH_THERMAL_CONFIG *PchThermalConfig;
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));
+ //
+ // Locate SiPolicyPpi
+ //
+ SiPolicy = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSpiConfigGuid, (VOID *) &SpiConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gCio2ConfigGuid, (VOID *) &Cio2Config);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *) &P2sbConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPort61ConfigGuid, (VOID *) &Port61hConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &PchSerialIrqConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &PchThermalConfig);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Update LAN policies
+ //
+ FspsUpd->FspsConfig.PchLanEnable = (UINT8)LanConfig->Enable;
+ FspsUpd->FspsConfig.PchLanLtrEnable = (UINT8)LanConfig->LtrEnable;
+ FspsUpd->FspsConfig.PchLanK1OffEnable = (UINT8)LanConfig->K1OffEnable;
+ FspsUpd->FspsConfig.PchLanClkReqSupported = (UINT8)LanConfig->ClkReqSupported;
+ FspsUpd->FspsConfig.PchLanClkReqNumber = (UINT8)LanConfig->ClkReqNumber;
+
+ //
+ // Update HDA policies
+ //
+ FspsUpd->FspsConfig.PchHdaEnable = (UINT8)HdAudioConfig->Enable;
+ FspsUpd->FspsConfig.PchHdaDspEnable = (UINT8)HdAudioConfig->DspEnable;
+ FspsUpd->FspsConfig.PchHdaIoBufferOwnership = (UINT8)HdAudioConfig->IoBufferOwnership;
+
+ FspsUpd->FspsConfig.PchHdaPme = (UINT8)HdAudioConfig->Pme;
+ FspsUpd->FspsConfig.PchHdaIoBufferVoltage = (UINT8)HdAudioConfig->IoBufferVoltage;
+ FspsUpd->FspsConfig.PchHdaVcType = (UINT8)HdAudioConfig->VcType;
+ FspsUpd->FspsConfig.PchHdaLinkFrequency = (UINT8)HdAudioConfig->HdAudioLinkFrequency;
+ FspsUpd->FspsConfig.PchHdaIDispLinkFrequency = (UINT8)HdAudioConfig->IDispLinkFrequency;
+ FspsUpd->FspsConfig.PchHdaIDispLinkTmode = (UINT8)HdAudioConfig->IDispLinkTmode;
+ FspsUpd->FspsConfig.PchHdaDspUaaCompliance = (UINT8)HdAudioConfig->DspUaaCompliance;
+ FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect = (UINT8)HdAudioConfig->IDispCodecDisconnect;
+ FspsUpd->FspsConfig.PchHdaDspEndpointDmic = (UINT8)HdAudioConfig->DspEndpointDmic;
+ FspsUpd->FspsConfig.PchHdaDspEndpointBluetooth = (UINT8)HdAudioConfig->DspEndpointBluetooth;
+ FspsUpd->FspsConfig.PchHdaDspEndpointI2s = (UINT8)HdAudioConfig->DspEndpointI2s;
+ FspsUpd->FspsConfig.PchHdaDspFeatureMask = (UINT32)HdAudioConfig->DspFeatureMask;
+ FspsUpd->FspsTestConfig.PchHdaResetWaitTimer = (UINT16)HdAudioConfig->ResetWaitTimer;
+ FspsUpd->FspsConfig.PchHdaVerbTableEntryNum = HdAudioConfig->VerbTableEntryNum;
+ FspsUpd->FspsConfig.PchHdaVerbTablePtr = HdAudioConfig->VerbTablePtr;
+
+ //
+ // Update CIO2 policies
+ //
+ FspsUpd->FspsConfig.PchCio2Enable = (UINT8)Cio2Config->DeviceEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortATermOvrEnable = (UINT8)Cio2Config->SkyCamPortATermOvrEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortBTermOvrEnable = (UINT8)Cio2Config->SkyCamPortBTermOvrEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortCTermOvrEnable = (UINT8)Cio2Config->SkyCamPortCTermOvrEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortDTermOvrEnable = (UINT8)Cio2Config->SkyCamPortDTermOvrEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortATrimEnable = (UINT8)Cio2Config->PortATrimEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortBTrimEnable = (UINT8)Cio2Config->PortBTrimEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortCTrimEnable = (UINT8)Cio2Config->PortCTrimEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortDTrimEnable = (UINT8)Cio2Config->PortDTrimEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortACtleEnable = (UINT8)Cio2Config->PortACtleEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortBCtleEnable = (UINT8)Cio2Config->PortBCtleEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortCDCtleEnable = (UINT8)Cio2Config->PortCDCtleEnable;
+ FspsUpd->FspsConfig.PchSkyCamPortACtleCapValue = (UINT8)Cio2Config->PortACtleCapValue;
+ FspsUpd->FspsConfig.PchSkyCamPortBCtleCapValue = (UINT8)Cio2Config->PortBCtleCapValue;
+ FspsUpd->FspsConfig.PchSkyCamPortCDCtleCapValue = (UINT8)Cio2Config->PortCDCtleCapValue;
+ FspsUpd->FspsConfig.PchSkyCamPortACtleResValue = (UINT8)Cio2Config->PortACtleResValue;
+ FspsUpd->FspsConfig.PchSkyCamPortBCtleResValue = (UINT8)Cio2Config->PortBCtleResValue;
+ FspsUpd->FspsConfig.PchSkyCamPortCDCtleResValue = (UINT8)Cio2Config->PortCDCtleResValue;
+ FspsUpd->FspsConfig.PchSkyCamPortAClkTrimValue = (UINT8)Cio2Config->PortAClkTrimValue;
+ FspsUpd->FspsConfig.PchSkyCamPortBClkTrimValue = (UINT8)Cio2Config->PortBClkTrimValue;
+ FspsUpd->FspsConfig.PchSkyCamPortCClkTrimValue = (UINT8)Cio2Config->PortCClkTrimValue;
+ FspsUpd->FspsConfig.PchSkyCamPortDClkTrimValue = (UINT8)Cio2Config->PortDClkTrimValue;
+ FspsUpd->FspsConfig.PchSkyCamPortADataTrimValue = (UINT16)Cio2Config->PortADataTrimValue;
+ FspsUpd->FspsConfig.PchSkyCamPortBDataTrimValue = (UINT16)Cio2Config->PortBDataTrimValue;
+ FspsUpd->FspsConfig.PchSkyCamPortCDDataTrimValue = (UINT16)Cio2Config->PortCDDataTrimValue;
+
+ //
+ // Update SCS policies
+ //
+ FspsUpd->FspsConfig.ScsEmmcEnabled = (UINT8)ScsConfig->ScsEmmcEnabled;
+ FspsUpd->FspsConfig.ScsEmmcHs400Enabled = (UINT8)ScsConfig->ScsEmmcHs400Enabled;
+ FspsUpd->FspsConfig.ScsSdCardEnabled = (UINT8)ScsConfig->ScsSdSwitch == 0 ? 0 : 1;
+ FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired = (UINT8)ScsConfig->ScsEmmcHs400TuningRequired;
+ FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid = (UINT8)ScsConfig->ScsEmmcHs400DllDataValid;
+ FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 = (UINT8)ScsConfig->ScsEmmcHs400RxStrobeDll1;
+ FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll = (UINT8)ScsConfig->ScsEmmcHs400TxDataDll;
+ FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength = (UINT8)ScsConfig->ScsEmmcHs400DriverStrength;
+
+ //
+ // Update ISH policies
+ //
+ FspsUpd->FspsConfig.PchIshEnable = (UINT8)IshConfig->Enable;
+ FspsUpd->FspsConfig.PchIshSpiGpioAssign = (UINT8)IshConfig->SpiGpioAssign;
+ FspsUpd->FspsConfig.PchIshUart0GpioAssign = (UINT8)IshConfig->Uart0GpioAssign;
+ FspsUpd->FspsConfig.PchIshUart1GpioAssign = (UINT8)IshConfig->Uart1GpioAssign;
+ FspsUpd->FspsConfig.PchIshI2c0GpioAssign = (UINT8)IshConfig->I2c0GpioAssign;
+ FspsUpd->FspsConfig.PchIshI2c1GpioAssign = (UINT8)IshConfig->I2c1GpioAssign;
+ FspsUpd->FspsConfig.PchIshI2c2GpioAssign = (UINT8)IshConfig->I2c2GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp0GpioAssign = (UINT8)IshConfig->Gp0GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp1GpioAssign = (UINT8)IshConfig->Gp1GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp2GpioAssign = (UINT8)IshConfig->Gp2GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp3GpioAssign = (UINT8)IshConfig->Gp3GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp4GpioAssign = (UINT8)IshConfig->Gp4GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp5GpioAssign = (UINT8)IshConfig->Gp5GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp6GpioAssign = (UINT8)IshConfig->Gp6GpioAssign;
+ FspsUpd->FspsConfig.PchIshGp7GpioAssign = (UINT8)IshConfig->Gp7GpioAssign;
+ FspsUpd->FspsConfig.PchIshPdtUnlock = (UINT8)IshConfig->PdtUnlock;
+
+ //
+ // Update SPI policies
+ //
+ FspsUpd->FspsConfig.ShowSpiController = (UINT8)SpiConfig->ShowSpiController;
+
+ //
+ // Update PCIE RP RootPort policies
+ //
+ for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) {
+ FspsUpd->FspsConfig.PcieRpHotPlug[Index] = (UINT8)PcieRpConfig->RootPort[Index].HotPlug;
+ FspsUpd->FspsConfig.PcieRpPmSci[Index] = (UINT8)PcieRpConfig->RootPort[Index].PmSci;
+ FspsUpd->FspsConfig.PcieRpExtSync[Index] = (UINT8)PcieRpConfig->RootPort[Index].ExtSync;
+ FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] = (UINT8)PcieRpConfig->RootPort[Index].TransmitterHalfSwing;
+ FspsUpd->FspsConfig.PcieRpClkReqSupport[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqSupported;
+ FspsUpd->FspsConfig.PcieRpClkReqNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqNumber;
+ FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] = (UINT8)PcieRpConfig->RootPort[Index].ClkReqDetect;
+ FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] = (UINT8)PcieRpConfig->RootPort[Index].AdvancedErrorReporting;
+ FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].UnsupportedRequestReport;
+ FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].FatalErrorReport;
+ FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].NoFatalErrorReport;
+ FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] = (UINT8)PcieRpConfig->RootPort[Index].CorrectableErrorReport;
+ FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnFatalError;
+ FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError;
+ FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] = (UINT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError;
+ FspsUpd->FspsConfig.PcieRpMaxPayload[Index] = (UINT8)PcieRpConfig->RootPort[Index].MaxPayload;
+ FspsUpd->FspsConfig.PcieRpDeviceResetPadActiveHigh[Index] = (UINT8)PcieRpConfig->RootPort[Index].DeviceResetPadActiveHigh;
+ FspsUpd->FspsConfig.PcieRpPcieSpeed[Index] = (UINT8)PcieRpConfig->RootPort[Index].PcieSpeed;
+ FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] = (UINT8)PcieRpConfig->RootPort[Index].Gen3EqPh3Method;
+ FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] = (UINT8)PcieRpConfig->RootPort[Index].PhysicalSlotNumber;
+ FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] = (UINT8)PcieRpConfig->RootPort[Index].CompletionTimeout;
+ FspsUpd->FspsConfig.PcieRpDeviceResetPad[Index] = (UINT32)PcieRpConfig->RootPort[Index].DeviceResetPad;
+ FspsUpd->FspsConfig.PcieRpAspm[Index] = (UINT8)PcieRpConfig->RootPort[Index].Aspm;
+ FspsUpd->FspsConfig.PcieRpL1Substates[Index] = (UINT8)PcieRpConfig->RootPort[Index].L1Substates;
+ FspsUpd->FspsConfig.PcieRpLtrEnable[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrEnable;
+ FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] = (UINT8)PcieRpConfig->RootPort[Index].LtrConfigLock;
+ FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency;
+ FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] = (UINT16)PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency;
+
+ FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode;
+ FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier;
+ FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue;
+
+ FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode;
+ FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index] = (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier;
+ FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue;
+
+ FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] = (UINT8)PcieRpConfig->RootPort[Index].SlotPowerLimitScale;
+ FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] = (UINT16)PcieRpConfig->RootPort[Index].SlotPowerLimitValue;
+ FspsUpd->FspsTestConfig.PcieRpUptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Uptp;
+ FspsUpd->FspsTestConfig.PcieRpDptp[Index] = (UINT8)PcieRpConfig->RootPort[Index].Dptp;
+ }
+
+ //
+ // Update PCIE RP EqPh3LaneParam policies
+ //
+ for (Index = 0; Index < KBL_PCH_H_PCIE_MAX_ROOT_PORTS; Index ++) {
+ FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cm;
+ FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] = (UINT8)PcieRpConfig->EqPh3LaneParam[Index].Cp;
+ }
+
+ //
+ // Update PCIE RP SwEqCoeffList policies
+ //
+ for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) {
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cm;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] = (UINT8)PcieRpConfig->SwEqCoeffList[Index].Cp;
+ }
+
+ //
+ // Update PCIE RP policies
+ //
+ FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode = (UINT8)PcieRpConfig->EnablePort8xhDecode;
+ FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex = (UINT8)PcieRpConfig->PchPciePort8xhDecodePortIndex;
+ FspsUpd->FspsConfig.PcieDisableRootPortClockGating = (UINT8)PcieRpConfig->DisableRootPortClockGating;
+ FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite = (UINT8)PcieRpConfig->EnablePeerMemoryWrite;
+ FspsUpd->FspsConfig.PcieAllowNoLtrIccPllShutdown = (UINT8)PcieRpConfig->AllowNoLtrIccPllShutdown;
+ FspsUpd->FspsConfig.PcieComplianceTestMode = (UINT8)PcieRpConfig->ComplianceTestMode;
+ FspsUpd->FspsConfig.PcieRpFunctionSwap = (UINT8)PcieRpConfig->RpFunctionSwap;
+ FspsUpd->FspsConfig.PcieDetectTimeoutMs = (UINT16)PcieRpConfig->DetectTimeoutMs;
+ FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = PcieRpConfig->PcieDeviceOverrideTablePtr;
+
+ //
+ // Update Sata Policies
+ //
+ FspsUpd->FspsConfig.SataEnable = (UINT8)SataConfig->Enable;
+ FspsUpd->FspsTestConfig.SataTestMode = (UINT8)SataConfig->TestMode;
+ FspsUpd->FspsConfig.SataSalpSupport = (UINT8)SataConfig->SalpSupport;
+ FspsUpd->FspsConfig.SataPwrOptEnable = (UINT8)SataConfig->PwrOptEnable;
+ FspsUpd->FspsConfig.EsataSpeedLimit = (UINT8)SataConfig->EsataSpeedLimit;
+ FspsUpd->FspsConfig.SataMode = (UINT8)SataConfig->SataMode;
+ FspsUpd->FspsConfig.SataSpeedLimit = (UINT8)SataConfig->SpeedLimit;
+
+ for (Index = 0; Index < PCH_MAX_SATA_PORTS; Index++) {
+ FspsUpd->FspsConfig.SataPortsEnable[Index] = (UINT8)SataConfig->PortSettings[Index].Enable;
+ FspsUpd->FspsConfig.SataPortsHotPlug[Index] = (UINT8)SataConfig->PortSettings[Index].HotPlug;
+ FspsUpd->FspsConfig.SataPortsInterlockSw[Index] = (UINT8)SataConfig->PortSettings[Index].InterlockSw;
+ FspsUpd->FspsConfig.SataPortsExternal[Index] = (UINT8)SataConfig->PortSettings[Index].External;
+ FspsUpd->FspsConfig.SataPortsSpinUp[Index] = (UINT8)SataConfig->PortSettings[Index].SpinUp;
+ FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] = (UINT8)SataConfig->PortSettings[Index].SolidStateDrive;
+ FspsUpd->FspsConfig.SataPortsDevSlp[Index] = (UINT8)SataConfig->PortSettings[Index].DevSlp;
+ FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] = (UINT8)SataConfig->PortSettings[Index].EnableDitoConfig;
+ FspsUpd->FspsConfig.SataPortsDmVal[Index] = (UINT8)SataConfig->PortSettings[Index].DmVal;
+ FspsUpd->FspsConfig.SataPortsDitoVal[Index] = (UINT16)SataConfig->PortSettings[Index].DitoVal;
+ FspsUpd->FspsConfig.SataPortsZpOdd[Index] = (UINT8)SataConfig->PortSettings[Index].ZpOdd;
+ }
+
+ FspsUpd->FspsConfig.SataRstRaidAlternateId = (UINT8)SataConfig->Rst.RaidDeviceId;
+ FspsUpd->FspsConfig.SataRstRaid0 = (UINT8)SataConfig->Rst.Raid0;
+ FspsUpd->FspsConfig.SataRstRaid1 = (UINT8)SataConfig->Rst.Raid1;
+ FspsUpd->FspsConfig.SataRstRaid10 = (UINT8)SataConfig->Rst.Raid10;
+ FspsUpd->FspsConfig.SataRstRaid5 = (UINT8)SataConfig->Rst.Raid5;
+ FspsUpd->FspsConfig.SataRstIrrt = (UINT8)SataConfig->Rst.Irrt;
+ FspsUpd->FspsConfig.SataRstOromUiBanner = (UINT8)SataConfig->Rst.OromUiBanner;
+ FspsUpd->FspsConfig.SataRstOromUiDelay = (UINT8)SataConfig->Rst.OromUiDelay;
+ FspsUpd->FspsConfig.SataRstHddUnlock = (UINT8)SataConfig->Rst.HddUnlock;
+ FspsUpd->FspsConfig.SataRstLedLocate = (UINT8)SataConfig->Rst.LedLocate;
+ FspsUpd->FspsConfig.SataRstIrrtOnly = (UINT8)SataConfig->Rst.IrrtOnly;
+ FspsUpd->FspsConfig.SataRstSmartStorage = (UINT8)SataConfig->Rst.SmartStorage;
+ FspsUpd->FspsConfig.SataRstOptaneMemory = (UINT8)SataConfig->Rst.OptaneMemory;
+
+ for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
+ FspsUpd->FspsConfig.SataRstPcieEnable[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].Enable;
+ FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort;
+ FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] = (UINT8)SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay;
+ }
+
+ //
+ // Update USB policies
+ //
+ FspsUpd->FspsConfig.PchDisableComplianceMode = (UINT8)UsbConfig->DisableComplianceMode;
+ for (Index = 0; Index < PCH_MAX_USB2_PORTS; Index++) {
+ FspsUpd->FspsConfig.PortUsb20Enable[Index] = (UINT8)UsbConfig->PortUsb20[Index].Enable;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb20[Index].OverCurrentPin;
+ FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Petxiset;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Txiset;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Predeemp;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = (UINT8)UsbConfig->PortUsb20[Index].Afe.Pehalfbit;
+ }
+ for (Index = 0; Index < PCH_MAX_USB3_PORTS; Index++) {
+ FspsUpd->FspsConfig.PortUsb30Enable[Index] = (UINT8)UsbConfig->PortUsb30[Index].Enable;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] = (UINT8)UsbConfig->PortUsb30[Index].OverCurrentPin;
+ FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable;
+ FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDeEmph;
+ FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable;
+ FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] = (UINT8)UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp;
+ }
+ FspsUpd->FspsConfig.SsicPortEnable = (UINT8)UsbConfig->SsicConfig.SsicPort[0].Enable;
+ FspsUpd->FspsConfig.XdciEnable = (UINT8)UsbConfig->XdciConfig.Enable;
+
+ //
+ // Update SerialIo policies
+ //
+ for (Index = 0; Index < PCH_SERIALIO_MAX_CONTROLLERS; Index++) {
+ FspsUpd->FspsConfig.SerialIoDevMode[Index] = (UINT8)SerialIoConfig->DevMode[Index];
+ }
+ for (Index = 0; Index < PCH_SERIALIO_MAX_I2C_CONTROLLERS; Index++) {
+ FspsUpd->FspsConfig.SerialIoI2cVoltage[Index] = (UINT8)SerialIoConfig->I2cVoltage[Index];
+ }
+ for (Index = 0; Index < PCH_SERIALIO_MAX_SPI_CONTROLLERS; Index++) {
+ FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] = (UINT8)SerialIoConfig->SpiCsPolarity[Index];
+ }
+ for (Index = 0; Index < PCH_SERIALIO_MAX_UART_CONTROLLERS; Index++) {
+ FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] = (UINT8)SerialIoConfig->UartHwFlowCtrl[Index];
+ }
+ FspsUpd->FspsConfig.SerialIoGpio = (UINT8)SerialIoConfig->Gpio;
+ FspsUpd->FspsConfig.SerialIoDebugUartNumber = (UINT8)SerialIoConfig->DebugUartNumber;
+ FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost = (UINT8)SerialIoConfig->EnableDebugUartAfterPost;
+
+ //
+ // Update Interrupt policies
+ //
+ FspsUpd->FspsConfig.DevIntConfigPtr = (UINT32)InterruptConfig->DevIntConfig;
+ FspsUpd->FspsConfig.NumOfDevIntConfig = InterruptConfig->NumOfDevIntConfig;
+ for (Index = 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) {
+ FspsUpd->FspsConfig.PxRcConfig[Index] = (UINT8)InterruptConfig->PxRcConfig[Index];
+ }
+ FspsUpd->FspsConfig.GpioIrqRoute = (UINT8)InterruptConfig->GpioIrqRoute;
+ FspsUpd->FspsConfig.SciIrqSelect = (UINT8)InterruptConfig->SciIrqSelect;
+ FspsUpd->FspsConfig.TcoIrqSelect = (UINT8)InterruptConfig->TcoIrqSelect;
+ FspsUpd->FspsConfig.TcoIrqEnable = (UINT8)InterruptConfig->TcoIrqEnable;
+
+ //
+ // Update LockDown policies
+ //
+ FspsUpd->FspsTestConfig.PchLockDownRtcLock = (UINT8)LockDownConfig->RtcLock;
+ FspsUpd->FspsTestConfig.PchLockDownGlobalSmi = (UINT8)LockDownConfig->GlobalSmi;
+ FspsUpd->FspsTestConfig.PchLockDownBiosInterface = (UINT8)LockDownConfig->BiosInterface;
+ FspsUpd->FspsConfig.PchLockDownBiosLock = (UINT8)LockDownConfig->BiosLock;
+ FspsUpd->FspsConfig.PchLockDownSpiEiss = (UINT8)LockDownConfig->SpiEiss;
+
+ //
+ // Update Dmi policies
+ //
+ FspsUpd->FspsConfig.PchDmiAspm = (UINT8)DmiConfig->DmiAspm;
+ FspsUpd->FspsConfig.PchPwrOptEnable = (UINT8)DmiConfig->PwrOptEnable;
+ if (DmiConfig->LegacyIoLowLatency) {
+ FspsUpd->FspsConfig.PchDmiAspm = 0;
+ FspsUpd->FspsConfig.PchLegacyIoLowLatency = TRUE;
+ }
+
+ //
+ // Update Flash Protection policies
+ //
+ for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) {
+ FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable;
+ FspsUpd->FspsConfig.PchReadProtectionEnable[Index] = (UINT8)FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable;
+ FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeLimit;
+ FspsUpd->FspsConfig.PchProtectedRangeBase[Index] = (UINT16)FlashProtectionConfig->ProtectRange[Index].ProtectedRangeBase;
+ }
+
+ //
+ // Update IO Apic policies
+ //
+ FspsUpd->FspsConfig.PchIoApicBdfValid = (UINT8)IoApicConfig->BdfValid;
+ FspsUpd->FspsConfig.PchIoApicBusNumber = (UINT8)IoApicConfig->BusNumber;
+ FspsUpd->FspsConfig.PchIoApicDeviceNumber = (UINT8)IoApicConfig->DeviceNumber;
+ FspsUpd->FspsConfig.PchIoApicFunctionNumber = (UINT8)IoApicConfig->FunctionNumber;
+ FspsUpd->FspsConfig.PchIoApicEntry24_119 = (UINT8)IoApicConfig->IoApicEntry24_119;
+ FspsUpd->FspsConfig.Early8254ClockGatingEnable = (UINT8)IoApicConfig->Early8254ClockGatingEnable;
+ FspsUpd->FspsConfig.PchIoApicId = (UINT8)IoApicConfig->IoApicId;
+ FspsUpd->FspsConfig.PchIoApicRangeSelect = (UINT8)IoApicConfig->ApicRangeSelect;
+
+ //
+ // Update P2sb policies
+ //
+ FspsUpd->FspsTestConfig.PchSbiUnlock = (UINT8)P2sbConfig->SbiUnlock;
+ FspsUpd->FspsTestConfig.PchSbAccessUnlock = (UINT8)P2sbConfig->SbAccessUnlock;
+
+ //
+ // Update Pch General policies
+ //
+ FspsUpd->FspsConfig.PchSubSystemVendorId = (UINT16)PchGeneralConfig->SubSystemVendorId;
+ FspsUpd->FspsConfig.PchSubSystemId = (UINT16)PchGeneralConfig->SubSystemId;
+ FspsUpd->FspsConfig.PchCrid = (UINT8)PchGeneralConfig->Crid;
+
+ //
+ // Update Pm policies
+ //
+ FspsUpd->FspsConfig.PchPmPmeB0S5Dis = (UINT8)PmConfig->WakeConfig.PmeB0S5Dis;
+ FspsUpd->FspsConfig.PchPmWolEnableOverride = (UINT8)PmConfig->WakeConfig.WolEnableOverride;
+ FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.PcieWakeFromDeepSx;
+ FspsUpd->FspsConfig.PchPmWoWlanEnable = (UINT8)PmConfig->WakeConfig.WoWlanEnable;
+ FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable = (UINT8)PmConfig->WakeConfig.WoWlanDeepSxEnable;
+ FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx = (UINT8)PmConfig->WakeConfig.LanWakeFromDeepSx;
+
+ FspsUpd->FspsConfig.PchPmDeepSxPol = (UINT8)PmConfig->PchDeepSxPol;
+ FspsUpd->FspsConfig.PchPmSlpS3MinAssert = (UINT8)PmConfig->PchSlpS3MinAssert;
+ FspsUpd->FspsConfig.PchPmSlpS4MinAssert = (UINT8)PmConfig->PchSlpS4MinAssert;
+ FspsUpd->FspsConfig.PchPmSlpSusMinAssert = (UINT8)PmConfig->PchSlpSusMinAssert;
+ FspsUpd->FspsConfig.PchPmSlpAMinAssert = (UINT8)PmConfig->PchSlpAMinAssert;
+
+ FspsUpd->FspsConfig.PchPmLpcClockRun = (UINT8)PmConfig->LpcClockRun;
+ FspsUpd->FspsConfig.PchPmSlpStrchSusUp = (UINT8)PmConfig->SlpStrchSusUp;
+ FspsUpd->FspsConfig.PchPmSlpLanLowDc = (UINT8)PmConfig->SlpLanLowDc;
+ FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod = (UINT8)PmConfig->PwrBtnOverridePeriod;
+ FspsUpd->FspsTestConfig.PchPmDisableEnergyReport = (UINT8)PmConfig->DisableEnergyReport;
+ FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown = (UINT8)PmConfig->DisableDsxAcPresentPulldown;
+ FspsUpd->FspsTestConfig.PchPmPmcReadDisable = (UINT8)PmConfig->PmcReadDisable;
+ FspsUpd->FspsConfig.PchPmDisableNativePowerButton = (UINT8)PmConfig->DisableNativePowerButton;
+ FspsUpd->FspsConfig.PchPmSlpS0Enable = (UINT8)PmConfig->SlpS0Enable;
+ FspsUpd->FspsConfig.PchPmSlpS0VmEnable = (UINT8)PmConfig->SlpS0VmEnable;
+ FspsUpd->FspsConfig.PchPmMeWakeSts = (UINT8)PmConfig->MeWakeSts;
+ FspsUpd->FspsConfig.PchPmWolOvrWkSts = (UINT8)PmConfig->WolOvrWkSts;
+ FspsUpd->FspsConfig.EnableTcoTimer = (UINT8)PmConfig->EnableTcoTimer;
+ FspsUpd->FspsConfig.PchPmPwrCycDur = (UINT8)PmConfig->PchPwrCycDur;
+
+ //
+ // Update Port61h policies
+ //
+ FspsUpd->FspsConfig.PchPort61hEnable = (UINT8)Port61hConfig->Enable;
+
+ //
+ // Update Pch Serial IRQ policies
+ //
+ FspsUpd->FspsConfig.PchSirqEnable = (UINT8)PchSerialIrqConfig->SirqEnable;
+ FspsUpd->FspsConfig.PchSirqMode = (UINT8)PchSerialIrqConfig->SirqMode;
+ FspsUpd->FspsConfig.PchStartFramePulse = (UINT8)PchSerialIrqConfig->StartFramePulse;
+
+ //
+ // Update Pch Thermal policies
+ //
+ FspsUpd->FspsConfig.PchThermalDeviceEnable = (UINT8)PchThermalConfig->ThermalDeviceEnable;
+ FspsUpd->FspsConfig.PchTsmicLock = (UINT8)PchThermalConfig->TsmicLock;
+
+ FspsUpd->FspsConfig.PchT0Level = (UINT16)PchThermalConfig->TTLevels.T0Level;
+ FspsUpd->FspsConfig.PchT1Level = (UINT16)PchThermalConfig->TTLevels.T1Level;
+ FspsUpd->FspsConfig.PchT2Level = (UINT16)PchThermalConfig->TTLevels.T2Level;
+ FspsUpd->FspsConfig.PchTTEnable = (UINT8)PchThermalConfig->TTLevels.TTEnable;
+ FspsUpd->FspsConfig.PchTTState13Enable = (UINT8)PchThermalConfig->TTLevels.TTState13Enable;
+ FspsUpd->FspsConfig.PchTTLock = (UINT8)PchThermalConfig->TTLevels.TTLock;
+ FspsUpd->FspsConfig.TTSuggestedSetting = (UINT8)PchThermalConfig->TTLevels.SuggestedSetting;
+ FspsUpd->FspsConfig.TTCrossThrottling = (UINT8)PchThermalConfig->TTLevels.PchCrossThrottling;
+
+ FspsUpd->FspsConfig.PchDmiTsawEn = (UINT8)PchThermalConfig->DmiHaAWC.DmiTsawEn;
+ FspsUpd->FspsConfig.DmiSuggestedSetting = (UINT8)PchThermalConfig->DmiHaAWC.SuggestedSetting;
+ FspsUpd->FspsConfig.DmiTS0TW = (UINT8)PchThermalConfig->DmiHaAWC.TS0TW;
+ FspsUpd->FspsConfig.DmiTS1TW = (UINT8)PchThermalConfig->DmiHaAWC.TS1TW;
+ FspsUpd->FspsConfig.DmiTS2TW = (UINT8)PchThermalConfig->DmiHaAWC.TS2TW;
+ FspsUpd->FspsConfig.DmiTS3TW = (UINT8)PchThermalConfig->DmiHaAWC.TS3TW;
+
+ FspsUpd->FspsConfig.SataP0T1M = (UINT8)PchThermalConfig->SataTT.P0T1M;
+ FspsUpd->FspsConfig.SataP0T2M = (UINT8)PchThermalConfig->SataTT.P0T2M;
+ FspsUpd->FspsConfig.SataP0T3M = (UINT8)PchThermalConfig->SataTT.P0T3M;
+ FspsUpd->FspsConfig.SataP0TDisp = (UINT8)PchThermalConfig->SataTT.P0TDisp;
+ FspsUpd->FspsConfig.SataP1T1M = (UINT8)PchThermalConfig->SataTT.P1T1M;
+ FspsUpd->FspsConfig.SataP1T2M = (UINT8)PchThermalConfig->SataTT.P1T2M;
+ FspsUpd->FspsConfig.SataP1T3M = (UINT8)PchThermalConfig->SataTT.P1T3M;
+ FspsUpd->FspsConfig.SataP1TDisp = (UINT8)PchThermalConfig->SataTT.P1TDisp;
+ FspsUpd->FspsConfig.SataP0Tinact = (UINT8)PchThermalConfig->SataTT.P0Tinact;
+ FspsUpd->FspsConfig.SataP0TDispFinit = (UINT8)PchThermalConfig->SataTT.P0TDispFinit;
+ FspsUpd->FspsConfig.SataP1Tinact = (UINT8)PchThermalConfig->SataTT.P1Tinact;
+ FspsUpd->FspsConfig.SataP1TDispFinit = (UINT8)PchThermalConfig->SataTT.P1TDispFinit;
+ FspsUpd->FspsConfig.SataThermalSuggestedSetting = (UINT8)PchThermalConfig->SataTT.SuggestedSetting;
+
+ FspsUpd->FspsConfig.PchMemoryThrottlingEnable = (UINT8)PchThermalConfig->MemoryThrottling.Enable;
+ FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable;
+ FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable;
+ FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable;
+ FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable;
+ FspsUpd->FspsConfig.PchMemoryPinSelection[0] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection;
+ FspsUpd->FspsConfig.PchMemoryPinSelection[1] = (UINT8)PchThermalConfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection;
+
+ FspsUpd->FspsConfig.PchTemperatureHotLevel = (UINT16)PchThermalConfig->PchHotLevel;
+
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c new file mode 100644 index 0000000000..bc2c7f3bec --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c @@ -0,0 +1,141 @@ +/** @file
+ Instance of Fsp Policy Initialization Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+/**
+ Performs FSP PEI Policy Pre-memory initialization.
+
+ @param[in] FspmUpdDataPtr Pointer to FSPM UPD data.
+**/
+VOID
+EFIAPI
+FspmPolicyInit (
+ IN OUT VOID *FspmUpd
+ )
+{
+ FSPM_UPD *FspmUpdDataPtr;
+ EFI_STATUS Status;
+
+ FspmUpdDataPtr = FspmUpd;
+
+ //
+ // Initialize Intel PEI Platform Policy
+ //
+ PeiPolicyInitPreMem ();
+
+ //
+ // SI Pei Fsp Policy Initialization
+ //
+ Status = PeiFspSiPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - SI Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+ }
+
+ //
+ // PCH Pei Fsp Policy Initialization
+ //
+ Status = PeiFspPchPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+ }
+
+ //
+ // Cpu Pei Fsp Policy Initialization
+ //
+ Status = PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+ }
+
+
+ //
+ // ME Pei Fsp Policy Initialization
+ //
+ Status = PeiFspMePolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - ME Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+ }
+
+ //
+ // SystemAgent Pei Fsp Policy Initialization
+ //
+ Status = PeiFspSaPolicyInitPreMem (FspmUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory Initialization fail, Status = %r\n", Status));
+ }
+
+ //
+ // Other Upd Initialization
+ //
+ Status = PeiFspMiscUpdInitPreMem (FspmUpdDataPtr);
+
+}
+
+/**
+ Performs FSP PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer UPD data region
+
+**/
+VOID
+EFIAPI
+FspsPolicyInit (
+ IN OUT VOID *FspsUpd
+ )
+{
+ FSPS_UPD *FspsUpdDataPtr;
+ EFI_STATUS Status;
+
+ FspsUpdDataPtr = FspsUpd;
+
+ //
+ // Initialize Intel PEI Platform Policy
+ //
+ PeiPolicyInit ();
+
+ //
+ // PCH Pei Fsp Policy Initialization
+ //
+ Status = PeiFspPchPolicyInit (FspsUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - PCH Pei Fsp Policy iInitialization fail, Status = %r\n", Status));
+ }
+
+ //
+ // ME Pei Fsp Policy Initialization
+ //
+ Status = PeiFspMePolicyInit (FspsUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - ME Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+ }
+
+ //
+ // SystemAgent Pei Fsp Policy Initialization
+ //
+ Status = PeiFspSaPolicyInit (FspsUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - SystemAgent Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+ }
+
+
+ //
+ // Cpu Pei Fsp Policy Initialization
+ //
+ Status = PeiFspCpuPolicyInit (FspsUpdDataPtr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "ERROR - CPU Pei Fsp Policy Initialization fail, Status = %r\n", Status));
+ }
+
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h new file mode 100644 index 0000000000..a17b642a1d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h @@ -0,0 +1,179 @@ +/** @file
+ Internal header file for Fsp Policy Initialization Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_FSP_POLICY_INIT_LIB_H_
+#define _PEI_FSP_POLICY_INIT_LIB_H_
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ConfigBlockLib.h>
+#include "PeiPolicyInitLib.h"
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+/**
+ Performs FSP SI PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP CPU PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+
+/**
+ Performs FSP ME PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP ME PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMePolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+
+/**
+ Performs FSP CPU PEI Policy post memory initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspCpuPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+#endif // _PEI_FSP_POLICY_INIT_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf new file mode 100644 index 0000000000..5a77bfb34a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf @@ -0,0 +1,146 @@ +### @file
+# Library functions for Fsp Policy Initialization Library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiFspPolicyInitLib
+ FILE_GUID = 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FspPolicyInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiFspPolicyInitLib.c
+ PeiFspSiPolicyInitLib.c
+ PeiFspPchPolicyInitLib.c
+ PeiFspCpuPolicyInitLib.c
+ PeiFspMePolicyInitLib.c
+ PeiFspSaPolicyInitLib.c
+ PeiFspMiscUpdInitLib.c
+
+ PeiPolicyInitPreMem.c
+ PeiPolicyInit.c
+ PeiPolicyInit.h
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+ KabylakeFspBinPkg/KabylakeFspBinPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ IoLib
+ PeiServicesLib
+ PcdLib
+ SmbusLib
+ MmPciLib
+ ConfigBlockLib
+ MemoryAllocationLib
+ DebugPrintErrorLevelLib
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+
+[Ppis]
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+
+[Guids]
+ gTraceHubPreMemConfigGuid ## CONSUMES
+ gSmbusPreMemConfigGuid ## CONSUMES
+ gDciPreMemConfigGuid ## CONSUMES
+ gHpetPreMemConfigGuid ## CONSUMES
+ gHsioPciePreMemConfigGuid ## CONSUMES
+ gHsioSataPreMemConfigGuid ## CONSUMES
+ gHsioPreMemConfigGuid ## CONSUMES
+ gPcieRpPreMemConfigGuid ## CONSUMES
+ gLpcPreMemConfigGuid ## CONSUMES
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+ gWatchDogPreMemConfigGuid ## CONSUMES
+ gLanConfigGuid ## CONSUMES
+ gPcieRpConfigGuid ## CONSUMES
+ gSataConfigGuid ## CONSUMES
+ gHdAudioConfigGuid ## CONSUMES
+ gCio2ConfigGuid ## CONSUMES
+ gScsConfigGuid ## CONSUMES
+ gIshConfigGuid ## CONSUMES
+ gSpiConfigGuid ## CONSUMES
+ gSataConfigGuid ## CONSUMES
+ gUsbConfigGuid ## CONSUMES
+ gSerialIoConfigGuid ## CONSUMES
+ gInterruptConfigGuid ## CONSUMES
+ gLockDownConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## PRODUCES
+ gMemoryConfigGuid ## CONSUMES
+ gMemoryConfigNoCrcGuid ## CONSUMES
+ gGraphicsPeiConfigGuid ## CONSUMES
+ gMePeiPreMemConfigGuid ## CONSUMES
+ gMePeiConfigGuid ## CONSUMES
+ gAmtPeiConfigGuid ## CONSUMES
+ gDmiConfigGuid ## CONSUMES
+ gFlashProtectionConfigGuid ## CONSUMES
+ gIoApicConfigGuid ## CONSUMES
+ gPmConfigGuid ## CONSUMES
+ gP2sbConfigGuid ## CONSUMES
+ gPchGeneralConfigGuid ## CONSUMES
+ gPort61ConfigGuid ## CONSUMES
+ gSerialIrqConfigGuid ## CONSUMES
+ gThermalConfigGuid ## CONSUMES
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gCpuTxtPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gBiosGuardConfigGuid ## CONSUMES
+ gCpuOverclockingPreMemConfigGuid ## CONSUMES
+ gCpuConfigLibPreMemConfigGuid ## CONSUMES
+ gCpuSgxConfigGuid ## CONSUMES
+ gCpuPowerMgmtBasicConfigGuid ## CONSUMES
+ gCpuPowerMgmtCustomConfigGuid ## CONSUMES
+ gCpuTestConfigGuid ## CONSUMES
+ gCpuPidTestConfigGuid ## CONSUMES
+ gCpuPowerMgmtTestConfigGuid ## CONSUMES
+ gSmramCpuDataHeaderGuid ## CONSUMES
+ gFspReservedMemoryResourceHobTsegGuid ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c new file mode 100644 index 0000000000..3d218f8ba9 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c @@ -0,0 +1,578 @@ +/** @file
+ Implementation of Fsp SA Policy Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Pci.h>
+#include <MrcSpdData.h>
+#include <PchAccess.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+
+#define MAX_SPD_PAGE_COUNT (2)
+#define MAX_SPD_PAGE_SIZE (256)
+#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
+#define SPD_PAGE_ADDRESS_0 (0x6C)
+#define SPD_PAGE_ADDRESS_1 (0x6E)
+#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02)
+#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B)
+#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C)
+#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
+#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
+#define XMP_ID_STRING (0x4A0C)
+#define SPD3_MANUF_START (117)
+#define SPD3_MANUF_END (127)
+#define SPD4_MANUF_START (320)
+#define SPD4_MANUF_END (328)
+#define SPDLP_MANUF_START (320)
+#define SPDLP_MANUF_END (328)
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] = {
+ { 0, 1, (1 << SpdCold),},
+ { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
+ { 3, 41, (1 << SpdCold),},
+ { 60, 63, (1 << SpdCold),},
+ { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+ { 128, 145, (1 << SpdCold),},
+#ifdef SUPPORT_SPD_CRC
+ { 39, 59, (1 << SpdCold),},
+ { 64, 125, (1 << SpdCold),},
+#endif
+ { 176, 179, (1 << SpdCold),},
+ { 180, 184, (1 << SpdCold),},
+ { 185, 215, (1 << SpdCold),},
+ { 220, 250, (1 << SpdCold),},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] = {
+ { 0, 1, (1 << SpdCold),},
+ { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
+ { 3, 40, (1 << SpdCold),},
+ { 117, 131, (1 << SpdCold),},
+ { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+ { 329, 348, (1 << SpdCold),},
+#ifdef SUPPORT_SPD_CRC
+ { 32, 119, (1 << SpdCold),},
+ { 126, 255, (1 << SpdCold),},
+ { 349, 383, (1 << SpdCold),},
+#endif
+ { 384, 387, (1 << SpdCold),},
+ { 388, 389, (1 << SpdCold),},
+ { 393, 431, (1 << SpdCold),},
+ { 440, 478, (1 << SpdCold),},
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] = {
+ { 0, 1, (1 << SpdCold),},
+ { 2, 2, (1 << SpdCold) | (1 << SpdFast),},
+ { 3, 32, (1 << SpdCold),},
+ { 120, 130, (1 << SpdCold),},
+ { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),},
+ { 329, 348, (1 << SpdCold),},
+#ifdef SUPPORT_SPD_CRC
+ { 31, 121, (1 << SpdCold),},
+ { 126, 255, (1 << SpdCold),},
+ { 349, 383, (1 << SpdCold),},
+#endif
+ { 384, 387, (1 << SpdCold),},
+ { 388, 389, (1 << SpdCold),},
+ { 393, 431, (1 << SpdCold),},
+ { 440, 478, (1 << SpdCold),},
+};
+
+
+/**
+ Read the SPD data over the SMBus, at the specified SPD address, starting at
+ the specified starting offset and read the given amount of data.
+
+ @param[in] SpdAddress - SPD SMBUS address
+ @param[in, out] Buffer - Buffer to store the data.
+ @param[in] Start - Starting SPD offset
+ @param[in] Size - The number of bytes of data to read and also the size of the buffer.
+ @param[in, out] Page - The final page that is being pointed to.
+
+ @retval EFI_SUCCESS if the read is successful, otherwise error status.
+**/
+static
+EFI_STATUS
+InternalDoSpdRead (
+ IN const UINT8 SpdAddress,
+ IN OUT UINT8 *const Buffer,
+ IN const UINT16 Start,
+ IN UINT16 Size,
+ IN OUT UINT8 *const Page
+ )
+{
+ EFI_STATUS EfiStatus;
+ BOOLEAN PageUpdate;
+ UINT16 Count;
+ UINT16 Index;
+
+ EfiStatus = EFI_DEVICE_ERROR;
+ if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) {
+ Count = 0;
+ PageUpdate = FALSE;
+ while (Size--) {
+ Index = Start + Count;
+ if ((Index / MAX_SPD_PAGE_SIZE) != *Page) {
+ *Page = (UINT8) (Index / MAX_SPD_PAGE_SIZE);
+ PageUpdate = TRUE;
+ }
+ Index %= MAX_SPD_PAGE_SIZE;
+ if (PageUpdate == TRUE) {
+ PageUpdate = FALSE;
+ SmBusWriteDataByte ((*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, &EfiStatus);
+ }
+ Buffer[Count] = SmBusReadDataByte (SpdAddress | ((UINT32) Index << 8), &EfiStatus);
+ if (EFI_SUCCESS != EfiStatus) {
+ Buffer[Count] = 0;
+ break;
+ }
+ Count++;
+ }
+ EfiStatus = EFI_SUCCESS;
+ }
+ return (EfiStatus);
+}
+
+/**
+ See if there is valid XMP SPD data.
+
+ @param[in] Debug - Mrc debug structure.
+ @param[in, out] Spd - Mrc SPD structure.
+ @param[in] XmpStart - The current offset in the SPD.
+
+ @retval TRUE if valid, FALSE in not.
+**/
+static
+BOOLEAN
+InternalVerifyXmp (
+ IN OUT MrcSpd *const Spd,
+ IN const UINT16 XmpStart
+ )
+{
+ SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1;
+ SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2;
+ BOOLEAN Xmp;
+
+ Xmp = FALSE;
+
+ switch (((UINT8 *)Spd)[2]) {
+ case SPD_DDR3_SDRAM_TYPE_NUMBER:
+ Header1 = &Spd->Ddr3.Xmp.Header;
+ if (XmpStart == ((UINT32) (Header1) - (UINT32) Spd)) {
+ Xmp = TRUE;
+ if ((Header1->XmpRevision.Data & 0xFE) == 0x12) {
+ return (TRUE);
+ } else {
+ Header1->XmpId = 0;
+ Header1->XmpOrgConf.Data = 0;
+ Header1->XmpRevision.Data = 0;
+ }
+ }
+ break;
+ case SPD_DDR4_SDRAM_TYPE_NUMBER:
+ Header2 = &Spd->Ddr4.EndUser.Xmp.Header;
+ if (XmpStart == ((UINT32) (Header2) - (UINT32) Spd)) {
+ Xmp = TRUE;
+ if ((Header2->XmpRevision.Data) == 0x20) {
+ return (TRUE);
+ } else {
+ Header2->XmpId = 0;
+ Header2->XmpOrgConf.Data = 0;
+ Header2->XmpRevision.Data = 0;
+ }
+ }
+ break;
+ case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
+ case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+ return (TRUE);
+ default:
+ return (FALSE);
+ }
+ if (!Xmp) {
+ return (TRUE);
+ }
+ return (FALSE);
+}
+
+/**
+ Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ The SPD data locations read is controlled by the current boot mode.
+
+ @param[in] BootMode - The current MRC boot mode.
+ @param[in] Address - SPD SmBus address offset.
+ @param[in] Buffer - Buffer that contains the data read from the SPD.
+ @param[in] SpdDdr3Table - Indicates which SPD bytes to read.
+ @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes.
+ @param[in] SpdDdr4Table - Indicates which SPD bytes to read.
+ @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes.
+ @param[in] SpdLpddrTable - Indicates which SPD bytes to read.
+ @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes.
+
+ @retval TRUE if the read is successful, otherwise FALSE on error.
+**/
+BOOLEAN
+InternalGetSpdData (
+ IN SPD_BOOT_MODE BootMode,
+ IN UINT8 Address,
+ IN OUT UINT8 *Buffer,
+ IN UINT8 *SpdDdr3Table,
+ IN UINT32 SpdDdr3TableSize,
+ IN UINT8 *SpdDdr4Table,
+ IN UINT32 SpdDdr4TableSize,
+ IN UINT8 *SpdLpddrTable,
+ IN UINT32 SpdLpddrTableSize
+ )
+{
+ const SPD_OFFSET_TABLE *Tbl;
+ const SPD_OFFSET_TABLE *TableSelect;
+ EFI_STATUS Status;
+ UINT32 Byte;
+ UINT32 Stop;
+ UINT8 Page;
+
+ Page = (UINT8) (~0);
+ Status = InternalDoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1, &Page);
+ if (EFI_SUCCESS == Status) {
+ switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) {
+ case SPD_DDR3_SDRAM_TYPE_NUMBER:
+ case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+ default:
+ TableSelect = (SPD_OFFSET_TABLE *) SpdDdr3Table;
+ Stop = (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE));
+ break;
+ case SPD_DDR4_SDRAM_TYPE_NUMBER:
+ TableSelect = (SPD_OFFSET_TABLE *) SpdDdr4Table;
+ Stop = (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE));
+ break;
+ case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
+ TableSelect = (SPD_OFFSET_TABLE *) SpdLpddrTable;
+ Stop = (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE));
+ break;
+ }
+ for (Byte = 0; (EFI_SUCCESS == Status) && (Byte < Stop); Byte++) {
+ Tbl = &TableSelect[Byte];
+ if ((1 << BootMode) & Tbl->BootMode) {
+ Status = InternalDoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tbl->End - Tbl->Start + 1, &Page);
+ if (Status == EFI_SUCCESS) {
+ if (SpdCold == BootMode) {
+ if (FALSE == InternalVerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) {
+ break;
+ }
+ }
+ } else {
+ break;
+ }
+ }
+ }
+ }
+
+ return ((EFI_SUCCESS == Status) ? TRUE : FALSE);
+}
+
+/**
+ Initialize the Smbus PPI and program the Smbus BAR
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+InternalInitializePchSmbus (
+ VOID
+ )
+{
+ UINTN SmbusRegBase;
+ SmbusRegBase = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SMBUS,
+ PCI_FUNCTION_NUMBER_PCH_SMBUS
+ );
+
+ ///
+ /// Since PEI has no PCI enumerator, set the BAR & I/O space enable ourselves
+ ///
+ MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE, B_PCH_SMBUS_BASE_BAR, PcdGet16 (PcdSmbusBaseAddress));
+
+ MmioOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE);
+
+ ///
+ /// Reset the SMBus host controller
+ ///
+ MmioOr8 (SmbusRegBase + R_PCH_SMBUS_HOSTC, B_PCH_SMBUS_HOSTC_SSRESET);
+
+ ///
+ /// Enable the SMBus host controller
+ ///
+ MmioAndThenOr8 (
+ SmbusRegBase + R_PCH_SMBUS_HOSTC,
+ (UINT8)(~(B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN)),
+ B_PCH_SMBUS_HOSTC_HST_EN
+ );
+
+ ///
+ /// Clear Status Register before anyone uses the interfaces
+ ///
+ IoWrite8 (PcdGet16(PcdSmbusBaseAddress) + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Update Spd Data
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+ @param[in] MemConfigNoCrc Pointer to Mem Config No Crc.
+ @param[in] MiscPeiPreMemConfig Pointer to Misc Config.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval Other The function fail
+**/
+VOID
+EFIAPI
+InternalUpdateSpdData (
+ IN OUT FSPM_UPD *FspmUpd,
+ IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc,
+ IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig
+ )
+{
+ UINT8 Socket;
+ UINT8 *SpdData;
+
+ InternalInitializePchSmbus ();
+
+ DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n"));
+ if (FspmUpd == NULL || MemConfigNoCrc == NULL) {
+ DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n"));
+ DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n"));
+ return;
+ }
+
+ if (*((UINT32 *)MiscPeiPreMemConfig->SpdAddressTable) != 0x0) {
+ //
+ // Update MemConfigNoCrc->SpdData->SpdData
+ //
+ for (Socket = 0; Socket < SA_MC_MAX_SOCKETS; Socket++) {
+ SpdData = (UINT8 *)((UINT32)MemConfigNoCrc->SpdData->SpdData + (Socket * SA_MC_MAX_SPD_SIZE));
+ InternalGetSpdData (
+ 0,
+ MiscPeiPreMemConfig->SpdAddressTable[Socket],
+ (UINT8 *)SpdData,
+ (UINT8 *)&mSpdDdr3Table,
+ sizeof(mSpdDdr3Table),
+ (UINT8 *)&mSpdDdr4Table,
+ sizeof(mSpdDdr4Table),
+ (UINT8 *)&mSpdLpddrTable,
+ sizeof(mSpdLpddrTable)
+ );
+ }
+ }
+
+ FspmUpd->FspmConfig.MemorySpdPtr00 = (UINT32)MemConfigNoCrc->SpdData->SpdData;
+ FspmUpd->FspmConfig.MemorySpdPtr01 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (1 * SA_MC_MAX_SPD_SIZE);
+ FspmUpd->FspmConfig.MemorySpdPtr10 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (2 * SA_MC_MAX_SPD_SIZE);
+ FspmUpd->FspmConfig.MemorySpdPtr11 = (UINT32)MemConfigNoCrc->SpdData->SpdData + (3 * SA_MC_MAX_SPD_SIZE);
+
+ DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n"));
+}
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIGURATION *MemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ //
+ // Locate SiPreMemPolicyPpi
+ //
+ SiPreMemPolicyPpi = NULL;
+ MiscPeiPreMemConfig = NULL;
+ MemConfig = NULL;
+ MemConfigNoCrc = NULL;
+
+
+ Status = PeiServicesLocatePpi(
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status) == FALSE) {
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+
+ //
+ // Update UPD:DqPinsInterleaved
+ //
+ FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8)MemConfig->DqPinsInterleaved;
+
+ //
+ // Update UPD:DqPinsInterleaved
+ //
+ FspmUpd->FspmConfig.CaVrefConfig = MemConfig->CaVrefConfig;
+
+ //
+ // Update UPD:MemorySpdPtrXX
+ //
+ InternalUpdateSpdData (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig);
+
+ //
+ // Update UPD:MemorySpdDataLen
+ //
+ FspmUpd->FspmConfig.MemorySpdDataLen = SA_MC_MAX_SPD_SIZE;
+
+ //
+ // Update UPD:PlatformMemorySize
+ //
+ //
+ // @todo: This value is used since #183932. Revisit.
+ //
+ FspmUpd->FspmConfig.PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
+ FspmUpd->FspmConfig.SaGv = MemConfig->SaGv;
+ FspmUpd->FspmConfig.RMT = (UINT8) MemConfig->RMT;
+ FspmUpd->FspmConfig.DdrFreqLimit = MemConfig->DdrFreqLimit;
+
+ FspmUpd->FspmConfig.SpdProfileSelected = MemConfig->SpdProfileSelected;
+ FspmUpd->FspmConfig.VddVoltage = MemConfig->VddVoltage;
+ FspmUpd->FspmConfig.RefClk = MemConfig->RefClk;
+ FspmUpd->FspmConfig.Ratio = MemConfig->Ratio;
+ FspmUpd->FspmConfig.OddRatioMode = (UINT8) MemConfig->OddRatioMode;
+ FspmUpd->FspmConfig.tCL = (UINT8) MemConfig->tCL;
+ FspmUpd->FspmConfig.tCWL = (UINT8) MemConfig->tCWL;
+ FspmUpd->FspmConfig.tFAW = MemConfig->tFAW;
+ FspmUpd->FspmConfig.tRAS = MemConfig->tRAS;
+ FspmUpd->FspmConfig.tRCDtRP = (UINT8) MemConfig->tRCDtRP;
+ FspmUpd->FspmConfig.tREFI = MemConfig->tREFI;
+ FspmUpd->FspmConfig.tRFC = MemConfig->tRFC;
+ FspmUpd->FspmConfig.tRRD = (UINT8) MemConfig->tRRD;
+ FspmUpd->FspmConfig.tRTP = (UINT8) MemConfig->tRTP;
+ FspmUpd->FspmConfig.tWR = (UINT8) MemConfig->tWR;
+ FspmUpd->FspmConfig.tWTR = (UINT8) MemConfig->tWTR;
+ FspmUpd->FspmConfig.NModeSupport = MemConfig->NModeSupport;
+ FspmUpd->FspmConfig.DllBwEn0 = MemConfig->DllBwEn0;
+ FspmUpd->FspmConfig.DllBwEn1 = MemConfig->DllBwEn1;
+ FspmUpd->FspmConfig.DllBwEn2 = MemConfig->DllBwEn2;
+ FspmUpd->FspmConfig.DllBwEn3 = MemConfig->DllBwEn3;
+ FspmUpd->FspmConfig.EvLoader = (UINT8) MemConfig->EvLoader;
+
+ //
+ // Update UPD:SmramMask
+ //
+ if (MemConfig != NULL) {
+ FspmUpd->FspmConfig.SmramMask = MemConfig->SmramMask;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyInit (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ VTD_CONFIG *Vtd;
+ //
+ // Locate SiPolicyPpi
+ //
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi(
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPolicyPpi
+ );
+ if ((Status == EFI_SUCCESS) && (SiPolicyPpi != NULL)) {
+ GtConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Vtd = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd);
+ ASSERT_EFI_ERROR (Status);
+
+ }
+
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiSaPolicy\n"));
+ if (GtConfig != NULL) {
+ //
+ // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled as default.
+ //
+ FspsUpd->FspsConfig.PeiGraphicsPeimInit = (UINT8) GtConfig->PeiGraphicsPeimInit; // SA: InternalOnly: For Internal validation we still need to enable both Enable/Disable Cases
+
+ //
+ // Update UPD: VBT & LogoPtr
+ //
+ FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32) GtConfig->GraphicsConfigPtr;
+ DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
+
+ FspsUpd->FspsConfig.LogoPtr = (UINT32) GtConfig->LogoPtr;
+ FspsUpd->FspsConfig.LogoSize = GtConfig->LogoSize;
+ DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+ DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfig is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+
+
+ }
+ if (Vtd != NULL) {
+ FspsUpd->FspsConfig.X2ApicOptOut = (UINT8) Vtd->X2ApicOptOut;
+ FspsUpd->FspsConfig.VtdBaseAddress[0] = Vtd->BaseAddress[0];
+ FspsUpd->FspsConfig.VtdBaseAddress[1] = Vtd->BaseAddress[1];
+ FspsUpd->FspsTestConfig.VtdDisable = (UINT8) Vtd->VtdDisable;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c new file mode 100644 index 0000000000..49601b1496 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c @@ -0,0 +1,51 @@ +/** @file
+ Implementation of Fsp SI Policy Initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PeiFspPolicyInitLib.h>
+#include <Ppi/SiPolicy.h>
+
+/**
+ Performs FSP SI PEI Policy initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSiPolicyInitPreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ //
+ // Locate SiPolicyPpi
+ //
+ SiPreMemPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c new file mode 100644 index 0000000000..abed092c46 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.c @@ -0,0 +1,47 @@ +/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPolicyInit.h"
+
+/**
+ Initialize Intel PEI Platform Policy
+
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+
+ //
+ // Call SiCreateConfigBlocks to initialize Silicon Policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = SiCreateConfigBlocks (&SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return;
+ }
+
+ //
+ // Install SiPolicyPpi.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SiInstallPolicyPpi (SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h new file mode 100644 index 0000000000..e85724411a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInit.h @@ -0,0 +1,24 @@ +/** @file
+ Header file for the PolicyInitPei PEIM.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_POLICY_INIT_H_
+#define _PEI_POLICY_INIT_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include "PeiSiPolicyInit.h"
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h new file mode 100644 index 0000000000..b5a7f4eef3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitLib.h @@ -0,0 +1,37 @@ +/** @file
+ Header file for the PolicyInitPei Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _POLICY_INIT_PEI_LIB_H_
+#define _POLICY_INIT_PEI_LIB_H_
+
+/**
+ Initialize Intel PEI Platform Policy
+
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+ VOID
+ );
+
+/**
+ Initialize Intel PEI Platform Policy
+
+**/
+VOID
+EFIAPI
+PeiPolicyInit (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c new file mode 100644 index 0000000000..35baba3183 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiPolicyInitPreMem.c @@ -0,0 +1,48 @@ +/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiPolicyInit.h"
+
+/**
+ Initialize Intel PEI Platform Policy
+
+**/
+VOID
+EFIAPI
+PeiPolicyInitPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+
+ DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memory...\n"));
+ //
+ // Call SiCreatePreMemConfigBlocks to initialize platform policy structure
+ // and get all intel default policy settings.
+ //
+ Status = SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install SiPreMemPolicyPpi.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memory\n"));
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h new file mode 100644 index 0000000000..4f4a80b9ae --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiFspPolicyInitLib/PeiSiPolicyInit.h @@ -0,0 +1,24 @@ +/** @file
+ Header file for the PeiSiPolicyInit
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SI_POLICY_INIT_PEI_H_
+#define _SI_POLICY_INIT_PEI_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/SiPolicyLib.h>
+
+#endif // _SI_POLICY_INIT_PEI_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c new file mode 100644 index 0000000000..b7db139ded --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c @@ -0,0 +1,244 @@ +/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSiPolicyLibrary.h"
+#include <Library/PcdLib.h>
+
+/**
+ Get Si config block table total size.
+
+ @retval Size of PCH config block table
+**/
+UINT16
+EFIAPI
+SiGetConfigBlockTotalSize (
+ VOID
+ )
+{
+ return (UINT16) sizeof (SI_CONFIG);
+}
+
+EFI_STATUS
+EFIAPI
+LoadSiConfigBlockDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ SI_CONFIG *SiConfig;
+
+ SiConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "SiConfig->Header.GuidHob.Name = %g\n", &SiConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "SiConfig->Header.GuidHob.Header.HobLength = 0x%x\n", SiConfig->Header.GuidHob.Header.HobLength));
+
+ SiConfig->Header.Revision = SI_CONFIG_REVISION;
+ //
+ // Temporary Bus range for silicon initialization.
+ //
+ SiConfig->TempPciBusMin = 2;
+ SiConfig->TempPciBusMax = 10;
+ //
+ // Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers.
+ // Minimum size is 2MB bytes.
+ //
+ SiConfig->TempMemBaseAddr = TEMP_MEM_BASE_ADDRESS;
+ SiConfig->TempMemSize = TEMP_MEM_SIZE;
+ //
+ // Temporary IO Base Address for PCI devices to be used to initialize IO registers.
+ // And size of temporary IO space.
+ //
+ SiConfig->TempIoBaseAddr = TEMP_IO_BASE_ADDRESS;
+ SiConfig->TempIoSize = TEMP_IO_SIZE;
+ //
+ // Check PcdSiCsmEnable to set CSM flag.
+ //
+ if (PcdGetBool (PcdSiCsmEnable)) {
+ SiConfig->CsmFlag = 1;
+ } else {
+ SiConfig->CsmFlag = 0;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ VOID *ConfigBlockPointer;
+ EFI_STATUS Status;
+ CONFIG_BLOCK_HEADER SiBlock;
+
+ //
+ // Initalize SiBlock
+ //
+ CopyMem (&(SiBlock.GuidHob.Name), &gSiConfigGuid, sizeof (EFI_GUID));
+ SiBlock.GuidHob.Header.HobLength = sizeof (SI_CONFIG);
+ SiBlock.Revision = SI_CONFIG_REVISION;
+ //
+ // Initialize ConfigBlockPointer
+ //
+ ConfigBlockPointer = (VOID *)&SiBlock;
+ //
+ // Add config block fro SiBlock
+ //
+ DEBUG ((DEBUG_INFO, "gSiConfigGuid = %g\n", &gSiConfigGuid));
+ DEBUG ((DEBUG_INFO, "SiConfig->Header.GuidHob.Name = %g\n", &(SiBlock.GuidHob.Name)));
+ Status = AddConfigBlock (ConfigBlockTableAddress, (VOID *) &ConfigBlockPointer);
+ ASSERT_EFI_ERROR (Status);
+
+ LoadSiConfigBlockDefault ((VOID *) ConfigBlockPointer);
+
+ return Status;
+}
+
+/**
+ SiCreateConfigBlocks creates the config blocksg of Silicon Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiCreateConfigBlocks (
+ OUT SI_POLICY_PPI **SiPolicyPpi
+ )
+{
+ UINT16 TotalBlockSize;
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicy;
+ UINT16 RequiredSize;
+
+ SiPolicy = NULL;
+ //
+ // TotalBlockSize = Si, Pch, AMT, ME, SA and CPU config block size.
+ //
+ TotalBlockSize = SiGetConfigBlockTotalSize () +
+ PchGetConfigBlockTotalSize () +
+ MeGetConfigBlockTotalSize () +
+ SaGetConfigBlockTotalSize () +
+ CpuGetConfigBlockTotalSize ();
+ DEBUG ((DEBUG_INFO, "TotalBlockSize = 0x%x\n", TotalBlockSize));
+
+ RequiredSize = sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;
+
+ Status = CreateConfigBlockTable (RequiredSize, (VOID *) &SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // General initialization
+ //
+ SiPolicy->TableHeader.Header.Revision = SI_POLICY_REVISION;
+ //
+ // Add config blocks.
+ //
+ Status = SiAddConfigBlocks ((VOID *) SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = PchAddConfigBlocks ((VOID *) SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = MeAddConfigBlocks ((VOID *) SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = SaAddConfigBlocks ((VOID *) SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = CpuAddConfigBlocks ((VOID *) SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Assignment for returning SaInitPolicy config block base address
+ //
+ *SiPolicyPpi = SiPolicy;
+ return Status;
+}
+
+/**
+ Print out all silicon policy information.
+
+ @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
+
+**/
+VOID
+DumpSiPolicy (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ //
+ // Print SI config blocks and serial out.
+ //
+ SiPrintPolicyPpi (SiPolicyPpi);
+ //
+ // Print PCH config blocks and serial out.
+ //
+ PchPrintPolicyPpi (SiPolicyPpi);
+ //
+ // Print ME config blocks and serial out.
+ //
+ MePrintPolicyPpi (SiPolicyPpi);
+ //
+ // Print SA config blocks and serial out.
+ //
+ SaPrintPolicyPpi (SiPolicyPpi);
+ //
+ // Print CPU config block and serial out.
+ //
+ CpuPrintPolicy (SiPolicyPpi);
+}
+
+/**
+ SiInstallPolicyPpi installs SiPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc;
+ SI_CONFIG *SiConfig;
+
+ SiPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SiPolicyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyPpiDesc->Guid = &gSiPolicyPpiGuid;
+ SiPolicyPpiDesc->Ppi = SiPolicyPpi;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n"));
+ DumpSiPolicy (SiPolicyPpi);
+
+ //
+ // Install Silicon Policy PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
\ No newline at end of file diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf new file mode 100644 index 0000000000..134f60be5e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf @@ -0,0 +1,62 @@ +## @file
+# Component description file for the PeiSiPolicyLib library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSiPolicyLib
+FILE_GUID = 97584FAE-9299-4202-9889-2D339E4BFA5B
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SiPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+CpuPolicyLib
+CpuPolicyLibPreMem
+PchPolicyLib
+PeiSaPolicyLib
+PeiMePolicyLib
+PcdLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PeiSiPolicyLib.c
+PeiSiPolicyLibrary.h
+SiPrintPolicy.c
+PeiSiPolicyLibPreMem.c
+
+
+[Guids]
+gSiConfigGuid ## CONSUMES
+
+
+[Ppis]
+gSiPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdSiCsmEnable ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c new file mode 100644 index 0000000000..3f80b990e9 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c @@ -0,0 +1,128 @@ +/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSiPolicyLibrary.h"
+
+
+/**
+ SiCreatePreMemConfigBlocks creates the config blocksg of Silicon PREMEM Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SiPreMemPolicyPpi The pointer to get Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiCreatePreMemConfigBlocks (
+ OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi
+ )
+{
+ UINT16 TotalBlockSize;
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+ UINT16 RequiredSize;
+
+ SiPreMemPolicy = NULL;
+ //
+ // TotalBlockSize = Pch , SA, ME and CPU config block size.
+ //
+ TotalBlockSize = PchGetPreMemConfigBlockTotalSize () +
+ MeGetConfigBlockTotalSizePreMem () +
+ SaGetConfigBlockTotalSizePreMem () +
+ CpuGetPreMemConfigBlockTotalSize ();
+ DEBUG ((DEBUG_INFO, "TotalBlockSize = 0x%x\n", TotalBlockSize));
+
+ RequiredSize = sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;
+
+ Status = CreateConfigBlockTable (RequiredSize, (VOID *)&SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // General initialization
+ //
+ SiPreMemPolicy->TableHeader.Header.Revision = SI_PREMEM_POLICY_REVISION;
+ //
+ // Add config blocks.
+ //
+ Status = PchAddPreMemConfigBlocks ((VOID *) SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = MeAddConfigBlocksPreMem ((VOID *) SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = SaAddConfigBlocksPreMem ((VOID *) SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = CpuAddPreMemConfigBlocks ((VOID *) SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Assignment for returning SaInitPolicy config block base address
+ //
+ *SiPreMemPolicyPpi = SiPreMemPolicy;
+ return Status;
+}
+
+/**
+ SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyPpi (
+ IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc;
+
+ SiPolicyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SiPolicyPreMemPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyPreMemPpiDesc->Guid = &gSiPreMemPolicyPpiGuid;
+ SiPolicyPreMemPpiDesc->Ppi = SiPolicyPreMemPpi;
+
+ //
+ // Print whole PCH_POLICY_PPI and serial out.
+ //
+ PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi);
+ //
+ // Print ME config blocks and serial out.
+ //
+ MePrintPolicyPpiPreMem (SiPolicyPreMemPpi);
+ //
+ // Print whole SI_POLICY_PPI and serial out.
+ //
+ SaPrintPolicyPpiPreMem (SiPolicyPreMemPpi);
+ //
+ // Print whole CPU of SI_PREMEM_POLICY_PPI and serial out.
+ //
+ CpuPreMemPrintPolicy (SiPolicyPreMemPpi);
+
+ //
+ // Install Silicon Policy PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyPreMemPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h new file mode 100644 index 0000000000..4c6ba6309d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h @@ -0,0 +1,42 @@ +/** @file
+ Header file for the PeiSiPolicyLib library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SI_POLICY_LIBRARY_H_
+#define _PEI_SI_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/PchPolicyLib.h>
+#include <Library/PeiMePolicyLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <PchAccess.h>
+#include <Library/CpuPolicyLib.h>
+#include <Library/CpuPolicyLibPreMem.h>
+
+#define TEMP_MEM_BASE_ADDRESS 0xFE600000
+#define TEMP_IO_BASE_ADDRESS 0xD000
+
+//
+// IO/MMIO resource limits
+//
+#define TEMP_MEM_SIZE V_PCH_XDCI_MEM_LENGTH
+#define TEMP_IO_SIZE 0x10
+
+#endif // _PEI_SI_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c new file mode 100644 index 0000000000..16cfb52565 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c @@ -0,0 +1,46 @@ +/** @file
+ This file is PeiSiPolicyLib library for printing Policy settings.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSiPolicyLibrary.h"
+
+/**
+ Print whole SI_POLICY_PPI and serial out.
+
+ @param[in] SiPolicyPpi The RC Policy PPI instance
+**/
+VOID
+EFIAPI
+SiPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ SI_CONFIG *SiConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *) &SiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "------------------------ Silicon Print Policy Start ------------------------\n"));
+ DEBUG ((DEBUG_INFO, " TempPciBusMin= %x\n", SiConfig->TempPciBusMin));
+ DEBUG ((DEBUG_INFO, " TempPciBusMax= %x\n", SiConfig->TempPciBusMax));
+ DEBUG ((DEBUG_INFO, " TempMemBaseAddr= %x\n", SiConfig->TempMemBaseAddr));
+ DEBUG ((DEBUG_INFO, " TempMemSize= %x\n", SiConfig->TempMemSize));
+ DEBUG ((DEBUG_INFO, " TempIoBaseAddr= %x\n", SiConfig->TempIoBaseAddr));
+ DEBUG ((DEBUG_INFO, " TempIoSize= %x\n", SiConfig->TempIoSize));
+ DEBUG ((DEBUG_INFO, " CsmFlag= %x\n", SiConfig->CsmFlag));
+ DEBUG ((DEBUG_INFO, "------------------------ Silicon Print Policy End --------------------------\n"));
+ DEBUG_CODE_END ();
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c new file mode 100644 index 0000000000..47ca04b98c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInit.c @@ -0,0 +1,215 @@ +/** @file
+ Source code file for Platform Init PEI module
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <CpuRegs.h>
+#include <PchAccess.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MmPciLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/GpioLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <SaPolicyCommon.h>
+
+#include <Guid/FirmwareFileSystem2.h>
+
+#include <GpioPinsSklLp.h>
+#include <Library/TimerLib.h>
+
+/**
+ Clear any SMI status or wake status left from boot.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+ClearIchSmiAndWake (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT16 ABase;
+ UINT16 Pm1Sts;
+ UINT32 Pm1Cnt;
+ UINT32 Data32;
+ UINT32 Gpe0Sts;
+ UINT32 SmiSts;
+ UINT16 DevActSts;
+ UINT16 TcoBase;
+ UINT16 Tco1Sts;
+ UINT16 LpcDeviceId;
+ UINTN LanBaseAddress;
+ UINT16 LanPmcs;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ return EFI_SUCCESS;
+ }
+
+ PchAcpiBaseGet (&ABase);
+
+ PchTcoBaseGet (&TcoBase);
+
+ //
+ // Read the ACPI registers
+ //
+ Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
+ Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
+
+ Gpe0Sts = IoRead32 (ABase + R_PCH_ACPI_GPE0_STS_127_96);
+ SmiSts = IoRead32 (ABase + R_PCH_SMI_STS);
+
+ Data32 = 0;
+ //
+ // Before clear B_PCH_ACPI_GPE0_STS_127_96_PME_B0, PMES bit of internal device must be cleared at first.
+ //
+ Data32 = (Gpe0Sts & B_PCH_ACPI_GPE0_STS_127_96_PME_B0);
+ if (Data32 != 0) {
+ //
+ // Check if Internal LAN waked up system
+ //
+ LanBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LAN,
+ PCI_FUNCTION_NUMBER_PCH_LAN
+ );
+ LanPmcs = MmioRead16 (LanBaseAddress + R_PCH_LAN_PMCS);
+ if ((LanPmcs & B_PCH_LAN_PMCS_PMES) != 0) {
+ //
+ // Clear PMES bit
+ //
+ MmioOr16 (LanBaseAddress + R_PCH_LAN_PMCS, B_PCH_LAN_PMCS_PMES);
+ DEBUG ((DEBUG_INFO, "Clear LAN PMES bit!\n"));
+ }
+ }
+
+ LpcDeviceId = GetLpcDid ();
+ //
+ // Clear any SMI or wake state from the boot
+ //
+ Pm1Sts |=
+ (
+ B_PCH_ACPI_PM1_STS_WAK |
+ B_PCH_ACPI_PM1_STS_PRBTNOR |
+ B_PCH_ACPI_PM1_STS_RTC |
+ B_PCH_ACPI_PM1_STS_PWRBTN |
+ B_PCH_ACPI_PM1_STS_GBL |
+ B_PCH_ACPI_PM1_STS_TMROF
+ );
+
+ Gpe0Sts |=
+ (
+ B_PCH_ACPI_GPE0_STS_127_96_PME_B0 |
+ B_PCH_ACPI_GPE0_STS_127_96_PME |
+ B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP |
+ B_PCH_ACPI_GPE0_STS_127_96_RI |
+ B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK |
+ B_PCH_ACPI_GPE0_STS_127_96_TC0SCI |
+ B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG |
+ B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE
+ );
+
+ //
+ // PCH Desktop
+ //
+ if (IS_PCH_LPC_DEVICE_ID_MOBILE (LpcDeviceId)) {
+ Gpe0Sts |= B_PCH_ACPI_GPE0_STS_127_96_BATLOW;
+ }
+
+ SmiSts |=
+ (
+ B_PCH_SMI_STS_SMBUS |
+ B_PCH_SMI_STS_PERIODIC |
+ B_PCH_SMI_STS_TCO |
+ B_PCH_SMI_STS_MCSMI |
+ B_PCH_SMI_STS_SWSMI_TMR |
+ B_PCH_SMI_STS_APM |
+ B_PCH_SMI_STS_ON_SLP_EN |
+ B_PCH_SMI_STS_BIOS
+ );
+ //
+ // Write them back
+ //
+ IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, Pm1Sts);
+ IoWrite32 (ABase + R_PCH_ACPI_GPE0_STS_127_96, Gpe0Sts);
+ IoWrite32 (ABase + R_PCH_SMI_STS, SmiSts);
+
+ DevActSts = IoRead16 (ABase + R_PCH_DEVACT_STS);
+ Tco1Sts = IoRead16 (TcoBase + R_PCH_TCO1_STS);
+
+ DevActSts |=
+ (
+ B_PCH_DEVACT_STS_KBC |
+ B_PCH_DEVACT_STS_PIRQDH |
+ B_PCH_DEVACT_STS_PIRQCG |
+ B_PCH_DEVACT_STS_PIRQBF |
+ B_PCH_DEVACT_STS_PIRQAE
+ );
+ Tco1Sts |=
+ (
+ B_PCH_TCO1_STS_DMISERR |
+ B_PCH_TCO1_STS_DMISMI |
+ B_PCH_TCO1_STS_DMISCI |
+ B_PCH_TCO1_STS_BIOSWR |
+ B_PCH_TCO1_STS_NEWCENTURY |
+ B_PCH_TCO1_STS_TIMEOUT |
+ B_PCH_TCO1_STS_TCO_INT |
+ B_PCH_TCO1_STS_SW_TCO_SMI
+ );
+
+ //
+ // clear GPI SMI STS
+ //
+ GpioClearAllGpiSmiSts ();
+
+ IoWrite16 (TcoBase + R_PCH_TCO1_STS, Tco1Sts);
+
+ //
+ // We do not want to write 1 to clear INTRD_DET bit.
+ //
+ IoWrite16 ((UINTN) (TcoBase + R_PCH_TCO2_STS), (UINT16) ~B_PCH_TCO2_STS_INTRD_DET);
+
+ IoWrite16 (ABase + R_PCH_DEVACT_STS, DevActSts);
+
+ //
+ // Clear Power Failure (PWR_FLR), It was used to check S3_Resume State.
+ //
+ // MmioOr8 (
+ // LpcBaseAddress + R_PCH_PMC_GEN_PMCON_B,
+ // B_PCH_PMC_GEN_PMCON_B_PWR_FLR
+ // );
+
+ return EFI_SUCCESS;
+}
+
+VOID
+LateSiliconInit (
+ VOID
+ )
+{
+ ClearIchSmiAndWake ();
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf new file mode 100644 index 0000000000..f26eea6be6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf @@ -0,0 +1,57 @@ +### @file
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SiliconInitLib
+ FILE_GUID = 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = SiliconInitLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ PeiServicesLib
+ PchCycleDecodingLib
+ PchPcrLib
+ PchPmcLib
+ PchSerialIoLib
+ MmPciLib
+ CpuPlatformLib
+ ConfigBlockLib
+ TimerLib
+ PchInfoLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SiliconInit.c
+ SiliconInitPreMem.c
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
+
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c new file mode 100644 index 0000000000..616584ffe7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMem.c @@ -0,0 +1,240 @@ +/** @file
+ Source code file for Platform Init Pre-Memory PEI module
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <PchAccess.h>
+#include <SaPolicyCommon.h>
+#include <CpuAccess.h>
+#include <SaAccess.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPmcLib.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Include/Library/ConfigBlockLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/PchSerialIoLib.h>
+
+//@todo it should be moved to Si Pkg.
+/**
+ Early Platform PCH initialization
+**/
+VOID
+EarlySiliconInit (
+ VOID
+ )
+{
+ UINT16 Data16;
+ UINT8 Data8;
+ UINTN LpcBaseAddress;
+ UINTN P2sbBase;
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+
+ ///
+ /// Program bar
+ ///
+ P2sbBase = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_P2SB,
+ PCI_FUNCTION_NUMBER_PCH_P2SB
+ );
+
+ MmioWrite32 (P2sbBase + R_PCH_P2SB_SBREG_BAR, PCH_PCR_BASE_ADDRESS);
+ MmioOr8 (P2sbBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+
+ ///
+ /// Program ACPI BASE
+ ///
+ PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
+
+ ///
+ /// Program PWRM BASE
+ ///
+ PchPwrmBaseSet (PCH_PWRM_BASE_ADDRESS);
+
+ ///
+ /// Program TCO BASE
+ ///
+ PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress));
+
+ ///
+ /// LPC I/O Configuration
+ ///
+ PchLpcIoDecodeRangesSet (
+ (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
+ (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
+ (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
+ );
+
+ PchLpcIoEnableDecodingSet (
+ B_PCH_LPC_IOE_ME2 |
+ B_PCH_LPC_IOE_SE |
+ B_PCH_LPC_IOE_ME1 |
+ B_PCH_LPC_IOE_KE |
+ B_PCH_LPC_IOE_HGE |
+ B_PCH_LPC_IOE_LGE |
+ B_PCH_LPC_IOE_FDE |
+ B_PCH_LPC_IOE_PPE |
+ B_PCH_LPC_IOE_CBE |
+ B_PCH_LPC_IOE_CAE
+ );
+
+
+ ///
+ /// Enable the upper 128-byte bank of RTC RAM
+ ///
+ PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
+
+ ///
+ /// Disable the Watchdog timer expiration from causing a system reset
+ ///
+ PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~0, B_PCH_PCR_ITSS_GIC_AME);
+
+ ///
+ /// Halt the TCO timer
+ ///
+ Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
+ Data16 |= B_PCH_TCO_CNT_TMR_HLT;
+ IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
+
+ ///
+ /// Clear the Second TO status bit
+ ///
+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, B_PCH_TCO2_STS_SECOND_TO);
+
+ ///
+ /// Disable SERR NMI and IOCHK# NMI in port 61
+ ///
+ Data8 = IoRead8 (R_PCH_NMI_SC);
+ Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
+ IoWrite8 (R_PCH_NMI_SC, Data8);
+
+ PchPcrAndThenOr32 (PID_ITSS, R_PCH_PCR_ITSS_GIC, (UINT32)~B_PCH_PCR_ITSS_GIC_AME, 0);
+
+ //
+ // Program timer 1 as refresh timer
+ //
+ IoWrite8 (0x43, 0x54);
+ IoWrite8 (0x41, 0x12);
+
+}
+
+// @todo: It should be moved Policy Init.
+/**
+ Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
+
+**/
+VOID
+SiliconInit (
+ VOID
+ )
+{
+ UINT16 Data16;
+ UINT8 Data8;
+ UINTN LpcBaseAddress;
+ UINT16 ABase;
+ UINT16 Pm1Sts;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+
+ ///
+ /// LPC I/O Configuration
+ ///
+ PchLpcIoDecodeRangesSet (
+ (V_PCH_LPC_IOD_LPT_378 << N_PCH_LPC_IOD_LPT) |
+ (V_PCH_LPC_IOD_COMB_3E8 << N_PCH_LPC_IOD_COMB) |
+ (V_PCH_LPC_IOD_COMA_3F8 << N_PCH_LPC_IOD_COMA)
+ );
+ PchLpcIoEnableDecodingSet (
+ B_PCH_LPC_IOE_ME2 |
+ B_PCH_LPC_IOE_SE |
+ B_PCH_LPC_IOE_ME1 |
+ B_PCH_LPC_IOE_KE |
+ B_PCH_LPC_IOE_HGE |
+ B_PCH_LPC_IOE_LGE |
+ B_PCH_LPC_IOE_FDE |
+ B_PCH_LPC_IOE_PPE |
+ B_PCH_LPC_IOE_CBE |
+ B_PCH_LPC_IOE_CAE
+ );
+ ///
+ /// Enable the upper 128-byte bank of RTC RAM
+ ///
+ PchPcrAndThenOr32 (PID_RTC, R_PCH_PCR_RTC_CONF, (UINT32)~0, B_PCH_PCR_RTC_CONF_UCMOS_EN);
+ ///
+ /// Disable the Watchdog timer expiration from causing a system reset
+ ///
+ PchPcrAndThenOr32 (PID_SMB, R_PCH_PCR_SMBUS_GC, (UINT32)~0, B_PCH_PCR_SMBUS_GC_NR);
+
+ ///
+ /// Halt the TCO timer
+ ///
+ Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT);
+ Data16 |= B_PCH_TCO_CNT_TMR_HLT;
+ IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO1_CNT, Data16);
+ ///
+ /// Clear the Second TO status bit
+ ///
+ IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_PCH_TCO2_STS, B_PCH_TCO2_STS_SECOND_TO);
+ ///
+ /// Disable SERR NMI and IOCHK# NMI in port 61
+ ///
+ Data8 = IoRead8 (R_PCH_NMI_SC);
+ Data8 |= (B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN);
+ IoWrite8 (R_PCH_NMI_SC, Data8);
+
+
+ ///
+ /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
+ ///
+ IoWrite16 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_EN, 0);
+ IoWrite32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_GPE0_EN_127_96, 0);
+ ///----------------------------------------------------------------------------------
+ ///
+ /// BIOS should check the WAK_STS bit in PM1_STS[15] (PCH register ABASE+00h) before memory
+ /// initialization to determine if ME has reset the system while the host was in a sleep state.
+ /// If WAK_STS is not set, BIOS should ensure a non-sleep exit path is taken by overwriting
+ /// PM1_CNT[12:10] (PCH register ABASE+04h) to 111b to force an s5 exit.
+ ///
+ PchAcpiBaseGet (&ABase);
+ Pm1Sts = IoRead16 (ABase + R_PCH_ACPI_PM1_STS);
+ if ((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) == 0) {
+ Pm1Cnt = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT);
+ Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S5;
+ IoWrite32 (ABase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
+ }
+
+}
+
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