diff options
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/SystemAgent')
70 files changed, 17196 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.aslc b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.aslc new file mode 100644 index 0000000000..bf7b56e23e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.aslc @@ -0,0 +1,411 @@ +/** @file
+ This file describes the contents of the ACPI DMA address Remapping
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "Dmar.h"
+
+EFI_ACPI_DMAR_TABLE DmarTable = {
+ {
+ EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_DMAR_TABLE),
+ EFI_ACPI_DMAR_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { 'I', 'N', 'T', 'E', 'L', ' ' },
+ EFI_ACPI_DMAR_OEM_TABLE_ID,
+ 0x1,
+ EFI_ACPI_DMAR_OEM_CREATOR_ID,
+ 1
+ },
+
+ //
+ // DMAR table specific entries below:
+ //
+
+ //
+ // 39-bit addressing Host Address Width
+ //
+ 38,
+
+ //
+ // Flags
+ //
+ 0,
+
+ //
+ // Reserved fields
+ //
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+
+ //
+ // First DRHD structure, VT-d Engine #1
+ //
+ {
+ 0, // Type = 0 (DRHD)
+ sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT), // Length of structure
+ 0, // Flag - Do not include all
+ 0, // Reserved fields
+ 0, // Segment
+ 0x00000000, // Base address of DMA-remapping hardware - Updated at boot time
+
+ //
+ // Device Scopes
+ //
+ {
+ {
+ 1, // Type
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Segment number
+ 0, // Reserved
+ 0, // Start bus number
+ {2, 0} // PCI path
+ }
+ }
+ },
+
+ //Second DRHD structure VT-d Engine# 2
+ {
+ 0, // Type = 0 (DRHD)
+ sizeof(EFI_ACPI_DRHD_ENGINE2_STRUCT), // Length of strucure.
+ 1, // Flag - Include all
+ 0, // Reserved
+ 0, // Segment Number
+ 0x00000000, // Base address of DMA-remapping hardware.
+
+ {
+ //
+ // Device Scopes
+ //
+ {
+ 3, // Type=IO APIC
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 2, // Enumeration ID
+ 0xF0, // Start bus number
+ {31, 0} // PCI path
+ },
+ //
+ // Device Scopes
+ //
+ {
+ 4, // Type=HPET
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 0, // Enumeration ID
+ 0xF0, // Start bus number
+ {31, 0} // PCI path
+ },
+ //
+ // Device Scopes - I2C0
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 1, // Enumeration ID
+ 0, // Start bus number
+ {21, 0} // PCI path
+ },
+ //
+ // Device Scopes - I2C1
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 2, // Enumeration ID
+ 0, // Start bus number
+ {21, 1} // PCI path
+ },
+ //
+ // Device Scopes - I2C2
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 3, // Enumeration ID
+ 0, // Start bus number
+ {21, 2} // PCI path
+ },
+ //
+ // Device Scopes - I2C3
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 4, // Enumeration ID
+ 0, // Start bus number
+ {21, 3} // PCI path
+ },
+ //
+ // Device Scopes - I2C4 (LP only)
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 5, // Enumeration ID
+ 0, // Start bus number
+ {25, 2} // PCI path
+ },
+ //
+ // Device Scopes - I2C5 (LP only)
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 6, // Enumeration ID
+ 0, // Start bus number
+ {25, 1} // PCI path
+ },
+ //
+ // Device Scopes - SPI0
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 7, // Enumeration ID
+ 0, // Start bus number
+ {30, 2} // PCI path
+ },
+ //
+ // Device Scopes - SPI1
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 8, // Enumeration ID
+ 0, // Start bus number
+ {30, 3} // PCI path
+ },
+ //
+ // Device Scopes - UA00
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 9, // Enumeration ID
+ 0, // Start bus number
+ {30, 0} // PCI path
+ },
+ //
+ // Device Scopes - UA01
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 10, // Enumeration ID
+ 0, // Start bus number
+ {30, 1} // PCI path
+ },
+ //
+ // Device Scopes - UA02
+ //
+ {
+ 5, // Type=ACPI_NAMESPACE_DEVICE
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 11, // Enumeration ID
+ 0, // Start bus number
+ {25, 0} // PCI path
+ }
+ }
+ },
+
+ //RMRR structure for USB devices.
+ {
+ 0x1, // Type 1 - RMRR structure
+ sizeof(EFI_ACPI_RMRR_USB_STRUC), // Length
+ 0x0000, // Reserved
+ 0x0000, // Segment Num
+ 0x00000000000E0000, // RMRR Base address - Updated in runtime.
+ 0x00000000000EFFFF, // RMRR Limit address - Updated in runtime.
+ {
+ {
+ 1, // Type
+ sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 0, // Enum ID
+ 0, // Start bus number
+ {20, 0} // PCI path
+ },
+ {
+ 1, // Type
+ sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 0, // Enum ID
+ 0, // Start bus number
+ {20, 1} // PCI path
+ }
+ }
+ },
+
+ //RMRR structure for IGD device.
+ {
+ 1, // Type 1 - RMRR structure
+ sizeof(EFI_ACPI_RMRR_IGD_STRUC), // Length
+ 0x0000, // Reserved
+ 0x0000, // Segment Num
+ 0x0000000000000000, // RMRR Base address - Updated in runtime.
+ 0x0000000000000000, // RMRR Limit address - Updated in runtime.
+ {
+ {
+ 1, // Type
+ sizeof(EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length
+ 0, // Reserved
+ 0, // Enum ID
+ 0, // Start bus number
+ {2, 0} // PCI path
+ }
+ }
+ },
+
+ // SKL ANDD structure.
+ // device path string limit is 20 including '\0'
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 1,
+ "\\_SB.PCI0.I2C0"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 2,
+ "\\_SB.PCI0.I2C1"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 3,
+ "\\_SB.PCI0.I2C2"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 4,
+ "\\_SB.PCI0.I2C3"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 5,
+ "\\_SB.PCI0.I2C4"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 6,
+ "\\_SB.PCI0.I2C5"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 7,
+ "\\_SB.PCI0.SPI0"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 8,
+ "\\_SB.PCI0.SPI1"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 9,
+ "\\_SB.PCI0.UA00"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 10,
+ "\\_SB.PCI0.UA01"
+ },
+
+ // ANDD structure.
+ {
+ 4, // Type 4 - ANDD structure
+ sizeof(EFI_ACPI_ANDD_STRUC), // Length
+ { 0, 0, 0 }, // Reserved [3]
+ 11,
+ "\\_SB.PCI0.UA02"
+ }
+};
+
+//
+// Dummy function required for build tools
+//
+#if defined (__GNUC__)
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&DmarTable;
+}
+#else
+int
+main (
+ VOID
+ )
+{
+ return 0;
+}
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.h new file mode 100644 index 0000000000..aaa027806b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.h @@ -0,0 +1,30 @@ +/** @file
+ This file describes the contents of the ACPI DMA address Remapping
+ Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_DMAR_H_
+#define _SA_DMAR_H_
+
+///
+/// Include standard ACPI table definitions
+///
+#include <IndustryStandard/Acpi30.h>
+#include <DmaRemappingTable.h>
+
+#pragma pack(1)
+
+#define EFI_ACPI_DMAR_OEM_TABLE_ID 0x204C424B ///< "KBL "
+#define EFI_ACPI_DMAR_OEM_CREATOR_ID 0x4C544E49 ///< "INTL"
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/HostBus.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/HostBus.asl new file mode 100644 index 0000000000..ea14d5d479 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/HostBus.asl @@ -0,0 +1,733 @@ +/** @file
+ This file contains the SystemAgent PCI Configuration space
+ definition.
+ It defines various System Agent PCI Configuration Space registers
+ which will be used to dynamically produce all resources in the Host Bus.
+ @note This ASL file needs to be included as part of platform ACPI DSDT table.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(M64B)
+External(M64L)
+External(M32B)
+External(M32L)
+
+//
+// Define various System Agent (SA) PCI Configuration Space
+// registers which will be used to dynamically produce all
+// resources in the Host Bus _CRS.
+//
+OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
+Field (HBUS, DWordAcc, NoLock, Preserve)
+{
+ Offset(0x40), // EPBAR (0:0:0:40)
+ EPEN, 1, // Enable
+ , 11,
+ EPBR, 20, // EPBAR [31:12]
+
+ Offset(0x48), // MCHBAR (0:0:0:48)
+ MHEN, 1, // Enable
+ , 14,
+ MHBR, 17, // MCHBAR [31:15]
+
+ Offset(0x50), // GGC (0:0:0:50)
+ GCLK, 1, // GGCLCK
+
+ Offset(0x54), // DEVEN (0:0:0:54)
+ D0EN, 1, // DEV0 Enable
+
+ Offset(0x60), // PCIEXBAR (0:0:0:60)
+ PXEN, 1, // Enable
+ PXSZ, 2, // PCI Express Size
+ , 23,
+ PXBR, 6, // PCI Express BAR [31:26]
+
+ Offset(0x68), // DMIBAR (0:0:0:68)
+ DIEN, 1, // Enable
+ , 11,
+ DIBR, 20, // DMIBAR [31:12]
+
+ Offset(0x70), // MESEG_BASE (0:0:0:70)
+ , 20,
+ MEBR, 12, // MESEG_BASE [31:20]
+
+ Offset(0x80), // PAM0 Register (0:0:0:80)
+ PMLK, 1, // PAM Lock bit.
+ , 3,
+ PM0H, 2, // PAM 0, High Nibble
+ , 2,
+
+ Offset(0x81), // PAM1 Register (0:0:0:81)
+ PM1L, 2, // PAM1, Low Nibble
+ , 2,
+ PM1H, 2, // PAM1, High Nibble
+ , 2,
+
+ Offset(0x82), // PAM2 Register (0:0:0:82)
+ PM2L, 2, // PAM2, Low Nibble
+ , 2,
+ PM2H, 2, // PAM2, High Nibble
+ , 2,
+
+ Offset(0x83), // PAM3 Register (0:0:0:83)
+ PM3L, 2, // PAM3, Low Nibble
+ , 2,
+ PM3H, 2, // PAM3, High Nibble
+ , 2,
+
+ Offset(0x84), // PAM4 Register (0:0:0:84)
+ PM4L, 2, // PAM4, Low Nibble
+ , 2,
+ PM4H, 2, // PAM4, High Nibble
+ , 2,
+
+ Offset(0x85), // PAM5 Register (0:0:0:85)
+ PM5L, 2, // PAM5, Low Nibble
+ , 2,
+ PM5H, 2, // PAM5, High Nibble
+ , 2,
+
+ Offset(0x86), // PAM6 Register (0:0:0:86)
+ PM6L, 2, // PAM6, Low Nibble
+ , 2,
+ PM6H, 2, // PAM6, High Nibble
+ , 2,
+
+ Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
+ , 20,
+ TUUD, 19, // TOUUD [38:20]
+
+ Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
+ , 20,
+ TLUD, 12, // TOLUD [31:20]
+}
+//
+// Define a buffer that will store all the bus, memory, and IO information
+// relating to the Host Bus. This buffer will be dynamically altered in
+// the _CRS and passed back to the OS.
+//
+Name(BUF0,ResourceTemplate()
+{
+ //
+ // Bus Number Allocation: Bus 0 to 0xFF
+ //
+ WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
+ 0x0000,0x00FF,0x00,0x0100,,,PB00)
+
+ //
+ // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
+
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+
+ //
+ // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
+ //
+ DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
+ 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
+
+ //
+ // Video Buffer Area ( 0xA0000 - 0xBFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
+
+ //
+ // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
+
+ //
+ // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
+
+ //
+ // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
+
+ //
+ // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
+
+ //
+ // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
+
+ //
+ // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
+
+ //
+ // BIOS Area ( 0xF0000 - 0xFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+ ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
+
+// //
+// // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
+// //
+// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
+// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
+
+ //
+ // PCI Memory Region ( TOLUD - 0xDFFFFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01)
+
+ //
+ // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
+ // (This is dummy range for OS compatibility, will patch it in _CRS)
+ //
+ QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
+
+ //
+ // PCH reserved resource ( 0xFD000000 - 0xFE7FFFFF )
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0xFD000000,0xFE7FFFFF,0x00,0x1800000,,,PM03)
+
+})
+
+Name(EP_B, 0) // to store EP BAR
+Name(MH_B, 0) // to store MCH BAR
+Name(PC_B, 0) // to store PCIe BAR
+Name(PC_L, 0) // to store PCIe BAR Length
+Name(DM_B, 0) // to store DMI BAR
+
+//
+// Get EP BAR
+//
+Method(GEPB,0,Serialized)
+{
+ if(LEqual(EP_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.EPBR,12,EP_B)
+ }
+ Return(EP_B)
+}
+
+//
+// Get MCH BAR
+//
+Method(GMHB,0,Serialized)
+{
+ if(LEqual(MH_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.MHBR,15,MH_B)
+ }
+ Return(MH_B)
+}
+
+//
+// Get PCIe BAR
+//
+Method(GPCB,0,Serialized)
+{
+ if(LEqual(PC_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.PXBR,26,PC_B)
+ }
+ Return(PC_B)
+}
+
+//
+// Get PCIe Length
+//
+Method(GPCL,0,Serialized)
+{
+ if(LEqual(PC_L,0))
+ {
+ ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L)
+ }
+ Return(PC_L)
+}
+
+//
+// Get DMI BAR
+//
+Method(GDMB,0,Serialized)
+{
+ if(LEqual(DM_B,0))
+ {
+ ShiftLeft(\_SB.PCI0.DIBR,12,DM_B)
+ }
+ Return(DM_B)
+}
+
+
+Method(_CRS,0,Serialized)
+{
+ //
+ // Fix up Max Bus Number and Length
+ //
+ Store(\_SB.PCI0.GPCL(),Local0)
+ CreateWordField(BUF0, ^PB00._MAX, PBMX)
+ Store(Subtract(ShiftRight(Local0,20),2), PBMX)
+ CreateWordField(BUF0, ^PB00._LEN, PBLN)
+ Store(Subtract(ShiftRight(Local0,20),1), PBLN)
+ //
+ // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF.
+ //
+ If(PM1L) // \_SB.PCI0
+ {
+ // PAMx != 0. Set length = 0.
+
+ CreateDwordField(BUF0, ^C000._LEN,C0LN)
+ Store(Zero,C0LN)
+ }
+
+ If(LEqual(PM1L,1))
+ {
+ CreateBitField(BUF0, ^C000._RW,C0RW)
+ Store(Zero,C0RW)
+ }
+
+ If(PM1H)
+ {
+ CreateDwordField(BUF0, ^C400._LEN,C4LN)
+ Store(Zero,C4LN)
+ }
+
+ If(LEqual(PM1H,1))
+ {
+ CreateBitField(BUF0, ^C400._RW,C4RW)
+ Store(Zero,C4RW)
+ }
+
+ If(PM2L)
+ {
+ CreateDwordField(BUF0, ^C800._LEN,C8LN)
+ Store(Zero,C8LN)
+ }
+
+ If(LEqual(PM2L,1))
+ {
+ CreateBitField(BUF0, ^C800._RW,C8RW)
+ Store(Zero,C8RW)
+ }
+
+ If(PM2H)
+ {
+ CreateDwordField(BUF0, ^CC00._LEN,CCLN)
+ Store(Zero,CCLN)
+ }
+
+ If(LEqual(PM2H,1))
+ {
+ CreateBitField(BUF0, ^CC00._RW,CCRW)
+ Store(Zero,CCRW)
+ }
+
+ If(PM3L)
+ {
+ CreateDwordField(BUF0, ^D000._LEN,D0LN)
+ Store(Zero,D0LN)
+ }
+
+ If(LEqual(PM3L,1))
+ {
+ CreateBitField(BUF0, ^D000._RW,D0RW)
+ Store(Zero,D0RW)
+ }
+
+ If(PM3H)
+ {
+ CreateDwordField(BUF0, ^D400._LEN,D4LN)
+ Store(Zero,D4LN)
+ }
+
+ If(LEqual(PM3H,1))
+ {
+ CreateBitField(BUF0, ^D400._RW,D4RW)
+ Store(Zero,D4RW)
+ }
+
+ If(PM4L)
+ {
+ CreateDwordField(BUF0, ^D800._LEN,D8LN)
+ Store(Zero,D8LN)
+ }
+
+ If(LEqual(PM4L,1))
+ {
+ CreateBitField(BUF0, ^D800._RW,D8RW)
+ Store(Zero,D8RW)
+ }
+
+ If(PM4H)
+ {
+ CreateDwordField(BUF0, ^DC00._LEN,DCLN)
+ Store(Zero,DCLN)
+ }
+
+ If(LEqual(PM4H,1))
+ {
+ CreateBitField(BUF0, ^DC00._RW,DCRW)
+ Store(Zero,DCRW)
+ }
+
+ If(PM5L)
+ {
+ CreateDwordField(BUF0, ^E000._LEN,E0LN)
+ Store(Zero,E0LN)
+ }
+
+ If(LEqual(PM5L,1))
+ {
+ CreateBitField(BUF0, ^E000._RW,E0RW)
+ Store(Zero,E0RW)
+ }
+
+ If(PM5H)
+ {
+ CreateDwordField(BUF0, ^E400._LEN,E4LN)
+ Store(Zero,E4LN)
+ }
+
+ If(LEqual(PM5H,1))
+ {
+ CreateBitField(BUF0, ^E400._RW,E4RW)
+ Store(Zero,E4RW)
+ }
+
+ If(PM6L)
+ {
+ CreateDwordField(BUF0, ^E800._LEN,E8LN)
+ Store(Zero,E8LN)
+ }
+
+ If(LEqual(PM6L,1))
+ {
+ CreateBitField(BUF0, ^E800._RW,E8RW)
+ Store(Zero,E8RW)
+ }
+
+ If(PM6H)
+ {
+ CreateDwordField(BUF0, ^EC00._LEN,ECLN)
+ Store(Zero,ECLN)
+ }
+
+ If(LEqual(PM6H,1))
+ {
+ CreateBitField(BUF0, ^EC00._RW,ECRW)
+ Store(Zero,ECRW)
+ }
+
+ If(PM0H)
+ {
+ CreateDwordField(BUF0, ^F000._LEN,F0LN)
+ Store(Zero,F0LN)
+ }
+
+ If(LEqual(PM0H,1))
+ {
+ CreateBitField(BUF0, ^F000._RW,F0RW)
+ Store(Zero,F0RW)
+ }
+
+ // Enable the 1MB region between 15-16MB if HENA = 1.
+ //
+ // If( MCHC.HENA)
+ // {
+ // CreateDwordField(BUF0, HOLE._LEN,H0LN)
+ // Store(0x100000,H0LN)
+ // }
+
+ //
+ // Create pointers to Memory Sizing values.
+ //
+ CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+ CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+ CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+ //
+ // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+ // TOM, so shift these bits into the correct position and fix up
+ // the Memory Region available to PCI.
+ //
+ Store (M32L, M1LN)
+ Store (M32B, M1MN)
+ Subtract (Add (M1MN, M1LN), 1, M1MX)
+
+ //
+ // Create pointers to Memory Sizing values.
+ // Patch PM02 range basing on memory size and OS type
+ //
+ If (LEqual(M64L, 0)) {
+ CreateQwordField(BUF0, ^PM02._LEN,MSLN)
+ //
+ // Set resource length to 0
+ //
+ Store (0, MSLN)
+ }
+ Else {
+ CreateQwordField(BUF0, ^PM02._LEN,M2LN)
+ CreateQwordField(BUF0, ^PM02._MIN,M2MN)
+ CreateQwordField(BUF0, ^PM02._MAX,M2MX)
+ //
+ // Set 64bit MMIO resource Base and Length
+ //
+ Store (M64L, M2LN)
+ Store (M64B, M2MN)
+ Subtract (Add (M2MN, M2LN), 1, M2MX)
+ }
+ Return(BUF0)
+}
+
+//
+//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))
+//
+Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33,
+ 0xf7, 0x1f,
+ 0x1c, 0x40,
+ 0x96, 0x57,
+ 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66})
+
+
+Name(SUPP,0) // PCI _OSC Support Field value
+Name(CTRL,0) // PCI _OSC Control Field value
+Name(XCNT, 0) // Variable used in _OSC for counting
+
+Method(_OSC,4,Serialized)
+{
+ //
+ // Check for proper UUID
+ // Save the capabilities buffer
+ //
+ Store(Arg3,Local0)
+
+ //
+ // Create DWord-adressable fields from the Capabilties Buffer
+ //
+ CreateDWordField(Local0,0,CDW1)
+ CreateDWordField(Local0,4,CDW2)
+ CreateDWordField(Local0,8,CDW3)
+
+
+ //
+ // Check for proper UUID
+ //
+ If(LEqual(Arg0,GUID))
+ {
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ //
+ // You can clear bits in CTRL here if you don't want OS to take
+ // control
+ //
+ If(LNot(NEXP))
+ {
+ And(CTRL, 0xFFFFFFF8, CTRL) // disable Native hot plug, PME
+ }
+
+ If(LAnd(LEqual(TBTS, 1),LEqual(TNAT, 1)))
+ {
+ // \_OSC disallow only Advanced Error Reporting control
+ And(CTRL, 0xFFFFFFF7, CTRL)
+ }
+
+ If(Not(And(CDW1,1))) // Query flag clear?
+ { // Disable GPEs for features granted native control.
+ If(And(CTRL,0x01))
+ {
+ NHPG()
+ }
+ If(And(CTRL,0x04)) // PME control granted?
+ {
+ NPME()
+ }
+ }
+
+ If(LNotEqual(Arg1,One))
+ {
+ //
+ // Unknown revision
+ //
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL))
+ {
+ //
+ // Capabilities bits were masked
+ //
+ Or(CDW1,0x10,CDW1)
+ }
+ //
+ // Update DWORD3 in the buffer
+ //
+ Store(CTRL,CDW3)
+ Store(CTRL,OSCC)
+ Return(Local0)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Local0)
+ }
+} // End _OSC
+
+//
+// Added code for Dual IRQ support. Two set of ACPI IRQ tables were generated.
+// Code has been added to select the appropriate IRQ table by checking the CPUID.
+//
+Scope(\_SB.PCI0)
+{
+ Method(AR00) {
+ Return(\_SB.AR00)
+ }
+
+ Method(PR00) {
+ Return(\_SB.PR00)
+ }
+
+ Method(AR02) {
+ Return(\_SB.AR02)
+ }
+
+ Method(PR02) {
+ Return(\_SB.PR02)
+ }
+
+ Method(AR04) {
+ Return(\_SB.AR04)
+ }
+
+ Method(PR04) {
+ Return(\_SB.PR04)
+ }
+
+ Method(AR05) {
+ Return(\_SB.AR05)
+ }
+
+ Method(PR05) {
+ Return(\_SB.PR05)
+ }
+
+ Method(AR06) {
+ Return(\_SB.AR06)
+ }
+
+ Method(PR06) {
+ Return(\_SB.PR06)
+ }
+
+ Method(AR07) {
+ Return(\_SB.AR07)
+ }
+
+ Method(PR07) {
+ Return(\_SB.PR07)
+ }
+
+ Method(AR08) {
+ Return(\_SB.AR08)
+ }
+
+ Method(PR08) {
+ Return(\_SB.PR08)
+ }
+
+ Method(AR09) {
+ Return(\_SB.AR09)
+ }
+
+ Method(PR09) {
+ Return(\_SB.PR09)
+ }
+
+ Method(AR0A) {
+ Return(\_SB.AR0A)
+ }
+
+ Method(PR0A) {
+ Return(\_SB.PR0A)
+ }
+
+ Method(AR0B) {
+ Return(\_SB.AR0B)
+ }
+
+ Method(PR0B) {
+ Return(\_SB.PR0B)
+ }
+
+ //
+ // I.G.D
+ //
+ Device(GFX0) {
+ Name(_ADR, 0x00020000)
+ }
+
+ //
+ // Device ISP0 is the ISP PCI device
+ //
+ Device(ISP0) {
+ Name(_ADR, 0x00050000)
+ }
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaAcpiTables.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaAcpiTables.inf new file mode 100644 index 0000000000..ff39573378 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaAcpiTables.inf @@ -0,0 +1,61 @@ +## @file
+# Component description file for the ACPI tables
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+
+[Defines]
+INF_VERSION = 0x00010005
+BASE_NAME = SaAcpiTables
+FILE_GUID = 3c0ed5e2-91ea-4b94-820d-9daf9a3bb4a2
+MODULE_TYPE = USER_DEFINED
+VERSION_STRING = 1.0
+
+[Sources]
+ Dmar/Dmar.aslc
+ Dmar/Dmar.h
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+
+[Protocols]
+
+[PPIs]
+
+[Guids]
+
+[Depex]
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx.asl new file mode 100644 index 0000000000..c853700c40 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx.asl @@ -0,0 +1,1782 @@ +/** @file
+ This file contains the IGD OpRegion/Software ACPI Reference
+ Code.
+ It defines the methods to enable/disable output switching,
+ store display switching and LCD brightness BIOS control
+ and return valid addresses for all display device encoders
+ present in the system, etc.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+External(\ECST, MethodObj)
+External(\ECON, IntObj)
+External(OSYS, IntObj)
+External(CPSC)
+External(\GUAM, MethodObj)
+External(DSEN)
+External(S0ID)
+
+// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will
+// get called during initialization to prepare for an ACPI Display
+// Switch Event. During an ACPI Display Switch, the OS will call
+// _DOS = 2 immediately after a Notify=0x80 to temporarily disable
+// all Display Switching. After ACPI Display Switching is complete,
+// the OS will call _DOS = 0 to re-enable ACPI Display Switching.
+Method(_DOS,1)
+{
+ //
+ // Store Display Switching and LCD brightness BIOS control bit
+ //
+ Store(And(Arg0,7),DSEN)
+}
+
+//
+// Enumerate the Display Environment. This method will return
+// valid addresses for all display device encoders present in the
+// system. The Miniport Driver will reject the addresses for every
+// encoder that does not have an attached display device. After
+// enumeration is complete, the OS will call the _DGS methods
+// during a display switch only for the addresses accepted by the
+// Miniport Driver. For hot-insertion and removal of display
+// devices, a re-enumeration notification will be required so the
+// address of the newly present display device will be accepted by
+// the Miniport Driver.
+//
+Method(_DOD,0)
+{
+ If (LEqual(IMTP,1)) {
+ //
+ // Increment number of devices if iMGU is enabled
+ //
+ Store(1, NDID)
+ } Else {
+ Store(0, NDID)
+ }
+
+ If(LNotEqual(DIDL, Zero))
+ {
+ Store(SDDL(DIDL),DID1)
+ }
+ If(LNotEqual(DDL2, Zero))
+ {
+ Store(SDDL(DDL2),DID2)
+ }
+ If(LNotEqual(DDL3, Zero))
+ {
+ Store(SDDL(DDL3),DID3)
+ }
+ If(LNotEqual(DDL4, Zero))
+ {
+ Store(SDDL(DDL4),DID4)
+ }
+ If(LNotEqual(DDL5, Zero))
+ {
+ Store(SDDL(DDL5),DID5)
+ }
+ If(LNotEqual(DDL6, Zero))
+ {
+ Store(SDDL(DDL6),DID6)
+ }
+ If(LNotEqual(DDL7, Zero))
+ {
+ Store(SDDL(DDL7),DID7)
+ }
+ If(LNotEqual(DDL8, Zero))
+ {
+ Store(SDDL(DDL8),DID8)
+ }
+ If(LNotEqual(DDL9, Zero))
+ {
+ Store(SDDL(DDL9),DID9)
+ }
+ If(LNotEqual(DD10, Zero))
+ {
+ Store(SDDL(DD10),DIDA)
+ }
+ If(LNotEqual(DD11, Zero))
+ {
+ Store(SDDL(DD11),DIDB)
+ }
+ If(LNotEqual(DD12, Zero))
+ {
+ Store(SDDL(DD12),DIDC)
+ }
+ If(LNotEqual(DD13, Zero))
+ {
+ Store(SDDL(DD13),DIDD)
+ }
+ If(LNotEqual(DD14, Zero))
+ {
+ Store(SDDL(DD14),DIDE)
+ }
+ If(LNotEqual(DD15, Zero))
+ {
+ Store(SDDL(DD15),DIDF)
+ }
+
+ //
+ // Enumerate the encoders. Note that for
+ // current silicon, the maximum number of encoders
+ // possible is 15.
+ //
+ If(LEqual(NDID,1))
+ {
+ Name(TMP1,Package() {
+ 0xFFFFFFFF})
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP1,0))
+ } Else {
+ Store(Or(0x10000,DID1),Index(TMP1,0))
+ }
+ Return(TMP1)
+ }
+
+ If(LEqual(NDID,2))
+ {
+ Name(TMP2,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP2,0))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP2,1))
+ } Else {
+ Store(Or(0x10000,DID2),Index(TMP2,1))
+ }
+ Return(TMP2)
+ }
+
+ If(LEqual(NDID,3))
+ {
+ Name(TMP3,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP3,0))
+ Store(Or(0x10000,DID2),Index(TMP3,1))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP3,2))
+ } Else {
+ Store(Or(0x10000,DID3),Index(TMP3,2))
+ }
+ Return(TMP3)
+ }
+
+ If(LEqual(NDID,4))
+ {
+ Name(TMP4,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP4,0))
+ Store(Or(0x10000,DID2),Index(TMP4,1))
+ Store(Or(0x10000,DID3),Index(TMP4,2))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP4,3))
+ } Else {
+ Store(Or(0x10000,DID4),Index(TMP4,3))
+ }
+ Return(TMP4)
+ }
+
+ If(LEqual(NDID,5))
+ {
+ Name(TMP5,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP5,0))
+ Store(Or(0x10000,DID2),Index(TMP5,1))
+ Store(Or(0x10000,DID3),Index(TMP5,2))
+ Store(Or(0x10000,DID4),Index(TMP5,3))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP5,4))
+ } Else {
+ Store(Or(0x10000,DID5),Index(TMP5,4))
+ }
+ Return(TMP5)
+ }
+
+ If(LEqual(NDID,6))
+ {
+ Name(TMP6,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP6,0))
+ Store(Or(0x10000,DID2),Index(TMP6,1))
+ Store(Or(0x10000,DID3),Index(TMP6,2))
+ Store(Or(0x10000,DID4),Index(TMP6,3))
+ Store(Or(0x10000,DID5),Index(TMP6,4))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP6,5))
+ } Else {
+ Store(Or(0x10000,DID6),Index(TMP6,5))
+ }
+ Return(TMP6)
+ }
+
+ If(LEqual(NDID,7))
+ {
+ Name(TMP7,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP7,0))
+ Store(Or(0x10000,DID2),Index(TMP7,1))
+ Store(Or(0x10000,DID3),Index(TMP7,2))
+ Store(Or(0x10000,DID4),Index(TMP7,3))
+ Store(Or(0x10000,DID5),Index(TMP7,4))
+ Store(Or(0x10000,DID6),Index(TMP7,5))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP7,6))
+ } Else {
+ Store(Or(0x10000,DID7),Index(TMP7,6))
+ }
+ Return(TMP7)
+ }
+
+ If(LEqual(NDID,8))
+ {
+ Name(TMP8,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP8,0))
+ Store(Or(0x10000,DID2),Index(TMP8,1))
+ Store(Or(0x10000,DID3),Index(TMP8,2))
+ Store(Or(0x10000,DID4),Index(TMP8,3))
+ Store(Or(0x10000,DID5),Index(TMP8,4))
+ Store(Or(0x10000,DID6),Index(TMP8,5))
+ Store(Or(0x10000,DID7),Index(TMP8,6))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP8,7))
+ } Else {
+ Store(Or(0x10000,DID8),Index(TMP8,7))
+ }
+ Return(TMP8)
+ }
+
+ If(LEqual(NDID,9))
+ {
+ Name(TMP9,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMP9,0))
+ Store(Or(0x10000,DID2),Index(TMP9,1))
+ Store(Or(0x10000,DID3),Index(TMP9,2))
+ Store(Or(0x10000,DID4),Index(TMP9,3))
+ Store(Or(0x10000,DID5),Index(TMP9,4))
+ Store(Or(0x10000,DID6),Index(TMP9,5))
+ Store(Or(0x10000,DID7),Index(TMP9,6))
+ Store(Or(0x10000,DID8),Index(TMP9,7))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMP9,8))
+ } Else {
+ Store(Or(0x10000,DID9),Index(TMP9,8))
+ }
+ Return(TMP9)
+ }
+
+ If(LEqual(NDID,0x0A))
+ {
+ Name(TMPA,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPA,0))
+ Store(Or(0x10000,DID2),Index(TMPA,1))
+ Store(Or(0x10000,DID3),Index(TMPA,2))
+ Store(Or(0x10000,DID4),Index(TMPA,3))
+ Store(Or(0x10000,DID5),Index(TMPA,4))
+ Store(Or(0x10000,DID6),Index(TMPA,5))
+ Store(Or(0x10000,DID7),Index(TMPA,6))
+ Store(Or(0x10000,DID8),Index(TMPA,7))
+ Store(Or(0x10000,DID9),Index(TMPA,8))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMPA,9))
+ } Else {
+ Store(Or(0x10000,DIDA),Index(TMPA,9))
+ }
+ Return(TMPA)
+ }
+
+ If(LEqual(NDID,0x0B))
+ {
+ Name(TMPB,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPB,0))
+ Store(Or(0x10000,DID2),Index(TMPB,1))
+ Store(Or(0x10000,DID3),Index(TMPB,2))
+ Store(Or(0x10000,DID4),Index(TMPB,3))
+ Store(Or(0x10000,DID5),Index(TMPB,4))
+ Store(Or(0x10000,DID6),Index(TMPB,5))
+ Store(Or(0x10000,DID7),Index(TMPB,6))
+ Store(Or(0x10000,DID8),Index(TMPB,7))
+ Store(Or(0x10000,DID9),Index(TMPB,8))
+ Store(Or(0x10000,DIDA),Index(TMPB,9))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMPB,10))
+ } Else {
+ Store(Or(0x10000,DIDB),Index(TMPB,10))
+ }
+ Return(TMPB)
+ }
+
+ If(LEqual(NDID,0x0C))
+ {
+ Name(TMPC,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPC,0))
+ Store(Or(0x10000,DID2),Index(TMPC,1))
+ Store(Or(0x10000,DID3),Index(TMPC,2))
+ Store(Or(0x10000,DID4),Index(TMPC,3))
+ Store(Or(0x10000,DID5),Index(TMPC,4))
+ Store(Or(0x10000,DID6),Index(TMPC,5))
+ Store(Or(0x10000,DID7),Index(TMPC,6))
+ Store(Or(0x10000,DID8),Index(TMPC,7))
+ Store(Or(0x10000,DID9),Index(TMPC,8))
+ Store(Or(0x10000,DIDA),Index(TMPC,9))
+ Store(Or(0x10000,DIDB),Index(TMPC,10))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMPC,11))
+ } Else {
+ Store(Or(0x10000,DIDC),Index(TMPC,11))
+ }
+ Return(TMPC)
+ }
+
+ If(LEqual(NDID,0x0D))
+ {
+ Name(TMPD,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPD,0))
+ Store(Or(0x10000,DID2),Index(TMPD,1))
+ Store(Or(0x10000,DID3),Index(TMPD,2))
+ Store(Or(0x10000,DID4),Index(TMPD,3))
+ Store(Or(0x10000,DID5),Index(TMPD,4))
+ Store(Or(0x10000,DID6),Index(TMPD,5))
+ Store(Or(0x10000,DID7),Index(TMPD,6))
+ Store(Or(0x10000,DID8),Index(TMPD,7))
+ Store(Or(0x10000,DID9),Index(TMPD,8))
+ Store(Or(0x10000,DIDA),Index(TMPD,9))
+ Store(Or(0x10000,DIDB),Index(TMPD,10))
+ Store(Or(0x10000,DIDC),Index(TMPD,11))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMPD,12))
+ } Else {
+ Store(Or(0x10000,DIDD),Index(TMPD,12))
+ }
+ Return(TMPD)
+ }
+
+ If(LEqual(NDID,0x0E))
+ {
+ Name(TMPE,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPE,0))
+ Store(Or(0x10000,DID2),Index(TMPE,1))
+ Store(Or(0x10000,DID3),Index(TMPE,2))
+ Store(Or(0x10000,DID4),Index(TMPE,3))
+ Store(Or(0x10000,DID5),Index(TMPE,4))
+ Store(Or(0x10000,DID6),Index(TMPE,5))
+ Store(Or(0x10000,DID7),Index(TMPE,6))
+ Store(Or(0x10000,DID8),Index(TMPE,7))
+ Store(Or(0x10000,DID9),Index(TMPE,8))
+ Store(Or(0x10000,DIDA),Index(TMPE,9))
+ Store(Or(0x10000,DIDB),Index(TMPE,10))
+ Store(Or(0x10000,DIDC),Index(TMPE,11))
+ Store(Or(0x10000,DIDD),Index(TMPE,12))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMPE,13))
+ } Else {
+ Store(Or(0x10000,DIDE),Index(TMPE,13))
+ }
+ Return(TMPE)
+ }
+
+ If(LEqual(NDID,0x0F))
+ {
+ Name(TMPF,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPF,0))
+ Store(Or(0x10000,DID2),Index(TMPF,1))
+ Store(Or(0x10000,DID3),Index(TMPF,2))
+ Store(Or(0x10000,DID4),Index(TMPF,3))
+ Store(Or(0x10000,DID5),Index(TMPF,4))
+ Store(Or(0x10000,DID6),Index(TMPF,5))
+ Store(Or(0x10000,DID7),Index(TMPF,6))
+ Store(Or(0x10000,DID8),Index(TMPF,7))
+ Store(Or(0x10000,DID9),Index(TMPF,8))
+ Store(Or(0x10000,DIDA),Index(TMPF,9))
+ Store(Or(0x10000,DIDB),Index(TMPF,10))
+ Store(Or(0x10000,DIDC),Index(TMPF,11))
+ Store(Or(0x10000,DIDD),Index(TMPF,12))
+ Store(Or(0x10000,DIDE),Index(TMPF,13))
+ If (LEqual(IMTP,1)) {
+ //
+ // IGFX need report ISP0 as GFX0 child
+ //
+ Store(0x0002CA00,Index(TMPF,14))
+ } Else {
+ Store(Or(0x10000,DIDF),Index(TMPF,14))
+ }
+ Return(TMPF)
+ }
+
+ If(LEqual(NDID,0x10))
+ {
+ Name(TMPG,Package() {
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF,
+ 0xFFFFFFFF})
+ Store(Or(0x10000,DID1),Index(TMPG,0))
+ Store(Or(0x10000,DID2),Index(TMPG,1))
+ Store(Or(0x10000,DID3),Index(TMPG,2))
+ Store(Or(0x10000,DID4),Index(TMPG,3))
+ Store(Or(0x10000,DID5),Index(TMPG,4))
+ Store(Or(0x10000,DID6),Index(TMPG,5))
+ Store(Or(0x10000,DID7),Index(TMPG,6))
+ Store(Or(0x10000,DID8),Index(TMPG,7))
+ Store(Or(0x10000,DID9),Index(TMPG,8))
+ Store(Or(0x10000,DIDA),Index(TMPG,9))
+ Store(Or(0x10000,DIDB),Index(TMPG,10))
+ Store(Or(0x10000,DIDC),Index(TMPG,11))
+ Store(Or(0x10000,DIDD),Index(TMPG,12))
+ Store(Or(0x10000,DIDE),Index(TMPG,13))
+ Store(Or(0x10000,DIDF),Index(TMPG,14))
+ //
+ // IGFX need report ISP0 as GFX0 child
+ // NDID can only be 0x10 if IMGU is enabled
+ //
+ Store(0x0002CA00,Index(TMPG,15))
+ Return(TMPG)
+ }
+
+ //
+ // If nothing else, return Unknown LFP.
+ // (Prevents compiler warning.)
+ //
+ Return(Package() {0x00000400})
+}
+
+Device(DD01)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID1),0x400))
+ {
+ Store(0x1, EDPV)
+ Store(NXD1, NXDX)
+ Store(DID1, DIDX)
+ Return(1)
+ }
+ If(LEqual(DID1,0))
+ {
+ Return(1)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID1))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ Return(CDDS(DID1))
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD1)
+ }
+ Return(NDDS(DID1))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD02)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID2),0x400))
+ {
+ Store(0x2, EDPV)
+ Store(NXD2, NXDX)
+ Store(DID2, DIDX)
+ Return(2)
+ }
+ If(LEqual(DID2,0))
+ {
+ Return(2)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID2))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(LIDS,0))
+ {
+ Return(0x0)
+ }
+ Return(CDDS(DID2))
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ //
+ // Return the Next State.
+ //
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD2)
+ }
+ Return(NDDS(DID2))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD03)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID3),0x400))
+ {
+ Store(0x3, EDPV)
+ Store(NXD3, NXDX)
+ Store(DID3, DIDX)
+ Return(3)
+ }
+ If(LEqual(DID3,0))
+ {
+ Return(3)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID3))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID3,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID3))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD3)
+ }
+ Return(NDDS(DID3))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD04)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID4),0x400))
+ {
+ Store(0x4, EDPV)
+ Store(NXD4, NXDX)
+ Store(DID4, DIDX)
+ Return(4)
+ }
+ If(LEqual(DID4,0))
+ {
+ Return(4)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID4))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID4,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID4))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD4)
+ }
+ Return(NDDS(DID4))
+ }
+
+ //
+ // Device Set State. (See table above.)
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD05)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID5),0x400))
+ {
+ Store(0x5, EDPV)
+ Store(NXD5, NXDX)
+ Store(DID5, DIDX)
+ Return(5)
+ }
+ If(LEqual(DID5,0))
+ {
+ Return(5)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID5))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID5,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID5))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD5)
+ }
+ Return(NDDS(DID5))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD06)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID6),0x400))
+ {
+ Store(0x6, EDPV)
+ Store(NXD6, NXDX)
+ Store(DID6, DIDX)
+ Return(6)
+ }
+ If(LEqual(DID6,0))
+ {
+ Return(6)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID6))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID6,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID6))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD6)
+ }
+ Return(NDDS(DID6))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD07)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID7),0x400))
+ {
+ Store(0x7, EDPV)
+ Store(NXD7, NXDX)
+ Store(DID7, DIDX)
+ Return(7)
+ }
+ If(LEqual(DID7,0))
+ {
+ Return(7)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID7))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID7,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID7))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD7)
+ }
+ Return(NDDS(DID7))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD08)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID8),0x400))
+ {
+ Store(0x8, EDPV)
+ Store(NXD8, NXDX)
+ Store(DID8, DIDX)
+ Return(8)
+ }
+ If(LEqual(DID8,0))
+ {
+ Return(8)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID8))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID8,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID8))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DID8))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD09)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DID9),0x400))
+ {
+ Store(0x9, EDPV)
+ Store(NXD8, NXDX)
+ Store(DID9, DIDX)
+ Return(9)
+ }
+ If(LEqual(DID9,0))
+ {
+ Return(9)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DID9))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DID9,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DID9))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DID9))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD0A)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDA),0x400))
+ {
+ Store(0xA, EDPV)
+ Store(NXD8, NXDX)
+ Store(DIDA, DIDX)
+ Return(0x0A)
+ }
+ If(LEqual(DIDA,0))
+ {
+ Return(0x0A)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDA))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDA,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DIDA))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DIDA))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD0B)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDB),0x400))
+ {
+ Store(0xB, EDPV)
+ Store(NXD8, NXDX)
+ Store(DIDB, DIDX)
+ Return(0X0B)
+ }
+ If(LEqual(DIDB,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDB))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDB,0))
+ {
+ Return(0x0B)
+ }
+ Else
+ {
+ Return(CDDS(DIDB))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DIDB))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD0C)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDC),0x400))
+ {
+ Store(0xC, EDPV)
+ Store(NXD8, NXDX)
+ Store(DIDC, DIDX)
+ Return(0X0C)
+ }
+ If(LEqual(DIDC,0))
+ {
+ Return(0x0C)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDC))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDC,0))
+ {
+ Return(0x0C)
+ }
+ Else
+ {
+ Return(CDDS(DIDC))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DIDC))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD0D)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDD),0x400))
+ {
+ Store(0xD, EDPV)
+ Store(NXD8, NXDX)
+ Store(DIDD, DIDX)
+ Return(0X0D)
+ }
+ If(LEqual(DIDD,0))
+ {
+ Return(0x0D)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDD))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDD,0))
+ {
+ Return(0x0D)
+ }
+ Else
+ {
+ Return(CDDS(DIDD))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DIDD))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD0E)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDE),0x400))
+ {
+ Store(0xE, EDPV)
+ Store(NXD8, NXDX)
+ Store(DIDE, DIDX)
+ Return(0X0E)
+ }
+ If(LEqual(DIDE,0))
+ {
+ Return(0x0E)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDE))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDE,0))
+ {
+ Return(0x0E)
+ }
+ Else
+ {
+ Return(CDDS(DIDE))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DIDE))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+Device(DD0F)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(And(0x0F00,DIDF),0x400))
+ {
+ Store(0xF, EDPV)
+ Store(NXD8, NXDX)
+ Store(DIDF, DIDX)
+ Return(0X0F)
+ }
+ If(LEqual(DIDF,0))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDF))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(DIDC,0))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(CDDS(DIDF))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXD8)
+ }
+ Return(NDDS(DIDF))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+}
+
+//
+//Device for eDP
+//
+Device(DD1F)
+{
+ //
+ // Return Unique ID.
+ //
+ Method(_ADR,0,Serialized)
+ {
+ If(LEqual(EDPV, 0x0))
+ {
+ Return(0x1F)
+ }
+ Else
+ {
+ Return(And(0xFFFF,DIDX))
+ }
+ }
+
+ //
+ // Return the Current Status.
+ //
+ Method(_DCS,0)
+ {
+ If(LEqual(EDPV, 0x0))
+ {
+ Return(0x00)
+ }
+ Else
+ {
+ Return(CDDS(DIDX))
+ }
+ }
+
+ //
+ // Query Graphics State (active or inactive).
+ //
+ Method(_DGS,0)
+ {
+ If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD)))
+ {
+ Return (NXDX)
+ }
+ Return(NDDS(DIDX))
+ }
+
+ //
+ // Device Set State.
+ //
+ Method(_DSS,1)
+ {
+ DSST(Arg0)
+ }
+
+ //
+ // Query List of Brightness Control Levels Supported.
+ //
+ Method(_BCL,0)
+ {
+ //
+ // List of supported brightness levels in the following sequence.
+ // Level when machine has full power.
+ // Level when machine is on batteries.
+ // Other supported levels.
+ //
+ Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})
+ }
+
+ //
+ // Set the Brightness Level.
+ //
+ Method (_BCM,1)
+ {
+ //
+ // Set the requested level if it is between 0 and 100%.
+ //
+ If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))
+ {
+ \_SB.PCI0.GFX0.AINT(1, Arg0)
+ Store(Arg0,BRTL) // Store Brightness Level.
+ }
+ }
+
+ //
+ // Brightness Query Current level.
+ //
+ Method (_BQC,0)
+ {
+ Return(BRTL)
+ }
+}
+
+Method(SDDL,1)
+{
+ Increment(NDID)
+ Store(And(Arg0,0xF0F),Local0)
+ Or(0x80000000,Local0, Local1)
+ If(LEqual(DIDL,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL2,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL3,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL4,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL5,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL6,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL7,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL8,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DDL9,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD10,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD11,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD12,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD13,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD14,Local0))
+ {
+ Return(Local1)
+ }
+ If(LEqual(DD15,Local0))
+ {
+ Return(Local1)
+ }
+ Return(0)
+}
+
+Method(CDDS,1)
+{
+ Store(And(Arg0,0xF0F),Local0)
+
+ If(LEqual(0, Local0))
+ {
+ Return(0x1D)
+ }
+ If(LEqual(CADL, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL2, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL3, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL4, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL5, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL6, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL7, Local0))
+ {
+ Return(0x1F)
+ }
+ If(LEqual(CAL8, Local0))
+ {
+ Return(0x1F)
+ }
+ Return(0x1D)
+}
+
+Method(NDDS,1)
+{
+ Store(And(Arg0,0xF0F),Local0)
+
+ If(LEqual(0, Local0))
+ {
+ Return(0)
+ }
+ If(LEqual(NADL, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL2, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL3, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL4, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL5, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL6, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL7, Local0))
+ {
+ Return(1)
+ }
+ If(LEqual(NDL8, Local0))
+ {
+ Return(1)
+ }
+ Return(0)
+}
+
+//
+// Device Set State Table
+// BIT31 BIT30 Execution
+// 0 0 Don't implement.
+// 0 1 Cache change. Nothing to Implement.
+// 1 0 Don't Implement.
+// 1 1 Display Switch Complete. Implement.
+//
+Method(DSST,1)
+{
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))
+ {
+ //
+ // State change was performed by the
+ // Video Drivers. Simply update the
+ // New State.
+ //
+ Store(NSTE,CSTE)
+ }
+}
+
+//
+// Include IGD OpRegion/Software SCI interrupt handler/DSM which is used by
+// the graphics drivers to request data from system BIOS.
+//
+include ("IgfxOpRn.asl")
+include ("IgfxDsm.asl")
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxCommon.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxCommon.asl new file mode 100644 index 0000000000..4d28ad0068 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxCommon.asl @@ -0,0 +1,487 @@ +/** @file
+ IGD OpRegion/Software SCI Reference Code.
+ This file contains ASL code with the purpose of handling events
+ i.e. hotkeys and other system interrupts.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+//
+// Notes:
+// 1. The following routines are to be called from the appropriate event
+// handlers.
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.
+// Therefore, an OEM must call these methods from the existing event
+// handler infrastructure. Details on when/why to call each method is
+// included in the method header under the "usage" section.
+//
+
+/************************************************************************;
+;* ACPI Notification Methods
+;************************************************************************/
+
+
+/************************************************************************;
+;*
+;* Name: PDRD
+;*
+;* Description: Check if the graphics driver is ready to process
+;* notifications and video extensions.
+;*
+;* Usage: This method is to be called prior to performing any
+;* notifications or handling video extensions.
+;* Ex: If (PDRD()) {Return (FAIL)}
+;*
+;* Input: None
+;*
+;* Output: None
+;*
+;* References: DRDY (Driver ready status), ASLP (Driver recommended
+;* sleep timeout value).
+;*
+;************************************************************************/
+
+External(HNOT, MethodObj)
+
+Method(PDRD)
+{
+ //
+ // If DRDY is clear, the driver is not ready. If the return value is
+ // !=0, do not perform any notifications or video extension handling.
+ //
+ Return(LNot(DRDY))
+}
+
+/************************************************************************;
+;*
+;* Name: PSTS
+;*
+;* Description: Check if the graphics driver has completed the previous
+;* "notify" command.
+;*
+;* Usage: This method is called before every "notify" command. A
+;* "notify" should only be set if the driver has completed the
+;* previous command. Else, ignore the event and exit the parent
+;* method.
+;* Ex: If (PSTS()) {Return (FAIL)}
+;*
+;* Input: None
+;*
+;* Output: None
+;*
+;* References: CSTS (Notification status), ASLP (Driver recommended sleep
+;* timeout value).
+;*
+;************************************************************************/
+
+Method(PSTS)
+{
+ If(LGreater(CSTS, 2))
+ {
+ //
+ // Sleep for ASLP milliseconds if the status is not "success,
+ // failure, or pending"
+ //
+ Sleep(ASLP)
+ }
+
+ Return(LEqual(CSTS, 3)) // Return True if still Dispatched
+}
+
+/************************************************************************;
+;*
+;* Name: GNOT
+;*
+;* Description: Call the appropriate methods to query the graphics driver
+;* status. If all methods return success, do a notification of
+;* the graphics device.
+;*
+;* Usage: This method is to be called when a graphics device
+;* notification is required (display switch hotkey, etc).
+;*
+;* Input: Arg0 = Current event type:
+;* 1 = display switch
+;* 2 = lid
+;* 3 = dock
+;* Arg1 = Notification type:
+;* 0 = Re-enumeration
+;* 0x80 = Display switch
+;*
+;* Output: Returns 0 = success, 1 = failure
+;*
+;* References: PDRD and PSTS methods. OSYS (OS version)
+;*
+;************************************************************************/
+
+Method(GNOT, 2)
+{
+ //
+ // Check for 1. Driver loaded, 2. Driver ready.
+ // If any of these cases is not met, skip this event and return failure.
+ //
+ If(PDRD())
+ {
+ Return(0x1) // Return failure if driver not loaded.
+ }
+
+ Store(Arg0, CEVT) // Set up the current event value
+ Store(3, CSTS) // CSTS=BIOS dispatched an event
+
+ If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver supports hotplug
+ {
+ //
+ // Re-enumerate the Graphics Device for non-XP operating systems.
+ //
+ Notify(\_SB.PCI0.GFX0, Arg1)
+ }
+
+ If(CondRefOf(HNOT))
+ {
+ HNOT(Arg0) //Notification handler for Switchable graphics
+ }
+ Else
+ {
+ Notify(\_SB.PCI0.GFX0,0x80)
+ }
+
+ Return(0x0) // Return success
+}
+
+/************************************************************************;
+;*
+;* Name: GHDS
+;*
+;* Description: Handle a hotkey display switching event (performs a
+;* Notify(GFX0, 0).
+;*
+;* Usage: This method must be called when a hotkey event occurs and the
+;* purpose of that hotkey is to do a display switch.
+;*
+;* Input: Arg0 = Toggle table number.
+;*
+;* Output: Returns 0 = success, 1 = failure.
+;* CEVT and TIDX are indirect outputs.
+;*
+;* References: TIDX, GNOT
+;*
+;************************************************************************/
+
+Method(GHDS, 1)
+{
+ Store(Arg0, TIDX) // Store the table number
+ //
+ // Call GNOT for CEVT = 1 = hotkey, notify value = 0
+ //
+ Return(GNOT(1, 0)) // Return stats from GNOT
+}
+
+/************************************************************************;
+;*
+;* Name: GLID
+;*
+;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the
+;* lid notify).
+;*
+;* Usage: This method must be called when a lid event occurs. A
+;* Notify(LID0, 0x80) must follow the call to this method.
+;*
+;* Input: Arg0 = Lid state:
+;* 0 = All closed
+;* 1 = internal LFP lid open
+;* 2 = external lid open
+;* 3 = both external and internal open
+;*
+;* Output: Returns 0=success, 1=failure.
+;* CLID and CEVT are indirect outputs.
+;*
+;* References: CLID, GNOT
+;*
+;************************************************************************/
+
+Method(GLID, 1)
+{
+
+ If (LEqual(Arg0,1))
+ {
+ Store(3,CLID)
+ }
+ Else
+ {
+ Store(Arg0, CLID)
+ }
+ //
+ //Store(Arg0, CLID) // Store the current lid state
+ // Call GNOT for CEVT=2=Lid, notify value = 0
+ //
+ if (GNOT(2, 0)) {
+ Or (CLID, 0x80000000, CLID)
+ Return (1) // Return Fail
+ }
+
+ Return (0) // Return Pass
+}
+
+/************************************************************************;
+;*
+;* Name: GDCK
+;*
+;* Description: Handle a docking event by updating the current docking status
+;* and doing a notification.
+;*
+;* Usage: This method must be called when a docking event occurs.
+;*
+;* Input: Arg0 = Docking state:
+;* 0 = Undocked
+;* 1 = Docked
+;*
+;* Output: Returns 0=success, 1=failure.
+;* CDCK and CEVT are indirect outputs.
+;*
+;* References: CDCK, GNOT
+;*
+;************************************************************************/
+
+Method(GDCK, 1)
+{
+ Store(Arg0, CDCK) // Store the current dock state
+ //
+ // Call GNOT for CEVT=4=Dock, notify value = 0
+ //
+ Return(GNOT(4, 0)) // Return stats from GNOT
+}
+
+/************************************************************************;
+;* ASLE Interrupt Methods
+;************************************************************************/
+
+/************************************************************************;
+;*
+;* Name: PARD
+;*
+;* Description: Check if the driver is ready to handle ASLE interrupts
+;* generate by the system BIOS.
+;*
+;* Usage: This method must be called before generating each ASLE
+;* interrupt.
+;*
+;* Input: None
+;*
+;* Output: Returns 0 = success, 1 = failure.
+;*
+;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep
+;* timeout value)
+;*
+;************************************************************************/
+
+Method(PARD)
+{
+ If(LNot(ARDY))
+ {
+ //
+ // Sleep for ASLP milliseconds if the driver is not ready.
+ //
+ Sleep(ASLP)
+ }
+ //
+ // If ARDY is clear, the driver is not ready. If the return value is
+ // !=0, do not generate the ASLE interrupt.
+ //
+ Return(LNot(ARDY))
+}
+
+//
+// Intel Ultrabook Event Handler. Arg0 represents the Ultrabook Event Bit # to pass
+// to the Intel Graphics Driver. Note that this is a serialized method, meaning
+// sumultaneous events are not allowed.
+//
+Method(IUEH,1,Serialized)
+{
+ And(IUER,0xC0,IUER) // Clear all button events on entry.
+ XOr(IUER,Shiftleft(1,Arg0),IUER) // Toggle status.
+
+ If(LLessEqual(Arg0,4)) // Button Event?
+ {
+ Return(AINT(5,0)) // Generate event and return status.
+
+ }
+ Else // Indicator Event.
+ {
+ Return(AINT(Arg0,0)) // Generate event and return status.
+ }
+}
+
+/************************************************************************;
+;*
+;* Name: AINT
+;*
+;* Description: Call the appropriate methods to generate an ASLE interrupt.
+;* This process includes ensuring the graphics driver is ready
+;* to process the interrupt, ensuring the driver supports the
+;* interrupt of interest, and passing information about the event
+;* to the graphics driver.
+;*
+;* Usage: This method must called to generate an ASLE interrupt.
+;*
+;* Input: Arg0 = ASLE command function code:
+;* 0 = Set ALS illuminance
+;* 1 = Set backlight brightness
+;* 2 = Do Panel Fitting
+;* 4 = Reserved
+;* 5 = Button Indicator Event
+;* 6 = Convertible Indicator Event
+;* 7 = Docking Indicator Event
+;* Arg1 = If Arg0 = 0, current ALS reading:
+;* 0 = Reading below sensor range
+;* 1-0xFFFE = Current sensor reading
+;* 0xFFFF = Reading above sensor range
+;* Arg1 = If Arg0 = 1, requested backlight percentage
+;*
+;* Output: Returns 0 = success, 1 = failure
+;*
+;* References: PARD method.
+;*
+;************************************************************************/
+
+Method(AINT, 2)
+{
+ //
+ // Return failure if the requested feature is not supported by the
+ // driver.
+ //
+ If(LNot(And(TCHE, ShiftLeft(1, Arg0))))
+ {
+ Return(0x1)
+ }
+ //
+ // Return failure if the driver is not ready to handle an ASLE
+ // interrupt.
+ //
+ If(PARD())
+ {
+ Return(0x1)
+ }
+ //
+ // Handle Intel Ultrabook Events.
+ //
+ If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7)))
+ {
+ Store(ShiftLeft(1,Arg0), ASLC) // Set Ultrbook Event [6:4].
+ Store(0x01, ASLE) // Generate ASLE interrupt
+
+ Store(0,Local2) // Use Local2 as a timeout counter. Intialize to zero.
+
+ While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0))) // Wait 1 second or until Driver ACKs a success.
+ {
+ Sleep(4) // Delay 4 ms.
+ Increment(Local2) // Increment Timeout.
+ }
+
+ Return(0) // Return success
+ }
+ //
+ // Evaluate the first argument (Panel fitting, backlight brightness, or ALS).
+ //
+ If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change.
+ {
+ If(CPFM) // If current mode field is non-zero use it.
+ {
+ And(CPFM, 0x0F, Local0) // Create variables without reserved
+ And(EPFM, 0x0F, Local1) // or valid bits.
+
+ If(LEqual(Local0, 1)) // If current mode is centered,
+ {
+ If(And(Local1, 6)) // and if stretched is enabled,
+ {
+ Store(6, PFIT) // request stretched.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 8)) // if aspect ratio is enabled,
+ {
+ Store(8, PFIT) // request aspect ratio.
+ }
+ Else // Only centered mode is enabled
+ {
+ Store(1, PFIT) // so request centered. (No change.)
+ }
+ }
+ }
+ If(LEqual(Local0, 6)) // If current mode is stretched,
+ {
+ If(And(Local1, 8)) // and if aspect ratio is enabled,
+ {
+ Store(8, PFIT) // request aspect ratio.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 1)) // if centered is enabled,
+ {
+ Store(1, PFIT) // request centered.
+ }
+ Else // Only stretched mode is enabled
+ {
+ Store(6, PFIT) // so request stretched. (No change.)
+ }
+ }
+ }
+ If(LEqual(Local0, 8)) // If current mode is aspect ratio,
+ {
+ If(And(Local1, 1)) // and if centered is enabled,
+ {
+ Store(1, PFIT) // request centered.
+ }
+ Else // Otherwise,
+ {
+ If(And(Local1, 6)) // if stretched is enabled,
+ {
+ Store(6, PFIT) // request stretched.
+ }
+ Else // Only aspect ratio mode is enabled
+ {
+ Store(8, PFIT) // so request aspect ratio. (No change.)
+ }
+ }
+ }
+ }
+ //
+ // The following code for panel fitting (within the Else condition) is retained for backward compatiblity.
+ //
+ Else // If CFPM field is zero use PFIT and toggle the
+ {
+ Xor(PFIT,7,PFIT) // mode setting between stretched and centered only.
+ }
+ Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases.
+ Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1]
+ }
+ Else
+ {
+ If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness.
+ {
+ Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255.
+ Or(BCLP, 0x80000000, BCLP) // Set the valid bit.
+ Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1]
+ }
+ Else
+ {
+ If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace
+ {
+ Store(Arg1, ALSI)
+ Store(1, ASLC) // Store "ALS event" to ASLC[31:1]
+ }
+ Else
+ {
+ Return(0x1) // Unsupported function
+ }
+ }
+ }
+
+ Store(0x01, ASLE) // Generate ASLE interrupt
+ Return(0x0) // Return success
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxDsm.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxDsm.asl new file mode 100644 index 0000000000..974f7b706d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxDsm.asl @@ -0,0 +1,359 @@ +/** @file
+ IGD OpRegion/_DSM Reference Code.
+ This file contains Get BIOS Data and Callback functions for
+ the Integrated Graphics Device (IGD) OpRegion/DSM mechanism
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// _DSM Device Specific Method
+//
+// Arg0: UUID Unique function identifier
+// Arg1: Integer Revision Level
+// Arg2: Integer Function Index (1 = Return Supported Functions)
+// Arg3: Additional Inputs/Package Parameters Bits [31:0] input as {Byte0, Byte1, Byte2, Byte3} to BIOS which is passed as 32 bit DWORD by Driver
+//
+Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
+
+ If (LEqual(Arg0, ToUUID ("3E5B41C6-EB1D-4260-9D15-C71FBADAE414"))) {
+ //
+ // _DSM Definition for Igd functions
+ // Arguments:
+ // Arg0: UUID: 3E5B41C6-EB1D-4260-9D15-C71FBADAE414
+ // Arg1: Revision ID: 1
+ // Arg2: Function Index: 16
+ // Arg3: Additional Inputs Bits[31:0] Arg3 {Byte0, Byte1, Byte2, Byte3}
+ //
+ // Return:
+ // Success for simple notification, Opregion update for some routines and a Package for AKSV
+ //
+ //
+ // Switch by function index
+ //
+ Switch(ToInteger(Arg2)) {
+ //
+ // Function Index: 0
+ // Standard query - A bitmask of functions supported
+ //
+ // Return: A bitmask of functions supported
+ //
+ Case (0)
+ {
+ If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store("iGfx Supported Functions Bitmap ", Debug)
+ Return (0x1E7FF) // For SKL bit 11 and 12 is not supported
+ }
+ }
+
+ //
+ // Function Index: 1
+ // Adapter Power State Notification
+ // Arg3 Bits [7:0]: Adapter Power State bits [7:0] from Driver 00h = D0; 01h = D1; 02h = D2; 04h = D3 (Cold/Hot); 08h = D4 (Hibernate Notification)
+ // Return: Success
+ //
+ Case(1) {
+ If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store(" Adapter Power State Notification ", Debug)
+
+ //
+ // Handle Low Power S0 Idle Capability if enabled
+ //
+ If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {
+ //
+ // Call GUAM to trigger CS Entry
+ // If Adapter Power State Notification = D1 (Arg3[0]=0x01)
+ //
+ If (LEqual (And(DerefOf (Index (Arg3,0)), 0xFF), 0x01)) {
+ // GUAM - Global User Absent Mode Notification Method
+ \GUAM(One) // 0x01 - Power State Standby (CS Entry)
+ }
+ Store(And(DerefOf (Index (Arg3,1)), 0xFF), Local0)
+ //
+ // Call GUAM
+ // If Display Turn ON Notification (Arg3 [1] == 0) for CS Exit
+ //
+ If (LEqual (Local0, 0)) {
+ // GUAM - Global User Absent Mode Notification Method
+ \GUAM(0)
+ }
+ }
+
+ // Upon notification from driver that the Adapter Power State = D0,
+ // check if previous lid event failed. If it did, retry the lid
+ // event here.
+ If(LEqual(DerefOf (Index (Arg3,0)), 0)) {
+ Store(CLID, Local0)
+ If(And(0x80000000,Local0)) {
+ And(CLID, 0x0000000F, CLID)
+ GLID(CLID)
+ }
+ }
+ Return(0x01)
+ }
+ }
+ //
+ // Function Index: 2
+ // Display Power State Notification
+ // Arg3: Display Power State Bits [15:8]
+ // 00h = On
+ // 01h = Standby
+ // 02h = Suspend
+ // 04h = Off
+ // 08h = Reduced On
+ // Return: Success
+ //
+ Case(2) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+
+ Store("Display Power State Notification ", Debug)
+ Return(0x01)
+ }
+ }
+
+ //
+ // Function Index: 3
+ // BIOS POST Completion Notification
+ // Return: Success
+ //
+ Case(3) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+ Store("BIOS POST Completion Notification ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 4
+ // Pre-Hires Set Mode
+ // Return: Success
+ //
+ Case(4) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("Pre-Hires Set Mode ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 5
+ // Post-Hires Set Mode
+ // Return: Success
+ //
+ Case(5) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("Post-Hires Set Mode ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 6
+ // SetDisplayDeviceNotification (Display Switch)
+ // Return: Success
+ //
+ Case(6) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("SetDisplayDeviceNotification", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 7
+ // SetBootDevicePreference
+ // Return: Success
+ //
+ Case(7) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ //<TODO> An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+
+ Store("SetBootDevicePreference ", Debug)
+ And(DerefOf (Index (Arg3,0)), 0xFF, IBTT) // Save the boot display to NVS
+ Return(0x01)
+ }
+ }
+
+ //
+ // Function Index: 8
+ // SetPanelPreference
+ // Return: Success
+ //
+ Case(8) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ // An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+
+ Store("SetPanelPreference ", Debug)
+
+ // Set the panel-related NVRAM variables based the input from the driver.
+ And(DerefOf (Index (Arg3,0)), 0xFF, IPSC)
+
+ // Change panel type if a change is requested by the driver (Change if
+ // panel type input is non-zero). Zero=No change requested.
+ If(And(DerefOf (Index (Arg3,1)), 0xFF)) {
+ And(DerefOf (Index (Arg3,1)), 0xFF, IPAT)
+ Decrement(IPAT) // 0 = no change, so fit to CMOS map
+ }
+ And(ShiftRight(DerefOf (Index (Arg3,2)), 4), 0x7, IBIA)
+ Return(0x01) // Success
+ }
+ }
+
+ //
+ // Function Index: 9
+ // FullScreenDOS
+ // Return: Success
+ //
+ Case(9) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("FullScreenDOS ", Debug)
+ Return(0x01) // Not supported, but no failure
+ }
+ }
+
+ //
+ // Function Index: 10
+ // APM Complete
+ // Return: Adjusted Lid State
+ //
+ Case(10) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+
+ Store("APM Complete ", Debug)
+ Store(ShiftLeft(LIDS, 8), Local0) // Report the lid state
+ Add(Local0, 0x100, Local0) // Adjust the lid state, 0 = Unknown
+ Return(Local0)
+ }
+ }
+
+ //
+ //
+ // Function Index: 13
+ // GetBootDisplayPreference
+ // Arg3 Bits [30:16] : Boot Device Ports
+ // Arg3 Bits [7:0] : Boot Device Type
+ // Return: Boot device port and Boot device type from saved configuration
+ //
+ Case(13) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+
+ Store("GetBootDisplayPreference ", Debug)
+ Or(ShiftLeft(DerefOf (Index (Arg3,3)), 24), ShiftLeft(DerefOf (Index (Arg3,2)), 16), Local0) // Combine Arg3 Bits [31:16]
+ And(Local0, 0xEFFF0000, Local0)
+ And(Local0, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), Local0)
+ Or(IBTT, Local0, Local0) // Arg3 Bits [7:0] = Boot device type
+ Return(Local0)
+ }
+ }
+
+ //
+ // Function Index: 14
+ // GetPanelDetails
+ // Return: Different Panel Settings
+ //
+ Case(14) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("GetPanelDetails ", Debug)
+
+ // Report the scaling setting
+ // Bits [7:0] - Panel Scaling
+ // Bits contain the panel scaling user setting from CMOS
+ // 00h = On: Auto
+ // 01h = On: Force Scaling
+ // 02h = Off
+ // 03h = Maintain Aspect Ratio
+
+ Store(IPSC, Local0)
+ Or(Local0, ShiftLeft(IPAT, 8), Local0)
+
+ // Adjust panel type, 0 = VBT default
+ // Bits [15:8] - Panel Type
+ // Bits contain the panel type user setting from CMOS
+ // 00h = Not Valid, use default Panel Type & Timings from VBT
+ // 01h - 0Fh = Panel Number
+
+ Add(Local0, 0x100, Local0)
+
+ // Report the lid state and Adjust it
+ // Bits [16] - Lid State
+ // Bits contain the current panel lid state
+ // 0 = Lid Open
+ // 1 = Lid Closed
+
+ Or(Local0, ShiftLeft(LIDS, 16), Local0)
+ Add(Local0, 0x10000, Local0)
+
+ // Report the BIA setting
+ // Bits [22:20] - Backlight Image Adaptation (BIA) Control
+ // Bits contain the backlight image adaptation control user setting from CMOS
+ // 000 = VBT Default
+ // 001 = BIA Disabled (BLC may still be enabled)
+ // 010 - 110 = BIA Enabled at Aggressiveness Level [1 - 5]
+
+ Or(Local0, ShiftLeft(IBIA, 20), Local0)
+ Return(Local0)
+ }
+ }
+
+ //
+ // Function Index: 15
+ // GetInternalGraphics
+ // Return: Different Internal Grahics Settings
+ //
+
+ Case(15) {
+ if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1
+ Store("GetInternalGraphics ", Debug)
+
+ Store(GIVD, Local0) // Local0[0] - VGA mode(1=VGA)
+ Xor(Local0, 1, Local0) // Invert the VGA mode polarity
+ Or(Local0, ShiftLeft(3, 11), Local0) // Local0[12:11] - DVMT version (11b = 5.0)
+
+ //
+ // Report DVMT 5.0 Total Graphics memory size.
+ //
+ Or(Local0, ShiftLeft(IDMS, 17), Local0) // Bits 20:17 are for Gfx total memory size
+ Return(Local0)
+ }
+ }
+
+ //
+ // Function Index: 16
+ // GetAKSV
+ // Retrun: 5 bytes of AKSV
+ //
+ Case(16) {
+ if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1
+
+ Store("GetAKSV ", Debug)
+ Name (KSVP, Package()
+ {
+ 0x80000000,
+ 0x8000
+ })
+ Store(KSV0, Index(KSVP,0)) // First four bytes of AKSV
+ Store(KSV1, Index(KSVP,1)) // Fifth byte of AKSV
+ Return(KSVP) // Success
+ }
+ }
+ } // End of switch(Arg2)
+
+ } // End of if (ToUUID("3E5B41C6-EB1D-4260-9D15-C71FBADAE414D"))
+
+
+ Return (Buffer () {0x00})
+} // End of _DSM
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpGbda.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpGbda.asl new file mode 100644 index 0000000000..cd86e25fca --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpGbda.asl @@ -0,0 +1,119 @@ +/** @file
+ IGD OpRegion/Software SCI Reference Code.
+ This file contains Get BIOS Data Area funciton support for
+ the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+Method (GBDA, 0, Serialized)
+{
+ //
+ // Supported calls: Sub-function 0
+ //
+ If (LEqual(GESF, 0))
+ {
+ //
+ //<NOTE> Reference code is set to Intel's validated implementation.
+ //
+ Store(0x0000659, PARM)
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Success
+ }
+ //
+ // Requested callbacks: Sub-function 1
+ //
+ If (LEqual(GESF, 1))
+ {
+ //
+ //<NOTE> Call back functions are where the driver calls the
+ // system BIOS at function indicated event.
+ //
+ Store(0x300482, PARM)
+ If(LEqual(S0ID, One)){
+ Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems
+ }
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Success
+ }
+ //
+ // Get Boot display Preferences: Sub-function 4
+ //
+ If (LEqual(GESF, 4))
+ {
+ //
+ //<NOTE> Get Boot Display Preferences function.
+ //
+ And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports
+ And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)
+ Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Success
+ }
+ //
+ // Panel details: Sub-function 5
+ //
+ If (LEqual(GESF, 5))
+ {
+ //
+ //<NOTE> Get Panel Details function.
+ //
+ Store(IPSC, PARM) // Report the scaling setting
+ Or(PARM, ShiftLeft(IPAT, 8), PARM)
+ Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default
+ Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state
+ Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown
+ Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting
+ Store(Zero, GESF)
+ Return(SUCC)
+ }
+ //
+ // Internal graphics: Sub-function 7
+ //
+ If (LEqual(GESF, 7))
+ {
+ Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA)
+ Xor(PARM, 1, PARM) // Invert the VGA mode polarity
+ Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0)
+
+ //
+ // Report DVMT 5.0 Total Graphics memory size.
+ //
+ Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total memory size
+ Store(1, GESF) // Set the modified settings flag
+ Return(SUCC)
+ }
+ //
+ // Spread spectrum clocks: Sub-function 10
+ //
+ If (LEqual(GESF, 10))
+ {
+ Store(0, PARM) // Assume SSC is disabled
+ If(ISSC)
+ {
+ Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled
+ }
+ Store(0, GESF) // Set the modified settings flag
+ Return(SUCC) // Success
+ }
+
+ If (LEqual(GESF, 11))
+ {
+ Store(KSV0, PARM) // First four bytes of AKSV
+ Store(KSV1, GESF) // Fifth byte of AKSV
+
+ Return(SUCC) // Success
+ }
+ //
+ // A call to a reserved "Get BIOS data" function was received.
+ //
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(CRIT) // Reserved, "Critical failure"
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpRn.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpRn.asl new file mode 100644 index 0000000000..4e3b6c5522 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpRn.asl @@ -0,0 +1,297 @@ +/** @file
+ IGD OpRegion/Software SCI Reference Code.
+ This file contains the interrupt handler code for the Integrated
+ Graphics Device (IGD) OpRegion/Software SCI mechanism.
+ It defines OperationRegions to cover the IGD PCI configuration space
+ as described in the IGD OpRegion specification.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+//
+//NOTES:
+//
+// (1) The code contained in this file inherits the scope in which it
+// was included. So BIOS developers must be sure to include this
+// file in the scope associated with the graphics device
+// (ex. \_SB.PCI0.GFX0).
+// (2) Create a _L06 method under the GPE scope to handle the event
+// generated by the graphics driver. The _L06 method must call
+// the GSCI method in this file.
+// (3) The MCHP operation region assumes that _ADR and _BBN names
+// corresponding to bus 0, device0, function 0 have been declared
+// under the PCI0 scope.
+// (4) Before the first execution of the GSCI method, the base address
+// of the GMCH SCI OpRegion must be programmed where the driver can
+// access it. A 32bit scratch register at 0xFC in the IGD PCI
+// configuration space (B0/D2/F0/R0FCh) is used for this purpose.
+
+// Define an OperationRegion to cover the GMCH PCI configuration space as
+// described in the IGD OpRegion specificiation.
+//
+
+//
+// Define an OperationRegion to cover the IGD PCI configuration space as
+// described in the IGD OpRegion specificiation.
+//
+OperationRegion(IGDP, PCI_Config, 0x40, 0xC0)
+Field(IGDP, AnyAcc, NoLock, Preserve)
+{
+ Offset(0x10), // Mirror of gfx control reg
+ , 1,
+ GIVD, 1, // IGD VGA disable bit
+ , 2,
+ GUMA, 3, // Stolen memory size
+ , 9,
+ Offset(0xA4),
+ ASLE, 8, // Reg 0xE4, ASLE interrupt register
+ , 24, // Only use first byte of ASLE reg
+ Offset(0xA8), // Reg 0xE8, SWSCI control register
+ GSSE, 1, // Graphics SCI event (1=event pending)
+ GSSB, 14, // Graphics SCI scratchpad bits
+ GSES, 1, // Graphics event select (1=SCI)
+ Offset(0xBC),
+ ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion
+
+}
+
+//
+// Define an OperationRegion to cover the IGD OpRegion layout.
+//
+OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)
+Field(IGDM, AnyAcc, NoLock, Preserve)
+{
+ //
+ // OpRegion Header
+ //
+ SIGN, 128, // Signature-"IntelGraphicsMem"
+ SIZE, 32, // OpRegion Size
+ OVER, 32, // OpRegion Version
+ SVER, 256, // System BIOS Version
+ VVER, 128, // VBIOS Version
+ GVER, 128, // Driver version
+ MBOX, 32, // Mailboxes supported
+ DMOD, 32, // Driver Model
+ PCON, 32, // Platform Configuration
+ DVER, 64, // GOP Version
+ //
+ // OpRegion Mailbox 1 (Public ACPI Methods)
+ // Note: Mailbox 1 is normally reserved for desktop platforms.
+ //
+ Offset(0x100),
+ DRDY, 32, // Driver readiness (ACPI notification)
+ CSTS, 32, // Notification status
+ CEVT, 32, // Current event
+ Offset(0x120),
+ DIDL, 32, // Supported display device ID list
+ DDL2, 32, // Allows for 8 devices
+ DDL3, 32,
+ DDL4, 32,
+ DDL5, 32,
+ DDL6, 32,
+ DDL7, 32,
+ DDL8, 32,
+ CPDL, 32, // Currently present display list
+ CPL2, 32, // Allows for 8 devices
+ CPL3, 32,
+ CPL4, 32,
+ CPL5, 32,
+ CPL6, 32,
+ CPL7, 32,
+ CPL8, 32,
+ CADL, 32, // Currently active display list
+ CAL2, 32, // Allows for 8 devices
+ CAL3, 32,
+ CAL4, 32,
+ CAL5, 32,
+ CAL6, 32,
+ CAL7, 32,
+ CAL8, 32,
+ NADL, 32, // Next active display list
+ NDL2, 32, // Allows for 8 devices
+ NDL3, 32,
+ NDL4, 32,
+ NDL5, 32,
+ NDL6, 32,
+ NDL7, 32,
+ NDL8, 32,
+ ASLP, 32, // ASL sleep timeout
+ TIDX, 32, // Toggle table index
+ CHPD, 32, // Current hot plug enable indicator
+ CLID, 32, // Current lid state indicator
+ CDCK, 32, // Current docking state indicator
+ SXSW, 32, // Display switch notify on resume
+ EVTS, 32, // Events supported by ASL (diag only)
+ CNOT, 32, // Current OS notifications (diag only)
+ NRDY, 32,
+ //
+ //Extended DIDL list
+ //
+ DDL9, 32,
+ DD10, 32,
+ DD11, 32,
+ DD12, 32,
+ DD13, 32,
+ DD14, 32,
+ DD15, 32,
+ //
+ //Extended Currently attached Display Device List CPD2
+ //
+ CPL9, 32,
+ CP10, 32,
+ CP11, 32,
+ CP12, 32,
+ CP13, 32,
+ CP14, 32,
+ CP15, 32,
+ //
+ // OpRegion Mailbox 2 (Software SCI Interface)
+ //
+ Offset(0x200), // SCIC
+ SCIE, 1, // SCI entry bit (1=call unserviced)
+ GEFC, 4, // Entry function code
+ GXFC, 3, // Exit result
+ GESF, 8, // Entry/exit sub-function/parameter
+ , 16, // SCIC[31:16] reserved
+ Offset(0x204), // PARM
+ PARM, 32, // PARM register (extra parameters)
+ DSLP, 32, // Driver sleep time out
+ //
+ // OpRegion Mailbox 3 (BIOS to Driver Notification)
+ // Note: Mailbox 3 is normally reserved for desktop platforms.
+ //
+ Offset(0x300),
+ ARDY, 32, // Driver readiness (power conservation)
+ ASLC, 32, // ASLE interrupt command/status
+ TCHE, 32, // Technology enabled indicator
+ ALSI, 32, // Current ALS illuminance reading
+ BCLP, 32, // Backlight brightness
+ PFIT, 32, // Panel fitting state or request
+ CBLV, 32, // Current brightness level
+ BCLM, 320, // Backlight brightness level duty cycle mapping table
+ CPFM, 32, // Current panel fitting mode
+ EPFM, 32, // Enabled panel fitting modes
+ PLUT, 592, // Optional. 74-byte Panel LUT Table
+ PFMB, 32, // Optional. PWM Frequency and Minimum Brightness
+ CCDV, 32, // Optional. Gamma, Brightness, Contrast values.
+ PCFT, 32, // Optional. Power Conservation Features
+ SROT, 32, // Supported rotation angle.
+ IUER, 32, // Optional. Intel Ultrabook Event Register.
+ FDSP, 64, // Optional. FFS Display Physical address
+ FDSS, 32, // Optional. FFS Display Size
+ STAT, 32, // State Indicator
+ //
+ // OpRegion Mailbox 4 (VBT)
+ //
+ Offset(0x400),
+ GVD1, 0xC000, // 6K bytes maximum VBT image
+ //
+ // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)
+ //
+ Offset(0x1C00),
+ PHED, 32, // Panel Header
+ BDDC, 2048, // Panel EDID (Max 256 bytes)
+
+}
+
+//
+// Convert boot display type into a port mask.
+//
+Name (DBTB, Package()
+{
+ 0x0000, // Automatic
+ 0x0007, // Port-0 : Integrated CRT
+ 0x0038, // Port-1 : DVO-A, or Integrated LVDS
+ 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C
+ 0x0E00, // Port-3 : SDVO-C
+ 0x003F, // [CRT + DVO-A / Integrated LVDS]
+ 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C]
+ 0x0E07, // [CRT + SDVO-C]
+ 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B]
+ 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C]
+ 0x0FC0, // [SDVO-B + SDVO-C]
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x0000, // Reserved
+ 0x7000, // Port-4: Integrated TV
+ 0x7007, // [Integrated TV + CRT]
+ 0x7038, // [Integrated TV + LVDS]
+ 0x71C0, // [Integrated TV + DVOB]
+ 0x7E00 // [Integrated TV + DVOC]
+})
+
+//
+// Core display clock value table.
+//
+Name (CDCT, Package()
+{
+ Package() {228, 320},
+ Package() {222, 333},
+ Package() {222, 333},
+ Package() { 0, 0},
+ Package() {222, 333},
+})
+
+//
+// Defined exit result values:
+//
+Name (SUCC, 1) // Exit result: Success
+Name (NVLD, 2) // Exit result: Invalid parameter
+Name (CRIT, 4) // Exit result: Critical failure
+Name (NCRT, 6) // Exit result: Non-critical failure
+
+/************************************************************************;
+;*
+;* Name: GSCI
+;*
+;* Description: Handles an SCI generated by the graphics driver. The
+;* PARM and SCIC input fields are parsed to determine the
+;* functionality requested by the driver. GBDA or SBCB
+;* is called based on the input data in SCIC.
+;*
+;* Usage: The method must be called in response to a GPE 06 event
+;* which will be generated by the graphics driver.
+;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}
+;*
+;* Input: PARM and SCIC are indirect inputs
+;*
+;* Output: PARM and SIC are indirect outputs
+;*
+;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback
+;* method)
+;*
+;************************************************************************/
+
+Method (GSCI, 0, Serialized)
+{
+ Include("IgfxOpGbda.asl") // "Get BIOS Data" Functions
+ Include("IgfxOpSbcb.asl") // "System BIOS CallBacks"
+
+ If (LEqual(GEFC, 4))
+ {
+ Store(GBDA(), GXFC) // Process Get BIOS Data functions
+ }
+
+ If (LEqual(GEFC, 6))
+ {
+ Store(SBCB(), GXFC) // Process BIOS Callback functions
+ }
+
+ Store(0, GEFC) // Wipe out the entry function code
+ Store(1, CPSC) // Clear CPUSCI_STS to clear the PCH TCO SCI status
+ Store(0, GSSE) // Clear the SCI generation bit in PCI space.
+ Store(0, SCIE) // Clr SCI serviced bit to signal completion
+
+ Return(Zero)
+}
+
+Include("IgfxCommon.asl") // IGD SCI mobile features
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpSbcb.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpSbcb.asl new file mode 100644 index 0000000000..1f688e3b4a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpSbcb.asl @@ -0,0 +1,268 @@ +/** @file
+ This file contains the system BIOS call back functionality for the
+ OpRegion/Software SCI mechanism.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Method (SBCB, 0, Serialized)
+{
+ //
+ // Supported Callbacks: Sub-function 0
+ //
+ If (LEqual(GESF, 0x0))
+ {
+ //
+ //<NOTE> An OEM may support the driver->SBIOS status callbacks, but
+ // the supported callbacks value must be modified. The code that is
+ // executed upon reception of the callbacks must be also be updated
+ // to perform the desired functionality.
+ //
+ Store(0x00000000, PARM) // No callbacks supported
+ //Store(0x000787FD, PARM) // Used for Intel test implementaion
+ Store(0x000F87DD, PARM)
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // "Success"
+ }
+ //
+ // BIOS POST Completion: Sub-function 1
+ //
+ If (LEqual(GESF, 1))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Pre-Hires Set Mode: Sub-function 3
+ //
+ If (LEqual(GESF, 3))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Post-Hires Set Mode: Sub-function 4
+ //
+ If (LEqual(GESF, 4))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Display Switch: Sub-function 5
+ //
+ If (LEqual(GESF, 5))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Adapter Power State: Sub-function 7
+ //
+ If (LEqual(GESF, 7))
+ {
+ //
+ // Handle Low Power S0 Idle Capability if enabled
+ //
+ If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {
+ //
+ // Call GUAM to trigger CS Entry
+ // If Adapter Power State Notification = D1 (PARM[7:0]=0x01)
+ //
+ If (LEqual (And(PARM,0xFF), 0x01)) {
+ // GUAM - Global User Absent Mode Notification Method
+ \GUAM(One) // 0x01 - Power State Standby (CS Entry)
+ }
+ If (LEqual (And(PARM,0xFF), 0x00)) {
+ // GUAM - Global User Absent Mode Notification Method
+ \GUAM(0)
+ }
+ }
+ //
+ // Upon notification from driver that the Adapter Power State = D0,
+ // check if previous lid event failed. If it did, retry the lid
+ // event here.
+ //
+ If(LEqual(PARM, 0))
+ {
+ Store(CLID, Local0)
+ If(And(0x80000000,Local0))
+ {
+ And(CLID, 0x0000000F, CLID)
+ GLID(CLID)
+ }
+ }
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Display Power State: Sub-function 8
+ //
+ If (LEqual(GESF, 8))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Set Boot Display: Sub-function 9
+ //
+ If (LEqual(GESF, 9))
+ {
+ //
+ //<NOTE> An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+ //
+ And(PARM, 0xFF, IBTT) // Save the boot display to NVS
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Reserved, "Critical failure"
+ }
+ //
+ // Set Panel Details: Sub-function 10 (0Ah)
+ //
+ If (LEqual(GESF, 10))
+ {
+ //
+ //<NOTE> An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+ // Set the panel-related NVRAM variables based the input from the driver.
+ //
+ And(PARM, 0xFF, IPSC)
+ //
+ // Change panel type if a change is requested by the driver (Change if
+ // panel type input is non-zero). Zero=No change requested.
+ //
+ If(And(ShiftRight(PARM, 8), 0xFF))
+ {
+ And(ShiftRight(PARM, 8), 0xFF, IPAT)
+ Decrement(IPAT) // 0 = no change, so fit to CMOS map
+ }
+ And(ShiftRight(PARM, 20), 0x7, IBIA)
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Success
+ }
+ //
+ // Set Internal Graphics: Sub-function 11 (0Bh)
+ //
+ If (LEqual(GESF, 11))
+ {
+ //
+ //<NOTE> An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+ //
+ And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option
+ If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed size != 0
+ {
+ //
+ // Fixed memory
+ //
+ And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size
+ }
+ Else
+ {
+ //
+ // DVMT memory
+ //
+ And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size
+ }
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Success
+ }
+ //
+ // Post-Hires to DOS FS: Sub-function 16 (10h)
+ //
+ If (LEqual(GESF, 16))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // APM Complete: Sub-function 17 (11h)
+ //
+ If (LEqual(GESF, 17))
+ {
+ Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state
+ Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Set Spread Spectrum Clocks: Sub-function 18 (12h)
+ //
+ If (LEqual(GESF, 18))
+ {
+ //
+ //<NOTE> An OEM may elect to implement this method. In that case,
+ // the input values must be saved into non-volatile storage for
+ // parsing during the next boot. The following Sample code is Intel
+ // validated implementation.
+ //
+ If(And(PARM, 1))
+ {
+ If(LEqual(ShiftRight(PARM, 1), 1))
+ {
+ Store(1, ISSC) // Enable HW SSC, only for clock 1
+ }
+ Else
+ {
+ Store(Zero, GESF)
+ Return(CRIT) // Failure, as the SSC clock must be 1
+ }
+ }
+ Else
+ {
+ Store(0, ISSC) // Disable SSC
+ }
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Success
+ }
+ //
+ // Post VBE/PM Callback: Sub-function 19 (13h)
+ //
+ If (LEqual(GESF, 19))
+ {
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Not supported, but no failure
+ }
+ //
+ // Set PAVP Data: Sub-function 20 (14h)
+ //
+ If (LEqual(GESF, 20))
+ {
+ And(PARM, 0xF, PAVP) // Store PAVP info
+ Store(Zero, GESF) // Clear the exit parameter
+ Store(Zero, PARM)
+ Return(SUCC) // Success
+ }
+
+ //
+ // A call to a reserved "System BIOS callbacks" function was received
+ //
+ Store(Zero, GESF) // Clear the exit parameter
+ Return(SUCC) // Reserved, "Critical failure"
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl new file mode 100644 index 0000000000..7bc2d80667 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl @@ -0,0 +1,32 @@ +/** @file
+ This file contains the device definition of the System Agent
+ ACPI reference code.
+ Currently defines the device objects for the
+ System Agent PCI Express* ports (PEG), iGfx and other devices.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+External(\_SB.PCI0, DeviceObj)
+External(\_SB.PCI0.GFX0, DeviceObj)
+External(\_SB.PCI0.PCIC, MethodObj)
+External(\_SB.PCI0.PCID, MethodObj)
+
+
+///
+/// I.G.D
+///
+Scope (\_SB.PCI0.GFX0)
+{
+ include("Igfx.asl")
+} // end I.G.D
+
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl new file mode 100644 index 0000000000..311810020f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl @@ -0,0 +1,135 @@ +/**@file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //
+ // Define SA NVS Area operatino region.
+ //
+
+
+
+ OperationRegion(SANV,SystemMemory, 0xFFFF0000,0xAA55)
+ Field(SANV,AnyAcc,Lock,Preserve)
+ {
+ Offset(0), ASLB, 32, // Offset(0), IGD OpRegion base address
+ Offset(4), IMON, 8, // Offset(4), IMON Current Value
+ Offset(5), IGDS, 8, // Offset(5), IGD State (Primary Display = 1)
+ Offset(6), IBTT, 8, // Offset(6), IGD Boot Display Device
+ Offset(7), IPAT, 8, // Offset(7), IGD Panel Type CMOS option
+ Offset(8), IPSC, 8, // Offset(8), IGD Panel Scaling
+ Offset(9), IBIA, 8, // Offset(9), IGD BIA Configuration
+ Offset(10), ISSC, 8, // Offset(10), IGD SSC Configuration
+ Offset(11), IDMS, 8, // Offset(11), IGD DVMT Memory Size
+ Offset(12), IF1E, 8, // Offset(12), IGD Function 1 Enable
+ Offset(13), HVCO, 8, // Offset(13), HPLL VCO
+ Offset(14), GSMI, 8, // Offset(14), GMCH SMI/SCI mode (0=SCI)
+ Offset(15), PAVP, 8, // Offset(15), IGD PAVP data
+ Offset(16), CADL, 8, // Offset(16), Current Attached Device List
+ Offset(17), CSTE, 16, // Offset(17), Current Display State
+ Offset(19), NSTE, 16, // Offset(19), Next Display State
+ Offset(21), NDID, 8, // Offset(21), Number of Valid Device IDs
+ Offset(22), DID1, 32, // Offset(22), Device ID 1
+ Offset(26), DID2, 32, // Offset(26), Device ID 2
+ Offset(30), DID3, 32, // Offset(30), Device ID 3
+ Offset(34), DID4, 32, // Offset(34), Device ID 4
+ Offset(38), DID5, 32, // Offset(38), Device ID 5
+ Offset(42), DID6, 32, // Offset(42), Device ID 6
+ Offset(46), DID7, 32, // Offset(46), Device ID 7
+ Offset(50), DID8, 32, // Offset(50), Device ID 8
+ Offset(54), DID9, 32, // Offset(54), Device ID 9
+ Offset(58), DIDA, 32, // Offset(58), Device ID 10
+ Offset(62), DIDB, 32, // Offset(62), Device ID 11
+ Offset(66), DIDC, 32, // Offset(66), Device ID 12
+ Offset(70), DIDD, 32, // Offset(70), Device ID 13
+ Offset(74), DIDE, 32, // Offset(74), Device ID 14
+ Offset(78), DIDF, 32, // Offset(78), Device ID 15
+ Offset(82), DIDX, 32, // Offset(82), Device ID for eDP device
+ Offset(86), NXD1, 32, // Offset(86), Next state DID1 for _DGS
+ Offset(90), NXD2, 32, // Offset(90), Next state DID2 for _DGS
+ Offset(94), NXD3, 32, // Offset(94), Next state DID3 for _DGS
+ Offset(98), NXD4, 32, // Offset(98), Next state DID4 for _DGS
+ Offset(102), NXD5, 32, // Offset(102), Next state DID5 for _DGS
+ Offset(106), NXD6, 32, // Offset(106), Next state DID6 for _DGS
+ Offset(110), NXD7, 32, // Offset(110), Next state DID7 for _DGS
+ Offset(114), NXD8, 32, // Offset(114), Next state DID8 for _DGS
+ Offset(118), NXDX, 32, // Offset(118), Next state DID for eDP
+ Offset(122), LIDS, 8, // Offset(122), Lid State (Lid Open = 1)
+ Offset(123), KSV0, 32, // Offset(123), First four bytes of AKSV (manufacturing mode)
+ Offset(127), KSV1, 8, // Offset(127), Fifth byte of AKSV (manufacturing mode)
+ Offset(128), BRTL, 8, // Offset(128), Brightness Level Percentage
+ Offset(129), ALSE, 8, // Offset(129), Ambient Light Sensor Enable
+ Offset(130), ALAF, 8, // Offset(130), Ambient Light Adjusment Factor
+ Offset(131), LLOW, 8, // Offset(131), LUX Low Value
+ Offset(132), LHIH, 8, // Offset(132), LUX High Value
+ Offset(133), ALFP, 8, // Offset(133), Active LFP
+ Offset(134), IMTP, 8, // Offset(134), IMGU ACPI device type
+ Offset(135), EDPV, 8, // Offset(135), Check for eDP display device
+ Offset(136), SGMD, 8, // Offset(136), SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only)
+ Offset(137), SGFL, 8, // Offset(137), SG Feature List
+ Offset(138), SGGP, 8, // Offset(138), PCIe0 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
+ Offset(139), HRE0, 8, // Offset(139), PCIe0 HLD RST IO Expander Number
+ Offset(140), HRG0, 32, // Offset(140), PCIe0 HLD RST GPIO Number
+ Offset(144), HRA0, 8, // Offset(144), PCIe0 HLD RST GPIO Active Information
+ Offset(145), PWE0, 8, // Offset(145), PCIe0 PWR Enable IO Expander Number
+ Offset(146), PWG0, 32, // Offset(146), PCIe0 PWR Enable GPIO Number
+ Offset(150), PWA0, 8, // Offset(150), PCIe0 PWR Enable GPIO Active Information
+ Offset(151), P1GP, 8, // Offset(151), PCIe1 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
+ Offset(152), HRE1, 8, // Offset(152), PCIe1 HLD RST IO Expander Number
+ Offset(153), HRG1, 32, // Offset(153), PCIe1 HLD RST GPIO Number
+ Offset(157), HRA1, 8, // Offset(157), PCIe1 HLD RST GPIO Active Information
+ Offset(158), PWE1, 8, // Offset(158), PCIe1 PWR Enable IO Expander Number
+ Offset(159), PWG1, 32, // Offset(159), PCIe1 PWR Enable GPIO Number
+ Offset(163), PWA1, 8, // Offset(163), PCIe1 PWR Enable GPIO Active Information
+ Offset(164), P2GP, 8, // Offset(164), PCIe2 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
+ Offset(165), HRE2, 8, // Offset(165), PCIe2 HLD RST IO Expander Number
+ Offset(166), HRG2, 32, // Offset(166), PCIe2 HLD RST GPIO Number
+ Offset(170), HRA2, 8, // Offset(170), PCIe2 HLD RST GPIO Active Information
+ Offset(171), PWE2, 8, // Offset(171), PCIe2 PWR Enable IO Expander Number
+ Offset(172), PWG2, 32, // Offset(172), PCIe2 PWR Enable GPIO Number
+ Offset(176), PWA2, 8, // Offset(176), PCIe2 PWR Enable GPIO Active Information
+ Offset(177), DLPW, 16, // Offset(177), Delay after power enable for PCIe
+ Offset(179), DLHR, 16, // Offset(179), Delay after Hold Reset for PCIe
+ Offset(181), EECP, 8, // Offset(181), PCIe0 Endpoint Capability Structure Offset
+ Offset(182), XBAS, 32, // Offset(182), Any Device's PCIe Config Space Base Address
+ Offset(186), GBAS, 16, // Offset(186), GPIO Base Address
+ Offset(188), NVGA, 32, // Offset(188), NVIG opregion address
+ Offset(192), NVHA, 32, // Offset(192), NVHM opregion address
+ Offset(196), AMDA, 32, // Offset(196), AMDA opregion address
+ Offset(200), LTRX, 8, // Offset(200), Latency Tolerance Reporting Enable
+ Offset(201), OBFX, 8, // Offset(201), Optimized Buffer Flush and Fill
+ Offset(202), LTRY, 8, // Offset(202), Latency Tolerance Reporting Enable
+ Offset(203), OBFY, 8, // Offset(203), Optimized Buffer Flush and Fill
+ Offset(204), LTRZ, 8, // Offset(204), Latency Tolerance Reporting Enable
+ Offset(205), OBFZ, 8, // Offset(205), Optimized Buffer Flush and Fill
+ Offset(206), SMSL, 16, // Offset(206), SA Peg Latency Tolerance Reporting Max Snoop Latency
+ Offset(208), SNSL, 16, // Offset(208), SA Peg Latency Tolerance Reporting Max No Snoop Latency
+ Offset(210), P0UB, 8, // Offset(210), Peg0 Unused Bundle Control
+ Offset(211), P1UB, 8, // Offset(211), Peg1 Unused Bundle Control
+ Offset(212), P2UB, 8, // Offset(212), Peg2 Unused Bundle Control
+ Offset(213), PCSL, 8, // Offset(213), The lowest C-state for the package
+ Offset(214), PBGE, 8, // Offset(214), Pegx Unused Bundle Control Global Enable (0=Disabled, 1=Enabled)
+ Offset(215), M64B, 64, // Offset(215), Base of above 4GB MMIO resource
+ Offset(223), M64L, 64, // Offset(223), Length of above 4GB MMIO resource
+ Offset(231), CPEX, 32, // Offset(231), CPU ID info to get Family Id or Stepping
+ Offset(235), EEC1, 8, // Offset(235), PCIe1 Endpoint Capability Structure Offset
+ Offset(236), EEC2, 8, // Offset(236), PCIe2 Endpoint Capability Structure Offset
+ Offset(237), SBN0, 8, // Offset(237), PCIe0 Secondary Bus Number (PCIe0 Endpoint Bus Number)
+ Offset(238), SBN1, 8, // Offset(238), PCIe1 Secondary Bus Number (PCIe0 Endpoint Bus Number)
+ Offset(239), SBN2, 8, // Offset(239), PCIe2 Secondary Bus Number (PCIe0 Endpoint Bus Number)
+ Offset(240), M32B, 32, // Offset(240), Base of below 4GB MMIO resource
+ Offset(244), M32L, 32, // Offset(244), Length of below 4GB MMIO resource
+ Offset(248), P0WK, 32, // Offset(248), PCIe0 RTD3 Device Wake GPIO Number
+ Offset(252), P1WK, 32, // Offset(252), PCIe1 RTD3 Device Wake GPIO Number
+ Offset(256), P2WK, 32, // Offset(256), PCIe2 RTD3 Device Wake GPIO Number
+ Offset (500), // Offset(260) : Offset(499), Reserved bytes
+ Offset (503), // Offset(500) : Offset(502), Reserved bytes
+ }
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl new file mode 100644 index 0000000000..b19a3cfa7b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl @@ -0,0 +1,28 @@ +/** @file
+ This file contains the SystemAgent SSDT Table ASL code.
+ It defines a Global NVS table which exchanges datas between OS
+ and BIOS.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+ "SaSsdt.aml",
+ "SSDT",
+ 0x02,
+ "SaSsdt",
+ "SaSsdt ",
+ 0x3000
+ )
+{
+ include ("SaNvs.asl")
+ include ("Sa.asl")
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf new file mode 100644 index 0000000000..43d7819263 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf @@ -0,0 +1,60 @@ +## @file
+# Component description file for the ACPI tables
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+
+[Defines]
+INF_VERSION = 0x00010005
+BASE_NAME = SaSsdt
+FILE_GUID = ca89914d-2317-452e-b245-36c6fb77a9c6
+MODULE_TYPE = USER_DEFINED
+VERSION_STRING = 1.0
+
+[Sources]
+ SaSsdt.asl
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ KabylakeSiliconPkg/SiPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+
+[Protocols]
+
+[PPIs]
+
+[Guids]
+
+[Depex]
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsDxeConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsDxeConfig.h new file mode 100644 index 0000000000..8f746dcc95 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsDxeConfig.h @@ -0,0 +1,57 @@ +/** @file
+ Graphics DXE Policy definitions
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GRAPHICS_DXE_CONFIG_H_
+#define _GRAPHICS_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#define GRAPHICS_DXE_CONFIG_REVISION 2
+
+/**
+ This configuration block is to configure IGD related variables used in DXE.
+ If Intel Gfx Device is not supported or disabled, all policies will be ignored.
+ The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecated IgdBiaConfig and IgdSscConfig.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
+ UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
+ EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
+ UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
+ UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
+ UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
+ UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
+ CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
+ /**
+ Offset 80: IGD Panel Type CMOS option\n
+ <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
+ 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
+ 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
+ **/
+ UINT8 IgdPanelType;
+ UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
+ UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdBiaConfig; ///< Offset 83: IGD BIA Configuration: <b>0=AUTO</b>, 1=Disabled, 2=Level1, 3=Level2, 4=Level3, 5=Level4, 6=Level5 //@deprecated since Revision2
+ UINT8 IgdSscConfig; ///< Offset 84: IGD SSC Configuration: <b>1=Off</b>, 2=Harware, 3=Software //@deprecated since Revision2
+ UINT8 LowPowerMode; ///< Offset 85: IGD Power Conservation Feature Flag: 0=Disable, <b>2=Enable</b>
+ UINT8 IgdDvmtMemSize; ///< Offset 86: IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
+ UINT8 GfxTurboIMON; ///< Offset 87: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
+} GRAPHICS_DXE_CONFIG;
+#pragma pack(pop)
+
+#endif // _GRAPHICS_DXE_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h new file mode 100644 index 0000000000..ee294650bf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/GraphicsPeiConfig.h @@ -0,0 +1,36 @@ +/** @file
+ Policy definition for Internal Graphics Config Block (PostMem)
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GRAPHICS_PEI_CONFIG_H_
+#define _GRAPHICS_PEI_CONFIG_H_
+#pragma pack(push, 1)
+
+#define GRAPHICS_PEI_CONFIG_REVISION 1
+
+/**
+ This configuration block is to configure IGD related variables used in PostMem PEI.
+ If Intel Gfx Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 :This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
+ UINT32 RsvdBits0 : 31; ///< Offser 28:16 :Reserved for future use
+ VOID* LogoPtr; ///< Offset 32 Address of Logo to be displayed in PEI
+ UINT32 LogoSize; ///< Offset 36 Logo Size
+ VOID* GraphicsConfigPtr; ///< Offset 40 Address of the Graphics Configuration Table
+} GRAPHICS_PEI_CONFIG;
+#pragma pack(pop)
+
+#endif // _GRAPHICS_PEI_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryConfig.h new file mode 100644 index 0000000000..8f77fa720b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryConfig.h @@ -0,0 +1,533 @@ +/** @file
+ Policy definition of Memory Config Block
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MEMORY_CONFIG_H_
+#define _MEMORY_CONFIG_H_
+
+#include <SaRegs.h>
+
+#pragma pack(push, 1)
+
+#define SA_MRC_ITERATION_MAX (6)
+#define SA_MRC_MAX_RCOMP (3)
+#define SA_MRC_MAX_RCOMP_TARGETS (5)
+
+#define MEMORY_CONFIG_REVISION 3
+
+///
+/// SMRAM Memory Range
+///
+#define PEI_MR_SMRAM_ABSEG_MASK 0x01
+#define PEI_MR_SMRAM_HSEG_MASK 0x02
+
+///
+/// SA SPD profile selections.
+///
+typedef enum {
+ Default, ///< 0, Default SPD
+ UserDefined, ///< 1, User Defined profile
+ XMPProfile1, ///< 2, XMP Profile 1
+ XMPProfile2 ///< 3, XMP Profile 2
+} SA_SPD;
+
+///
+/// Define the boot modes used by the SPD read function.
+///
+typedef enum {
+ SpdCold, ///< Cold boot
+ SpdWarm, ///< Warm boot
+ SpdS3, ///< S3 resume
+ SpdFast, ///< Fast boot
+ SpdBootModeMax ///< Delimiter
+} SPD_BOOT_MODE;
+
+typedef struct {
+ UINT8 SpdData[SA_MC_MAX_CHANNELS][SA_MC_MAX_SLOTS][SA_MC_MAX_SPD_SIZE];
+//Next Field Offset 2048
+} SPD_DATA_BUFFER;
+
+typedef struct {
+ UINT8 DqByteMap[SA_MC_MAX_CHANNELS][SA_MRC_ITERATION_MAX][2];
+//Next Field Offset 24
+} SA_MEMORY_DQ_MAPPING;
+
+typedef struct {
+ UINT8 DqsMapCpu2Dram[SA_MC_MAX_CHANNELS][SA_MC_MAX_BYTES_NO_ECC];
+//Next Field Offset 16
+} SA_MEMORY_DQS_MAPPING;
+
+typedef struct {
+ UINT16 RcompResistor[SA_MRC_MAX_RCOMP]; ///< Offset 0: Reference RCOMP resistors on motherboard
+ UINT16 RcompTarget[SA_MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
+//Next Field Offset 16
+} SA_MEMORY_RCOMP;
+
+typedef struct {
+ UINT16 Start; ///< Offset 0
+ UINT16 End; ///< Offset 2
+ UINT8 BootMode; ///< Offset 4
+ UINT8 Rsvd[3]; ///< Offset 5 Reserved for future use
+} SPD_OFFSET_TABLE;
+
+///
+/// SA memory address decode.
+///
+typedef struct
+{
+ UINT8 Controller; ///< Offset 0 Zero based Controller number
+ UINT8 Channel; ///< Offset 1 Zero based Channel number
+ UINT8 Dimm; ///< Offset 2 Zero based DIMM number
+ UINT8 Rank; ///< Offset 3 Zero based Rank number
+ UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
+ UINT8 Bank; ///< Offset 5 Zero based Bank number
+ UINT16 Cas; ///< Offset 6 Zero based CAS number
+ UINT32 Ras; ///< Offset 8 Zero based RAS number
+} SA_ADDRESS_DECODE;
+
+typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress);
+typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress);
+typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress);
+typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value);
+typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value);
+typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value);
+typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address);
+typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address);
+typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address);
+typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address);
+typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value);
+typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value);
+typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value);
+typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value);
+typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status);
+typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status);
+typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status);
+typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status);
+typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset);
+typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset);
+typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year);
+typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID *GlobalData);
+typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes);
+typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value);
+typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value);
+typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value);
+typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits);
+typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits);
+typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier);
+typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder);
+typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize);
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
+typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand);
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status);
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status);
+typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd);
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value);
+typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch);
+typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber);
+typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel);
+typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...);
+typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String);
+typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam);
+typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb);
+typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost);
+typedef VOID (EFIAPI * SA_UPDATE_VREF_WAIT_STABLE) (VOID *GlobalData, UINT8 VrefType, UINT8 UpdateMrcData, INT32 Offset, UINT8 RankMask, UINT8 DeviceMask, BOOLEAN PDAmode, UINT8 SkipWait);
+typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location);
+typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location);
+typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data);
+typedef UINT32 (EFIAPI * SA_THERMAL_OVERRIDES) (VOID *GlobalData);
+typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus);
+typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue);
+typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT32 PrmrrBaseAddress, UINT32 PrmrrSize);
+
+
+///
+/// Function calls into the SA.
+///
+typedef struct {
+ SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
+ SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
+ SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
+ SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
+ SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
+ SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
+ SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
+ SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
+ SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
+ SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
+ SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
+ SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
+ SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
+ SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
+ SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
+ SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
+ SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
+ SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
+ SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
+ SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
+ SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
+ SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
+ SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
+ SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
+ SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
+ SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
+ SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
+ SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
+ SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
+ SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
+ SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
+ SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
+ SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
+ SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
+ SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
+ SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
+ SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
+ SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
+ SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
+ SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
+ SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
+ SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
+ SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+} SA_FUNCTION_CALLS;
+
+///
+/// Function calls into the MRC.
+///
+typedef struct {
+ SA_GET_MC_ADDRESS_DECODE GetMcAddressDecode; ///< Offset 0: - Converts system address to DRAM address.
+ SA_GET_MC_ADDRESS_ENCODE GetMcAddressEncode; ///< Offset 4: - Converts DRAM address to system address.
+ SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 8: - Returns whether Channel is or is not present.
+ SA_PRINTF MrcPrintf; ///< Offset 12: - Print to output stream/device.
+ SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 16: - Change the margin.
+ SA_SIGN_EXTEND MrcSignExtend; ///< Offset 20: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+ SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 24: - Move CMD/CTL/CLK/CKE PIs during training.
+ SA_UPDATE_VREF_WAIT_STABLE UpdateVrefWaitStable; ///< Offset 28: - Update the Vref value and wait until it is stable.
+ SA_THERMAL_OVERRIDES MrcThermalOverrides; ///< Offset 32: - Update memory thermal conditions.
+} SA_MEMORY_FUNCTIONS;
+
+/**
+ Memory Configuration
+ The contents of this structure are CRC'd by the MRC for option change detection.
+ This structure is copied en mass to the MrcInput structure.
+ If you add fields here, you must update the MrcInput structure.\n
+ <b>Revision 1</b>:
+ - Initial version.
+
+ <b>Revision 2</b>:
+ - Added CMDSR, CMDDSEQ and CMDNORM.
+ - Added Ddr4DdpSharedClock and Ddr4DdpSharedZq.
+
+ <b>Revision 3</b>:
+ - Added EWRDSEQ.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 HobBufferSize; ///< Offset 28 Size of HOB buffer for MRC
+ //
+ // The following parameters are used only when SpdProfileSelected is UserDefined (CUSTOM PROFILE)
+ //
+ UINT8 SpdProfileSelected; ///< Offset 29 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Customized profile, 2=XMP profile 1, 3=XMP profile 2.
+ UINT16 tCL; ///< Offset 30 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
+ UINT16 tRCDtRP; ///< Offset 32 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tRAS; ///< Offset 34 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
+ UINT16 tWR; ///< Offset 36 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
+ UINT16 tRFC; ///< Offset 38 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
+ UINT16 tRRD; ///< Offset 40 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
+ UINT16 tWTR; ///< Offset 42 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRTP; ///< Offset 44 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
+ UINT16 tFAW; ///< Offset 46 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tCWL; ///< Offset 48 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
+ UINT16 tREFI; ///< Offset 50 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
+ UINT16 VddVoltage; ///< Offset 52 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT8 NModeSupport; ///< Offset 54 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
+
+ UINT8 McLock; ///< Offset 55 Enable/Disable memory configuration register locking: 0=Disable, <b>1=Enable</b>.
+ //
+ // Thermal Management
+ //
+ UINT32 ThermalManagement:1; ///< Offset 56 Memory Thermal Management Support: <b>0=Disable</b>, 1=Enable.
+ UINT32 PeciInjectedTemp:1; ///< - Enable/Disable memory temperatures to be injected to the processor via PECI: <b>0=Disable</b>, 1=Enable.
+ UINT32 ExttsViaTsOnBoard:1; ///< - Enable/Disable routing TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH: <b>0=Disable</b>, 1=Enable.
+ UINT32 ExttsViaTsOnDimm:1; ///< - Enable/Disable routing TS-on-DIMM's ALERT# to EXTTS# pin on the PCH: <b>0=Disable</b>, 1=Enable.
+ UINT32 VirtualTempSensor:1; ///< - Enable/Disable Virtual Temperature Sensor (VTS): <b>0=Disable</b>, 1=Enable.
+ UINT32 RsvdBits0:27;
+ //
+ // Training Algorithms
+ //
+ UINT32 ECT:1; ///< Offset 60 Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 SOT:1; ///< - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDMPRTC2D:1; ///< - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDMPRT:1; ///< - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RCVET:1; ///< - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 JWRL:1; ///< - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 EWRTC2D:1; ///< - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDTC2D:1; ///< - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRTC1D:1; ///< - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC1D:1; ///< - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC1D:1; ///< - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMODTT:1; ///< - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 DIMMRONT:1; ///< - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDSEQT:1; ///< - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRSRT:1; ///< - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
+ UINT32 RDODTT:1; ///< - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDEQT:1; ///< - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDAPT:1; ///< - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRTC2D:1; ///< - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC2D:1; ///< - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC2D:1; ///< - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDVC2D:1; ///< - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDVC:1; ///< - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
+ UINT32 LCT:1; ///< - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RTL:1; ///< - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 TAT:1; ///< - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RMT:1; ///< - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
+ UINT32 MEMTST:1; ///< - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
+ UINT32 ALIASCHK:1; ///< - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
+ UINT32 RCVENC1D:1; ///< - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 RMC:1; ///< - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 WRDSUDT:1; ///< - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+
+ UINT32 MrcSafeConfig:1; ///< Offset 64 MRC Safe Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 EccSupport:1; ///< - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
+ UINT32 RemapEnable:1; ///< - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
+ UINT32 ScramblerSupport:1; ///< - Memory scrambler support: 0=Disable, <b>1=Enable</b>
+ UINT32 OddRatioMode:1; ///< - If Odd Ratio Mode is enabled, QCLK frequency has an addition of 133/100 MHz: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcTimeMeasure:1; ///< - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcFastBoot:1; ///< - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
+ UINT32 DqPinsInterleaved:1; ///< - Interleaving mode of DQ/DQS pins for HSW_ULT which depends on board routing: <b>0=Disable</b>, 1=Enable
+ UINT32 RankInterleave:1; ///< - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 EnhancedInterleave:1; ///< - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 WeaklockEn:1; ///< - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 CmdTriStateDis:1; ///< - CMD Tri-State Support: <b>0=Enable</b>, 1=Disable. Note: This should be set to 1 (Disable) if Command RTT is not present on the platform.
+ UINT32 MemoryTrace:1; ///< - Memory Trace to second DDR channel using Stacked Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 ChHashEnable:1; ///< - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 EnableExtts:1; ///< - Enable Extts: <b>0=Disable</b>, 1=Enable
+ UINT32 EnableCltm:1; ///< - Enable Closed Loop Thermal Management: <b>0=Disable</b>, 1=Enable
+ UINT32 EnableOltm:1; ///< - Enable Open Loop Thermal Management: <b>0=Disable</b>, 1=Enable
+ UINT32 EnablePwrDn:1; ///< - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 EnablePwrDnLpddr:1; ///< - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 LockPTMregs:1; ///< - Lock PCU Thermal Management registers: 0=Disable, <b>1=Enable</b>
+ UINT32 UserPowerWeightsEn:1; ///< - Allows user to explicitly set power weight, scale factor, and channel power floor values: <b>0=Disable</b>, 1=Enable
+ UINT32 RaplLim2Lock:1; ///< - Lock DDR_RAPL_LIMIT register: <b>0=Disable</b>, 1=Enable
+ UINT32 RaplLim2Ena:1; ///< - Enable Power Limit 2: <b>0=Disable</b>, 1=Enable
+ UINT32 RaplLim1Ena:1; ///< - Enable Power Limit 1: <b>0=Disable</b>, 1=Enable
+ UINT32 SrefCfgEna:1; ///< - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeatLpddr:1; ///< - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeat:1; ///< - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
+ UINT32 AutoSelfRefreshSupport:1; ///< - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
+ UINT32 ExtTemperatureSupport:1; ///< - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
+ UINT32 MobilePlatform:1; ///< - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
+ UINT32 Force1Dpc:1; ///< - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
+ UINT32 ForceSingleRank:1; ///< - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
+
+ UINT32 RhPrevention:1; ///< Offset 68 RH Prevention Enable/Disable: 0=Disable, <b>1=Enable</b>
+ UINT32 VttTermination:1; ///< - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
+ UINT32 VttCompForVsshi:1; ///< - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
+ UINT32 ExitOnFailure:1; ///< - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
+ UINT32 Vc1ReadMeter:1; ///< - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 DdrThermalSensor:1; ///< - Ddr Thermal Sensor: 0=Disable, <b>1=Enable</b>
+ UINT32 LpddrMemWriteLatencySet:1; ///< - LPDDR3 Write Latency Set option: 0=Set A, <b>1=Set B</b>
+ UINT32 EvLoader:1; ///< - Option to Enable EV Loader: <b>0=Disable</b>,1=Enable
+ UINT32 EvLoaderDelay:1; ///< - Option to Enable EV Loader Delay: 0=Disable, <b>1=Enable</b>
+ UINT32 Ddr4DdpSharedClock:1; ///< - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 Ddr4DdpSharedZq:1; ///< - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 RsvdBits1:21;
+
+ UINT32 BClkFrequency; ///< Offset 72 - Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
+ UINT16 DdrFreqLimit; ///< Offset 76 Memory Frequency Limit: <b>0=Auto (limited by SPD/CPU capability)</b>, for valid values see MrcFrequency in MrcInterface.h
+ /**
+ Selects the DDR base reference clock\n
+ <b>0x00 = 133MHz</b>
+ 0x01 = 100MHz
+ **/
+ UINT8 RefClk; ///< Offset 78
+ /**
+ Selects the ratio to multiply the reference clock by for the DDR frequency\n
+ When RefClk is 133MHz\n
+ <b>0x00 = Auto</b>, 0x03 through 0x0C are valid values, all others are invalid\n
+ When RefClk is 100MHz\n
+ <b>0x00 = Auto</b>, 0x06 through 0x10 are valid values, all others are invalid\n
+ **/
+ UINT8 Ratio; ///< Offset 79
+ UINT8 ProbelessTrace; ///< Offset 80 Probeless Trace: <b>0=Disabled</b>, 1=GDXC IOT/MOT, 2=HD Port. <b>Note: Enabling ProbelessTrace will also need enabling IED together.</b>
+ UINT8 GdxcIotSize; ///< Offset 81 GDXC IOT Size in 8MB granularity: 0=Minimal, 128=Maximum, <b>4=32MB</b>.
+ UINT8 GdxcMotSize; ///< Offset 82 GDXC MOT Size in 8MB granularity: 0=Minimal, 128=Maximum, <b>12=96MB</b>.
+ /**
+ - Channel Hash Enable.\n
+ NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8\n
+ 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
+ **/
+ UINT8 ChHashInterleaveBit; ///< Offset 83
+ UINT16 ChHashMask; ///< Offset 84 - Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ /**
+ Disables a DIMM slot in the channel even if a DIMM is present\n
+ Array index represents the channel number (0 = channel 0, 1 = channel 1)\n
+ <b>0x0 = DIMM 0 and DIMM 1 enabled</b>\n
+ 0x1 = DIMM 0 disabled, DIMM 1 enabled\n
+ 0x2 = DIMM 0 enabled, DIMM 1 disabled\n
+ 0x3 = DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n
+ **/
+ UINT8 DisableDimmChannel[SA_MC_MAX_CHANNELS];///< Offset 86
+
+ UINT8 RaplLim2WindX; ///< Offset 88 - Power Limit 2 Time Window X value: 0=Minimal, 3=Maximum, <b>1=Default</b>
+ UINT8 RaplLim2WindY; ///< Offset 89 - Power Limit 2 Time Window Y value: 0=Minimal, 3=Maximum, <b>1=Default</b>
+ UINT8 RaplLim1WindX; ///< Offset 90 - Power Limit 1 Time Window X value: <b>0=Minimal</b>, 3=Maximum
+ UINT8 RaplLim1WindY; ///< Offset 91 - Power Limit 1 Time Window Y value: <b>0=Minimal</b>, 31=Maximum
+ UINT16 RaplLim2Pwr; ///< Offset 92 - Power Limit 2: 0=Minimal, 16383=Maximum, <b>222=Default</b>
+ UINT16 RaplLim1Pwr; ///< Offset 94 - Power Limit 1: <b>0=Minimal</b>, 16383=Maximum
+ UINT8 WarmThresholdCh0Dimm0; ///< Offset 96 - Warm Threshold (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmThresholdCh0Dimm1; ///< Offset 97 - Warm Threshold (Channel 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmThresholdCh1Dimm0; ///< Offset 98 - Warm Threshold (Channel 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmThresholdCh1Dimm1; ///< Offset 99 - Warm Threshold (Channel 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotThresholdCh0Dimm0; ///< Offset 100 - Hot Threshold (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotThresholdCh0Dimm1; ///< Offset 101 - Hot Threshold (Channel 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotThresholdCh1Dimm0; ///< Offset 102 - Hot Threshold (Channel 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotThresholdCh1Dimm1; ///< Offset 103 - Hot Threshold (Channel 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmBudgetCh0Dimm0; ///< Offset 104 - Warm Budget (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmBudgetCh0Dimm1; ///< Offset 105 - Warm Budget (Channel 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmBudgetCh1Dimm0; ///< Offset 106 - Warm Budget (Channel 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmBudgetCh1Dimm1; ///< Offset 107 - Warm Budget (Channel 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotBudgetCh0Dimm0; ///< Offset 108 - Hot Budget (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotBudgetCh0Dimm1; ///< Offset 109 - Hot Budget (Channel 0, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotBudgetCh1Dimm0; ///< Offset 110 - Hot Budget (Channel 1, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotBudgetCh1Dimm1; ///< Offset 111 - Hot Budget (Channel 1, Dimm 1): 0=Minimal, <b>255=Maximum</b>
+ UINT8 IdleEnergyCh0Dimm0; ///< Offset 113 - Idle Energy (Channel 0, Dimm 0): 0=Minimal, 63=Maximum, <b>10=Default</b>
+ UINT8 IdleEnergyCh0Dimm1; ///< Offset 112 - Idle Energy (Channel 0, Dimm 1): 0=Minimal, 63=Maximum, <b>10=Default</b>
+ UINT8 IdleEnergyCh1Dimm0; ///< Offset 115 - Idle Energy (Channel 1, Dimm 0): 0=Minimal, 63=Maximum, <b>10=Default</b>
+ UINT8 IdleEnergyCh1Dimm1; ///< Offset 114 - Idle Energy (Channel 1, Dimm 1): 0=Minimal, 63=Maximum, <b>10=Default</b>
+ UINT8 PdEnergyCh0Dimm0; ///< Offset 117 - Power Down Energy (Channel 0, Dimm 0): 0=Minimal, 63=Maximum, <b>6=Default</b>
+ UINT8 PdEnergyCh0Dimm1; ///< Offset 116 - Power Down Energy (Channel 0, Dimm 1): 0=Minimal, 63=Maximum, <b>6=Default</b>
+ UINT8 PdEnergyCh1Dimm0; ///< Offset 119 - Power Down Energy (Channel 1, Dimm 0): 0=Minimal, 63=Maximum, <b>6=Default</b>
+ UINT8 PdEnergyCh1Dimm1; ///< Offset 118 - Power Down Energy (Channel 1, Dimm 1): 0=Minimal, 63=Maximum, <b>6=Default</b>
+ UINT8 ActEnergyCh0Dimm0; ///< Offset 121 - Activation Energy (Channel 0, Dimm 0): 0=Minimal, 255=Maximum, <b>172=Default</b>
+ UINT8 ActEnergyCh0Dimm1; ///< Offset 120 - Activation Energy (Channel 0, Dimm 1): 0=Minimal, 255=Maximum, <b>172=Default</b>
+ UINT8 ActEnergyCh1Dimm0; ///< Offset 123 - Activation Energy (Channel 1, Dimm 0): 0=Minimal, 255=Maximum, <b>172=Default</b>
+ UINT8 ActEnergyCh1Dimm1; ///< Offset 122 - Activation Energy (Channel 1, Dimm 1): 0=Minimal, 255=Maximum, <b>172=Default</b>
+ UINT8 RdEnergyCh0Dimm0; ///< Offset 125 - Read Energy (Channel 0, Dimm 0): 0=Minimal, 255=Maximum, <b>212=Default</b>
+ UINT8 RdEnergyCh0Dimm1; ///< Offset 124 - Read Energy (Channel 0, Dimm 1): 0=Minimal, 255=Maximum, <b>212=Default</b>
+ UINT8 RdEnergyCh1Dimm0; ///< Offset 127 - Read Energy (Channel 1, Dimm 0): 0=Minimal, 255=Maximum, <b>212=Default</b>
+ UINT8 RdEnergyCh1Dimm1; ///< Offset 126 - Read Energy (Channel 1, Dimm 1): 0=Minimal, 255=Maximum, <b>212=Default</b>
+ UINT8 WrEnergyCh0Dimm0; ///< Offset 129 - Write Energy (Channel 0, Dimm 0): 0=Minimal, 255=Maximum, <b>221=Default</b>
+ UINT8 WrEnergyCh0Dimm1; ///< Offset 128 - Write Energy (Channel 0, Dimm 1): 0=Minimal, 255=Maximum, <b>221=Default</b>
+ UINT8 WrEnergyCh1Dimm0; ///< Offset 131 - Write Energy (Channel 1, Dimm 0): 0=Minimal, 255=Maximum, <b>221=Default</b>
+ UINT8 WrEnergyCh1Dimm1; ///< Offset 130 - Write Energy (Channel 1, Dimm 1): 0=Minimal, 255=Maximum, <b>221=Default</b>
+
+ UINT16 SrefCfgIdleTmr; ///< Offset 132 - Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
+ UINT8 MaxRttWr; ///< Offset 134 - Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
+ UINT8 ThrtCkeMinTmr; ///< Offset 135 - Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x30=Default</b>
+ UINT8 ThrtCkeMinTmrLpddr; ///< Offset 136 - Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x40=Default</b>
+
+ UINT8 EnergyScaleFact; ///< Offset 137 - Energy Scale Factor. 0=Minimal, 7=Maximum, <b>4=Default</b>
+ UINT8 RaplPwrFlCh1; ///< Offset 138 - Power Channel 1 Floor value: <b>0=Minimal</b>, 255=Maximum
+ UINT8 RaplPwrFlCh0; ///< Offset 139 - Power Channel 0 Floor value: <b>0=Minimal</b>, 255=Maximum
+ UINT8 PowerDownMode; ///< Offset 140 - CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
+ UINT8 PwdwnIdleCounter; ///< Offset 141 - CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
+ UINT8 CkeRankMapping; ///< Offset 142 - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies which rank CKE[i] goes to.
+ UINT8 BerEnable; ///< Offset 143 - BER Enable and # of Addresses passed in: <b>0=Minimal</b>, 8=Maximum
+ UINT64 BerAddress[4]; ///< Offset 144 - BER Address(es): <b>0=Minimal</b>, 0xFFFFFFFFFFFFFFFF=Maximum (step is 0x40)
+ UINT16 PciIndex; ///< Offset 176 - Pci index register address: <b>0xCF8=Default</b>
+ UINT16 PciData; ///< Offset 178 - Pci data register address: <b>0xCFC=Default</b>
+
+ UINT8 StrongWkLeaker; ///< Offset 180 - Strong Weak Leaker: 1=Minimal, <b>7=Maximum</b>
+ UINT8 CaVrefConfig; ///< Offset 181 0=VREF_CA goes to both CH_A and CH_B, 1=VREF_CA to CH_A, VREF_DQ_A to CH_B, <b>2=VREF_CA to CH_A, VREF_DQ_B to CH_B</b>
+ UINT16 FreqSaGvLow; ///< Offset 182 SA GV Low: 0 is Auto/default, otherwise holds the frequency value: <b>0=Default</b>, 1067, 1200, 1333, 1400, 1600, 1800, 1867. NOTE: must be below or equal to the SA GV High frequency.
+ UINT32 Vc1ReadMeterTimeWindow; ///< Offset 184 - VC1 Read Meter Time Window: 0=Minimal, 0x1FFFF=Maximum, <b>0x320=Default</b>
+ UINT16 Vc1ReadMeterThreshold; ///< Offset 188 - VC1 Read Meter Threshold (within Time Window): 0=Minimal, 0xFFFF=Maximum, <b>0x118=Default</b>
+ UINT16 Idd3n; ///< Offset 190 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
+ UINT16 Idd3p; ///< Offset 192 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
+ UINT8 EpgEnable; ///< Offset 194 Enable Energy Performance Gain.
+ UINT8 RhSolution; ///< Offset 195 Type of solution to be used for RHP - 0/1 = HardwareRhp/Refresh2x
+ UINT8 RhActProbability; ///< Offset 196 Activation probability for Hardware RHP
+ UINT8 SaGv; ///< Offset 197 SA GV: <b>0=Disabled</b>, 1=FixedLow, 2=FixedHigh, 3=Enabled
+
+ UINT8 UserThresholdEnable; ///< Offset 198 - Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 UserBudgetEnable; ///< Offset 199 - Flag to manually select the Budget Regiseters for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 TsodTcritMax; ///< Offset 200 - TSOD Tcrit Maximum Value to be Configure , 0=Minimal, 128=Maximum, , <b>105=Default</b>
+ UINT8 TsodEventMode; ///< Offset 201 - Flag to Enable Event Mode Interruption in TSOD Configuration Register, 0=Disable, 1=Enable, <b>1=Default</b>
+ UINT8 TsodEventPolarity; ///< Offset 202 - Event Signal Polarity in TSOD Configuration Register, 0=Low, 1=High, <b>0=Default</b>
+ UINT8 TsodCriticalEventOnly; ///< Offset 203 - Critical Trigger Only in TSOD Configuration Register,0=Disable, 1=Enable, <b>1=Default</b>
+ UINT8 TsodEventOutputControl; ///< Offset 204 - Event Output Control in TSOD Configuration Register,0=Disable, 1=Enable, <b>1=Default</b>
+ UINT8 TsodAlarmwindowLockBit; ///< Offset 205 - Alarm Windows Lock Bit in TSOD Configuration Register,0=Unlock, 1=Lock, <b>0=Default</b>
+ UINT8 TsodCriticaltripLockBit;///< Offset 206 - Critical Trip Lock Bit in TSOD Configuration Register,0=Unlock, 1=Lock, <b>0=Default</b>
+ UINT8 TsodShutdownMode; ///< Offset 207 - Shutdown Mode TSOD Configuration Register,0=Enable, 1=Disable, <b>0=Default</b>
+ UINT8 TsodThigMax; ///< Offset 208 - Thigh Max Value In the for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 TsodManualEnable; ///< Offset 209 - Flag to manually select the TSOD Register Values , 0=Disable, 1=Enable, <b>0=Default</b>
+
+ UINT8 RetrainOnFastFail; ///< Offset 210 - Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
+ UINT8 ForceOltmOrRefresh2x; ///< Offset 211 - Force OLTM or 2X Refresh when needed. <b>0 = Force OLTM</b>, 1 = Force 2x Refresh
+ UINT8 DllBwEn0; ///< Offset 212 - DllBwEn value for 1067
+ UINT8 DllBwEn1; ///< Offset 213 - DllBwEn value for 1333
+ UINT8 DllBwEn2; ///< Offset 214 - DllBwEn value for 1600
+ UINT8 DllBwEn3; ///< Offset 215 - DllBwEn value for 1867 and up
+ UINT32 VddSettleWaitTime; ///< Offset 216 - Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
+ UINT8 EnCmdRate; ///< Offset 220 - CMD Rate Enable: 0=Disable, 1=1 CMD, 2=2 CMDs, <b>3=3 CMDs</b>, 4=4 CMDs, 5=5 CMDs, 6=6 CMDs, 7=7 CMDs
+ UINT8 Refresh2X; ///< Offset 221 - Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
+ UINT8 SmramMask; ///< Offset 222 Reserved memory ranges for SMRAM
+ UINT8 Rsvd0; ///< Offset 223 - Reserved.
+
+ //
+ // Training Algorithms
+ //
+ UINT32 CMDSR : 1; ///< Offset 224 - CMD Slew Rate Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDDSEQ : 1; ///< - CMD Drive Strength and Tx Equalization: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDNORM : 1; ///< - CMD Normalization: 0=Disable, <b>1=Enable</b>.
+ UINT32 EWRDSEQ : 1; ///< - Early DQ Write Drive Strength and Equalization Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 RsvdBits2 :28;
+} MEMORY_CONFIGURATION;
+
+/**
+ No CRC Memory Configuration
+ The contents of this structure are not CRC'd by the MRC for option change detection.\n
+ <b>Revision 1</b>:
+ - Initial version.
+
+ <b>Revision 2</b>:
+ - No changes (updated due to a change in MEMORY_CONFIGURATION)
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ SA_FUNCTION_CALLS SaCall; ///< Offset 28 - Function calls into the SA.
+ SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 204 - Function calls into the MRC.
+ SPD_DATA_BUFFER *SpdData; ///< Offset 240 - Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
+ SA_MEMORY_DQ_MAPPING *DqByteMap; ///< Offset 244 - LPDDR3 DQ byte mapping to CMD/CTL/CLK, from the CPU side.
+ SA_MEMORY_DQS_MAPPING *DqsMap; ///< Offset 248 - LPDDR3 DQS byte swizzling between CPU and DRAM.
+ SA_MEMORY_RCOMP *RcompData; ///< Offset 252 - DDR RCOMP resistors and target values.
+ /**
+ The minimum platform memory size required to pass control into DXE.
+ @note Some debug features, such as Intel Processor Trace and Intel Trace Hub,
+ may require updating this policy to a larger value to accommodate those memory requests.
+ @note 4GB restriction: Due to 32-bit memory address space restriction,
+ increasing this value above default is not guaranteed to work, and will depend on available memory in 4GB space.
+ **/
+ UINT64 PlatformMemorySize; ///< Offset 256
+ UINT32 MmaTestContentPtr; ///< Offset 264 - Pointer to MMA Test Content Data. Used in FSP.
+ UINT32 MmaTestContentSize; ///< Offset 268 - Size of MMA Test Content Data. Used in FSP.
+ UINT32 MmaTestConfigPtr; ///< Offset 272 - Pointer to MMA Test Config Data. Used in FSP.
+ UINT32 MmaTestConfigSize; ///< Offset 276 - Size of MMA Test Config Data. Used in FSP.
+ UINT32 CleanMemory:1; ///< Offset 280 - Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
+ UINT32 RsvdBits0:31;
+ /**
+ Sets the serial debug message level\n
+ 0x00 = Disabled\n
+ 0x01 = Errors only\n
+ 0x02 = Errors and Warnings\n
+ <b>0x03 = Errors, Warnings, and Info</b>\n
+ 0x04 = Errors, Warnings, Info, and Events\n
+ 0x05 = Displays Memory Init Execution Time Summary only\n
+ **/
+ UINT8 SerialDebugLevel; ///< Offset 284
+ UINT8 Rsvd0[3]; ///< Offset 285
+} MEMORY_CONFIG_NO_CRC;
+#pragma pack(pop)
+
+#endif // _MEMORY_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/MiscDxeConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/MiscDxeConfig.h new file mode 100644 index 0000000000..18a5371c4b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/MiscDxeConfig.h @@ -0,0 +1,35 @@ +/** @file
+ MISC DXE policy definitions
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MISC_DXE_CONFIG_H_
+#define _MISC_DXE_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#define MISC_DXE_CONFIG_REVISION 1
+
+/**
+ This data structure includes miscellaneous configuration variables such SA thermal device
+ control. The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 EnableAbove4GBMmio : 1; ///< Enable/disable above 4GB MMIO resource support: <b>0=Disable</b>, 1=Enable
+ UINT32 RsvdBits0 : 31; ///< Reserved bits.
+ EFI_PHYSICAL_ADDRESS *RmrrUsbBaseAddress; ///< The field is used to describe the platform USB Reserved memory for Intel VT-d support. Platform code should provide this information for Intel VT-d DXE driver use
+} MISC_DXE_CONFIG;
+#pragma pack(pop)
+
+#endif // _MISC_DXE_CONFIG_H_
\ No newline at end of file diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h new file mode 100644 index 0000000000..0bf1934207 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPeiPreMemConfig.h @@ -0,0 +1,38 @@ +/** @file
+ Policy details for miscellaneous configuration in System Agent
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_
+#define _SA_MISC_PEI_PREMEM_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#ifndef SA_MC_MAX_SOCKETS
+#define SA_MC_MAX_SOCKETS 4
+#endif
+
+#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 1
+
+/**
+ This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming
+ different System Agent BARs, TsegSize, IedSize, MmioSize required etc.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory DIMMs' SPD address for reading SPD data. <b>example: SpdAddressTable[0]=0xA2(C0D0), SpdAddressTable[1]=0xA0(C0D1), SpdAddressTable[2]=0xA2(C1D0), SpdAddressTable[3]=0xA0(C1D1)</b>
+ UINT32 MchBar; ///< Offset 36 Address of System Agent MCHBAR: <b>0xFED10000</b>
+} SA_MISC_PEI_PREMEM_CONFIG;
+#pragma pack(pop)
+
+#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdConfig.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdConfig.h new file mode 100644 index 0000000000..086d70849a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdConfig.h @@ -0,0 +1,46 @@ +/** @file
+ VT-d policy definitions.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _VTD_CONFIG_H_
+#define _VTD_CONFIG_H_
+
+#pragma pack(push, 1)
+
+#define SA_VTD_ENGINE_NUMBER 2
+
+#define VTD_CONFIG_REVISION 1
+
+/**
+ The data elements should be initialized by a Platform Module.
+ The data structure is for VT-d driver initialization\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ /**
+ Offset 28:0 :
+ VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.
+ This policy is for debug purpose only.
+ If VT-D is not supported, all other policies in this config block will be ignored.
+ <b>0 = To use Vt-d</b>;
+ 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.
+ **/
+ UINT32 VtdDisable : 1;
+ UINT32 X2ApicOptOut : 1; ///< Offset 28:1 :This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
+ UINT32 RsvdBits0 : 30; ///< Offset 28:2 :Reserved bits for future use
+ UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< Offset 32: This field is used to describe the base addresses for VT-d function: <b>BaseAddress[0]=0xFED90000, BaseAddress[0]=0xFED91000 </b>
+} VTD_CONFIG;
+#pragma pack(pop)
+
+#endif // _VTD_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/DmaRemappingTable.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/DmaRemappingTable.h new file mode 100644 index 0000000000..0c49f98f2c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/DmaRemappingTable.h @@ -0,0 +1,112 @@ +/** @file
+ This code defines ACPI DMA Remapping table related definitions.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DMA_REMAPPING_TABLE_H_
+#define _DMA_REMAPPING_TABLE_H_
+
+#include <Uefi.h>
+#include <Base.h>
+#include <IndustryStandard/Acpi30.h>
+
+#pragma pack(1)
+///
+/// DMAR table signature
+///
+#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< "DMAR"
+#define EFI_ACPI_DMAR_TABLE_REVISION 1
+#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10
+#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18
+#define MAX_PCI_DEPTH 5
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Length;
+ UINT16 Reserved;
+ UINT8 EnumId;
+ UINT8 StartBusNumber;
+ UINT8 PciPath[2]; // device, function
+} EFI_ACPI_DEV_SCOPE_STRUCTURE;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Flags;
+ UINT8 Reserved;
+ UINT16 SegmentNum;
+ EFI_PHYSICAL_ADDRESS RegisterBaseAddress;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1];
+} EFI_ACPI_DRHD_ENGINE1_STRUCT;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Flags;
+ UINT8 Reserved;
+ UINT16 SegmentNum;
+ EFI_PHYSICAL_ADDRESS RegisterBaseAddress;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[14];
+} EFI_ACPI_DRHD_ENGINE2_STRUCT;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 Reserved;
+ UINT16 SegmentNum;
+ EFI_PHYSICAL_ADDRESS RmrBaseAddress;
+ EFI_PHYSICAL_ADDRESS RmrLimitAddress;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];
+} EFI_ACPI_RMRR_USB_STRUC;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT16 Reserved;
+ UINT16 SegmentNum;
+ EFI_PHYSICAL_ADDRESS RmrBaseAddress;
+ EFI_PHYSICAL_ADDRESS RmrLimitAddress;
+ EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD
+} EFI_ACPI_RMRR_IGD_STRUC;
+
+typedef struct {
+ UINT16 Type;
+ UINT16 Length;
+ UINT8 Reserved[3];
+ UINT8 AcpiDeviceNumber;
+ UINT8 AcpiObjectName[20];
+} EFI_ACPI_ANDD_STRUC;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT8 HostAddressWidth;
+ UINT8 Flags;
+ UINT8 Reserved[10];
+ EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1;
+ EFI_ACPI_DRHD_ENGINE2_STRUCT DrhdEngine2;
+ EFI_ACPI_RMRR_USB_STRUC RmrrUsb;
+ EFI_ACPI_RMRR_IGD_STRUC RmrrIgd;
+ EFI_ACPI_ANDD_STRUC AnddI2C0;
+ EFI_ACPI_ANDD_STRUC AnddI2C1;
+ EFI_ACPI_ANDD_STRUC AnddI2C2;
+ EFI_ACPI_ANDD_STRUC AnddI2C3;
+ EFI_ACPI_ANDD_STRUC AnddI2C4;
+ EFI_ACPI_ANDD_STRUC AnddI2C5;
+ EFI_ACPI_ANDD_STRUC AnddSpi0;
+ EFI_ACPI_ANDD_STRUC AnddSpi1;
+ EFI_ACPI_ANDD_STRUC AnddUa00;
+ EFI_ACPI_ANDD_STRUC AnddUa01;
+ EFI_ACPI_ANDD_STRUC AnddUa02;
+} EFI_ACPI_DMAR_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h new file mode 100644 index 0000000000..12274d797d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicyLib.h @@ -0,0 +1,65 @@ +/** @file
+ Prototype of the DxeSaPolicyLib library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DXE_SA_POLICY_LIB_H_
+#define _DXE_SA_POLICY_LIB_H_
+
+#include <Protocol/SaPolicy.h>
+
+/**
+ This function prints the DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+**/
+VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+;
+
+/**
+ CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SaPolicy The pointer to get SA Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks(
+ IN OUT SA_POLICY_PROTOCOL **SaPolicy
+);
+
+/**
+ SaInstallPolicyProtocol installs SA Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SaPolicy The pointer to SA Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+;
+
+#endif // _DXE_SA_POLICY_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h new file mode 100644 index 0000000000..6348fd003e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicyLib.h @@ -0,0 +1,91 @@ +/** @file
+ Prototype of the PeiSaPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_SA_POLICY_LIB_H_
+#define _PEI_SA_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function prints the PEI phase PreMem policy.
+
+ @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI instance
+**/
+VOID
+EFIAPI
+SaPrintPolicyPpiPreMem (
+ IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
+ );
+
+/**
+ This function prints the PEI phase policy.
+
+ @param[in] SiPolicyPpi The RC Policy PPI instance
+**/
+VOID
+EFIAPI
+SaPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ Get SA config block table total size.
+
+ @retval Size of SA config block table
+**/
+UINT16
+EFIAPI
+SaGetConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ Get SA config block table total size.
+
+ @retval Size of SA config block table
+**/
+UINT16
+EFIAPI
+SaGetConfigBlockTotalSizePreMem (
+ VOID
+ );
+
+/**
+ SaAddConfigBlocksPreMem add all SA config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SaAddConfigBlocksPreMem (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+/**
+ SaAddConfigBlocks add all SA config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SaAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+#endif // _PEI_SA_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLib.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLib.h new file mode 100644 index 0000000000..f3762e91a5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLib.h @@ -0,0 +1,34 @@ +/** @file
+ Header file for SaPlatformLib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_PLATFORM_LIB_H_
+#define _SA_PLATFORM_LIB_H_
+
+#include <SaAccess.h>
+#include <CpuAccess.h>
+
+/**
+ Determine if PCH Link is DMI/OPI
+
+ @param[in] CpuModel CPU model
+
+ @retval TRUE DMI
+ @retval FALSE OPI
+**/
+BOOLEAN
+IsPchLinkDmi (
+ IN CPU_FAMILY CpuModel
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/MemInfoHob.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/MemInfoHob.h new file mode 100644 index 0000000000..dbf93ac265 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/MemInfoHob.h @@ -0,0 +1,244 @@ +/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE 1
+#define MAX_CH 2
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef bmCold
+#define bmCold 0 // Cold boot
+#endif
+#ifndef bmWarm
+#define bmWarm 1 // Warm boot
+#endif
+#ifndef bmS3
+#define bmS3 2 // S3 resume
+#endif
+#ifndef bmFast
+#define bmFast 3 // Fast boot
+#endif
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 3
+#endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ UINT8 Revision;
+ UINT16 DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ UINT32 FreqMax;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT32 PrmrrBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/GopPolicy.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/GopPolicy.h new file mode 100644 index 0000000000..e7e72e5e53 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/GopPolicy.h @@ -0,0 +1,78 @@ +/** @file
+ Interface definition for GopPolicy Protocol.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GOP_POLICY_PROTOCOL_H_
+#define _GOP_POLICY_PROTOCOL_H_
+
+
+#define GOP_POLICY_PROTOCOL_REVISION_01 0x01
+#define GOP_POLICY_PROTOCOL_REVISION_03 0x03
+
+typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+typedef enum {
+ Docked,
+ UnDocked,
+ DockStatusMax
+} DOCK_STATUS;
+
+///
+/// Function to retrieve LID status
+///
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS * CurrentLidStatus
+ );
+
+///
+/// Function to retrieve Dock status
+///
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_DOCK_STATUS) (
+ OUT DOCK_STATUS CurrentDockStatus
+);
+
+///
+/// Function to retrieve VBT table address and size
+///
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS * VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+/**
+ System Agent Graphics Output Protocol (GOP) - Policy Protocol\n
+ Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot\n
+ When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization\n
+ All functions in this protocol should be initialized by platform code basing on platform implementation\n
+**/
+typedef struct {
+ UINT32 Revision; ///< Protocol revision
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol function to get Lid Status. Platform code should provide this function basing on design.
+ GET_VBT_DATA GetVbtData; ///< Protocol function to get Vbt Data address and size. Platform code should provide this function basing on design.
+ GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function pointer for get platform dock status.
+ EFI_GUID GopOverrideGuid; ///< A GUID provided by BIOS in case GOP is to be overridden.
+} GOP_POLICY_PROTOCOL;
+
+extern EFI_GUID gGopPolicyProtocolGuid;
+extern EFI_GUID gIntelGraphicsVbtGuid;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRegion.h new file mode 100644 index 0000000000..b39ccc31d4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRegion.h @@ -0,0 +1,170 @@ +/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+@par Specification Reference:
+ - IGD OpRegion/Software SCI SPEC
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+/**
+ Protocol data definitions
+
+
+ OpRegion structures:
+ Sub-structures define the different parts of the OpRegion followed by the
+ main structure representing the entire OpRegion.
+
+ Note: These structures are packed to 1 byte offsets because the exact
+ data location is requred by the supporting design specification due to
+ the fact that the data is used by ASL and Graphics driver code compiled
+ separatly.
+**/
+#pragma pack(1)
+///
+/// OpRegion header (mailbox 0) structure and defines.
+///
+typedef struct {
+ CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion signature
+ UINT32 SIZE; ///< Offset 16 OpRegion size
+ UINT32 OVER; ///< Offset 20 OpRegion structure version
+ UINT8 SVER[0x20]; ///< Offset 24 System BIOS build version
+ UINT8 VVER[0x10]; ///< Offset 56 Video BIOS build version
+ UINT8 GVER[0x10]; ///< Offset 72 Graphic driver build version
+ UINT32 MBOX; ///< Offset 88 Mailboxes supported
+ UINT32 DMOD; ///< Offset 92 Driver Model
+ UINT32 PCON; ///< Offset 96 Platform Capabilities
+ CHAR16 DVER[0x10]; ///< Offset 100 GOP Version
+ UINT8 RHD1[0x7C]; ///< Offset 132 Reserved
+} OPREGION_HEADER;
+#pragma pack()
+#pragma pack(1)
+///
+/// OpRegion mailbox 1 (public ACPI Methods).
+///
+typedef struct {
+ UINT32 DRDY; ///< Offset 0 Driver readiness
+ UINT32 CSTS; ///< Offset 4 Status
+ UINT32 CEVT; ///< Offset 8 Current event
+ UINT8 RM11[0x14]; ///< Offset 12 Reserved
+ UINT32 DIDL; ///< Offset 32 Supported display device 1
+ UINT32 DDL2; ///< Offset 36 Supported display device 2
+ UINT32 DDL3; ///< Offset 40 Supported display device 3
+ UINT32 DDL4; ///< Offset 44 Supported display device 4
+ UINT32 DDL5; ///< Offset 48 Supported display device 5
+ UINT32 DDL6; ///< Offset 52 Supported display device 6
+ UINT32 DDL7; ///< Offset 56 Supported display device 7
+ UINT32 DDL8; ///< Offset 60 Supported display device 8
+ UINT32 CPDL; ///< Offset 64 Currently present display device 1
+ UINT32 CPL2; ///< Offset 68 Currently present display device 2
+ UINT32 CPL3; ///< Offset 72 Currently present display device 3
+ UINT32 CPL4; ///< Offset 76 Currently present display device 4
+ UINT32 CPL5; ///< Offset 80 Currently present display device 5
+ UINT32 CPL6; ///< Offset 84 Currently present display device 6
+ UINT32 CPL7; ///< Offset 88 Currently present display device 7
+ UINT32 CPL8; ///< Offset 92 Currently present display device 8
+ UINT32 CADL; ///< Offset 96 Currently active display device 1
+ UINT32 CAL2; ///< Offset 100 Currently active display device 2
+ UINT32 CAL3; ///< Offset 104 Currently active display device 3
+ UINT32 CAL4; ///< Offset 108 Currently active display device 4
+ UINT32 CAL5; ///< Offset 112 Currently active display device 5
+ UINT32 CAL6; ///< Offset 116 Currently active display device 6
+ UINT32 CAL7; ///< Offset 120 Currently active display device 7
+ UINT32 CAL8; ///< Offset 124 Currently active display device 8
+ UINT32 NADL; ///< Offset 128 Next active device 1
+ UINT32 NDL2; ///< Offset 132 Next active device 2
+ UINT32 NDL3; ///< Offset 136 Next active device 3
+ UINT32 NDL4; ///< Offset 140 Next active device 4
+ UINT32 NDL5; ///< Offset 144 Next active device 5
+ UINT32 NDL6; ///< Offset 148 Next active device 6
+ UINT32 NDL7; ///< Offset 152 Next active device 7
+ UINT32 NDL8; ///< Offset 156 Next active device 8
+ UINT32 ASLP; ///< Offset 160 ASL sleep timeout
+ UINT32 TIDX; ///< Offset 164 Toggle table index
+ UINT32 CHPD; ///< Offset 168 Current hot plug enable indicator
+ UINT32 CLID; ///< Offset 172 Current lid state indicator
+ UINT32 CDCK; ///< Offset 176 Current docking state indicator
+ UINT32 SXSW; ///< Offset 180 Display Switch notification on Sx State resume
+ UINT32 EVTS; ///< Offset 184 Events supported by ASL
+ UINT32 CNOT; ///< Offset 188 Current OS Notification
+ UINT32 NRDY; ///< Offset 192 Reasons for DRDY = 0
+ UINT8 RM12[0x3C]; ///< Offset 196 Reserved
+} OPREGION_MBOX1;
+#pragma pack()
+#pragma pack(1)
+///
+/// OpRegion mailbox 2 (Software SCI Interface).
+///
+typedef struct {
+ UINT32 SCIC; ///< Offset 0 Software SCI function number parameters
+ UINT32 PARM; ///< Offset 4 Software SCI additional parameters
+ UINT32 DSLP; ///< Offset 8 Driver sleep timeout
+ UINT8 RM21[0xF4]; ///< Offset 12 Reserved
+} OPREGION_MBOX2;
+#pragma pack()
+#pragma pack(1)
+///
+/// OpRegion mailbox 3 (Power Conservation).
+///
+typedef struct {
+ UINT32 ARDY; ///< Offset 0 Driver readiness
+ UINT32 ASLC; ///< Offset 4 ASLE interrupt command / status
+ UINT32 TCHE; ///< Offset 8 Technology enabled indicator
+ UINT32 ALSI; ///< Offset 12 Current ALS illuminance reading
+ UINT32 BCLP; ///< Offset 16 Backlight britness to set
+ UINT32 PFIT; ///< Offset 20 Panel fitting Request
+ UINT32 CBLV; ///< Offset 24 Brightness Current State
+ UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Level Duty Cycle Mapping Table
+ UINT32 CPFM; ///< Offset 68 Panel Fitting Current Mode
+ UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes
+ UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table
+ UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness
+ UINT32 CCDV; ///< Offset 154 Color Correction Default Values
+ UINT32 PCFT; ///< Offset 158 Power Conservation Features
+ UINT32 SROT; ///< Offset 162 Supported Rotation angle
+ UINT32 IUER; ///< Offset 166 Intel Ultrabook Event Register
+ UINT64 FDSP; ///< Offset 170 FFS Display Physical address
+ UINT32 FDSS; ///< Offset 178 FFS Display Size
+ UINT8 RM32[0x4A]; ///< Offset 182 Reserved
+} OPREGION_MBOX3;
+#pragma pack()
+#pragma pack(1)
+///
+/// OpRegion mailbox 4 (VBT).
+///
+typedef struct {
+ UINT8 GVD1[0x1C00]; ///< Reserved
+} OPREGION_VBT;
+#pragma pack()
+#pragma pack(1)
+///
+/// IGD OpRegion Structure
+///
+typedef struct {
+ OPREGION_HEADER Header; ///< OpRegion header
+ OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods
+ OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface
+ OPREGION_MBOX3 MBox3; ///< Mailbox 3: Power Conservation
+ OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data)
+} IGD_OPREGION_STRUC;
+#pragma pack()
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+ IGD_OPREGION_STRUC *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/MemInfo.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/MemInfo.h new file mode 100644 index 0000000000..ceadd739d6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/MemInfo.h @@ -0,0 +1,122 @@ +/** @file
+ This protocol provides the memory information data, such as
+ total physical memory size, memory frequency, memory size
+ of each dimm and rank.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MEM_INFO_PROTOCOL_H_
+#define _MEM_INFO_PROTOCOL_H_
+
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gMemInfoProtocolGuid;
+
+//
+// Protocol definitions
+//
+#define NODE_NUM 1
+#define CH_NUM 2
+#define DIMM_NUM 2
+#define RANK_NUM 2
+#define SLOT_NUM (CH_NUM * DIMM_NUM)
+#define PROFILE_NUM 4 // number of memory profiles supported
+#define XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 3
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+#pragma pack(1)
+///
+/// Memory timing Structure
+///
+typedef struct {
+ UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time
+ UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT8 Rsvd[2]; ///< Offset 30
+} MEMORY_TIMING;
+
+// @todo use the MemInfoHob data instead of duplicate structure.
+///
+/// Memory information Data Structure
+///
+typedef struct {
+ MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timming information for the DIMM
+ UINT32 memSize; ///< Offset 128 Total physical memory size
+ UINT16 ddrFreq; ///< Offset 132 DDR Current Frequency
+ UINT16 ddrFreqMax; ///< Offset 134 DDR Maximum Frequency
+ UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Size of each DIMM
+ UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The voltage setting for the DIMM
+ UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152 The enumeration value from MrcDimmSts
+ UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156 Number of ranks in a DIMM
+ UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160 SPD data of each DIMM
+ UINT8 RefClk; ///< Offset 192 Reference Clock
+ UINT8 Ratio; ///< Offset 193 Clock Multiplier
+ BOOLEAN EccSupport; ///< Offset 194 ECC supported or not
+ UINT8 Profile; ///< Offset 195 Currently running memory profile
+ UINT8 XmpProfileEnable; ///< Offset 196 If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 DdrType; ///< Offset 197 Current DDR type, see DDR_TYPE_xxx defines above
+ UINT8 Reserved[2]; ///< Offset 198 Reserved bytes for future use
+ UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200 The Default XMP tCK values read from SPD.
+} MEMORY_INFO_DATA;
+#pragma pack()
+
+///
+/// Memory information Protocol definition
+///
+typedef struct {
+ MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure
+} MEM_INFO_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaGlobalNvsArea.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaGlobalNvsArea.h new file mode 100644 index 0000000000..5daf183c1a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaGlobalNvsArea.h @@ -0,0 +1,32 @@ +/** @file
+ Definition of the System Agent global NVS area protocol.
+ This protocol publishes the address and format of a global ACPI NVS buffer
+ used as a communications buffer between SMM/DXE/PEI code and ASL code.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SYSTEM_AGENT_GLOBAL_NVS_AREA_H_
+#define _SYSTEM_AGENT_GLOBAL_NVS_AREA_H_
+
+#include "SaNvs.h"
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaGlobalNvsAreaProtocolGuid;
+
+///
+/// System Agent Global NVS Area Protocol
+///
+typedef struct {
+ SYSTEM_AGENT_GLOBAL_NVS_AREA *Area; ///< System Agent Global NVS Area Structure
+} SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaNvs.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaNvs.h new file mode 100644 index 0000000000..8f6ec57304 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaNvs.h @@ -0,0 +1,138 @@ +/**@file
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+ //
+ // Define SA NVS Area operatino region.
+ //
+
+#ifndef _SA_NVS_H_
+#define _SA_NVS_H_
+
+#pragma pack (push,1)
+typedef struct {
+ UINT32 IgdOpRegionAddress; ///< Offset 0 IGD OpRegion base address
+ UINT8 GfxTurboIMON; ///< Offset 4 IMON Current Value
+ UINT8 IgdState; ///< Offset 5 IGD State (Primary Display = 1)
+ UINT8 IgdBootType; ///< Offset 6 IGD Boot Display Device
+ UINT8 IgdPanelType; ///< Offset 7 IGD Panel Type CMOS option
+ UINT8 IgdPanelScaling; ///< Offset 8 IGD Panel Scaling
+ UINT8 IgdBiaConfig; ///< Offset 9 IGD BIA Configuration
+ UINT8 IgdSscConfig; ///< Offset 10 IGD SSC Configuration
+ UINT8 IgdDvmtMemSize; ///< Offset 11 IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; ///< Offset 12 IGD Function 1 Enable
+ UINT8 IgdHpllVco; ///< Offset 13 HPLL VCO
+ UINT8 IgdSciSmiMode; ///< Offset 14 GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; ///< Offset 15 IGD PAVP data
+ UINT8 CurrentDeviceList; ///< Offset 16 Current Attached Device List
+ UINT16 CurrentDisplayState; ///< Offset 17 Current Display State
+ UINT16 NextDisplayState; ///< Offset 19 Next Display State
+ UINT8 NumberOfValidDeviceId; ///< Offset 21 Number of Valid Device IDs
+ UINT32 DeviceId1; ///< Offset 22 Device ID 1
+ UINT32 DeviceId2; ///< Offset 26 Device ID 2
+ UINT32 DeviceId3; ///< Offset 30 Device ID 3
+ UINT32 DeviceId4; ///< Offset 34 Device ID 4
+ UINT32 DeviceId5; ///< Offset 38 Device ID 5
+ UINT32 DeviceId6; ///< Offset 42 Device ID 6
+ UINT32 DeviceId7; ///< Offset 46 Device ID 7
+ UINT32 DeviceId8; ///< Offset 50 Device ID 8
+ UINT32 DeviceId9; ///< Offset 54 Device ID 9
+ UINT32 DeviceId10; ///< Offset 58 Device ID 10
+ UINT32 DeviceId11; ///< Offset 62 Device ID 11
+ UINT32 DeviceId12; ///< Offset 66 Device ID 12
+ UINT32 DeviceId13; ///< Offset 70 Device ID 13
+ UINT32 DeviceId14; ///< Offset 74 Device ID 14
+ UINT32 DeviceId15; ///< Offset 78 Device ID 15
+ UINT32 DeviceIdX; ///< Offset 82 Device ID for eDP device
+ UINT32 NextStateDid1; ///< Offset 86 Next state DID1 for _DGS
+ UINT32 NextStateDid2; ///< Offset 90 Next state DID2 for _DGS
+ UINT32 NextStateDid3; ///< Offset 94 Next state DID3 for _DGS
+ UINT32 NextStateDid4; ///< Offset 98 Next state DID4 for _DGS
+ UINT32 NextStateDid5; ///< Offset 102 Next state DID5 for _DGS
+ UINT32 NextStateDid6; ///< Offset 106 Next state DID6 for _DGS
+ UINT32 NextStateDid7; ///< Offset 110 Next state DID7 for _DGS
+ UINT32 NextStateDid8; ///< Offset 114 Next state DID8 for _DGS
+ UINT32 NextStateDidEdp; ///< Offset 118 Next state DID for eDP
+ UINT8 LidState; ///< Offset 122 Lid State (Lid Open = 1)
+ UINT32 AKsv0; ///< Offset 123 First four bytes of AKSV (manufacturing mode)
+ UINT8 AKsv1; ///< Offset 127 Fifth byte of AKSV (manufacturing mode)
+ UINT8 BrightnessPercentage; ///< Offset 128 Brightness Level Percentage
+ UINT8 AlsEnable; ///< Offset 129 Ambient Light Sensor Enable
+ UINT8 AlsAdjustmentFactor; ///< Offset 130 Ambient Light Adjusment Factor
+ UINT8 LuxLowValue; ///< Offset 131 LUX Low Value
+ UINT8 LuxHighValue; ///< Offset 132 LUX High Value
+ UINT8 ActiveLFP; ///< Offset 133 Active LFP
+ UINT8 ImguAcpiMode; ///< Offset 134 IMGU ACPI device type
+ UINT8 EdpValid; ///< Offset 135 Check for eDP display device
+ UINT8 SgMode; ///< Offset 136 SG Mode (0=Disabled, 1=SG Muxed, 2=SG Muxless, 3=DGPU Only)
+ UINT8 SgFeatureList; ///< Offset 137 SG Feature List
+ UINT8 Pcie0GpioSupport; ///< Offset 138 PCIe0 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
+ UINT8 Pcie0HoldRstExpanderNo; ///< Offset 139 PCIe0 HLD RST IO Expander Number
+ UINT32 Pcie0HoldRstGpioNo; ///< Offset 140 PCIe0 HLD RST GPIO Number
+ UINT8 Pcie0HoldRstActiveInfo; ///< Offset 144 PCIe0 HLD RST GPIO Active Information
+ UINT8 Pcie0PwrEnExpanderNo; ///< Offset 145 PCIe0 PWR Enable IO Expander Number
+ UINT32 Pcie0PwrEnGpioNo; ///< Offset 146 PCIe0 PWR Enable GPIO Number
+ UINT8 Pcie0PwrEnActiveInfo; ///< Offset 150 PCIe0 PWR Enable GPIO Active Information
+ UINT8 Pcie1GpioSupport; ///< Offset 151 PCIe1 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
+ UINT8 Pcie1HoldRstExpanderNo; ///< Offset 152 PCIe1 HLD RST IO Expander Number
+ UINT32 Pcie1HoldRstGpioNo; ///< Offset 153 PCIe1 HLD RST GPIO Number
+ UINT8 Pcie1HoldRstActiveInfo; ///< Offset 157 PCIe1 HLD RST GPIO Active Information
+ UINT8 Pcie1PwrEnExpanderNo; ///< Offset 158 PCIe1 PWR Enable IO Expander Number
+ UINT32 Pcie1PwrEnGpioNo; ///< Offset 159 PCIe1 PWR Enable GPIO Number
+ UINT8 Pcie1PwrEnActiveInfo; ///< Offset 163 PCIe1 PWR Enable GPIO Active Information
+ UINT8 Pcie2GpioSupport; ///< Offset 164 PCIe2 GPIO Support (0=Disabled, 1=PCH Based, 2=I2C Based)
+ UINT8 Pcie2HoldRstExpanderNo; ///< Offset 165 PCIe2 HLD RST IO Expander Number
+ UINT32 Pcie2HoldRstGpioNo; ///< Offset 166 PCIe2 HLD RST GPIO Number
+ UINT8 Pcie2HoldRstActiveInfo; ///< Offset 170 PCIe2 HLD RST GPIO Active Information
+ UINT8 Pcie2PwrEnExpanderNo; ///< Offset 171 PCIe2 PWR Enable IO Expander Number
+ UINT32 Pcie2PwrEnGpioNo; ///< Offset 172 PCIe2 PWR Enable GPIO Number
+ UINT8 Pcie2PwrEnActiveInfo; ///< Offset 176 PCIe2 PWR Enable GPIO Active Information
+ UINT16 DelayAfterPwrEn; ///< Offset 177 Delay after power enable for PCIe
+ UINT16 DelayAfterHoldReset; ///< Offset 179 Delay after Hold Reset for PCIe
+ UINT8 Pcie0EpCapOffset; ///< Offset 181 PCIe0 Endpoint Capability Structure Offset
+ UINT32 XPcieCfgBaseAddress; ///< Offset 182 Any Device's PCIe Config Space Base Address
+ UINT16 GpioBaseAddress; ///< Offset 186 GPIO Base Address
+ UINT32 NvIgOpRegionAddress; ///< Offset 188 NVIG opregion address
+ UINT32 NvHmOpRegionAddress; ///< Offset 192 NVHM opregion address
+ UINT32 ApXmOpRegionAddress; ///< Offset 196 AMDA opregion address
+ UINT8 Peg0LtrEnable; ///< Offset 200 Latency Tolerance Reporting Enable
+ UINT8 Peg0ObffEnable; ///< Offset 201 Optimized Buffer Flush and Fill
+ UINT8 Peg1LtrEnable; ///< Offset 202 Latency Tolerance Reporting Enable
+ UINT8 Peg1ObffEnable; ///< Offset 203 Optimized Buffer Flush and Fill
+ UINT8 Peg2LtrEnable; ///< Offset 204 Latency Tolerance Reporting Enable
+ UINT8 Peg2ObffEnable; ///< Offset 205 Optimized Buffer Flush and Fill
+ UINT16 PegLtrMaxSnoopLatency; ///< Offset 206 SA Peg Latency Tolerance Reporting Max Snoop Latency
+ UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 208 SA Peg Latency Tolerance Reporting Max No Snoop Latency
+ UINT8 Peg0PowerDownUnusedBundles; ///< Offset 210 Peg0 Unused Bundle Control
+ UINT8 Peg1PowerDownUnusedBundles; ///< Offset 211 Peg1 Unused Bundle Control
+ UINT8 Peg2PowerDownUnusedBundles; ///< Offset 212 Peg2 Unused Bundle Control
+ UINT8 PackageCstateLimit; ///< Offset 213 The lowest C-state for the package
+ UINT8 PwrDnBundlesGlobalEnable; ///< Offset 214 Pegx Unused Bundle Control Global Enable (0=Disabled, 1=Enabled)
+ UINT64 Mmio64Base; ///< Offset 215 Base of above 4GB MMIO resource
+ UINT64 Mmio64Length; ///< Offset 223 Length of above 4GB MMIO resource
+ UINT32 CpuIdInfo; ///< Offset 231 CPU ID info to get Family Id or Stepping
+ UINT8 Pcie1EpCapOffset; ///< Offset 235 PCIe1 Endpoint Capability Structure Offset
+ UINT8 Pcie2EpCapOffset; ///< Offset 236 PCIe2 Endpoint Capability Structure Offset
+ UINT8 Pcie0SecBusNum; ///< Offset 237 PCIe0 Secondary Bus Number (PCIe0 Endpoint Bus Number)
+ UINT8 Pcie1SecBusNum; ///< Offset 238 PCIe1 Secondary Bus Number (PCIe0 Endpoint Bus Number)
+ UINT8 Pcie2SecBusNum; ///< Offset 239 PCIe2 Secondary Bus Number (PCIe0 Endpoint Bus Number)
+ UINT32 Mmio32Base; ///< Offset 240 Base of below 4GB MMIO resource
+ UINT32 Mmio32Length; ///< Offset 244 Length of below 4GB MMIO resource
+ UINT32 Pcie0WakeGpioNo; ///< Offset 248 PCIe0 RTD3 Device Wake GPIO Number
+ UINT32 Pcie1WakeGpioNo; ///< Offset 252 PCIe1 RTD3 Device Wake GPIO Number
+ UINT32 Pcie2WakeGpioNo; ///< Offset 256 PCIe2 RTD3 Device Wake GPIO Number
+ UINT8 Reserved0[240]; ///< Offset 260:499
+ UINT8 Reserved1[3]; ///< Offset 500:502
+} SYSTEM_AGENT_GLOBAL_NVS_AREA;
+
+#pragma pack(pop)
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h new file mode 100644 index 0000000000..577eaa8ffc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h @@ -0,0 +1,58 @@ +/** @file
+ Interface definition details between System Agent and platform drivers during DXE phase.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_POLICY_H_
+#define _SA_POLICY_H_
+
+#include <SaAccess.h>
+#include <ConfigBlock.h>
+#include <Library/ConfigBlockLib.h>
+#include <ConfigBlock/GraphicsDxeConfig.h>
+#include <ConfigBlock/MiscDxeConfig.h>
+
+///
+/// Extern the GUID for protocol users.
+///
+extern EFI_GUID gSaPolicyProtocolGuid;
+extern EFI_GUID gGraphicsDxeConfigGuid;
+
+/**
+ Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external
+ modules maybe have consumed this macro in their source code. Directly
+ update the SA_POLICY_PROTOCOL_REVISION version number may cause those
+ external modules to auto mark themselves wrong version info.
+ Always create new version macro for new Policy protocol interface.
+**/
+#define SA_POLICY_PROTOCOL_REVISION 1
+
+/**
+ SA DXE Policy
+
+ The SA_POLICY_PROTOCOL producer drvier is recommended to
+ set all the SA_POLICY_PROTOCOL size buffer zero before init any member parameter,
+ this clear step can make sure no random value for those unknow new version parameters.
+
+ Make sure to update the Revision if any change to the protocol, including the existing
+ internal structure definations.\n
+ Note: Here revision will be bumped up when adding/removing any config block under this structure.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+} SA_POLICY_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaAccess.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaAccess.h new file mode 100644 index 0000000000..5d343ba57a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaAccess.h @@ -0,0 +1,52 @@ +/** @file
+ Macros to simplify and abstract the interface to PCI configuration.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SAACCESS_H_
+#define _SAACCESS_H_
+
+#include "SaRegs.h"
+
+///
+/// SystemAgent Base Address definition
+///
+#ifndef STALL_ONE_MICRO_SECOND
+#define STALL_ONE_MICRO_SECOND 1
+#endif
+#ifndef STALL_ONE_MILLI_SECOND
+#define STALL_ONE_MILLI_SECOND 1000
+#endif
+
+//
+// SA PCI Express* Port configuration
+//
+#define SA_PEG_BUS_NUM 0x00
+#define SA_PEG_DEV_NUM 0x01
+#define SA_PEG10_DEV_NUM SA_PEG_DEV_NUM
+#define SA_PEG10_FUN_NUM 0x00
+#define SA_PEG11_DEV_NUM SA_PEG_DEV_NUM
+#define SA_PEG11_FUN_NUM 0x01
+#define SA_PEG12_DEV_NUM SA_PEG_DEV_NUM
+#define SA_PEG12_FUN_NUM 0x02
+#define SA_PEG_MAX_FUN 0x03
+
+///
+/// SgMode settings
+///
+typedef enum {
+ SgModeDisabled = 0,
+ SgModeReserved,
+ SgModeMuxless,
+ SgModeDgpu,
+ SgModeMax
+} SG_MODE;
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.h new file mode 100644 index 0000000000..bfe6011763 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.h @@ -0,0 +1,40 @@ +/** @file
+ Main System Agent Policy structure definition which will contain several config blocks during runtime.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_POLICY_COMMON_H_
+#define _SA_POLICY_COMMON_H_
+
+#include <Uefi.h>
+#include <Library/SmbusLib.h>
+#include <SaAccess.h>
+#include <ConfigBlock.h>
+#include <Library/ConfigBlockLib.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+#include <ConfigBlock/GraphicsPeiConfig.h>
+#include <ConfigBlock/VtdConfig.h>
+
+
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gSiPolicyPpiGuid;
+extern EFI_GUID gSiPreMemPolicyPpiGuid;
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+extern EFI_GUID gGraphicsPeiConfigGuid;
+extern EFI_GUID gVtdConfigGuid;
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#endif // _SA_POLICY_COMMON_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaRegs.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaRegs.h new file mode 100644 index 0000000000..5f92981f4b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Include/SaRegs.h @@ -0,0 +1,787 @@ +/** @file
+ Register names for System Agent (SA) registers
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_REGS_H_
+#define _SA_REGS_H_
+
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define V_SA_MC_VID 0x8086
+#define R_SA_MC_DEVICE_ID 0x02
+#define R_SA_MC_CAPID0_B 0xE8
+
+//
+// Macros that judge which type a device ID belongs to
+//
+
+//
+// CPU Mobile SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_SKL_MB_ULT_1 0x1904 ///< Skylake Ult (OPI) (2+1F/1.5F/2F/3/3E) Mobile SA DID
+#define V_SA_DEVICE_ID_SKL_MB_ULX_2 0x190C ///< Skylake Ulx (OPI) (2+1F/1.5F/2) SA DID
+#define V_SA_DEVICE_ID_SKL_MB_ULX_3 0x1924 ///< Skylake Ulx (OPI)
+//
+// CPU Halo SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_SKL_HALO_1 0x1900 ///< Skylake Halo (2+2/1) SA DID
+#define V_SA_DEVICE_ID_SKL_HALO_2 0x1910 ///< Skylake Halo (4+2/4E/3FE) SA DID
+#define V_SA_DEVICE_ID_SKL_HALO_3 0x1918 ///< Skylake Halo (4+3E/4E) Embedded SA DID
+//
+// CPU Desktop SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_SKL_DT_1 0x190F ///< Skylake Desktop (2+1F/1.5F/2) SA DID
+#define V_SA_DEVICE_ID_SKL_DT_2 0x191F ///< Skylake Desktop (4+2/4) SA DID
+//
+// CPU Server SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_SKL_SVR_1 0x1908 ///< Skylake Server (2+2/3E) SA DID
+#define V_SA_DEVICE_ID_SKL_SVR_2 0x1918 ///< Skylake Server (4+1/2/4E) SA DID
+
+//
+// KabyLake CPU Mobile SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_KBL_MB_ULT_1 0x5904 ///< Kabylake Ult (OPI) (2+1F/1.5F/2F/3/3E) Mobile SA DID
+#define V_SA_DEVICE_ID_KBLR_MB_ULT_1 0x5914 ///< Kabylake-R Ult Mobile SA DID
+#define V_SA_DEVICE_ID_KBL_MB_ULX_1 0x590C ///< Kabylake Ulx (OPI) (2+1F/1.5F/2) SA DID
+//
+// KabyLake CPU Halo SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_KBL_HALO_1 0x5900 ///< Kabylake Halo (2+2/1) SA DID
+#define V_SA_DEVICE_ID_KBL_HALO_2 0x5910 ///< Kabylake Halo (4+2/4E/3FE) SA DID
+//
+// KabyLake CPU Desktop SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_KBL_DT_1 0x590F ///< Kabylake Desktop (2+1F/1.5F/2) SA DID
+#define V_SA_DEVICE_ID_KBL_DT_2 0x591F ///< Kabylake Desktop (4+1.5F/2/4) SA DID
+//
+// KabyLake CPU Server SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_KBL_SVR_1 0x5908 ///< Kabylake Server (2+2/3E) SA DID
+#define V_SA_DEVICE_ID_KBL_SVR_2 0x5918 ///< Kabylake Server (4+1/2/4E) SA DID
+//
+// CoffeeLake CPU Desktop SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_CFL_DT 0x3EC2 ///< CoffeeLake Desktop (6+2) SA DID
+
+///
+/// Device IDs that are Mobile specific B0:D0:F0
+///
+#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \
+ ( \
+ (DeviceId == V_SA_DEVICE_ID_SKL_MB_ULT_1) || \
+ (DeviceId == V_SA_DEVICE_ID_SKL_MB_ULX_2) || \
+ (DeviceId == V_SA_DEVICE_ID_SKL_MB_ULX_3) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_MB_ULT_1) || \
+ (DeviceId == V_SA_DEVICE_ID_KBLR_MB_ULT_1) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_MB_ULX_1) \
+ )
+
+///
+/// Device IDs that are Desktop specific B0:D0:F0
+///
+#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \
+ ( \
+ (DeviceId == V_SA_DEVICE_ID_SKL_DT_1) || \
+ (DeviceId == V_SA_DEVICE_ID_SKL_DT_2) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_DT_1) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_DT_2) || \
+ (DeviceId == V_SA_DEVICE_ID_CFL_DT) \
+ )
+
+///
+/// Device IDS that are Server specific B0:D0:F0
+///
+#define IS_SA_DEVICE_ID_SERVER(DeviceId) \
+ ( \
+ (DeviceId == V_SA_DEVICE_ID_SKL_SVR_1) || \
+ (DeviceId == V_SA_DEVICE_ID_SKL_SVR_2) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_SVR_1) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_SVR_2) \
+ )
+
+///
+/// Device IDs that are Halo specific B0:D0:F0
+///
+#define IS_SA_DEVICE_ID_HALO(DeviceId) \
+ ( \
+ (DeviceId == V_SA_DEVICE_ID_SKL_HALO_1) || \
+ (DeviceId == V_SA_DEVICE_ID_SKL_HALO_2) || \
+ (DeviceId == V_SA_DEVICE_ID_SKL_HALO_3) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_HALO_1) || \
+ (DeviceId == V_SA_DEVICE_ID_KBL_HALO_2) \
+ )
+
+/**
+ <b>Description</b>:
+ This is the base address for the PCI Express Egress Port MMIO Configuration space. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
+ All the bits in this register are locked in LT mode.
+**/
+#define R_SA_PXPEPBAR (0x40)
+//
+// Description of PXPEPBAREN (0:0)
+// - 0: PXPEPBAR is disabled and does not claim any memory
+// - 1: PXPEPBAR memory mapped accesses are claimed and decoded appropriately
+// - This register is locked by LT.
+//
+#define N_SA_PXPEPBAR_PXPEPBAREN_OFFSET (0x0)
+#define S_SA_PXPEPBAR_PXPEPBAREN_WIDTH (0x1)
+#define B_SA_PXPEPBAR_PXPEPBAREN_MASK (0x1)
+#define V_SA_PXPEPBAR_PXPEPBAREN_DEFAULT (0x0)
+//
+// Description of PXPEPBAR (12:38)
+// - This field corresponds to bits 38 to 12 of the base address PCI Express Egress Port MMIO configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the PCI Express Egress Port MMIO register set. All the bits in this register are locked in LT mode.
+//
+#define N_SA_PXPEPBAR_PXPEPBAR_OFFSET (0xc)
+#define S_SA_PXPEPBAR_PXPEPBAR_WIDTH (0x1b)
+#define B_SA_PXPEPBAR_PXPEPBAR_MASK (0x7ffffff000)
+#define V_SA_PXPEPBAR_PXPEPBAR_DEFAULT (0x0)
+
+/**
+ <b>Description</b>:
+ - This is the base address for the Host Memory Mapped Configuration space. There is no physical memory within this 32KB window that can be addressed. The 32KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Host MMIO Memory Mapped Configuation space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0].
+ - All the bits in this register are locked in LT mode.
+ - The register space contains memory control, initialization, timing, and buffer strength registers; clocking registers; and power and thermal management registers.
+**/
+#define R_SA_MCHBAR (0x48)
+/**
+ Description of MCHBAREN (0:0)
+ - 0: MCHBAR is disabled and does not claim any memory
+ - 1: MCHBAR memory mapped accesses are claimed and decoded appropriately
+ - This register is locked by LT.
+**/
+#define N_SA_MCHBAR_MCHBAREN_OFFSET (0x0)
+#define S_SA_MCHBAR_MCHBAREN_WIDTH (0x1)
+#define B_SA_MCHBAR_MCHBAREN_MASK (0x1)
+#define V_SA_MCHBAR_MCHBAREN_DEFAULT (0x0)
+/**
+ Description of MCHBAR (15:38)
+ - This field corresponds to bits 38 to 15 of the base address Host Memory Mapped configuration space. BIOS will program this register resulting in a base address for a 32KB block of contiguous memory address space. This register ensures that a naturally aligned 32KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the Host Memory Mapped register set. All the bits in this register are locked in LT mode.
+**/
+#define N_SA_MCHBAR_MCHBAR_OFFSET (0xf)
+#define S_SA_MCHBAR_MCHBAR_WIDTH (0x18)
+#define B_SA_MCHBAR_MCHBAR_MASK (0x7fffff8000ULL)
+#define V_SA_MCHBAR_MCHBAR_DEFAULT (0x0)
+
+/**
+ <b>Description</b>:
+ - All the bits in this register are LT lockable.
+**/
+#define R_SA_GGC (0x50)
+/**
+ Description of GGCLCK (0:0)
+ - When set to 1b, this bit will lock all bits in this register.
+**/
+#define N_SA_GGC_GGCLCK_OFFSET (0x0)
+#define S_SA_GGC_GGCLCK_WIDTH (0x1)
+#define B_SA_GGC_GGCLCK_MASK (0x1)
+#define V_SA_GGC_GGCLCK_DEFAULT (0x0)
+/**
+ Description of IVD (1:1)
+ - 0: Enable. Device 2 (IGD) claims VGA memory and IO cycles, the Sub-Class Code within Device 2 Class Code register is 00.
+ - 1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO), and the Sub- Class Code field within Device 2 function 0 Class Code register is 80.
+ - BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 7:3 of this register) pre-allocates no memory.
+ - This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override (CAPID0[46] = 1) or via a register (DEVEN[3] = 0).
+ - This register is locked by LT lock.
+**/
+#define N_SA_GGC_IVD_OFFSET (0x1)
+#define S_SA_GGC_IVD_WIDTH (0x1)
+#define B_SA_GGC_IVD_MASK (0x2)
+#define V_SA_GGC_IVD_DEFAULT (0x0)
+/**
+ For SKL
+ Description of GMS (8:15)
+ - This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
+ - This register is also LT lockable.
+ - Valid options are 0 (0x0) to 2048MB (0x40) in multiples of 32 MB
+ - Default is 64MB
+ - All other values are reserved
+ - Hardware does not clear or set any of these bits automatically based on IGD being disabled/enabled.
+ - BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this register) is 0.
+**/
+#define N_SKL_SA_GGC_GMS_OFFSET (0x8)
+#define S_SKL_SA_GGC_GMS_WIDTH (0x8)
+#define B_SKL_SA_GGC_GMS_MASK (0xff00)
+#define V_SKL_SA_GGC_GMS_DEFAULT (0x01)
+
+/**
+ For SKL
+ Description of GGMS (6:7)
+ - This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.
+ - GSM is assumed to be a contiguous physical DRAM space with DSM, and BIOS needs to allocate a contiguous memory chunk. Hardware will derive the base of GSM from DSM only using the GSM size programmed in the register.
+ - Valid options:
+ - 0h: 0 MB of memory pre-allocated for GTT.
+ - 1h: 2 MB of memory pre-allocated for GTT.
+ - 2h: 4 MB of memory pre-allocated for GTT. (default)
+ - 3h: 8 MB of memory pre-allocated for GTT.
+ - Others: Reserved
+ - Hardware functionality in case of programming this value to Reserved is not guaranteed.
+**/
+#define N_SKL_SA_GGC_GGMS_OFFSET (0x6)
+#define S_SKL_SA_GGC_GGMS_WIDTH (0x2)
+#define B_SKL_SA_GGC_GGMS_MASK (0xc0)
+#define V_SKL_SA_GGC_GGMS_DEFAULT (2)
+#define V_SKL_SA_GGC_GGMS_DIS 0
+#define V_SKL_SA_GGC_GGMS_2MB 1
+#define V_SKL_SA_GGC_GGMS_4MB 2
+#define V_SKL_SA_GGC_GGMS_8MB 3
+
+/**
+ Description:
+ - Allows for enabling/disabling of PCI devices and functions that are within the CPU package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register.
+ All the bits in this register are LT Lockable.
+**/
+#define R_SA_DEVEN (0x54)
+#define B_SA_DEVEN_D2EN_MASK (0x10)
+
+/**
+ Description
+ - Protected Audio Video Path Control
+ - All the bits in this register are locked by LT. When locked the R/W bits are RO.
+**/
+#define R_SA_PAVPC (0x58)
+/**
+ Description of PCME (0:0)
+ - This field enables Protected Content Memory within Graphics Stolen Memory.
+ - This register is locked (becomes read-only) when PAVPLCK = 1b.
+ - This register is read-only (stays at 0b) when PAVP fuse is set to "disabled"
+ - 0: Protected Content Memory is disabled
+ - 1: Protected Content Memory is enabled
+**/
+#define N_SA_PAVPC_PCME_OFFSET (0x0)
+#define S_SA_PAVPC_PCME_WIDTH (0x1)
+#define B_SA_PAVPC_PCME_MASK (0x1)
+#define V_SA_PAVPC_PCME_MASK (0x0)
+/**
+ Description of PAVPE (1:1)
+ - 0: PAVP path is disabled
+ - 1: PAVP path is enabled
+ - This register is locked (becomes read-only) when PAVPLCK = 1b
+ - This register is read-only (stays at 0b) when PAVP capability is set to "disabled" as defined by CAPID0_B[PAVPE].
+**/
+#define N_SA_PAVPC_PAVPE_OFFSET (0x1)
+#define S_SA_PAVPC_PAVPE_WIDTH (0x1)
+#define B_SA_PAVPC_PAVPE_MASK (0x2)
+#define V_SA_PAVPC_PAVPE_DEFAULT (0x0)
+/**
+ Description of PAVPLCK (2:2)
+ - This bit will lock all writeable contents in this register when set (including itself).
+ - This bit will be locked if PAVP is fused off.
+**/
+#define N_SA_PAVPC_PAVPLCK_OFFSET (0x2)
+#define S_SA_PAVPC_PAVPLCK_WIDTH (0x1)
+#define B_SA_PAVPC_PAVPLCK_MASK (0x4)
+#define V_SA_PAVPC_PAVPLCK_DEFAULT (0x0)
+/**
+ Description of PCMBASE (20:31)
+ - This field is used to set the base of Protected Content Memory.
+ - This corresponds to bits 31:20 of the system memory address range, giving a 1MB granularity. This value MUST be at least 1MB above the base and below the top of stolen memory.
+ - This register is locked (becomes read-only) when PAVPE = 1b.
+**/
+#define N_SA_PAVPC_PCMBASE_OFFSET (0x14)
+#define S_SA_PAVPC_PCMBASE_WIDTH (0xc)
+#define B_SA_PAVPC_PCMBASE_MASK (0xfff00000)
+#define V_SA_PAVPC_PCMBASE_DEFAULT (0x0)
+
+#define R_SA_DPR (0x5c) ///< DMA protected range register
+/**
+ Description of LOCK (0:0)
+ - This bit will lock all writeable settings in this register, including itself.
+**/
+#define N_SA_DPR_LOCK_OFFSET (0x0)
+#define S_SA_DPR_LOCK_WIDTH (0x1)
+#define B_SA_DPR_LOCK_MASK (0x1)
+#define V_SA_DPR_LOCK_DEFAULT (0x0)
+/**
+ Description of PRS (1:1)
+ - This field indicates the status of DPR.
+ - 0: DPR protection disabled
+ - 1: DPR protection enabled
+**/
+#define N_SA_DPR_PRS_OFFSET (0x1)
+#define S_SA_DPR_PRS_WIDTH (0x1)
+#define B_SA_DPR_PRS_MASK (0x2)
+#define V_SA_DPR_PRS_DEFAULT (0x0)
+/**
+ Description of EPM (2:2)
+ - This field controls DMA accesses to the DMA Protected Range (DPR) region.
+ - 0: DPR is disabled
+ - 1: DPR is enabled. All DMA requests accessing DPR region are blocked.
+ - HW reports the status of DPR enable/disable through the PRS field in this register.
+**/
+#define N_SA_DPR_EPM_OFFSET (0x2)
+#define S_SA_DPR_EPM_WIDTH (0x1)
+#define B_SA_DPR_EPM_MASK (0x4)
+#define V_SA_DPR_EPM_DEFAULT (0x0)
+/**
+ Description of DPRSIZE (11:4)
+ - This field is used to specify the size of memory protected from DMA access in MB
+ - The maximum amount of memory that will be protected is 255MB
+ - The Top of protected range is the base of TSEG-1
+**/
+#define N_DPR_DPRSIZE_OFFSET (0x4)
+#define V_DPR_DPRSIZE_WIDTH (0x8)
+#define V_DPR_DPRSIZE_MASK (0xFF0)
+#define V_DPR_DPRSIZE_DEFAULT (0x0)
+/**
+ Description of TOPOFDPR (31:20)
+ - This is the Top address 1 of DPR - Base of TSEG
+**/
+#define N_SA_DPR_TOPOFDPR_OFFSET (20)
+#define S_SA_DPR_TOPOFDPR_WIDTH (0xC)
+#define B_SA_DPR_TOPOFDPR_MASK (0xFFF00000)
+#define V_SA_DPR_TOPOFDPR_DEFAULT (0x0)
+
+/**
+ This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0] All the bits in this register are locked in LT mode.
+**/
+#define R_SA_DMIBAR (0x68)
+/**
+ Description of DMIBAREN (0:0)
+ - 0: DMIBAR is disabled and does not claim any memory
+ - 1: DMIBAR memory mapped accesses are claimed and decoded appropriately
+ - This register is locked by LT.
+**/
+#define N_SA_DMIBAR_DMIBAREN_OFFSET (0x0)
+#define S_SA_DMIBAR_DMIBAREN_WIDTH (0x1)
+#define B_SA_DMIBAR_DMIBAREN_MASK (0x1)
+#define V_SA_DMIBAR_DMIBAREN_DEFAULT (0x0)
+/**
+ Description of DMIBAR (12:38)
+ - This field corresponds to bits 38 to 12 of the base address DMI configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the DMI register set. All the Bits in this register are locked in LT mode.
+**/
+#define N_SA_DMIBAR_DMIBAR_OFFSET (0xc)
+#define S_SA_DMIBAR_DMIBAR_WIDTH (0x1b)
+#define B_SA_DMIBAR_DMIBAR_MASK (0x7ffffff000)
+#define V_SA_DMIBAR_DMIBAR_DEFAULT (0x0)
+
+/**
+ Description:
+ - This register determines the Mask Address register of the memory range that is pre-allocated to the Manageability Engine. Together with the MESEG_BASE register it controls the amount of memory allocated to the ME.
+ - This register is locked by LT.
+**/
+#define R_SA_MESEG_MASK (0x78)
+/**
+ Description of MELCK (10:10)
+ - This field indicates whether all bits in the MESEG_BASE and MESEG_MASK registers are locked. When locked, updates to any field for these registers must be dropped.
+**/
+#define N_SA_MESEG_MASK_MELCK_OFFSET (0xa)
+#define S_SA_MESEG_MASK_MELCK_WIDTH (0x1)
+#define B_SA_MESEG_MASK_MELCK_MASK (0x400)
+#define V_SA_MESEG_MASK_MELCK_DEFAULT (0x0)
+/**
+ Description of ME_STLEN_EN (11:11)
+ - Indicates whether the ME stolen Memory range is enabled or not.
+**/
+#define N_SA_MESEG_MASK_ME_STLEN_EN_OFFSET (0xb)
+#define S_SA_MESEG_MASK_ME_STLEN_EN_WIDTH (0x1)
+#define V_SA_MESEG_MASK_ME_STLEN_EN_DEFAULT (0x0)
+#define B_SA_MESEG_MASK_ME_STLEN_EN_MASK (0x800)
+/**
+ Description of MEMASK (20:38)
+ - This field indicates the bits that must match MEBASE in order to qualify as an ME Memory Range access.
+ - For example, if the field is set to 7FFFFh, then ME Memory is 1MB in size.
+ - Another example is that if the field is set to 7FFFEh, then ME Memory is 2MB in size.
+ - In other words, the size of ME Memory Range is limited to power of 2 times 1MB.
+**/
+#define N_SA_MESEG_MASK_MEMASK_OFFSET (0x14)
+#define S_SA_MESEG_MASK_MEMASK_WIDTH (0x13)
+#define V_SA_MESEG_MASK_MEMASK_DEFAULT (0x0)
+#define B_SA_MESEG_MASK_MEMASK_MASK (0x7ffff00000)
+/**
+ Description:
+ - This register controls the read, write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core.
+ - Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are:
+ - RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI.
+ - WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI.
+ - The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+**/
+#define R_SA_PAM0 (0x80)
+///
+/// Description:
+/// This register controls the read, write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core.
+/// Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are:
+/// RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI.
+/// WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI.
+/// The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM5 (0x85)
+///
+/// Description:
+/// This register controls the read, write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core.
+/// Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are:
+/// RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI.
+/// WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI.
+/// The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only.
+///
+#define R_SA_PAM6 (0x86)
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+#define B_SA_SMRAMC_D_LCK_MASK (0x10)
+#define B_SA_SMRAMC_D_CLS_MASK (0x20)
+#define B_SA_SMRAMC_D_OPEN_MASK (0x40)
+///
+/// Description:
+///
+#define R_SA_REMAPBASE (0x90)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_REMAPBASE_LOCK_OFFSET (0x0)
+#define S_SA_REMAPBASE_LOCK_WIDTH (0x1)
+#define B_SA_REMAPBASE_LOCK_MASK (0x1)
+#define V_SA_REMAPBASE_LOCK_DEFAULT (0x0)
+///
+/// Description of REMAPBASE (20:38)
+/// The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[19:0] of the Remap Base Address are assumed to be 0's. Thus the bottom of the defined memory range will be aligned to a 1MB boundary.
+/// When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled.
+/// These bits are LT lockable.
+///
+#define N_SA_REMAPBASE_REMAPBASE_OFFSET (0x14)
+#define S_SA_REMAPBASE_REMAPBASE_WIDTH (0x13)
+#define V_SA_REMAPBASE_REMAPBASE_DEFAULT (0x7ffff00000)
+#define B_SA_REMAPBASE_REMAPBASE_MASK (0x7ffff00000)
+
+///
+/// Description:
+///
+#define R_SA_REMAPLIMIT (0x98)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_REMAPLIMIT_LOCK_OFFSET (0x0)
+#define S_SA_REMAPLIMIT_LOCK_WIDTH (0x1)
+#define B_SA_REMAPLIMIT_LOCK_MASK (0x1)
+#define V_SA_REMAPLIMIT_LOCK_DEFAULT (0x0)
+///
+/// Description of REMAPLMT (20:38)
+/// The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[19:0] of the remap limit address are assumed to be F's. Thus the top of the defined range will be one byte less than a 1MB boundary.
+/// When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled.
+/// These Bits are LT lockable.
+///
+#define N_SA_REMAPLIMIT_REMAPLMT_OFFSET (0x14)
+#define S_SA_REMAPLIMIT_REMAPLMT_WIDTH (0x13)
+#define V_SA_REMAPLIMIT_REMAPLMT_DEFAULT (0x0)
+#define B_SA_REMAPLIMIT_REMAPLMT_MASK (0x7ffff00000)
+
+///
+/// Description:
+/// This Register contains the size of physical memory. BIOS determines the memory size reported to the OS using this Register.
+///
+#define R_SA_TOM (0xa0)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TOM_LOCK_OFFSET (0x0)
+#define S_SA_TOM_LOCK_WIDTH (0x1)
+#define B_SA_TOM_LOCK_MASK (0x1)
+#define V_SA_TOM_LOCK_DEFAULT (0x0)
+
+///
+/// Description of TOM (20:38)
+/// This register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped IO). These bits correspond to address bits 38:20 (1MB granularity). Bits 19:0 are assumed to be 0. All the bits in this register are locked in LT mode.
+///
+#define N_SA_TOM_TOM_OFFSET (0x14)
+#define S_SA_TOM_TOM_WIDTH (0x13)
+#define B_SA_TOM_TOM_MASK (0x7ffff00000)
+#define V_SA_TOM_TOM_DEFAULT (0x7ffff00000)
+
+///
+/// Description:
+/// This 64 bit register defines the Top of Upper Usable DRAM.
+/// Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1byte, 1MB aligned, since reclaim limit is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4GB.
+/// BIOS Restriction: Minimum value for TOUUD is 4GB.
+/// These bits are LT lockable.
+///
+#define R_SA_TOUUD (0xa8)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TOUUD_LOCK_OFFSET (0x0)
+#define S_SA_TOUUD_LOCK_WIDTH (0x1)
+#define B_SA_TOUUD_LOCK_MASK (0x1)
+#define V_SA_TOUUD_LOCK_DEFAULT (0x0)
+///
+/// Description of TOUUD (20:38)
+/// This register contains bits 38 to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system. Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit 1MB aligned since reclaim limit + 1byte is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4GB.
+/// All the bits in this register are locked in LT mode.
+///
+#define N_SA_TOUUD_TOUUD_OFFSET (0x14)
+#define S_SA_TOUUD_TOUUD_WIDTH (0x13)
+#define B_SA_TOUUD_TOUUD_MASK (0x7ffff00000ULL)
+#define V_SA_TOUUD_TOUUD_DEFAULT (0x0)
+
+///
+/// Description:
+/// This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20).
+///
+#define R_SA_BDSM (0xb0)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_BDSM_LOCK_OFFSET (0x0)
+#define S_SA_BDSM_LOCK_WIDTH (0x1)
+#define B_SA_BDSM_LOCK_MASK (0x1)
+#define V_SA_BDSM_LOCK_DEFAULT (0x0)
+///
+/// Description of BDSM (20:31)
+/// This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 52 bits 6:4) from TOLUD (PCI Device 0 offset BC bits 31:20).
+///
+#define N_SA_BDSM_BDSM_OFFSET (0x14)
+#define S_SA_BDSM_BDSM_WIDTH (0xc)
+#define B_SA_BDSM_BDSM_MASK (0xfff00000)
+#define V_SA_BDSM_BDSM_DEFAULT (0x0)
+
+///
+/// Description:
+/// This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
+///
+#define R_SA_BGSM (0xb4)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_BGSM_LOCK_OFFSET (0x0)
+#define S_SA_BGSM_LOCK_WIDTH (0x1)
+#define B_SA_BGSM_LOCK_MASK (0x1)
+#define V_SA_BGSM_LOCK_DEFAULT (0x0)
+///
+/// Description of BGSM (20:31)
+/// This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 11:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).
+///
+#define N_SA_BGSM_BGSM_OFFSET (0x14)
+#define S_SA_BGSM_BGSM_WIDTH (0xc)
+#define B_SA_BGSM_BGSM_MASK (0xfff00000)
+#define V_SA_BGSM_BGSM_DEFAULT (0x0)
+
+///
+/// Description:
+/// This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
+///
+#define R_SA_TSEGMB (0xb8)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TSEGMB_LOCK_OFFSET (0x0)
+#define S_SA_TSEGMB_LOCK_WIDTH (0x1)
+#define B_SA_TSEGMB_LOCK_MASK (0x1)
+#define V_SA_TSEGMB_LOCK_DEFAULT (0x0)
+///
+/// Description of TSEGMB (20:31)
+/// This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20).
+///
+#define N_SA_TSEGMB_TSEGMB_OFFSET (0x14)
+#define S_SA_TSEGMB_TSEGMB_WIDTH (0xc)
+#define B_SA_TSEGMB_TSEGMB_MASK (0xfff00000)
+#define V_SA_TSEGMB_TSEGMB_DEFAULT (0x0)
+
+///
+/// Description:
+/// This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of LOCK (0:0)
+/// This bit will lock all writeable settings in this register, including itself.
+///
+#define N_SA_TOLUD_LOCK_OFFSET (0x0)
+#define S_SA_TOLUD_LOCK_WIDTH (0x1)
+#define B_SA_TOLUD_LOCK_MASK (0x1)
+#define V_SA_TOLUD_LOCK_DEFAULT (0x0)
+///
+/// Description of TOLUD (20:31)
+/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+/// This register must be 1MB aligned when reclaim is enabled.
+///
+#define N_SA_TOLUD_TOLUD_OFFSET (0x14)
+#define S_SA_TOLUD_TOLUD_WIDTH (0xc)
+#define V_SA_TOLUD_TOLUD_DEFAULT (0x100000)
+#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)
+
+#define R_SA_MC_CAPID0_A_OFFSET 0xE4
+
+#define R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET 0x5DA8
+//
+// Thermal Management Controls
+//
+///
+/// Device 2 Register Equates
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define SA_IGD_BUS 0x00
+#define SA_IGD_DEV 0x02
+#define SA_IGD_FUN_0 0x00
+#define SA_IGD_FUN_1 0x01
+#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3)
+#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN
+#define V_SA_IGD_VID 0x8086
+#define SA_GT_APERTURE_SIZE_256MB 1 ///< 256MB is the recommanded GT Aperture Size as per BWG.
+
+///
+/// For SKL IGD
+///
+#define V_SA_PCI_DEV_2_GT1_SULTM_ID 0x01906 ///< Dev2-SKL ULT GT1 (2+1F) Mobile
+#define V_SA_PCI_DEV_2_GT15F_SULTM_ID 0x01913 ///< Dev2-SKL ULT GT1.5 (2+1.5F) Mobile
+#define V_SA_PCI_DEV_2_GT2_SULTM_ID 0x01916 ///< Dev2-SKL ULT GT2 (2+2) Mobile
+#define V_SA_PCI_DEV_2_GT2F_SULTM_ID 0x01921 ///< Dev2-SKL ULT GT2 (2+2F) Mobile
+#define V_SA_PCI_DEV_2_GT3_SULTM_ID 0x01926 ///< Dev2-SKL ULT GT3 (3+3/3E) Mobile
+#define V_SA_PCI_DEV_2_GT1_SHALM_ID 0x0190B ///< Dev2-SKL Halo GT1 (2+1)
+#define V_SA_PCI_DEV_2_GT2_SHALM_ID 0x0191B ///< Dev2-SKL Halo GT2 (4/2+2)
+#define V_SA_PCI_DEV_2_GT3_SHALM_ID 0x0192B ///< Dev2-SKL Halo GT3 (4+3FE)
+#define V_SA_PCI_DEV_2_GT4_SHALM_ID 0x0193B ///< Dev2-SKL Halo GT4 (4+4E)
+#define V_SA_PCI_DEV_2_GT3_SHALM_EMB_ID 0x0192D ///< Dev2-SKL Halo GT3 (4+3E) Embedded
+#define V_SA_PCI_DEV_2_GT4_SHALM_EMB_ID 0x0193D ///< Dev2-SKL Halo GT4 (4+4E) Embedded
+#define V_SA_PCI_DEV_2_GT1_SULXM_ID 0x0190E ///< Dev2-SKL ULX GT1(2+1F) Mobile
+#define V_SA_PCI_DEV_2_GT15_SULXM_ID 0x01915 ///< Dev2-SKL ULX GT1.5(2+1.5F) Mobile
+#define V_SA_PCI_DEV_2_GT2_SULXM_ID 0x0191E ///< Dev2-SKL ULX GT2 (2+2)Mobile
+#define V_SA_PCI_DEV_2_GT1_SSR_ID 0x0190A ///< Dev2-SKL GT1 (4+1F) Server
+#define V_SA_PCI_DEV_2_GT2_SSR_ID 0x0191A ///< Dev2-SKL GT2 (4/2+2) Server
+#define V_SA_PCI_DEV_2_GT3_SSR_ID 0x0192A ///< Dev2-SKL GT3 (2+3E) Server
+#define V_SA_PCI_DEV_2_GT4_SSR_ID 0x0193A ///< Dev2-SKL GT4 (4+4E) Server
+#define V_SA_PCI_DEV_2_GT1_SDT_ID 0x01902 ///< Dev2-SKL GT1 (2+1F) Desktop
+#define V_SA_PCI_DEV_2_GT2_SDT_ID 0x01912 ///< Dev2-SKL GT2 (4/2+2) Desktop
+#define V_SA_PCI_DEV_2_GT15_SDT_ID 0x01917 ///< Dev2-SKL GT1.5 (2+1.5F) Desktop
+#define V_SA_PCI_DEV_2_GT4_SDT_ID 0x01932 ///< Dev2-SKL GT4 (4+4E) Desktop
+///
+/// For KBL IGD
+///
+#define V_SA_PCI_DEV_2_GT1_KULTM_ID 0x05906 ///< Dev2-KBL ULT GT1 (2+1F) Mobile
+#define V_SA_PCI_DEV_2_GT15F_KULTM_ID 0x05913 ///< Dev2-KBL ULT GT1.5 (2+1.5F) Mobile
+#define V_SA_PCI_DEV_2_GT2_KULTM_ID 0x05916 ///< Dev2-KBL ULT GT2 (2+2) Mobile
+#define V_SA_PCI_DEV_2_GT2F_KULTM_ID 0x05921 ///< Dev2-KBL ULT GT2 (2+2F) Mobile
+#define V_SA_PCI_DEV_2_GT3_KULTM_ID 0x05926 ///< Dev2-KBL ULT GT3 (3+3/3E) Mobile
+#define V_SA_PCI_DEV_2_GT3E_KULTM_ID 0x05927 ///< Dev2-KBL ULT GT3 (2+3/3E) Mobile
+#define V_SA_PCI_DEV_2_GT1_KHALM_ID 0x0590B ///< Dev2-KBL Halo GT1 (2+1)
+#define V_SA_PCI_DEV_2_GT2_KHALM_ID 0x0591B ///< Dev2-KBL Halo GT2 (4/2+2)
+#define V_SA_PCI_DEV_2_GT3_KHALM_ID 0x0592B ///< Dev2-KBL Halo GT3 (4+3FE)
+#define V_SA_PCI_DEV_2_GT4_KHALM_ID 0x0593B ///< Dev2-KBL Halo GT4 (4+4E)
+#define V_SA_PCI_DEV_2_GT1_KULXM_ID 0x0590E ///< Dev2-KBL ULX GT1(2+1F) Mobile
+#define V_SA_PCI_DEV_2_GT15_KULXM_ID 0x05915 ///< Dev2-KBL ULX GT1.5(2+1.5F) Mobile
+#define V_SA_PCI_DEV_2_GT2_KULXM_ID 0x0591E ///< Dev2-KBL ULX GT2 (2+2)Mobile
+#define V_SA_PCI_DEV_2_GT1_KSR_ID 0x0590A ///< Dev2-KBL GT1 (4+1F) Server
+#define V_SA_PCI_DEV_2_GT2_KSR_ID 0x0591A ///< Dev2-KBL GT2 (4/2+2) Server
+#define V_SA_PCI_DEV_2_GT3_KSR_ID 0x0592A ///< Dev2-KBL GT3 (2+3E) Server
+#define V_SA_PCI_DEV_2_GT4_KSR_ID 0x0593A ///< Dev2-KBL GT4 (4+4E) Server
+#define V_SA_PCI_DEV_2_GT1_KDT_ID 0x05902 ///< Dev2-KBL GT1 (2+1F) Desktop
+#define V_SA_PCI_DEV_2_GT2_KDT_ID 0x05912 ///< Dev2-KBL GT2 (4/2+2) Desktop
+#define V_SA_PCI_DEV_2_GT15_KDT_ID 0x05917 ///< Dev2-KBL GT1.5 (2+1.5F) Desktop
+#define V_SA_PCI_DEV_2_GT4_KDT_ID 0x05932 ///< Dev2-KBL GT4 (4+4E) Desktop
+#define V_SA_PCI_DEV_2_GT2_KWKS_ID 0x0591D ///< Dev2-KBL GT2 (4+2) WorkStation
+#define V_SA_PCI_DEV_2_GT4_KWKS_ID 0x0593D ///< Dev2-KBL GT4 (4+4E) WorkStation
+///
+/// For CFL IGD
+///
+#define V_SA_PCI_DEV_2_GT2_CDT_ID 0x03E92 ///< Dev2-CFL GT2 (6+2) Desktop
+
+#define R_SA_IGD_VID 0x00
+#define R_SA_IGD_DID 0x02
+#define R_SA_IGD_CMD 0x04
+
+///
+/// GTTMMADR for SKL is 16MB alignment (Base address = [38:24])
+///
+#define R_SA_IGD_GTTMMADR 0x10
+#define R_SA_IGD_GMADR 0x18
+#define R_SA_IGD_IOBAR 0x20
+#define R_SA_IGD_BSM_OFFSET 0x005C ///< Base of Stolen Memory
+#define R_SA_IGD_MSAC_OFFSET 0x0062 ///< Multisize Aperture Control
+#define R_SA_IGD_SWSCI_OFFSET 0x00E8
+#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage
+///
+/// Maximum number of SDRAM channels supported by the memory controller
+///
+///
+/// Maximum number of SDRAM channels supported by the memory controller
+///
+#define SA_MC_MAX_CHANNELS 2
+///
+/// Maximum number of DIMM sockets supported by each channel
+///
+#define SA_MC_MAX_SLOTS 2
+
+///
+/// Maximum number of sides supported per DIMM
+///
+#define SA_MC_MAX_SIDES 2
+
+///
+/// Maximum number of DIMM sockets supported by the memory controller
+///
+#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS)
+
+///
+/// Maximum number of rows supported by the memory controller
+///
+#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES)
+
+///
+/// Maximum number of rows supported by the memory controller
+///
+#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS)
+
+///
+/// Maximum memory supported by the memory controller
+/// 4 GB in terms of KB
+///
+#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024)
+
+///
+/// Define the SPD Address for DIMM 0
+///
+#define SA_MC_DIMM0_SPD_ADDRESS 0xA0
+
+///
+/// Define the maximum number of data bytes on a system with no ECC memory support.
+///
+#define SA_MC_MAX_BYTES_NO_ECC (8)
+
+///
+/// Define the maximum number of SPD data bytes on a DIMM.
+///
+#define SA_MC_MAX_SPD_SIZE (512)
+
+///
+/// Vt-d Engine base address.
+///
+#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT2 for IGD
+#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT3 for all other - PEG, USB, SATA etc
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h new file mode 100644 index 0000000000..02ec08fc96 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h @@ -0,0 +1,107 @@ +/** @file
+ The GUID definition for SaConfigHob
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_CONFIG_HOB_H_
+#define _SA_CONFIG_HOB_H_
+
+#include <SaAccess.h>
+#include <Base.h>
+
+extern EFI_GUID gSaConfigHobGuid;
+
+#pragma pack (push,1)
+///
+/// DPR Directory Types
+///
+typedef enum {
+ EnumDprDirectoryTxt = 0,
+ EnumDprDirectoryBiosGuard
+} DPR_DIRECTORY_ELEMENT;
+
+#define DPR_DIRECTORY_TYPE_TXT 0x01
+#define DPR_DIRECTORY_TYPE_BIOSGUARD 0x02
+#define DPR_DIRECTORY_MAX 2
+#define SA_VTD_ENGINE_NUMBER 2
+
+///
+/// DPR directory entry definition
+///
+typedef struct {
+ UINT8 Type; ///< DPR Directory Type
+ UINT8 Size; ///< DPR Size in MB
+ UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear)
+ UINT16 Reserved; ///< Must be 0
+} DPR_DIRECTORY_ENTRY;
+
+///
+/// The data elements should be initialized by a Platform Module.
+/// The data structure is for VT-d driver initialization
+///
+typedef struct {
+ BOOLEAN VtdDisable; ///< 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table
+ UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field is used to describe the base addresses for VT-d function
+ BOOLEAN X2ApicOptOut; ///< This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. <b>1=Enable/Set</b> and 0=Disable/Clear
+ BOOLEAN InterruptRemappingSupport; ///< This field is used to indicate Interrupt Remapping supported or not
+} SA_VTD_CONFIGURATION_HOB;
+
+///
+/// SA GPIO Data Structure
+///
+typedef struct {
+ UINT8 ExpanderNo; ///< =Expander No For I2C based GPIO
+ UINT32 GpioNo; ///< GPIO pad
+ BOOLEAN Active; ///< 0=Active Low; 1=Active High
+} SA_GPIO;
+
+///
+/// SA PCIE RTD3 GPIO Data Structure
+///
+typedef struct {
+ UINT8 GpioSupport; ///< 0=Not Supported; 1=PCH based; 2=I2C Based
+ SA_GPIO HoldRst; ///< Offset 8 This field contain PCIe HLD RESET GPIO value and level information
+ SA_GPIO PwrEnable; ///< This field contain PCIe PWR Enable GPIO value and level information
+ UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 Device Wake GPIO number
+} PCIE_RTD3_GPIO;
+
+///
+/// SG Info HOB
+///
+typedef struct {
+ SG_MODE SgMode;
+ UINT8 RootPortDev;
+ UINT8 RootPortFun;
+ PCIE_RTD3_GPIO Rtd3Pcie0Gpio;
+ PCIE_RTD3_GPIO Rtd3Pcie1Gpio;
+ PCIE_RTD3_GPIO Rtd3Pcie2Gpio;
+ UINT16 DelayAfterPwrEn;
+ UINT16 DelayAfterHoldReset;
+} SA_RTD3;
+
+///
+/// System Agent Config Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaConfigHobGuid
+ DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX]; ///< DPR directory entry definition
+ BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+ SA_RTD3 SaRtd3; ///< SG Info HOB
+ UINT8 ApertureSize; ///< Aperture size value
+ UINT8 ImguAcpiMode; ///< IMGU ACPI mode: 0=Disabled, 1=IGFX Child device, 2=ACPI device
+ SA_VTD_CONFIGURATION_HOB VtdData; ///< VT-d Data HOB
+ BOOLEAN CridEnable; ///< This field inidicates if CRID is enabled or disabled (to support Intel(R) SIPP)
+ BOOLEAN SkipPamLock; ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
+ UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN]; ///< PCIe power down unused bundles support
+ UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///< PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B)
+} SA_CONFIG_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c new file mode 100644 index 0000000000..4909ed8f62 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.c @@ -0,0 +1,250 @@ +/** @file
+ This file provide services for DXE phase policy default initialization
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DxeSaPolicyLibrary.h"
+
+
+extern EFI_GUID gGraphicsDxeConfigGuid;
+extern EFI_GUID gMiscDxeConfigGuid;
+/**
+ This function prints the SA DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+**/
+VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+ MISC_DXE_CONFIG *MiscDxeConfig;
+
+ //
+ // Get requisite IP Config Blocks which needs to be used here
+ //
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG_CODE_BEGIN ();
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BEGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revision));
+ ASSERT (SaPolicy->TableHeader.Header.Revision == SA_POLICY_PROTOCOL_REVISION);
+ DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n"));
+ DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableAbove4GBMmio));
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print END -----------------\n"));
+ DEBUG_CODE_END ();
+
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ GraphicsDxeConfig = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Name = %g\n", &GraphicsDxeConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", GraphicsDxeConfig->Header.GuidHob.Header.HobLength));
+ ///
+ /// Initialize the Graphics configuration
+ ///
+ GraphicsDxeConfig->VbtAddress = 0x00000000;
+ GraphicsDxeConfig->Size = 0;
+ GraphicsDxeConfig->PlatformConfig = 1;
+ GraphicsDxeConfig->AlsEnable = 2;
+ GraphicsDxeConfig->BacklightControlSupport = 2;
+ GraphicsDxeConfig->IgdBootType = 0;
+ GraphicsDxeConfig->IgdPanelType = 0;
+ GraphicsDxeConfig->IgdPanelScaling = 0;
+ GraphicsDxeConfig->IgdBlcConfig = 2;
+ GraphicsDxeConfig->LowPowerMode = 1;
+ GraphicsDxeConfig->IgdDvmtMemSize = 1;
+ GraphicsDxeConfig->GfxTurboIMON = 31;
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+LoadMiscDxeDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ MISC_DXE_CONFIG *MiscDxeConfig;
+
+ MiscDxeConfig = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "MiscDxeConfig->Header.GuidHob.Name = %g\n", &MiscDxeConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "MiscDxeConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MiscDxeConfig->Header.GuidHob.Header.HobLength));
+ ///
+ /// RMRR Base and Limit Address for USB
+ ///
+ MiscDxeConfig->RmrrUsbBaseAddress = AllocateZeroPool (sizeof (EFI_PHYSICAL_ADDRESS) * 2);
+ ASSERT (MiscDxeConfig->RmrrUsbBaseAddress != NULL);
+ if (MiscDxeConfig->RmrrUsbBaseAddress != NULL) {
+ ///
+ /// BIOS must update USB RMRR base address
+ ///
+ MiscDxeConfig->RmrrUsbBaseAddress[0] = 0;
+ MiscDxeConfig->RmrrUsbBaseAddress[1] = 0;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ LoadSaDxeConfigBlockDefault - Initialize default settings for each SA Config block
+
+ @param[in] ConfigBlockPointer The buffer pointer that will be initialized as specific config block
+ @param[in] BlockId Request to initialize defaults of specified config block by given Block ID
+
+ @retval EFI_SUCCESS The given buffer has contained the defaults of requested config block
+ @retval EFI_NOT_FOUND Block ID is not defined so no default Config block will be initialized
+**/
+EFI_STATUS
+EFIAPI
+LoadSaDxeConfigBlockDefault (
+ IN VOID *ConfigBlockPointer,
+ IN EFI_GUID BlockGuid
+ )
+{
+ if (CompareGuid (&BlockGuid, &gGraphicsDxeConfigGuid)) {
+ LoadIgdDxeDefault (ConfigBlockPointer);
+ } else if (CompareGuid (&BlockGuid, &gMiscDxeConfigGuid)) {
+ LoadMiscDxeDefault (ConfigBlockPointer);
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ return EFI_SUCCESS;
+}
+
+
+/**
+ CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[out] SaPolicy The pointer to get SA DXE Protocol instance
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+ IN OUT SA_POLICY_PROTOCOL **SaPolicy
+ )
+{
+ UINT16 TotalBlockSize;
+ UINT16 TotalBlockCount;
+ UINT16 BlockCount;
+ VOID *ConfigBlockPointer;
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaInitPolicy;
+ UINT16 RequiredSize;
+ STATIC CONFIG_BLOCK_HEADER SklSaDxeIpBlocks [] = {
+ {{{0, sizeof (GRAPHICS_DXE_CONFIG), 0}, {0}}, GRAPHICS_DXE_CONFIG_REVISION, 0, {0, 0}},
+ {{{0, sizeof (MISC_DXE_CONFIG), 0}, {0}}, MISC_DXE_CONFIG_REVISION, 0, {0, 0}}
+};
+
+ SaInitPolicy = NULL;
+ TotalBlockCount = sizeof (SklSaDxeIpBlocks) / sizeof (CONFIG_BLOCK_HEADER);
+ DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount));
+
+ TotalBlockSize = 0;
+ for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
+ TotalBlockSize += (UINT32) SklSaDxeIpBlocks[BlockCount].GuidHob.Header.HobLength;
+ DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize));
+ }
+
+ RequiredSize = sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;
+
+ Status = CreateConfigBlockTable (RequiredSize, (VOID *)&SaInitPolicy);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Initalize SklSaIpBlocks table GUID
+ //
+ CopyMem (&SklSaDxeIpBlocks[0].GuidHob.Name, &gGraphicsDxeConfigGuid, sizeof (EFI_GUID));
+ CopyMem (&SklSaDxeIpBlocks[1].GuidHob.Name, &gMiscDxeConfigGuid, sizeof (EFI_GUID));
+
+ //
+ // Initialize Policy Revision
+ //
+ SaInitPolicy->TableHeader.Header.Revision = SA_POLICY_PROTOCOL_REVISION;
+ //
+ // Initialize ConfigBlockPointer to NULL
+ //
+ ConfigBlockPointer = NULL;
+ //
+ // Loop to identify each config block from SklSaDxeIpBlocks[] Table and add each of them
+ //
+ for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
+ ConfigBlockPointer = (VOID *)&SklSaDxeIpBlocks[BlockCount];
+ Status = AddConfigBlock ((VOID *) SaInitPolicy, (VOID *)&ConfigBlockPointer);
+ ASSERT_EFI_ERROR (Status);
+ LoadSaDxeConfigBlockDefault ((VOID *) ConfigBlockPointer, SklSaDxeIpBlocks[BlockCount].GuidHob.Name);
+ }
+ //
+ // Assignment for returning SaPolicy config block base address
+ //
+ *SaPolicy = SaInitPolicy;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ SaInstallPolicyProtocol installs SA Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SaPolicy The pointer to SA Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Print SA DXE Policy
+ ///
+ SaPrintPolicyProtocol (SaPolicy);
+
+ ///
+ /// Install protocol to to allow access to this Policy.
+ ///
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gSaPolicyProtocolGuid,
+ SaPolicy,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
\ No newline at end of file diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf new file mode 100644 index 0000000000..f75ecb1388 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf @@ -0,0 +1,49 @@ +## @file
+# Component description file for the PeiSaPolicy library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeSaPolicyLib
+FILE_GUID = B402A3A4-4B82-410E-B79C-5914880A05E7
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeSaPolicyLib
+
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+PciLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+DxeSaPolicyLib.c
+DxeSaPolicyLibrary.h
+
+[Guids]
+gGraphicsDxeConfigGuid
+gMiscDxeConfigGuid
+[Protocols]
+gSaPolicyProtocolGuid ## PRODUCES
\ No newline at end of file diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h new file mode 100644 index 0000000000..f754072411 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h @@ -0,0 +1,26 @@ +/** @file
+ Header file for the DxeSaPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DXE_SA_POLICY_LIBRARY_H_
+#define _DXE_SA_POLICY_LIBRARY_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ConfigBlockLib.h>
+
+#include <Protocol/SaPolicy.h>
+#endif // _DXE_SA_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf new file mode 100644 index 0000000000..860da17031 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf @@ -0,0 +1,44 @@ +## @file
+# Component description file for SA Platform Lib
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmSaPlatformLib
+FILE_GUID = 9DB5ACB4-DB23-43AE-A283-2ABEF365CBE0
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = SaPlatformLib
+
+
+[LibraryClasses]
+BaseLib
+BaseMemoryLib
+DebugLib
+IoLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+
+[Sources]
+SaPlatformLibrary.h
+SaPlatformLibrary.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c new file mode 100644 index 0000000000..df662b0222 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c @@ -0,0 +1,35 @@ +/** @file
+ SA Platform Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "SaPlatformLibrary.h"
+#include <Library/MmPciLib.h>
+#include <SaRegs.h>
+
+/**
+ Determine if PCH Link is DMI/OPI
+
+ @param[in] CpuModel CPU model
+
+ @retval TRUE DMI
+ @retval FALSE OPI
+**/
+BOOLEAN
+IsPchLinkDmi (
+ IN CPU_FAMILY CpuModel
+ )
+{
+ if (((CpuModel == EnumCpuSklDtHalo) || (CpuModel == EnumCpuKblDtHalo)) && ((MmioRead8 (MmPciBase (0, 0, 0) + R_SA_MC_DEVICE_ID) & (BIT2 | BIT1)) != BIT2)) {
+ return TRUE; // DMI
+ }
+ return FALSE; // OPI
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h new file mode 100644 index 0000000000..632b801ad2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h @@ -0,0 +1,27 @@ +/** @file
+ Header file for SA Platform Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_
+#define _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <SaAccess.h>
+#include <CpuAccess.h>
+#include <Library/SaPlatformLib.h>
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.S b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.S new file mode 100644 index 0000000000..d8fe66154a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.S @@ -0,0 +1,58 @@ +## @file
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+ASM_GLOBAL ASM_PFX(SaMmioRead64)
+ASM_PFX(SaMmioRead64):
+ subl $16, %esp
+ movq %mm0, (%esp) #Save mm0 on stack
+ movl 20(%esp), %edx #edx = Address
+ movq (%edx), %mm0 #mm0 = [Address]
+ movq %mm0, 8(%esp) #Store mm0 on Stack
+ movq (%esp), %mm0 #Restore mm0
+ emms
+ movl 8(%esp), %eax #eax = [Address][31:0]
+ movl 12(%esp), %edx #edx = [Address][64:32]
+ addl $16, %esp
+ ret
+
+#-----------------------------------------------------------------------------
+#
+# Section: SaMmioWrite64
+#
+# Description: Write 64 bits to the Memory Mapped I/O space.
+# Use MMX instruction for atomic access, because some MC registers have side effect.
+#
+# @param[in] Address - Memory mapped I/O address.
+# @param[in] Value - The value to write.
+#
+#-----------------------------------------------------------------------------
+
+#UINT64
+#SaMmioWrite64 (
+# IN UINTN Address,
+# IN UINT64 Value
+# )
+
+ASM_GLOBAL ASM_PFX(SaMmioWrite64)
+ASM_PFX(SaMmioWrite64):
+ subl $8, %esp
+ movq %mm0, (%esp) #Save mm0 on Stack
+ movl 12(%esp), %edx #edx = Address
+ movq 16(%esp), %mm0 #mm0 = Value
+ movq %mm0, (%edx) #[Address] = Value
+ movq (%esp), %mm0 #Restore mm0
+ emms
+ movl 16(%esp), %eax #eax = Value[31:0]
+ movl 20(%esp), %edx #edx = Value[64:32]
+ addl $8, %esp
+ ret
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.asm b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.asm new file mode 100644 index 0000000000..bef8aafe1a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.asm @@ -0,0 +1,85 @@ +;; @file
+; This file provides assembly 64-bit atomic reads/writes required for memory initialization.
+;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;;
+
+.686p
+.xmm
+.model small, c
+
+.CODE
+
+;-----------------------------------------------------------------------------
+;
+; Section: SaMmioRead64
+;
+; Description: Read 64 bits from the Memory Mapped I/O space.
+; Use MMX instruction for atomic access, because some MC registers have side effect.
+;
+; @param[in] Address - Memory mapped I/O address.
+;
+;-----------------------------------------------------------------------------
+
+;UINT64
+;SaMmioRead64 (
+; IN UINTN Address
+; )
+
+SaMmioRead64 PROC NEAR PUBLIC
+ sub esp, 16
+ movq [esp], mm0 ;Save mm0 on stack
+ mov edx, [esp + 20] ;edx = Address
+ movq mm0, [edx] ;mm0 = [Address]
+ movq [esp + 8], mm0 ;Store mm0 on Stack
+ movq mm0, [esp] ;Restore mm0
+ emms
+ mov eax, [esp + 8] ;eax = [Address][31:0]
+ mov edx, [esp + 12] ;edx = [Address][64:32]
+ add esp, 16
+ ret
+SaMmioRead64 ENDP
+
+;-----------------------------------------------------------------------------
+;
+; Section: SaMmioWrite64
+;
+; Description: Write 64 bits to the Memory Mapped I/O space.
+; Use MMX instruction for atomic access, because some MC registers have side effect.
+;
+; @param[in] Address - Memory mapped I/O address.
+; @param[in] Value - The value to write.
+;
+;-----------------------------------------------------------------------------
+
+;UINT64
+;SaMmioWrite64 (
+; IN UINTN Address,
+; IN UINT64 Value
+; )
+
+SaMmioWrite64 PROC NEAR PUBLIC
+ sub esp, 8
+ movq [esp], mm0 ;Save mm0 on Stack
+ mov edx, [esp + 12] ;edx = Address
+ movq mm0, [esp + 16] ;mm0 = Value
+ movq [edx], mm0 ;[Address] = Value
+ movq mm0, [esp] ;Restore mm0
+ emms
+ mov eax, [esp + 16] ;eax = Value[31:0]
+ mov edx, [esp + 20] ;edx = Value[64:32]
+ add esp, 8
+ ret
+SaMmioWrite64 ENDP
+
+end
+
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.nasm b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.nasm new file mode 100644 index 0000000000..5bc17065bd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.nasm @@ -0,0 +1,79 @@ +;; @file
+; This file provides assembly 64-bit atomic reads/writes required for memory initialization.
+;
+; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials are licensed and made available under
+; the terms and conditions of the BSD License that accompanies this distribution.
+; The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;;
+
+
+SECTION .TEXT
+
+;-----------------------------------------------------------------------------
+;
+; Section: SaMmioRead64
+;
+; Description: Read 64 bits from the Memory Mapped I/O space.
+; Use MMX instruction for atomic access, because some MC registers have side effect.
+;
+; @param[in] Address - Memory mapped I/O address.
+;
+;-----------------------------------------------------------------------------
+
+;UINT64
+;SaMmioRead64 (
+; IN UINTN Address
+; )
+
+global ASM_PFX(SaMmioRead64)
+ASM_PFX(SaMmioRead64):
+ sub esp, 16
+ movq [esp], mm0 ;Save mm0 on stack
+ mov edx, [esp + 20] ;edx = Address
+ movq mm0, [edx] ;mm0 = [Address]
+ movq [esp + 8], mm0 ;Store mm0 on Stack
+ movq mm0, [esp] ;Restore mm0
+ emms
+ mov eax, [esp + 8] ;eax = [Address][31:0]
+ mov edx, [esp + 12] ;edx = [Address][64:32]
+ add esp, 16
+ ret
+
+;-----------------------------------------------------------------------------
+;
+; Section: SaMmioWrite64
+;
+; Description: Write 64 bits to the Memory Mapped I/O space.
+; Use MMX instruction for atomic access, because some MC registers have side effect.
+;
+; @param[in] Address - Memory mapped I/O address.
+; @param[in] Value - The value to write.
+;
+;-----------------------------------------------------------------------------
+
+;UINT64
+;SaMmioWrite64 (
+; IN UINTN Address,
+; IN UINT64 Value
+; )
+
+global ASM_PFX(SaMmioWrite64)
+ASM_PFX(SaMmioWrite64):
+ sub esp, 8
+ movq [esp], mm0 ;Save mm0 on Stack
+ mov edx, [esp + 12] ;edx = Address
+ movq mm0, [esp + 16] ;mm0 = Value
+ movq [edx], mm0 ;[Address] = Value
+ movq mm0, [esp] ;Restore mm0
+ emms
+ mov eax, [esp + 16] ;eax = Value[31:0]
+ mov edx, [esp + 20] ;edx = Value[64:32]
+ add esp, 8
+ ret
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcOemPlatform.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcOemPlatform.c new file mode 100644 index 0000000000..e4d6f1b35c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcOemPlatform.c @@ -0,0 +1,747 @@ +/** @file
+ This file is SampleCode for Intel SA PEI Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "MrcOemPlatform.h"
+#include <Library/CpuPlatformLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmbusLib.h>
+#include <PchAccess.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/PchCycleDecodingLib.h>
+
+#pragma pack (push, 1)
+typedef union {
+ struct {
+ UINT32 : 8;
+ UINT32 MAX_NON_TURBO_LIM_RATIO : 8;
+ UINT32 : 16;
+ UINT32 : 32;
+ } Bits;
+ UINT64 Data;
+ UINT32 Data32[2];
+ UINT16 Data16[4];
+ UINT8 Data8[8];
+} PCU_CR_PLATFORM_INFO_STRUCT;
+
+#pragma pack (pop)
+
+#define SA_SYSTEM_BCLK (100)
+#define PCU_CR_PLATFORM_INFO (0xCE)
+#define MRC_POST_CODE_LOW_BYTE_ADDR (0x48)
+#define MRC_POST_CODE_HIGH_BYTE_ADDR (0x49)
+#define MAX_SPD_PAGE_COUNT (2)
+#define MAX_SPD_PAGE_SIZE (256)
+#define MAX_SPD_DDR3_SIZE (MAX_SPD_PAGE_SIZE * 1)
+#define MAX_SPD_DDR4_SIZE (MAX_SPD_PAGE_SIZE * 2)
+#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COUNT)
+#define SPD_PAGE_ADDRESS_0 (0x6C)
+#define SPD_PAGE_ADDRESS_1 (0x6E)
+#define SPD_DDR3_XMP_OFFSET (176)
+#define SPD_DDR4_XMP_OFFSET (384)
+#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02)
+#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B)
+#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C)
+#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1)
+#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F)
+
+/**
+ Read the SPD data over the SMBus, at the specified SPD address, starting at
+ the specified starting offset and read the given amount of data.
+
+ @param[in] SpdAddress - SPD SMBUS address
+ @param[in, out] Buffer - Buffer to store the data.
+ @param[in] Start - Starting SPD offset
+ @param[in] Size - The number of bytes of data to read and also the size of the buffer.
+ @param[in, out] Page - The final page that is being pointed to.
+
+ @retval RETURN_SUCCESS if the read is successful, otherwise error status.
+**/
+static
+RETURN_STATUS
+DoSpdRead (
+ IN const UINT8 SpdAddress,
+ IN OUT UINT8 *const Buffer,
+ IN const UINT16 Start,
+ IN UINT16 Size,
+ IN OUT UINT8 *const Page
+ )
+{
+ RETURN_STATUS EfiStatus;
+ BOOLEAN PageUpdate;
+ UINT16 Count;
+ UINT16 Index;
+
+ EfiStatus = RETURN_DEVICE_ERROR;
+ if ((Buffer != NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MAX_SPD_SIZE)) {
+ Count = 0;
+ PageUpdate = FALSE;
+ while (Size--) {
+ Index = Start + Count;
+ if ((Index / MAX_SPD_PAGE_SIZE) != *Page) {
+ *Page = (UINT8) (Index / MAX_SPD_PAGE_SIZE);
+ PageUpdate = TRUE;
+ }
+ Index %= MAX_SPD_PAGE_SIZE;
+ if (PageUpdate == TRUE) {
+ PageUpdate = FALSE;
+ SmBusWriteDataByte ((*Page == 0) ? SPD_PAGE_ADDRESS_0 : SPD_PAGE_ADDRESS_1, 0, &EfiStatus);
+ }
+ Buffer[Count] = SmBusReadDataByte (SpdAddress | ((UINT32) Index << 8), &EfiStatus);
+ if (RETURN_SUCCESS != EfiStatus) {
+ Buffer[Count] = 0;
+ break;
+ }
+ Count++;
+ }
+ EfiStatus = RETURN_SUCCESS;
+ }
+ return (EfiStatus);
+}
+
+/**
+ See if there is valid XMP SPD data.
+
+ @param[in] Debug - Mrc debug structure.
+ @param[in, out] Spd - Mrc SPD structure.
+ @param[in] XmpStart - The current offset in the SPD.
+
+ @retval TRUE if valid, FALSE in not.
+**/
+static
+BOOLEAN
+VerifyXmp (
+ IN OUT MrcSpd *const Spd,
+ IN const UINT16 XmpStart
+ )
+{
+ SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1;
+ SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2;
+ BOOLEAN Xmp;
+
+ Xmp = FALSE;
+
+ switch (((UINT8 *) Spd) [2]) {
+ case SPD_DDR3_SDRAM_TYPE_NUMBER:
+ Header1 = &Spd->Ddr3.Xmp.Header;
+ if (XmpStart == ((UINT32) (Header1) - (UINT32) Spd)) {
+ Xmp = TRUE;
+ if ((Header1->XmpRevision.Data & 0xFE) == 0x12) {
+ return (TRUE);
+ } else {
+ Header1->XmpId = 0;
+ Header1->XmpOrgConf.Data = 0;
+ Header1->XmpRevision.Data = 0;
+ }
+ }
+ break;
+ case SPD_DDR4_SDRAM_TYPE_NUMBER:
+ Header2 = &Spd->Ddr4.EndUser.Xmp.Header;
+ if (XmpStart == ((UINT32) (Header2) - (UINT32) Spd)) {
+ Xmp = TRUE;
+ if ((Header2->XmpRevision.Data) == 0x20) {
+ return (TRUE);
+ } else {
+ Header2->XmpId = 0;
+ Header2->XmpOrgConf.Data = 0;
+ Header2->XmpRevision.Data = 0;
+ }
+ }
+ break;
+ case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+ case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
+ return (TRUE);
+ default:
+ return (FALSE);
+ }
+ if (!Xmp) {
+ return (TRUE);
+ }
+ return (FALSE);
+}
+
+/**
+ Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ The SPD data locations read is controlled by the current boot mode.
+
+ @param[in] BootMode - The current MRC boot mode.
+ @param[in] Address - SPD SmBus address offset.
+ @param[in] Buffer - Buffer that contains the data read from the SPD.
+ @param[in] SpdDdr3Table - Indicates which SPD bytes to read.
+ @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes.
+ @param[in] SpdDdr4Table - Indicates which SPD bytes to read.
+ @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes.
+ @param[in] SpdLpddrTable - Indicates which SPD bytes to read.
+ @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes.
+
+ @retval TRUE if the read is successful, otherwise FALSE on error.
+**/
+BOOLEAN
+GetSpdData (
+ IN SPD_BOOT_MODE BootMode,
+ IN UINT8 Address,
+ IN OUT UINT8 *Buffer,
+ IN UINT8 *SpdDdr3Table,
+ IN UINT32 SpdDdr3TableSize,
+ IN UINT8 *SpdDdr4Table,
+ IN UINT32 SpdDdr4TableSize,
+ IN UINT8 *SpdLpddrTable,
+ IN UINT32 SpdLpddrTableSize
+ )
+{
+ const SPD_OFFSET_TABLE *Tbl;
+ const SPD_OFFSET_TABLE *TableSelect;
+ RETURN_STATUS Status;
+ UINT32 Byte;
+ UINT32 Stop;
+ UINT8 Page;
+
+ Page = (UINT8) (~0);
+ Status = DoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1, &Page);
+ if (RETURN_SUCCESS == Status) {
+ switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) {
+ case SPD_DDR3_SDRAM_TYPE_NUMBER:
+ case SPD_LPDDR3_SDRAM_TYPE_NUMBER:
+ default:
+ TableSelect = (SPD_OFFSET_TABLE *) SpdDdr3Table;
+ Stop = (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE));
+ break;
+ case SPD_DDR4_SDRAM_TYPE_NUMBER:
+ TableSelect = (SPD_OFFSET_TABLE *) SpdDdr4Table;
+ Stop = (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE));
+ break;
+ case SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER:
+ TableSelect = (SPD_OFFSET_TABLE *) SpdLpddrTable;
+ Stop = (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE));
+ break;
+ }
+ for (Byte = 0; (RETURN_SUCCESS == Status) && (Byte < Stop); Byte++) {
+ Tbl = &TableSelect[Byte];
+ if ((1 << BootMode) & Tbl->BootMode) {
+ Status = DoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tbl->End - Tbl->Start + 1, &Page);
+ if (Status == RETURN_SUCCESS) {
+ if (SpdCold == BootMode) {
+ if (FALSE == VerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) {
+ break;
+ }
+ }
+ } else {
+ break;
+ }
+ }
+ }
+ }
+
+ return ((RETURN_SUCCESS == Status) ? TRUE : FALSE);
+}
+
+//
+// This is from MdeModulePkg\Include\Guid\StatusCodeDataTypeDebug.h
+// Might need to be adjusted for a particular BIOS core
+//
+#ifndef EFI_STATUS_CODE_DATA_MAX_SIZE
+#define EFI_STATUS_CODE_DATA_MAX_SIZE 200
+#endif
+
+/**
+ Output a string to the debug stream/device.
+ If there is a '%' sign in the string, convert it to '%%', so that DEBUG() macro will print it properly.
+
+ @param[in] String - The string to output.
+
+ @retval Nothing.
+**/
+VOID
+SaDebugPrint (
+ VOID *String
+ )
+{
+ CHAR8 Str[EFI_STATUS_CODE_DATA_MAX_SIZE];
+ CHAR8 *InputStr;
+ CHAR8 *OutputStr;
+ UINT32 i;
+
+ InputStr = (CHAR8 *) String;
+ OutputStr = Str;
+ i = 0;
+ while (*InputStr != 0) {
+ if (i < (EFI_STATUS_CODE_DATA_MAX_SIZE - 2)) {
+ *OutputStr++ = *InputStr;
+ i++;
+ if (*InputStr++ == '%') {
+ *OutputStr++ = '%';
+ i++;
+ }
+ }
+ }
+ *OutputStr = 0; // Terminating NULL
+ DEBUG ((DEBUG_ERROR, Str));
+ return;
+}
+
+/**
+ Calculate the PCI device address for the given Bus/Device/Function/Offset.
+
+ @param[in] Bus - PCI bus
+ @param[in] Device - PCI device
+ @param[in] Function - PCI function
+ @param[in] Offset - Offset
+
+ @retval The PCI device address.
+**/
+UINT32
+GetPciDeviceAddress (
+ IN const UINT8 Bus,
+ IN const UINT8 Device,
+ IN const UINT8 Function,
+ IN const UINT8 Offset
+ )
+{
+ return (
+ ((UINT32) ((Bus) & 0xFF) << 16) |
+ ((UINT32) ((Device) & 0x1F) << 11) |
+ ((UINT32) ((Function) & 0x07) << 8) |
+ ((UINT32) ((Offset) & 0xFF) << 0) |
+ (1UL << 31));
+}
+
+/**
+ Calculate the PCIE device address for the given Bus/Device/Function/Offset.
+
+ @param[in] Bus - PCI bus
+ @param[in] Device - PCI device
+ @param[in] Function - PCI function
+ @param[in] Offset - Offset
+
+ The PCIE device address.
+
+ @retval The PCIe device address
+**/
+UINT32
+GetPcieDeviceAddress (
+ IN const UINT8 Bus,
+ IN const UINT8 Device,
+ IN const UINT8 Function,
+ IN const UINT8 Offset
+ )
+{
+ return (
+ ((UINT32) Bus << 20) +
+ ((UINT32) Device << 15) +
+ ((UINT32) Function << 12) +
+ ((UINT32) Offset << 0));
+}
+
+/**
+ Read specific RTC/CMOS RAM
+
+ @param[in] Location Point to RTC/CMOS RAM offset for read
+
+ @retval The data of specific location in RTC/CMOS RAM.
+**/
+UINT8
+PeiRtcRead (
+ IN const UINT8 Location
+ )
+{
+ UINT8 RtcIndexPort;
+ UINT8 RtcDataPort;
+
+ //
+ // CMOS access registers (using alternative access not to handle NMI bit)
+ //
+ if (Location < RTC_BANK_SIZE) {
+ //
+ // First bank
+ //
+ RtcIndexPort = R_PCH_RTC_INDEX_ALT;
+ RtcDataPort = R_PCH_RTC_TARGET_ALT;
+ } else {
+ //
+ // Second bank
+ //
+ RtcIndexPort = R_PCH_RTC_EXT_INDEX_ALT;
+ RtcDataPort = R_PCH_RTC_EXT_TARGET_ALT;
+ }
+
+ IoWrite8 (RtcIndexPort, Location & RTC_INDEX_MASK);
+ return IoRead8 (RtcDataPort);
+}
+
+/**
+ Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform.
+ Since RTC time is stored in BCD, convert each value to binary.
+
+ @param[out] Seconds - The current second (0-59).
+ @param[out] Minutes - The current minute (0-59).
+ @param[out] Hours - The current hour (0-23).
+ @param[out] DayOfMonth - The current day of the month (1-31).
+ @param[out] Month - The current month (1-12).
+ @param[out] Year - The current year (2000-2099).
+
+ @retval Nothing.
+**/
+VOID
+GetRtcTime (
+ OUT UINT8 *const Seconds,
+ OUT UINT8 *const Minutes,
+ OUT UINT8 *const Hours,
+ OUT UINT8 *const DayOfMonth,
+ OUT UINT8 *const Month,
+ OUT UINT16 *const Year
+ )
+{
+ UINT32 Timeout;
+
+ //
+ // Wait until RTC "update in progress" bit goes low.
+ //
+ Timeout = 0x0FFFFF;
+ do {
+ IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGA);
+ if ((IoRead8 (RTC_TARGET_REGISTER) & RTC_UPDATE_IN_PROGRESS) != RTC_UPDATE_IN_PROGRESS) {
+ break;
+ }
+ } while (--Timeout > 0);
+
+ if (0 == Timeout) {
+ IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGB);
+ IoWrite8 (RTC_TARGET_REGISTER, RTC_HOLD | RTC_MODE_24HOUR);
+
+ IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGA);
+ IoWrite8 (RTC_TARGET_REGISTER, RTC_CLOCK_DIVIDER | RTC_RATE_SELECT);
+
+ IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGC);
+ IoRead8 (RTC_TARGET_REGISTER);
+
+ IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGD);
+ IoRead8 (RTC_TARGET_REGISTER);
+
+ IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGB);
+ IoWrite8 (RTC_TARGET_REGISTER, RTC_MODE_24HOUR);
+ }
+ //
+ // Read seconds
+ //
+ IoWrite8 (RTC_INDEX_REGISTER, RTC_SECONDS);
+ *Seconds = IoRead8 (RTC_TARGET_REGISTER);
+
+ //
+ // Read minutes
+ //
+ IoWrite8 (RTC_INDEX_REGISTER, RTC_MINUTES);
+ *Minutes = IoRead8 (RTC_TARGET_REGISTER);
+
+ //
+ // Read hours
+ //
+ IoWrite8 (RTC_INDEX_REGISTER, RTC_HOURS);
+ *Hours = IoRead8 (RTC_TARGET_REGISTER);
+
+ //
+ // Read day of month
+ //
+ IoWrite8 (RTC_INDEX_REGISTER, RTC_DAY_OF_MONTH);
+ *DayOfMonth = IoRead8 (RTC_TARGET_REGISTER);
+
+ //
+ // Read month
+ //
+ IoWrite8 (RTC_INDEX_REGISTER, RTC_MONTH);
+ *Month = IoRead8 (RTC_TARGET_REGISTER);
+
+ //
+ // Read year and add current century.
+ //
+ IoWrite8 (RTC_INDEX_REGISTER, RTC_YEAR);
+ *Year = IoRead8 (RTC_TARGET_REGISTER);
+
+ *Seconds = BCD2BINARY (*Seconds);
+ *Minutes = BCD2BINARY (*Minutes);
+ *Hours = BCD2BINARY (*Hours);
+ *DayOfMonth = BCD2BINARY (*DayOfMonth);
+ *Month = BCD2BINARY (*Month);
+ *Year = BCD2BINARY (*Year) + CENTURY_OFFSET;
+}
+
+/**
+ Gets CPU current time.
+
+ @param[in] GlobalData - Pointer to global MRC data struct.
+
+ @retval The current CPU time in milliseconds.
+**/
+UINT64
+GetCpuTime (
+ IN VOID *GlobalData
+ )
+{
+ MrcParameters *MrcData;
+ MrcInput *Inputs;
+ PCU_CR_PLATFORM_INFO_STRUCT Msr;
+ UINT32 TimeBase;
+
+ MrcData = (MrcParameters *) GlobalData;
+ Inputs = &MrcData->Inputs;
+
+ Msr.Data = AsmReadMsr64 (PCU_CR_PLATFORM_INFO);
+ TimeBase = (Inputs->BClkFrequency / 1000) * Msr.Bits.MAX_NON_TURBO_LIM_RATIO; //In Millisec
+ return ((TimeBase == 0) ? 0 : DivU64x32 (AsmReadTsc (), TimeBase));
+}
+
+/**
+ Sets the specified number of memory words, a word at a time, at the
+ specified destination.
+
+ @param[in, out] Dest - Destination pointer.
+ @param[in] NumWords - The number of dwords to set.
+ @param[in] Value - The value to set.
+
+ @retval Pointer to the buffer.
+**/
+VOID *
+SetMemWord (
+ IN OUT VOID *Dest,
+ IN UINTN NumWords,
+ IN const UINT16 Value
+ )
+{
+ UINT16 *Buffer;
+
+ Buffer = (UINT16 *) Dest;
+ while (0 != NumWords--) {
+ *Buffer++ = Value;
+ }
+
+ return (Dest);
+}
+
+/**
+ Sets the specified number of memory dwords, a dword at a time, at the
+ specified destination.
+
+ @param[in, out] Dest - Destination pointer.
+ @param[in] NumDwords - The number of dwords to set.
+ @param[in] Value - The value to set.
+
+ @retval Pointer to the buffer.
+**/
+VOID *
+SetMemDword (
+ IN OUT VOID *Dest,
+ IN UINT32 NumDwords,
+ IN const UINT32 Value
+ )
+{
+ UINT32 *Buffer;
+
+ Buffer = (UINT32 *) Dest;
+ while (0 != NumDwords--) {
+ *Buffer++ = Value;
+ }
+
+ return (Dest);
+}
+
+
+/**
+ Gets the current memory voltage (VDD).
+
+ @param[in] GlobalData - Pointer to global MRC data struct.
+ @param[in] DefaultVdd - Default Vdd for the given platform.
+
+ @retval The current memory voltage (VDD), in millivolts. 0 means platform default.
+**/
+UINT32
+GetMemoryVdd (
+ IN VOID *GlobalData,
+ IN UINT32 DefaultVdd
+ )
+{
+ MrcParameters *MrcData;
+ UINT32 CurrentVoltage;
+
+ MrcData = (MrcParameters *) GlobalData;
+ CurrentVoltage = DefaultVdd;
+
+ return CurrentVoltage;
+}
+
+/**
+ Sets the memory voltage (VDD) to the specified value.
+
+ @param[in] GlobalData - Pointer to global MRC data struct.
+ @param[in] DefaultVdd - Default Vdd for the given platform.
+ @param[in] Voltage - The new memory voltage to set.
+
+ @retval The actual memory voltage (VDD), in millivolts, that is closest to what the caller passed in.
+**/
+UINT32
+SetMemoryVdd (
+ IN VOID *GlobalData,
+ IN UINT32 DefaultVdd,
+ IN UINT32 Voltage
+ )
+{
+ MrcParameters *MrcData;
+
+ MrcData = (MrcParameters *) GlobalData;
+
+ return Voltage;
+}
+
+/**
+ This function is used by the OEM to do a dedicated task during the MRC.
+
+ @param[in] GlobalData - include all the MRC data
+ @param[in] OemStatusCommand - A command that indicates the task to perform.
+ @param[in] Pointer - general ptr for general use.
+
+ @retval The status of the task.
+**/
+MrcStatus
+CheckPoint (
+ IN VOID *GlobalData,
+ IN MrcOemStatusCommand OemStatusCommand,
+ IN VOID *Pointer
+ )
+{
+ const SA_MEMORY_FUNCTIONS *SaCall;
+ MrcParameters *MrcData;
+ MrcInput *Inputs;
+ MrcStatus Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ EFI_STATUS Status1;
+
+ //
+ // Locate SiPreMemPolicyPpi to do a GetConfigBlock() to access platform data
+ //
+ Status1 = PeiServicesLocatePpi (
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR (Status1);
+
+ Status1 = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR (Status1);
+ MrcData = (MrcParameters *) GlobalData;
+ Inputs = &MrcData->Inputs;
+ SiPreMemPolicyPpi = (SI_PREMEM_POLICY_PPI *) Inputs->SiPreMemPolicyPpi;
+ SaCall = &MemConfigNoCrc->MrcCall;
+ Status = mrcSuccess;
+
+ switch (OemStatusCommand) {
+ case OemAfterNormalMode:
+ SaCall->MrcThermalOverrides (MrcData);
+ break;
+
+ default:
+ break;
+ }
+
+ return (mrcSuccess);
+}
+
+/**
+ Typically used to display to the I/O port 80h.
+
+ @param[in] GlobalData - Mrc Global Data
+ @param[in] DisplayDebugNumber - the number to display on port 80.
+
+ @retval Nothing.
+**/
+VOID
+DebugHook (
+ IN VOID *GlobalData,
+ UINT16 DisplayDebugNumber
+ )
+{
+ MrcParameters *MrcData;
+ MrcOutput *Outputs;
+ MrcDebug *Debug;
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+
+ MrcData = (MrcParameters *) GlobalData;
+ Outputs = &MrcData->Outputs;
+ Debug = &Outputs->Debug;
+
+ Debug->PostCode[MRC_POST_CODE] = DisplayDebugNumber;
+ IoWrite16 (0x80, DisplayDebugNumber);
+ DEBUG ((DEBUG_INFO, "Post Code: %04Xh\n", DisplayDebugNumber));
+
+ //
+ // Locate SiPreMemPolicyPpi to do a GetConfigBlock() to access platform data
+ //
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ if (Status == EFI_SUCCESS) {
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ }
+ return;
+}
+
+/**
+ Hook to take any action after returning from MrcStartMemoryConfiguration()
+ and prior to taking any action regarding MrcStatus. Pre-populated with issuing
+ Intel Silicon View Technology (ISVT) checkpoint 0x10.
+
+ @param[in] GlobalData - Mrc Global Data
+ @param[in] MrcStatus - Mrc status variable
+**/
+void
+ReturnFromSmc (
+ IN VOID *GlobalData,
+ IN UINT32 MrcStatus
+ )
+{
+ return;
+}
+
+/**
+ Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+
+ @param[in] PciEBaseAddress - PCI express base address.
+ @param[in] ResetValue - desired value of DRAM_RESET#. 1 - reset deasserted, 0 - reset asserted.
+**/
+VOID
+SaDramReset (
+ IN UINT32 PciEBaseAddress,
+ IN UINT32 ResetValue
+ )
+{
+ UINT32 MmioBase;
+ UINT32 PmCfg2;
+
+ //
+ // Get the PCH PWRM Base
+ //
+ PchPwrmBaseGet (&MmioBase);
+
+ //
+ // Set DRAM RESET# value via PCH register (both SKL PCH-H and SKL PCH-LP)
+ //
+ PmCfg2 = MmioRead32 (MmioBase + R_PCH_PWRM_CFG2);
+ PmCfg2 &= ~(B_PCH_PWRM_CFG2_DRAM_RESET_CTL);
+ PmCfg2 |= (ResetValue << 26);
+ MmioWrite32 (MmioBase + R_PCH_PWRM_CFG2, PmCfg2);
+
+ return;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcOemPlatform.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcOemPlatform.h new file mode 100644 index 0000000000..f561138b04 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcOemPlatform.h @@ -0,0 +1,313 @@ +/** @file
+ This file contains functions that read the SPD data for each DIMM slot over
+ the SMBus interface.
+ This file is SampleCode for Intel SA PEI Policy initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include "PeiSaPolicyLibrary.h"
+#include "MrcInterface.h"
+#include <SaRegs.h>
+
+#define RTC_INDEX_REGISTER (0x70)
+#define RTC_TARGET_REGISTER (0x71)
+
+#define RTC_INDEX_MASK (0x7F)
+#define RTC_BANK_SIZE (0x80)
+
+#define RTC_SECONDS (0x00)
+#define RTC_MINUTES (0x02)
+#define RTC_HOURS (0x04)
+#define RTC_DAY_OF_MONTH (0x07)
+#define RTC_MONTH (0x08)
+#define RTC_YEAR (0x09)
+#define CMOS_REGA (0x0A)
+#define CMOS_REGB (0x0B)
+#define CMOS_REGC (0x0C)
+#define CMOS_REGD (0x0D)
+
+#define RTC_UPDATE_IN_PROGRESS (0x80)
+#define RTC_HOLD (0x80)
+#define RTC_MODE_24HOUR (0x02)
+#define RTC_CLOCK_DIVIDER (0x20)
+#define RTC_RATE_SELECT (0x06)
+
+#define BCD2BINARY(A) (((((A) >> 4) & 0xF) * 10) + ((A) & 0xF))
+#define CENTURY_OFFSET (2000)
+
+/**
+ Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ The SPD data locations read is controlled by the current boot mode.
+
+ @param[in] BootMode - The current MRC boot mode.
+ @param[in] Address - SPD SmBus address offset.
+ @param[in] Buffer - Buffer that contains the data read from the SPD.
+ @param[in] SpdDdr3Table - Indicates which SPD bytes to read.
+ @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes.
+ @param[in] SpdDdr4Table - Indicates which SPD bytes to read.
+ @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes.
+ @param[in] SpdLpddrTable - Indicates which SPD bytes to read.
+ @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes.
+
+ @retval TRUE if the read is successful, otherwise FALSE on error.
+**/
+BOOLEAN
+GetSpdData (
+ IN SPD_BOOT_MODE BootMode,
+ IN UINT8 Address,
+ IN OUT UINT8 *Buffer,
+ IN UINT8 *SpdDdr3Table,
+ IN UINT32 SpdDdr3TableSize,
+ IN UINT8 *SpdDdr4Table,
+ IN UINT32 SpdDdr4TableSize,
+ IN UINT8 *SpdLpddrTable,
+ IN UINT32 SpdLpddrTableSize
+ );
+
+/**
+ Output a string to the debug stream/device.
+
+ @param[in] String - The string to output.
+**/
+VOID
+SaDebugPrint (
+ VOID *String
+ );
+
+/**
+ Calculate the PCI device address for the given Bus/Device/Function/Offset.
+
+ @param[in] Bus - PCI bus
+ @param[in] Device - PCI device
+ @param[in] Function - PCI function
+ @param[in] Offset - Offset
+
+ @retval The PCI device address.
+**/
+UINT32
+GetPciDeviceAddress (
+ IN const UINT8 Bus,
+ IN const UINT8 Device,
+ IN const UINT8 Function,
+ IN const UINT8 Offset
+ );
+
+/**
+ Calculate the PCIE device address for the given Bus/Device/Function/Offset.
+
+ @param[in] Bus - PCI bus
+ @param[in] Device - PCI device
+ @param[in] Function - PCI function
+ @param[in] Offset - Offset
+
+ The PCIE device address.
+
+ @retval The PCIe device address
+**/
+UINT32
+GetPcieDeviceAddress (
+ IN const UINT8 Bus,
+ IN const UINT8 Device,
+ IN const UINT8 Function,
+ IN const UINT8 Offset
+ );
+
+/**
+ Read specific RTC/CMOS RAM
+
+ @param[in] Location Point to RTC/CMOS RAM offset for read
+
+ @retval The data of specific location in RTC/CMOS RAM.
+**/
+UINT8
+PeiRtcRead (
+ IN const UINT8 Location
+ );
+
+/**
+ Returns the current time, as determined by reading the Real Time Clock (RTC) on the platform.
+ Since RTC time is stored in BCD, convert each value to binary.
+
+ @param[out] Seconds - The current second (0-59).
+ @param[out] Minutes - The current minute (0-59).
+ @param[out] Hours - The current hour (0-23).
+ @param[out] DayOfMonth - The current day of the month (1-31).
+ @param[out] Month - The current month (1-12).
+ @param[out] Year - The current year (2000-2099).
+**/
+VOID
+GetRtcTime (
+ OUT UINT8 *const Seconds,
+ OUT UINT8 *const Minutes,
+ OUT UINT8 *const Hours,
+ OUT UINT8 *const DayOfMonth,
+ OUT UINT8 *const Month,
+ OUT UINT16 *const Year
+ );
+
+/**
+ Gets CPU current time.
+
+ @param[in] GlobalData - Pointer to global MRC data struct.
+
+ @retval The current CPU time in milliseconds.
+**/
+UINT64
+GetCpuTime (
+ IN VOID *GlobalData
+ );
+
+/**
+ Sets the specified number of memory words, a word at a time, at the
+ specified destination.
+
+ @param[in, out] Dest - Destination pointer.
+ @param[in] NumWords - The number of dwords to set.
+ @param[in] Value - The value to set.
+
+ @retval Pointer to the buffer.
+**/
+VOID *
+SetMemWord (
+ IN OUT VOID *Dest,
+ IN UINTN NumWords,
+ IN const UINT16 Value
+ );
+
+/**
+ Sets the specified number of memory dwords, a dword at a time, at the
+ specified destination.
+
+ @param[in, out] Dest - Destination pointer.
+ @param[in] NumDwords - The number of dwords to set.
+ @param[in] Value - The value to set.
+
+ @retval Pointer to the buffer.
+**/
+VOID *
+SetMemDword (
+ IN OUT VOID *Dest,
+ IN UINT32 NumDwords,
+ IN const UINT32 Value
+ );
+
+/**
+ Read 64 bits from the Memory Mapped I/O space.
+ Use MMX instruction for atomic access, because some MC registers have side effect.
+
+ @param[in] Address - Memory mapped I/O address.
+**/
+UINT64
+SaMmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ Write 64 bits to the Memory Mapped I/O space.
+ Use MMX instruction for atomic access, because some MC registers have side effect.
+
+ @param[in] Address - Memory mapped I/O address.
+ @param[in] Value - The value to write.
+**/
+UINT64
+SaMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ Gets the current memory voltage (VDD).
+
+ @param[in] GlobalData - Pointer to global MRC data struct.
+ @param[in] DefaultVdd - Default Vdd for the given platform.
+
+ @retval The current memory voltage (VDD), in millivolts. 0 means platform default.
+**/
+UINT32
+GetMemoryVdd (
+ IN VOID *GlobalData,
+ IN UINT32 DefaultVdd
+ );
+
+/**
+ Sets the memory voltage (VDD) to the specified value.
+
+ @param[in] GlobalData - Pointer to global MRC data struct.
+ @param[in] DefaultVdd - Default Vdd for the given platform.
+ @param[in] Voltage - The new memory voltage to set.
+
+ @retval The actual memory voltage (VDD), in millivolts, that is closest to what the caller passed in.
+**/
+UINT32
+SetMemoryVdd (
+ IN VOID *GlobalData,
+ IN UINT32 DefaultVdd,
+ IN UINT32 Voltage
+ );
+
+/**
+ Check point that is called at various points in the MRC.
+
+ @param[in] GlobalData - MRC global data.
+ @param[in] Command - OEM command.
+ @param[in] Pointer - Command specific data.
+
+ @retval MrcStatus value.
+**/
+UINT32
+CheckPoint (
+ VOID *GlobalData,
+ UINT32 Command,
+ VOID *Pointer
+ );
+
+/**
+ Typically used to display to the I/O port 80h.
+
+ @param[in] GlobalData - Mrc Global Data
+ @param[in] DisplayDebugNumber - the number to display on port 80.
+
+ @retval Nothing.
+**/
+VOID
+DebugHook (
+ VOID *GlobalData,
+ UINT16 DisplayDebugNumber
+ );
+
+/**
+ Hook to take any action after returning from MrcStartMemoryConfiguration()
+ and prior to taking any action regarding MrcStatus. Pre-populated with issuing
+ Intel Silicon View Technology (ISVT) checkpoint 0x01.
+
+ @param[in] GlobalData - Mrc Global Data
+ @param[in] MrcStatus - Mrc status variable
+**/
+VOID
+ReturnFromSmc (
+ VOID *GlobalData,
+ UINT32 MrcStatus
+ );
+
+/**
+ Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+
+ @param[in] PciEBaseAddress - PCI express base address.
+ @param[in] ResetValue - desired value of DRAM_RESET#. 1 - reset deasserted, 0 - reset asserted.
+**/
+VOID
+SaDramReset (
+ IN UINT32 PciEBaseAddress,
+ IN UINT32 ResetValue
+ );
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c new file mode 100644 index 0000000000..ddc83ba4b2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.c @@ -0,0 +1,365 @@ +/** @file
+ This file provides services for PEI policy default initialization
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PeiSaPolicyLibrary.h"
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/CpuPlatformLib.h>
+#include <MrcTypes.h>
+#include "MrcInterface.h"
+
+
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+extern EFI_GUID gGraphicsPeiConfigGuid;
+extern EFI_GUID gVtdConfigGuid;
+
+//
+// Function call to Load defaults for Individial IP Blocks
+//
+VOID
+LoadSaMiscPeiPreMemDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+
+ MiscPeiPreMemConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Name = %g\n", &MiscPeiPreMemConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MiscPeiPreMemConfig->Header.GuidHob.Header.HobLength));
+}
+
+VOID
+LoadVtdDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ VTD_CONFIG *Vtd;
+
+ Vtd = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "Vtd->Header.GuidHob.Name = %g\n", &Vtd->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "Vtd->Header.GuidHob.Header.HobLength = 0x%x\n", Vtd->Header.GuidHob.Header.HobLength));
+
+ //
+ // Initialize the Vtd Configuration
+ //
+ Vtd->BaseAddress[0] = 0xFED90000;
+ Vtd->BaseAddress[1] = 0xFED91000;
+}
+
+VOID
+LoadGraphichsPeiDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_PEI_CONFIG *GtConfig;
+
+ GtConfig = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "GtConfig->Header.GuidHob.Name = %g\n", &GtConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "GtConfig->Header.GuidHob.Header.HobLength = 0x%x\n", GtConfig->Header.GuidHob.Header.HobLength));
+}
+
+VOID
+LoadMemConfigNoCrcDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+
+ MemConfigNoCrc = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "MemConfigNoCrc->Header.GuidHob.Name = %g\n", &MemConfigNoCrc->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "MemConfigNoCrc->Header.GuidHob.Header.HobLength = 0x%x\n", MemConfigNoCrc->Header.GuidHob.Header.HobLength));
+ //
+ // Allocating memory space for pointer structures inside MemConfigNoCrc
+ //
+ MemConfigNoCrc->SpdData = (SPD_DATA_BUFFER *) AllocateZeroPool (sizeof (SPD_DATA_BUFFER));
+ ASSERT (MemConfigNoCrc->SpdData != NULL);
+ if (MemConfigNoCrc->SpdData == NULL) {
+ return;
+ }
+
+ MemConfigNoCrc->DqByteMap = (SA_MEMORY_DQ_MAPPING *) AllocateZeroPool (sizeof (SA_MEMORY_DQ_MAPPING));
+ ASSERT (MemConfigNoCrc->DqByteMap != NULL);
+ if (MemConfigNoCrc->DqByteMap == NULL) {
+ return;
+ }
+
+ MemConfigNoCrc->DqsMap = (SA_MEMORY_DQS_MAPPING *) AllocateZeroPool (sizeof (SA_MEMORY_DQS_MAPPING));
+ ASSERT (MemConfigNoCrc->DqsMap != NULL);
+ if (MemConfigNoCrc->DqsMap == NULL) {
+ return;
+ }
+
+ MemConfigNoCrc->RcompData = (SA_MEMORY_RCOMP *) AllocateZeroPool (sizeof (SA_MEMORY_RCOMP));
+ ASSERT (MemConfigNoCrc->RcompData != NULL);
+ if (MemConfigNoCrc->RcompData == NULL) {
+ return;
+ }
+
+ //
+ // Set PlatformMemory Size
+ //
+ MemConfigNoCrc->PlatformMemorySize = PcdGet32 (PcdPeiMinMemorySize);
+
+ MemConfigNoCrc->SerialDebugLevel = 3; //< Enable MRC debug message
+
+}
+
+
+VOID
+LoadMemConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ MEMORY_CONFIGURATION *MemConfig;
+ CPU_SKU CpuSku;
+ UINT16 DeviceId;
+ BOOLEAN HasEdram;
+
+ CpuSku = GetCpuSku ();
+ DeviceId = MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID);
+ HasEdram = ((AsmReadMsr64 (MSR_PLATFORM_INFO) & B_PLATFORM_INFO_EDRAM_EN) != 0);
+
+
+ MemConfig = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "MemConfig->Header.GuidHob.Name = %g\n", &MemConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "MemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength));
+ //
+ // Initialize the Memory Configuration
+ //
+ MemConfig->EccSupport = 1;
+ MemConfig->ScramblerSupport = 1;
+ MemConfig->PowerDownMode = 0xFF;
+ MemConfig->RankInterleave = TRUE;
+ MemConfig->EnhancedInterleave = TRUE;
+ MemConfig->CmdTriStateDis = 0;
+ MemConfig->EnCmdRate = 3;
+ MemConfig->AutoSelfRefreshSupport = TRUE;
+ MemConfig->ExtTemperatureSupport = TRUE;
+
+ //
+ // Thermal Management Configuration
+ //
+ MemConfig->ThermalManagement = 1;
+ //
+ // Channel Hash Configuration
+ //
+ MemConfig->ChHashEnable = TRUE;
+ MemConfig->ChHashMask = ((CpuSku == EnumCpuUlt) && (HasEdram)) ? 0x30D0 : 0x30C8;
+ MemConfig->ChHashInterleaveBit = 2;
+ //
+ // Options for Thermal settings
+ //
+ MemConfig->EnablePwrDn = 1;
+ MemConfig->EnablePwrDnLpddr = 1;
+ MemConfig->DdrThermalSensor = 1;
+
+ MemConfig->EnergyScaleFact = 3;
+ MemConfig->WarmThresholdCh0Dimm0 = 0xFF;
+ MemConfig->WarmThresholdCh0Dimm1 = 0xFF;
+ MemConfig->WarmThresholdCh1Dimm0 = 0xFF;
+ MemConfig->WarmThresholdCh1Dimm1 = 0xFF;
+ MemConfig->HotThresholdCh0Dimm0 = 0xFF;
+ MemConfig->HotThresholdCh0Dimm1 = 0xFF;
+ MemConfig->HotThresholdCh1Dimm0 = 0xFF;
+ MemConfig->HotThresholdCh1Dimm1 = 0xFF;
+ MemConfig->WarmBudgetCh0Dimm0 = 0xFF;
+ MemConfig->WarmBudgetCh0Dimm1 = 0xFF;
+ MemConfig->WarmBudgetCh1Dimm0 = 0xFF;
+ MemConfig->WarmBudgetCh1Dimm1 = 0xFF;
+ MemConfig->HotBudgetCh0Dimm0 = 0xFF;
+ MemConfig->HotBudgetCh0Dimm1 = 0xFF;
+ MemConfig->HotBudgetCh1Dimm0 = 0xFF;
+ MemConfig->HotBudgetCh1Dimm1 = 0xFF;
+
+ MemConfig->SrefCfgEna = 1;
+ MemConfig->SrefCfgIdleTmr = 0x200;
+ MemConfig->ThrtCkeMinTmr = 0x30;
+ MemConfig->ThrtCkeMinDefeatLpddr = 1;
+ MemConfig->ThrtCkeMinTmrLpddr = 0x40;
+
+ //
+ // CA Vref routing: board-dependent
+ // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
+ // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
+ // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
+ //
+ //MemConfig->CaVrefConfig = 0;
+
+ MemConfig->VttTermination = ((CpuSku == EnumCpuUlx) || (CpuSku == EnumCpuUlt));
+ MemConfig->VttCompForVsshi = 1;
+
+ MemConfig->McLock = TRUE;
+
+ MemConfig->GdxcIotSize = 4;
+ MemConfig->GdxcMotSize = 12;
+
+ //
+ // MRC training steps
+ //
+ MemConfig->ERDMPRTC2D = 1;
+ MemConfig->SOT = 1;
+ MemConfig->RDMPRT = 1;
+ MemConfig->RCVET = 1;
+ MemConfig->JWRL = 1;
+ MemConfig->EWRTC2D = 1;
+ MemConfig->ERDTC2D = 1;
+ MemConfig->WRTC1D = 1;
+ MemConfig->WRVC1D = 1;
+ MemConfig->RDTC1D = 1;
+ MemConfig->DIMMODTT = 1;
+ MemConfig->DIMMRONT = 1;
+ MemConfig->WRSRT = 1;
+ MemConfig->RDODTT = 1;
+ MemConfig->RDEQT = 1;
+ MemConfig->RDAPT = 1;
+ MemConfig->WRTC2D = 1;
+ MemConfig->RDTC2D = 1;
+ MemConfig->CMDVC = 1;
+ MemConfig->WRVC2D = 1;
+ MemConfig->RDVC2D = 1;
+ MemConfig->LCT = 1;
+ MemConfig->RTL = 1;
+ MemConfig->TAT = 1;
+ MemConfig->ALIASCHK = 1;
+ MemConfig->RCVENC1D = 1;
+ MemConfig->RMC = 1;
+ MemConfig->CMDSR = 1;
+ MemConfig->CMDDSEQ = 1;
+ MemConfig->CMDNORM = 1;
+ MemConfig->EWRDSEQ = 1;
+
+ // MrcFastBoot enabled by default
+ MemConfig->MrcFastBoot = TRUE;
+ MemConfig->RemapEnable = TRUE;
+ MemConfig->BClkFrequency = 100 * 1000 * 1000;
+
+ MemConfig->Vc1ReadMeter = TRUE;
+ MemConfig->Vc1ReadMeterTimeWindow = 0x320;
+ MemConfig->Vc1ReadMeterThreshold = 0x118;
+ MemConfig->StrongWkLeaker = 7;
+
+ MemConfig->MobilePlatform = (IS_SA_DEVICE_ID_MOBILE (DeviceId)) ? TRUE : FALSE;
+ MemConfig->PciIndex = 0xCF8;
+ MemConfig->PciData = 0xCFC;
+ MemConfig->CkeRankMapping = 0xAA;
+ //
+ // SA GV: 0 - Disabled, 1 - FixedLow, 2 - FixedHigh, 3 - Enabled
+ //
+ //
+ // Current Simics will fail in MRC training when SAGV enabled so need to by default disable SAGV.
+ //
+ MemConfig->SaGv = 3; // This only affects ULX/ULT and CPU steppings C0/J0 and above; otherwise SA GV is disabled.
+
+ MemConfig->Idd3n = 26;
+ MemConfig->Idd3p = 11;
+
+ MemConfig->RhPrevention = TRUE; // Row Hammer prevention.
+ MemConfig->RhSolution = HardwareRhp; // Type of solution to be used for RHP - 0/1 = HardwareRhp/Refresh2x
+ MemConfig->RhActProbability = OneIn2To11; // Activation probability for Hardware RHP
+
+ MemConfig->LpddrMemWriteLatencySet = 1; // Enable LPDDR3 WL Set B if supported by DRAM
+ MemConfig->EvLoaderDelay = 1;
+
+ MemConfig->DllBwEn1 = 1;
+ MemConfig->DllBwEn2 = 2;
+ MemConfig->DllBwEn3 = 2;
+
+ MemConfig->RetrainOnFastFail = 1; // Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, 1 = Enabled
+}
+
+
+static COMPONENT_BLOCK_ENTRY mSaIpBlocksPreMem[] = {
+ { &gSaMiscPeiPreMemConfigGuid, sizeof(SA_MISC_PEI_PREMEM_CONFIG), SA_MISC_PEI_PREMEM_CONFIG_REVISION, LoadSaMiscPeiPreMemDefault },
+ { &gMemoryConfigGuid, sizeof(MEMORY_CONFIGURATION), MEMORY_CONFIG_REVISION, LoadMemConfigDefault },
+ { &gMemoryConfigNoCrcGuid, sizeof(MEMORY_CONFIG_NO_CRC), MEMORY_CONFIG_REVISION, LoadMemConfigNoCrcDefault }
+};
+
+static COMPONENT_BLOCK_ENTRY mSaIpBlocks [] = {
+ {&gGraphicsPeiConfigGuid, sizeof (GRAPHICS_PEI_CONFIG), GRAPHICS_PEI_CONFIG_REVISION, LoadGraphichsPeiDefault},
+ {&gVtdConfigGuid, sizeof (VTD_CONFIG), VTD_CONFIG_REVISION, LoadVtdDefault}
+};
+
+/**
+ Get SA config block table total size.
+
+ @retval Size of SA config block table
+**/
+UINT16
+EFIAPI
+SaGetConfigBlockTotalSize (
+ VOID
+ )
+{
+ return GetComponentConfigBlockTotalSize (&mSaIpBlocks[0], sizeof (mSaIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
+}
+
+/**
+ Get SA config block table total size.
+
+ @retval Size of SA config block table
+**/
+UINT16
+EFIAPI
+SaGetConfigBlockTotalSizePreMem (
+ VOID
+ )
+{
+ return GetComponentConfigBlockTotalSize (&mSaIpBlocksPreMem[0], sizeof (mSaIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY));
+}
+
+/**
+ SaAddConfigBlocksPreMem add all SA config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SaAddConfigBlocksPreMem (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SA AddConfigBlocks. TotalBlockCount = 0x%x\n", sizeof (mSaIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)));
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress, &mSaIpBlocksPreMem[0], sizeof (mSaIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY));
+ if (Status == EFI_SUCCESS) {
+ SaLoadSamplePolicyPreMem (ConfigBlockTableAddress);
+ }
+ return Status;
+}
+
+/**
+ SaAddConfigBlocks add all SA config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SaAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ DEBUG ((DEBUG_INFO, "SA AddConfigBlocks. TotalBlockCount = 0x%x\n", sizeof (mSaIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)));
+
+ return AddComponentConfigBlocks (ConfigBlockTableAddress, &mSaIpBlocks[0], sizeof (mSaIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf new file mode 100644 index 0000000000..0afd31b584 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf @@ -0,0 +1,72 @@ +## @file
+# Component description file for the PeiSaPolicy library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSaPolicyLib
+FILE_GUID = d7022865-ef1b-449d-8c3f-ac36488c408b
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = PeiSaPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+CpuMailboxLib
+SiConfigBlockLib
+RngLib
+SmbusLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+gSiPkgTokenSpaceGuid.PcdTsegSize
+gSiPkgTokenSpaceGuid.PcdMchBaseAddress
+gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
+gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize
+
+[Sources]
+PeiSaPolicyLib.c
+PeiSaPolicyLibrary.h
+MrcOemPlatform.c
+MrcOemPlatform.h
+SaPrintPolicy.c
+PeiSaPolicyLibSample.c
+
+[Sources.IA32]
+Ia32/MrcOemPlatform.asm | MSFT
+Ia32/MrcOemPlatform.S | GCC
+# Ia32/MrcOemPlatform.nasm | GCC # To support Nasm
+
+[Ppis]
+gSiPreMemPolicyPpiGuid ## CONSUMES
+gSiPolicyPpiGuid ## CONSUMES
+
+[Guids]
+gSaMiscPeiPreMemConfigGuid ## PRODUCES
+gMemoryConfigGuid ## PRODUCES
+gMemoryConfigNoCrcGuid ## PRODUCES
+gGraphicsPeiConfigGuid ## CONSUMES
+gVtdConfigGuid ## PRODUCES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLibSample.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLibSample.c new file mode 100644 index 0000000000..a65349b29c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLibSample.c @@ -0,0 +1,281 @@ +/** @file
+ This file provides services for Sample PEI policy default initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <SaPolicyCommon.h>
+#include "PeiSaPolicyLibrary.h"
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include "MrcOemPlatform.h"
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/RngLib.h>
+#include <Library/CpuMailboxLib.h>
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP, SKL SDS.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSkl[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+ { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+ { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0xFF, 0x00 } // CA Vref is one for all bytes
+ },
+ // Channel 1:
+ {
+ { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+ { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+ { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0xFF, 0x00 } // CA Vref is one for all bytes
+ }
+};
+
+//
+// DQS byte swizzling between CPU and DRAM - for SKL RVP1, RVP3, RVP13
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
+ { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
+};
+
+//
+// Reference RCOMP resistors on motherboard - for SKL RVP1/RVP3
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mRcompResistorSklRvp1[SA_MRC_MAX_RCOMP] = { 200, 81, 162 };
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP1/RVP3
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mRcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
+
+/**
+ Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32
+ or Elpida EDF8132A1MC-GD-F
+ or Samsung K4E8E304EB-EGCE
+ 1600, 12-15-15-34
+ 2 rank per channel, 2 SDRAMs per rank, 4x4Gb = 2GB total per channel
+**/
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] = {
+ 0x24, ///< 0 Number of Serial PD Bytes Written / SPD Device Size
+ 0x20, ///< 1 SPD Revision
+ 0x0F, ///< 2 DRAM Device Type
+ 0x0E, ///< 3 Module Type
+ 0x14, ///< 4 SDRAM Density and Banks: 8 Banks, 4 Gb SDRAM density
+ 0x11, ///< 5 SDRAM Addressing: 14 Rows, 10 Columns
+ 0x95, ///< 6 SDRAM Package Type: DDP, 1 Channel per die, Signal Loading Matrix 1
+ 0x00, ///< 7 SDRAM Optional Features
+ 0x00, ///< 8 SDRAM Thermal and Refresh Options
+ 0x00, ///< 9 Other SDRAM Optional Features
+ 0x00, ///< 10 Reserved - must be coded as 0x00
+ 0x03, ///< 11 Module Nominal Voltage, VDD
+ 0x0B, ///< 12 Module Organization, SDRAM width: 32 bits, 2 Ranks
+ 0x23, ///< 13 Module Memory Bus Width: 2 channels, 64 bit channel bus width
+ 0x00, ///< 14 Module Thermal Sensor
+ 0x00, ///< 15 Extended Module Type
+ 0x00, ///< 16 Reserved - must be coded as 0x00
+ 0x00, ///< 17 Timebases
+ 0x0A, ///< 18 SDRAM Minimum Cycle Time (tCKmin)
+ 0xFF, ///< 19 SDRAM Minimum Cycle Time (tCKmax)
+ 0x54, ///< 20 CAS Latencies Supported, First Byte (tCk): 12 10 8
+ 0x00, ///< 21 CAS Latencies Supported, Second Byte
+ 0x00, ///< 22 CAS Latencies Supported, Third Byte
+ 0x00, ///< 23 CAS Latencies Supported, Fourth Byte
+ 0x78, ///< 24 Minimum CAS Latency Time (tAAmin)
+ 0x00, ///< 25 Read and Write Latency Set Options
+ 0x90, ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0xA8, ///< 27 Minimum Row Precharge Delay Time for all banks (tRPab)
+ 0x90, ///< 28 Minimum Row Precharge Delay Time per bank (tRPpb)
+ 0x10, ///< 29 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Least Significant Byte
+ 0x04, ///< 30 Minimum Refresh Recovery Delay Time for all banks (tRFCab), Most Significant Byte
+ 0xE0, ///< 31 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Least Significant Byte
+ 0x01, ///< 32 Minimum Refresh Recovery Delay Time for per bank (tRFCpb), Most Significant Byte
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bit Mapping
+ 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bit Mapping
+ 0, 0, ///< 78 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 Fine Offset for Minimum Row Precharge Delay Time per bank (tRPpb)
+ 0x00, ///< 121 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+ 0x00, ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ 0x00, ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ 0x7F, ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
+ 0x00, ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x55, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 352 DRAM Stepping
+ 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+};
+
+#define SaIoRead8 IoRead8
+#define SaIoRead16 IoRead16
+#define SaIoRead32 IoRead32
+#define SaIoWrite8 IoWrite8
+#define SaIoWrite16 IoWrite16
+#define SaIoWrite32 IoWrite32
+#define SaCopyMem CopyMem
+#define SaSetMem SetMem
+#define SaLShiftU64 LShiftU64
+#define SaRShiftU64 RShiftU64
+#define SaMultU64x32 MultU64x32
+
+/**
+ SaLoadSamplePolicyPreMem - Load some policy default for reference board.
+
+ @param[in] ConfigBlockTableAddress The pointer for SA config blocks
+
+**/
+VOID
+SaLoadSamplePolicyPreMem (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ SA_FUNCTION_CALLS *MemCall;
+ EFI_STATUS Status;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+
+ MemConfigNoCrc = NULL;
+ Status = GetConfigBlock (ConfigBlockTableAddress, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR (Status);
+
+ if (MemConfigNoCrc == NULL) {
+ return;
+ }
+
+ DEBUG ((DEBUG_INFO, "Applying Sample policy defaults for RVP3\n"));
+ MemCall = &MemConfigNoCrc->SaCall;
+ MemCall->IoRead8 = &SaIoRead8;
+ MemCall->IoRead16 = &SaIoRead16;
+ MemCall->IoRead32 = &SaIoRead32;
+ MemCall->IoWrite8 = &SaIoWrite8;
+ MemCall->IoWrite16 = &SaIoWrite16;
+ MemCall->IoWrite32 = &SaIoWrite32;
+ MemCall->MmioRead8 = &MmioRead8;
+ MemCall->MmioRead16 = &MmioRead16;
+ MemCall->MmioRead32 = &MmioRead32;
+ MemCall->MmioRead64 = &SaMmioRead64;
+ MemCall->MmioWrite8 = &MmioWrite8;
+ MemCall->MmioWrite16 = &MmioWrite16;
+ MemCall->MmioWrite32 = &MmioWrite32;
+ MemCall->MmioWrite64 = &SaMmioWrite64;
+ MemCall->SmbusRead8 = &SmBusReadDataByte;
+ MemCall->SmbusRead16 = &SmBusReadDataWord;
+ MemCall->SmbusWrite8 = &SmBusWriteDataByte;
+ MemCall->SmbusWrite16 = &SmBusWriteDataWord;
+ MemCall->GetPciDeviceAddress = &GetPciDeviceAddress;
+ MemCall->GetPcieDeviceAddress = &GetPcieDeviceAddress;
+ MemCall->GetRtcTime = &GetRtcTime;
+ MemCall->GetCpuTime = &GetCpuTime;
+ MemCall->CopyMem = &SaCopyMem;
+ MemCall->SetMem = &SaSetMem;
+ MemCall->SetMemWord = &SetMemWord;
+ MemCall->SetMemDword = &SetMemDword;
+ MemCall->LeftShift64 = &SaLShiftU64;
+ MemCall->RightShift64 = &SaRShiftU64;
+ MemCall->MultU64x32 = &SaMultU64x32;
+ MemCall->DivU64x64 = &DivU64x64Remainder;
+ MemCall->GetSpdData = &GetSpdData;
+ MemCall->GetRandomNumber = &GetRandomNumber32;
+ MemCall->CpuMailboxRead = &MailboxRead;
+ MemCall->CpuMailboxWrite = &MailboxWrite;
+ MemCall->GetMemoryVdd = &GetMemoryVdd;
+ MemCall->SetMemoryVdd = &SetMemoryVdd;
+ MemCall->CheckPoint = &CheckPoint;
+ MemCall->DebugHook = &DebugHook;
+ MemCall->DebugPrint = &SaDebugPrint;
+ MemCall->GetRtcCmos = &PeiRtcRead;
+ MemCall->ReadMsr64 = &AsmReadMsr64;
+ MemCall->WriteMsr64 = &AsmWriteMsr64;
+ MemCall->MrcReturnFromSmc = &ReturnFromSmc;
+ MemCall->MrcDramReset = &SaDramReset;
+
+ //
+ // RCOMP resistors and target values: board-dependent
+ //
+ CopyMem ((VOID *) MemConfigNoCrc->RcompData->RcompResistor, mRcompResistorSklRvp1, sizeof (mRcompResistorSklRvp1));
+ CopyMem ((VOID *) MemConfigNoCrc->RcompData->RcompTarget, mRcompTargetSklRvp1, sizeof (mRcompTargetSklRvp1));
+
+ CopyMem ((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], mSkylakeRvp3Spd, sizeof (mSkylakeRvp3Spd));
+ CopyMem ((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], mSkylakeRvp3Spd, sizeof (mSkylakeRvp3Spd));
+ CopyMem ((VOID *) MemConfigNoCrc->DqByteMap, mDqByteMapSkl, sizeof (UINT8) * SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX *2);
+ CopyMem ((VOID *) MemConfigNoCrc->DqsMap, mDqsMapCpu2DramSklRvp, sizeof (UINT8) * SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO_ECC);
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h new file mode 100644 index 0000000000..e7fe3d2fcf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h @@ -0,0 +1,44 @@ +/** @file
+ Header file for the PeiSaPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_SA_POLICY_LIBRARY_H_
+#define _PEI_SA_POLICY_LIBRARY_H_
+
+#include <CpuRegs.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/SmbusLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/SiConfigBlockLib.h>
+
+/**
+ SaLoadSamplePolicyPreMem - Load some policy default for reference board.
+
+ @param[in] ConfigBlockTableAddress The pointer for SA config blocks
+
+**/
+VOID
+SaLoadSamplePolicyPreMem (
+ IN VOID *ConfigBlockTableAddress
+ );
+#endif // _PEI_SA_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c new file mode 100644 index 0000000000..0a6ddb8a8f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPrintPolicy.c @@ -0,0 +1,326 @@ +/** @file
+ This file provides service for PEI phase policy printing
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PeiSaPolicyLibrary.h"
+#include <Library/GpioNativeLib.h>
+
+/**
+ This function prints the PEI phase PreMem policy.
+
+ @param[in] SiPolicyPreMemPpi - Instance of SI_PREMEM_POLICY_PPI
+**/
+VOID
+EFIAPI
+SaPrintPolicyPpiPreMem (
+ IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ INTN Index;
+ INTN Index2;
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIGURATION *MemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+
+ //
+ // Get requisite IP Config Blocks which needs to be used here
+ //
+ Status = GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print BEGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.Header.Revision));
+ ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision == SI_PREMEM_POLICY_REVISION);
+
+ DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG -----------------\n"));
+ DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revision));
+ ASSERT (MiscPeiPreMemConfig->Header.Revision == SA_MISC_PEI_PREMEM_CONFIG_REVISION);
+ DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS));
+ for (Index = 0; Index < SA_MC_MAX_SOCKETS; Index++) {
+ DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Index]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+
+ DEBUG ((DEBUG_INFO, " MchBar : 0x%x\n", MiscPeiPreMemConfig->MchBar));
+ DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------------------------\n"));
+ DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig->Header.Revision));
+ ASSERT (MemConfig->Header.Revision == MEMORY_CONFIG_REVISION);
+ DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig->Header.GuidHob.Header.HobLength));
+ DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig->HobBufferSize));
+ DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig->EccSupport));
+ DEBUG ((DEBUG_INFO, " DdrFreqLimit: %d\n", MemConfig->DdrFreqLimit));
+ DEBUG ((DEBUG_INFO, " SpdProfileSelected : 0x%x\n", MemConfig->SpdProfileSelected));
+ DEBUG ((DEBUG_INFO, " tCL : 0x%x\n", MemConfig->tCL));
+ DEBUG ((DEBUG_INFO, " tRCDtRP : 0x%x\n", MemConfig->tRCDtRP));
+ DEBUG ((DEBUG_INFO, " tRAS : 0x%x\n", MemConfig->tRAS));
+ DEBUG ((DEBUG_INFO, " tWR : 0x%x\n", MemConfig->tWR));
+ DEBUG ((DEBUG_INFO, " tRFC : 0x%x\n", MemConfig->tRFC));
+ DEBUG ((DEBUG_INFO, " tRRD : 0x%x\n", MemConfig->tRRD));
+ DEBUG ((DEBUG_INFO, " tWTR : 0x%x\n", MemConfig->tWTR));
+ DEBUG ((DEBUG_INFO, " tRTP : 0x%x\n", MemConfig->tRTP));
+ DEBUG ((DEBUG_INFO, " tFAW : 0x%x\n", MemConfig->tFAW));
+ DEBUG ((DEBUG_INFO, " tCWL : 0x%x\n", MemConfig->tCWL));
+ DEBUG ((DEBUG_INFO, " tREFI : 0x%x\n", MemConfig->tREFI));
+ DEBUG ((DEBUG_INFO, " NModeSupport : 0x%x\n", MemConfig->NModeSupport));
+ DEBUG ((DEBUG_INFO, " VddVoltage : %d\n", MemConfig->VddVoltage));
+ DEBUG ((DEBUG_INFO, " ThermalManagement : 0x%x\n", MemConfig->ThermalManagement));
+ DEBUG ((DEBUG_INFO, " PeciInjectedTemp : 0x%x\n", MemConfig->PeciInjectedTemp));
+ DEBUG ((DEBUG_INFO, " ExttsViaTsOnBoard : 0x%x\n", MemConfig->ExttsViaTsOnBoard));
+ DEBUG ((DEBUG_INFO, " ExttsViaTsOnDimm : 0x%x\n", MemConfig->ExttsViaTsOnDimm));
+ DEBUG ((DEBUG_INFO, " VirtualTempSensor : 0x%x\n", MemConfig->VirtualTempSensor));
+
+ DEBUG ((DEBUG_INFO, " DisableDimmChannel[%d] :", SA_MC_MAX_CHANNELS));
+ for (Index = 0; Index < SA_MC_MAX_CHANNELS; Index++) {
+ DEBUG ((DEBUG_INFO, " 0x%x", MemConfig->DisableDimmChannel[Index]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+ DEBUG ((DEBUG_INFO, " RemapEnable : 0x%x\n", MemConfig->RemapEnable));
+ DEBUG ((DEBUG_INFO, " ScramblerSupport : 0x%x\n", MemConfig->ScramblerSupport));
+ DEBUG ((DEBUG_INFO, " SerialDebug : 0x%x\n", MemConfigNoCrc->SerialDebugLevel));
+ DEBUG ((DEBUG_INFO, " McLock : 0x%x\n", MemConfig->McLock));
+ DEBUG ((DEBUG_INFO, " ProbelessTrace : 0x%x\n", MemConfig->ProbelessTrace));
+ DEBUG ((DEBUG_INFO, " GdxcIotSize : 0x%x\n", MemConfig->GdxcIotSize));
+ DEBUG ((DEBUG_INFO, " GdxcMotSize : 0x%x\n", MemConfig->GdxcMotSize));
+
+ DEBUG ((DEBUG_INFO, " ECT : 0x%x\n", MemConfig->ECT));
+ DEBUG ((DEBUG_INFO, " SOT : 0x%x\n", MemConfig->SOT));
+ DEBUG ((DEBUG_INFO, " ERDMPRTC2D : 0x%x\n", MemConfig->ERDMPRTC2D));
+ DEBUG ((DEBUG_INFO, " RDMPRT : 0x%x\n", MemConfig->RDMPRT));
+ DEBUG ((DEBUG_INFO, " RCVET : 0x%x\n", MemConfig->RCVET));
+ DEBUG ((DEBUG_INFO, " JWRL : 0x%x\n", MemConfig->JWRL));
+ DEBUG ((DEBUG_INFO, " EWRDSEQ : 0x%x\n", MemConfig->EWRDSEQ));
+ DEBUG ((DEBUG_INFO, " EWRTC2D : 0x%x\n", MemConfig->EWRTC2D));
+ DEBUG ((DEBUG_INFO, " ERDTC2D : 0x%x\n", MemConfig->ERDTC2D));
+ DEBUG ((DEBUG_INFO, " WRTC1D : 0x%x\n", MemConfig->WRTC1D));
+ DEBUG ((DEBUG_INFO, " WRVC1D : 0x%x\n", MemConfig->WRVC1D));
+ DEBUG ((DEBUG_INFO, " RDTC1D : 0x%x\n", MemConfig->RDTC1D));
+ DEBUG ((DEBUG_INFO, " DIMMODTT : 0x%x\n", MemConfig->DIMMODTT));
+ DEBUG ((DEBUG_INFO, " DIMMRONT : 0x%x\n", MemConfig->DIMMRONT));
+ DEBUG ((DEBUG_INFO, " WRDSEQT : 0x%x\n", MemConfig->WRDSEQT));
+ DEBUG ((DEBUG_INFO, " WRSRT : 0x%x\n", MemConfig->WRSRT));
+ DEBUG ((DEBUG_INFO, " RDODTT : 0x%x\n", MemConfig->RDODTT));
+ DEBUG ((DEBUG_INFO, " RDEQT : 0x%x\n", MemConfig->RDEQT));
+ DEBUG ((DEBUG_INFO, " RDAPT : 0x%x\n", MemConfig->RDAPT));
+ DEBUG ((DEBUG_INFO, " WRTC2D : 0x%x\n", MemConfig->WRTC2D));
+ DEBUG ((DEBUG_INFO, " RDTC2D : 0x%x\n", MemConfig->RDTC2D));
+ DEBUG ((DEBUG_INFO, " WRVC2D : 0x%x\n", MemConfig->WRVC2D));
+ DEBUG ((DEBUG_INFO, " RDVC2D : 0x%x\n", MemConfig->RDVC2D));
+ DEBUG ((DEBUG_INFO, " CMDVC : 0x%x\n", MemConfig->CMDVC));
+ DEBUG ((DEBUG_INFO, " LCT : 0x%x\n", MemConfig->LCT));
+ DEBUG ((DEBUG_INFO, " RTL : 0x%x\n", MemConfig->RTL));
+ DEBUG ((DEBUG_INFO, " TAT : 0x%x\n", MemConfig->TAT));
+ DEBUG ((DEBUG_INFO, " RMT : 0x%x\n", MemConfig->RMT));
+ DEBUG ((DEBUG_INFO, " MEMTST : 0x%x\n", MemConfig->MEMTST));
+ DEBUG ((DEBUG_INFO, " ALIASCHK : 0x%x\n", MemConfig->ALIASCHK));
+ DEBUG ((DEBUG_INFO, " RCVENC1D : 0x%x\n", MemConfig->RCVENC1D));
+ DEBUG ((DEBUG_INFO, " RMC : 0x%x\n", MemConfig->RMC));
+ DEBUG ((DEBUG_INFO, " WRDSUDT : 0x%x\n", MemConfig->WRDSUDT));
+ DEBUG ((DEBUG_INFO, " CMDSR: %d\n CMDDSEQ: %d\n CMDNORM: %d\n",
+ MemConfig->CMDSR, MemConfig->CMDDSEQ, MemConfig->CMDNORM));
+
+ DEBUG ((DEBUG_INFO, " VddSettleWaitTime : 0x%x\n", MemConfig->VddSettleWaitTime));
+ DEBUG ((DEBUG_INFO, " RefClk : 0x%x\n", MemConfig->RefClk));
+ DEBUG ((DEBUG_INFO, " Ratio : 0x%x\n", MemConfig->Ratio));
+ DEBUG ((DEBUG_INFO, " OddRatioMode : 0x%x\n", MemConfig->OddRatioMode));
+ DEBUG ((DEBUG_INFO, " MrcTimeMeasure : 0x%x\n", MemConfig->MrcTimeMeasure));
+ DEBUG ((DEBUG_INFO, " MrcFastBoot : 0x%x\n", MemConfig->MrcFastBoot));
+ DEBUG ((DEBUG_INFO, " DqPinsInterleaved : 0x%x\n", MemConfig->DqPinsInterleaved));
+ DEBUG ((DEBUG_INFO, " MrcSafeConfig : 0x%x\n", MemConfig->MrcSafeConfig));
+
+ DEBUG ((DEBUG_INFO, " PowerDownMode : 0x%x\n", MemConfig->PowerDownMode));
+ DEBUG ((DEBUG_INFO, " PwdwnIdleCounter : 0x%x\n", MemConfig->PwdwnIdleCounter));
+ DEBUG ((DEBUG_INFO, " RankInterleave : 0x%x\n", MemConfig->RankInterleave));
+ DEBUG ((DEBUG_INFO, " EnhancedInterleave : 0x%x\n", MemConfig->EnhancedInterleave));
+ DEBUG ((DEBUG_INFO, " WeaklockEn : 0x%x\n", MemConfig->WeaklockEn));
+ DEBUG ((DEBUG_INFO, " EnCmdRate : 0x%x\n", MemConfig->EnCmdRate));
+ DEBUG ((DEBUG_INFO, " CmdTriStateDis : 0x%x\n", MemConfig->CmdTriStateDis));
+ DEBUG ((DEBUG_INFO, " BClkFrequency: %d Hz\n", MemConfig->BClkFrequency));
+ DEBUG ((DEBUG_INFO, " MemoryTrace : 0x%x\n", MemConfig->MemoryTrace));
+ DEBUG ((DEBUG_INFO, " ChHashEnable : 0x%x\n", MemConfig->ChHashEnable));
+ DEBUG ((DEBUG_INFO, " ChHashMask : 0x%x\n", MemConfig->ChHashMask));
+ DEBUG ((DEBUG_INFO, " ChHashInterleaveBit : 0x%x\n", MemConfig->ChHashInterleaveBit));
+ DEBUG ((DEBUG_INFO, " EnableExtts : 0x%x\n", MemConfig->EnableExtts));
+ DEBUG ((DEBUG_INFO, " EnableCltm : 0x%x\n", MemConfig->EnableCltm));
+ DEBUG ((DEBUG_INFO, " EnableOltm : 0x%x\n", MemConfig->EnableOltm));
+ DEBUG ((DEBUG_INFO, " EnablePwrDn : 0x%x\n", MemConfig->EnablePwrDn));
+ DEBUG ((DEBUG_INFO, " EnablePwrDnLpddr : 0x%x\n", MemConfig->EnablePwrDnLpddr));
+ DEBUG ((DEBUG_INFO, " Refresh2X : 0x%x\n", MemConfig->Refresh2X));
+ DEBUG ((DEBUG_INFO, " DdrThermalSensor : 0x%x\n", MemConfig->DdrThermalSensor));
+ DEBUG ((DEBUG_INFO, " LockPTMregs : 0x%x\n", MemConfig->LockPTMregs));
+ DEBUG ((DEBUG_INFO, " UserPowerWeightsEn : 0x%x\n", MemConfig->UserPowerWeightsEn));
+ DEBUG ((DEBUG_INFO, " EnergyScaleFact : 0x%x\n", MemConfig->EnergyScaleFact));
+ DEBUG ((DEBUG_INFO, " RaplPwrFlCh1 : 0x%x\n", MemConfig->RaplPwrFlCh1));
+ DEBUG ((DEBUG_INFO, " RaplPwrFlCh0 : 0x%x\n", MemConfig->RaplPwrFlCh0));
+ DEBUG ((DEBUG_INFO, " RaplLim2Lock : 0x%x\n", MemConfig->RaplLim2Lock));
+ DEBUG ((DEBUG_INFO, " RaplLim2WindX : 0x%x\n", MemConfig->RaplLim2WindX));
+ DEBUG ((DEBUG_INFO, " RaplLim2WindY : 0x%x\n", MemConfig->RaplLim2WindY));
+ DEBUG ((DEBUG_INFO, " RaplLim2Ena : 0x%x\n", MemConfig->RaplLim2Ena));
+ DEBUG ((DEBUG_INFO, " RaplLim2Pwr : 0x%x\n", MemConfig->RaplLim2Pwr));
+ DEBUG ((DEBUG_INFO, " RaplLim1WindX : 0x%x\n", MemConfig->RaplLim1WindX));
+ DEBUG ((DEBUG_INFO, " RaplLim1WindY : 0x%x\n", MemConfig->RaplLim1WindY));
+ DEBUG ((DEBUG_INFO, " RaplLim1Ena : 0x%x\n", MemConfig->RaplLim1Ena));
+ DEBUG ((DEBUG_INFO, " RaplLim1Pwr : 0x%x\n", MemConfig->RaplLim1Pwr));
+ DEBUG ((DEBUG_INFO, " WarmThresholdCh0Dimm0 : 0x%x\n", MemConfig->WarmThresholdCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " WarmThresholdCh0Dimm1 : 0x%x\n", MemConfig->WarmThresholdCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " WarmThresholdCh1Dimm0 : 0x%x\n", MemConfig->WarmThresholdCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " WarmThresholdCh1Dimm1 : 0x%x\n", MemConfig->WarmThresholdCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " HotThresholdCh0Dimm0 : 0x%x\n", MemConfig->HotThresholdCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " HotThresholdCh0Dimm1 : 0x%x\n", MemConfig->HotThresholdCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " HotThresholdCh1Dimm0 : 0x%x\n", MemConfig->HotThresholdCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " HotThresholdCh1Dimm1 : 0x%x\n", MemConfig->HotThresholdCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " WarmBudgetCh0Dimm0 : 0x%x\n", MemConfig->WarmBudgetCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " WarmBudgetCh0Dimm1 : 0x%x\n", MemConfig->WarmBudgetCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " WarmBudgetCh1Dimm0 : 0x%x\n", MemConfig->WarmBudgetCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " WarmBudgetCh1Dimm1 : 0x%x\n", MemConfig->WarmBudgetCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " HotBudgetCh0Dimm0 : 0x%x\n", MemConfig->HotBudgetCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " HotBudgetCh0Dimm1 : 0x%x\n", MemConfig->HotBudgetCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " HotBudgetCh1Dimm0 : 0x%x\n", MemConfig->HotBudgetCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " HotBudgetCh1Dimm1 : 0x%x\n", MemConfig->HotBudgetCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " IdleEnergyCh0Dimm0 : 0x%x\n", MemConfig->IdleEnergyCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " IdleEnergyCh0Dimm1 : 0x%x\n", MemConfig->IdleEnergyCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " IdleEnergyCh1Dimm0 : 0x%x\n", MemConfig->IdleEnergyCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " IdleEnergyCh1Dimm1 : 0x%x\n", MemConfig->IdleEnergyCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " PdEnergyCh0Dimm0 : 0x%x\n", MemConfig->PdEnergyCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " PdEnergyCh0Dimm1 : 0x%x\n", MemConfig->PdEnergyCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " PdEnergyCh1Dimm0 : 0x%x\n", MemConfig->PdEnergyCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " PdEnergyCh1Dimm1 : 0x%x\n", MemConfig->PdEnergyCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " ActEnergyCh0Dimm0 : 0x%x\n", MemConfig->ActEnergyCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " ActEnergyCh0Dimm1 : 0x%x\n", MemConfig->ActEnergyCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " ActEnergyCh1Dimm0 : 0x%x\n", MemConfig->ActEnergyCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " ActEnergyCh1Dimm1 : 0x%x\n", MemConfig->ActEnergyCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " RdEnergyCh0Dimm0 : 0x%x\n", MemConfig->RdEnergyCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " RdEnergyCh0Dimm1 : 0x%x\n", MemConfig->RdEnergyCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " RdEnergyCh1Dimm0 : 0x%x\n", MemConfig->RdEnergyCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " RdEnergyCh1Dimm1 : 0x%x\n", MemConfig->RdEnergyCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " WrEnergyCh0Dimm0 : 0x%x\n", MemConfig->WrEnergyCh0Dimm0));
+ DEBUG ((DEBUG_INFO, " WrEnergyCh0Dimm1 : 0x%x\n", MemConfig->WrEnergyCh0Dimm1));
+ DEBUG ((DEBUG_INFO, " WrEnergyCh1Dimm0 : 0x%x\n", MemConfig->WrEnergyCh1Dimm0));
+ DEBUG ((DEBUG_INFO, " WrEnergyCh1Dimm1 : 0x%x\n", MemConfig->WrEnergyCh1Dimm1));
+ DEBUG ((DEBUG_INFO, " SrefCfgEna : 0x%x\n", MemConfig->SrefCfgEna));
+ DEBUG ((DEBUG_INFO, " SrefCfgIdleTmr : 0x%x\n", MemConfig->SrefCfgIdleTmr));
+ DEBUG ((DEBUG_INFO, " ThrtCkeMinDefeat : 0x%x\n", MemConfig->ThrtCkeMinDefeat));
+ DEBUG ((DEBUG_INFO, " ThrtCkeMinTmr : 0x%x\n", MemConfig->ThrtCkeMinTmr));
+ DEBUG ((DEBUG_INFO, " ThrtCkeMinDefeatLpddr : 0x%x\n", MemConfig->ThrtCkeMinDefeatLpddr));
+ DEBUG ((DEBUG_INFO, " ThrtCkeMinTmrLpddr : 0x%x\n", MemConfig->ThrtCkeMinTmrLpddr));
+ DEBUG ((DEBUG_INFO, " AutoSelfRefreshSupport : 0x%x\n", MemConfig->AutoSelfRefreshSupport));
+ DEBUG ((DEBUG_INFO, " ExtTemperatureSupport : 0x%x\n", MemConfig->ExtTemperatureSupport));
+ DEBUG ((DEBUG_INFO, " MaxRttWr : 0x%x\n", MemConfig->MaxRttWr));
+ DEBUG ((DEBUG_INFO, " MobilePlatform : 0x%x\n", MemConfig->MobilePlatform));
+ DEBUG ((DEBUG_INFO, " Force1Dpc : 0x%x\n", MemConfig->Force1Dpc));
+
+
+ DEBUG ((DEBUG_INFO, " ForceSingleRank : 0x%x\n", MemConfig->ForceSingleRank));
+ DEBUG ((DEBUG_INFO, " PciIndex : 0x%x\n", MemConfig->PciIndex));
+ DEBUG ((DEBUG_INFO, " PciData : 0x%x\n", MemConfig->PciData));
+ DEBUG ((DEBUG_INFO, " CkeRankMapping : 0x%x\n", MemConfig->CkeRankMapping));
+ DEBUG ((DEBUG_INFO, " RhPrevention : 0x%x\n", MemConfig->RhPrevention));
+ DEBUG ((DEBUG_INFO, " RhSolution : 0x%x\n", MemConfig->RhSolution));
+ DEBUG ((DEBUG_INFO, " RhActProbability : 0x%x\n", MemConfig->RhActProbability));
+ DEBUG ((DEBUG_INFO, " VttTermination : 0x%x\n", MemConfig->VttTermination));
+ DEBUG ((DEBUG_INFO, " VttCompForVsshi : 0x%x\n", MemConfig->VttCompForVsshi));
+ DEBUG ((DEBUG_INFO, " BerEnable : 0x%x\n", MemConfig->BerEnable));
+ for (Index = 0; Index < 4; Index++) {
+ DEBUG ((DEBUG_INFO, " BerAddress[%d] : 0x%x\n",Index , MemConfig->BerAddress[Index]));
+ }
+ DEBUG ((DEBUG_INFO, " CleanMemory : 0x%x\n", MemConfigNoCrc->CleanMemory));
+ DEBUG ((DEBUG_INFO, " ExitOnFailure : 0x%x\n", MemConfig->ExitOnFailure));
+ DEBUG ((DEBUG_INFO, " Vc1ReadMeter : 0x%x\n", MemConfig->Vc1ReadMeter));
+ DEBUG ((DEBUG_INFO, " Vc1ReadMeterTimeWindow : 0x%x\n", MemConfig->Vc1ReadMeterTimeWindow));
+ DEBUG ((DEBUG_INFO, " Vc1ReadMeterThreshold : 0x%x\n", MemConfig->Vc1ReadMeterThreshold));
+ DEBUG ((DEBUG_INFO, " SaGv : 0x%x\n", MemConfig->SaGv));
+ DEBUG ((DEBUG_INFO, " FreqSaGvLow : 0x%x\n", MemConfig->FreqSaGvLow));
+ DEBUG ((DEBUG_INFO, " StrongWkLeaker : 0x%x\n", MemConfig->StrongWkLeaker));
+ DEBUG ((DEBUG_INFO, " CaVrefConfig : 0x%x\n", MemConfig->CaVrefConfig));
+ DEBUG ((DEBUG_INFO, " EvLoader : 0x%x\n", MemConfig->EvLoader));
+ DEBUG ((DEBUG_INFO, " EvLoaderDelay : 0x%x\n", MemConfig->EvLoaderDelay));
+ DEBUG ((DEBUG_INFO, " PlatformMemorySize : 0x%x\n", MemConfigNoCrc->PlatformMemorySize));
+ DEBUG ((DEBUG_INFO, " SmramMask : 0x%x\n", MemConfig->SmramMask));
+ DEBUG ((DEBUG_INFO, " DllBwEn0: %d\n DllBwEn1: %d\n DllBwEn2: %d\n DllBwEn3: %d\n",
+ MemConfig->DllBwEn0, MemConfig->DllBwEn1, MemConfig->DllBwEn2, MemConfig->DllBwEn3));
+ DEBUG ((DEBUG_INFO, " RetrainOnFastFail: %d\n ForceOltmOrRefresh2x: %d\n",
+ MemConfig->RetrainOnFastFail, MemConfig->ForceOltmOrRefresh2x));
+ for (Index = 0; Index < SA_MC_MAX_CHANNELS; Index++) {
+ DEBUG ((DEBUG_INFO, " DqByteMapCh%d : ", Index));
+ for (Index2 = 0; Index2 < SA_MRC_ITERATION_MAX; Index2++) {
+ DEBUG ((DEBUG_INFO, "0x%02x ", MemConfigNoCrc->DqByteMap->DqByteMap[Index][Index2][0]));
+ DEBUG ((DEBUG_INFO, "0x%02x ", MemConfigNoCrc->DqByteMap->DqByteMap[Index][Index2][1]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+ }
+ for (Index = 0; Index < SA_MC_MAX_CHANNELS; Index++) {
+ DEBUG ((DEBUG_INFO, " DqsMapCpu2DramCh%d : ", Index));
+ for (Index2 = 0; Index2 < SA_MC_MAX_BYTES_NO_ECC; Index2++) {
+ DEBUG ((DEBUG_INFO, "%d ", MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[Index][Index2]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+ }
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) Print END -----------------\n"));
+ DEBUG_CODE_END ();
+ return;
+}
+
+/**
+ This function prints the PEI phase policy.
+
+ @param[in] SiPolicyPpi - Instance of SI_POLICY_PPI
+**/
+VOID
+EFIAPI
+SaPrintPolicyPpi (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ EFI_STATUS Status;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ INTN Index;
+ VTD_CONFIG *Vtd;
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVtdConfigGuid, (VOID *) &Vtd);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BEGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header.Revision));
+ ASSERT (SiPolicyPpi->TableHeader.Header.Revision == SI_POLICY_REVISION);
+ DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG -----------------\n"));
+ DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision));
+ ASSERT (GtConfig->Header.Revision == GRAPHICS_PEI_CONFIG_REVISION);
+ DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphicsPeimInit));
+ DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr));
+ DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize));
+ DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsConfigPtr));
+ DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG -----------------\n"));
+ DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision));
+ ASSERT (Vtd->Header.Revision == VTD_CONFIG_REVISION);
+ DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable));
+ DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut));
+ DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER));
+ for (Index = 0; Index < SA_VTD_ENGINE_NUMBER; Index++) {
+ DEBUG ((DEBUG_INFO, " 0x%x", Vtd->BaseAddress[Index]));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print END -----------------\n"));
+ DEBUG_CODE_END ();
+ return;
+}
\ No newline at end of file diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcCommonTypes.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcCommonTypes.h new file mode 100644 index 0000000000..792b2ca58d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcCommonTypes.h @@ -0,0 +1,235 @@ +/** @file
+ This file contains the definitions common to the MRC API and other APIs.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MrcCommonTypes_h_
+#define _MrcCommonTypes_h_
+
+#define INT32_MIN (0x80000000)
+#ifndef INT32_MAX //INT32_MAX->Already defined
+#define INT32_MAX (0x7FFFFFFF)
+#endif
+#define INT16_MIN (0x8000)
+#define INT16_MAX (0x7FFF)
+
+///
+/// System boot mode.
+///
+typedef enum {
+ bmCold, ///< Cold boot
+ bmWarm, ///< Warm boot
+ bmS3, ///< S3 resume
+ bmFast, ///< Fast boot
+ MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
+ MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MrcBootMode;
+
+///
+/// DIMM memory package
+/// This enum matches SPD Module Type - SPD byte 3, bits [3:0]
+/// Note that DDR3 and DDR4 have different encoding for some module types
+///
+typedef enum {
+ RDimmMemoryPackage = 1,
+ UDimmMemoryPackage = 2,
+ SoDimmMemoryPackage = 3,
+ MicroDimmMemoryPackageDdr3 = 4,
+ LrDimmMemoryPackageDdr4 = 4,
+ MiniRDimmMemoryPackage = 5,
+ MiniUDimmMemoryPackage = 6,
+ MiniCDimmMemoryPackage = 7,
+ LpDimmMemoryPackage = 7,
+ SoUDimmEccMemoryPackageDdr3 = 8,
+ SoRDimmEccMemoryPackageDdr4 = 8,
+ SoRDimmEccMemoryPackageDdr3 = 9,
+ SoUDimmEccMemoryPackageDdr4 = 9,
+ SoCDimmEccMemoryPackage = 10,
+ LrDimmMemoryPackage = 11,
+ SoDimm16bMemoryPackage = 12,
+ SoDimm32bMemoryPackage = 13,
+ NonDimmMemoryPackage = 14,
+ MemoryPackageMax, ///< MEMORY_PACKAGE enumeration maximum value.
+ MemoryPackageDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MEMORY_PACKAGE;
+
+///
+/// Memory training I/O levels.
+///
+typedef enum {
+ DdrLevel = 0, ///< Refers to frontside of DIMM
+ LrbufLevel = 1, ///< Refers to data level at backside of LRDIMM or AEP buffer
+ RegALevel = 2, ///< Refers to cmd level at backside of register - side A
+ RegBLevel = 3, ///< Refers to cmd level at backside of register - side B
+ GsmLtMax, ///< GSM_LT enumeration maximum value.
+ GsmLtDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} GSM_LT;
+
+///
+/// Memory training margin group selectors.
+///
+typedef enum {
+ RecEnDelay = 0, ///< Linear delay (PI ticks), where the positive increment moves the RCVEN sampling window later in time relative to the RX DQS strobes.
+ RxDqsDelay = 1, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS strobe later in time relative to the RX DQ signal (i.e. toward the hold side of the eye).
+ RxDqDelay = 2, ///< Linear delay (PI ticks), where the positive increment moves the RX DQ byte/nibble/bitlane later in time relative to the RX DQS signal (i.e.closing the gap between DQ and DQS in the setup side of the eye).
+ RxDqsPDelay = 3, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS strobe for "even" chunks later in time relative to the RX DQ signal. Even chunks are 0, 2, 4, 6 within the 0 to 7 chunks of an 8 burst length cacheline, for example.
+ RxDqsNDelay = 4, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS strobe for "odd" chunks later in time relative to the RX DQ signal. Odd chunks are 1, 3, 5, 7 within the 0 to 7 chunks of an 8 burst length cacheline, for example.
+ RxVref = 5, ///< Linear increment (Vref ticks), where the positive increment moves the byte/nibble/bitlane RX Vref to a higher voltage.
+ RxEq = 6, ///< RX CTLE setting indicating a set of possible resistances, capacitance, current steering, etc. values, which may be a different set of values per product. The setting combinations are indexed by integer values.
+ RxDqBitDelay = 7, ///< Linear delay (PI ticks), where the positive increment moves the RX DQ bitlane later in time relative to the RX DQS signal (i.e.closing the gap between DQ and DQS in the setup side of the eye).
+ RxVoc = 8, ///< Monotonic increment (Sense Amp setting), where the positive increment moves the byte/nibble/bitlane's effective switching point to a lower Vref value.
+ RxOdt = 9, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ RxOdtUp = 10, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ RxOdtDn = 11, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ DramDrvStr = 12, ///< Drive strength setting resistance setting within a set of possible resistances (or currents), which may be a different set of values per product. Indexed by integer values.
+ McOdtDelay = 13, ///<
+ McOdtDuration = 14, ///<
+ SenseAmpDelay = 15, ///< This may be used to indicate CmdToDiffAmpEn for SoC's.
+ SenseAmpDuration = 16, ///<
+ RoundTripDelay = 17, ///< This may be used to indicate CmdToRdDataValid for SoC's.
+ RxDqsBitDelay = 18, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS within the bitlane later in time relative to the RX DQ signal (i.e.closing the gap between DQ and DQS in the hold side of the eye).
+ RxDqDqsDelay = 19, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS per strobe later in time relative to the RX DQ signal (i.e. closing the gap between DQS and DQ in the hold side of the eye. The difference between this parameter and RxDqsDelay is that both the DQ and DQS timings may be moved in order to increase the total range of DQDQS timings.
+ WrLvlDelay = 20, ///< Linear delay (PI ticks), where the positive increment moves both the TX DQS and TX DQ signals later in time relative to all other bus signals.
+ TxDqsDelay = 21, ///< Linear delay (PI ticks), where the positive increment moves the TX DQS strobe later in time relative to all other bus signals.
+ TxDqDelay = 22, ///< Linear delay (PI ticks), where the positive increment moves the TX DQ byte/nibble/bitlane later in time relative to all other bus signals.
+ TxVref = 23, ///< Linear increment (Vref ticks), where the positive increment moves the byte/nibble/bitlane TX Vref to a higher voltage. (Assuming this will abstract away from the range specifics for DDR4, for example.)
+ TxEq = 24, ///< TX EQ setting indicating a set of possible equalization levels, which may be a different set of values per product. The setting combinations are indexed by integer values.
+ TxDqBitDelay = 25, ///< Linear delay (PI ticks), where the positive increment moves the TX DQ bitlane later in time relative to all other bus signals.
+ TxRon = 26, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ TxRonUp = 27, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ TxRonDn = 28, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ TxSlewRate = 29, ///< Monotonic increment, where the positive increment moves the byte/nibble/bitlane's effective slew rate to a higher slope.
+ TxImode = 30, ///< TX I-Mode Boost setting indicating a set of possible current boost levels, which may be a different set of values per product. The setting combinations are indexed by integer values.
+ WrOdt = 31, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ NomOdt = 32, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ ParkOdt = 33, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+ TxTco = 34, ///<
+ RxCtleR = 36, ///<
+ RxCtleC = 37, ///<
+ RxDqsPBitDelay = 38, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS bitlane timing for "even" chunks later in time relative to the RX DQ bitlane signal. Even chunks are 0, 2, 4, 6 within the 0 to 7 chunks of an 8 burst length cacheline, for example.
+ RxDqsNBitDelay = 39, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS bitlane timing for "odd" chunks later in time relative to the RX DQ bitlane signal. Odd chunks are 1, 3, 5, 7 within the 0 to 7 chunks of an 8 burst length cacheline, for example.
+ CmdAll = 40, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CMD_ALL category later in time relative to all other signals on the bus.
+ CmdGrp0 = 41, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CMD_GRP0 category later in time relative to all other signals on the bus.
+ CmdGrp1 = 42, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CMD_GRP1 category later in time relative to all other signals on the bus.
+ CmdGrp2 = 43, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CMD_GRP2 category later in time relative to all other signals on the bus.
+ CtlAll = 44, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_ALL category later in time relative to all other signals on the bus.
+ CtlGrp0 = 45, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_GRP0 category later in time relative to all other signals on the bus.
+ CtlGrp1 = 46, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_GRP1 category later in time relative to all other signals on the bus.
+ CtlGrp2 = 47, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_GRP2 category later in time relative to all other signals on the bus.
+ CtlGrp3 = 48, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_GRP3 category later in time relative to all other signals on the bus.
+ CtlGrp4 = 49, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_GRP4 category later in time relative to all other signals on the bus.
+ CtlGrp5 = 50, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CTL_GRP5 category later in time relative to all other signals on the bus.
+ CmdCtlAll = 51, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CMD_CTL_ALL category later in time relative to all other signals on the bus.
+ CkAll = 52, ///< Linear delay (PI ticks), where the positive increment moves all signals assigned to the CK_ALL category later in time relative to all other signals on the bus.
+ CmdVref = 53, ///< Linear increment (Vref ticks), where the positive increment moves the CMD Vref to a higher voltage.
+ AlertVref = 54, ///< Linear increment (Vref ticks), where the positive increment moves the ALERT Vref to a higher voltage.
+ CmdRon = 55, ///< Resistance setting within a set of possible resistances, which may be a different set of values per product. Indexed by integer values.
+
+ EridDelay = 60, ///< Linear delay (PI ticks), where the positive increment moves the ERID signals later in time relative to the internal sampling clock (i.e.closing the gap between ERID and internal sampling clock in the setup side of the eye). This group is applicable for DDRT DIMMs.
+ EridVref = 61, ///< Linear increment (Vref ticks), where the positive increment moves the ERID Vref to a higher voltage. This group is applicable for DDRT DIMMs.
+ ErrorVref = 62, ///< Linear increment (Vref ticks), where the positive increment moves the ERROR Vref to a higher voltage. This group is applicable for DDRT DIMMs.
+ ReqVref = 63, ///< Linear increment (Vref ticks), where the positive increment moves the REQ Vref to a higher voltage. This group is applicable for DDRT DIMMs.
+ RecEnOffset = 64, ///< Linear delay (PI ticks), where the positive increment moves the RCVEN sampling window later in time relative to the RX DQS strobes.
+ RxDqsOffset = 65, ///< Linear delay (PI ticks), where the positive increment moves the RX DQS strobe later in time relative to the RX DQ signal (i.e. toward the hold side of the eye).
+ RxVrefOffset = 66, ///< Linear increment (Vref ticks), where the positive increment moves the byte/nibble/bitlane RX Vref to a higher voltage.
+ TxDqsOffset = 67, ///< Linear delay (PI ticks), where the positive increment moves the TX DQS strobe later in time relative to all other bus signals.
+ TxDqOffset = 68, ///< Linear delay (PI ticks), where the positive increment moves the TX DQ byte/nibble/bitlane later in time relative to all other bus signals.
+ GsmGtMax, ///< SSA_GSM_GT enumeration maximum value.
+ GsmGtDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} GSM_GT;
+
+typedef enum {
+ SigRasN = 0,
+ SigCasN = 1,
+ SigWeN = 2,
+ SigBa0 = 3,
+ SigBa1 = 4,
+ SigBa2 = 5,
+ SigA0 = 6,
+ SigA1 = 7,
+ SigA2 = 8,
+ SigA3 = 9,
+ SigA4 = 10,
+ SigA5 = 11,
+ SigA6 = 12,
+ SigA7 = 13,
+ SigA8 = 14,
+ SigA9 = 15,
+ SigA10 = 16,
+ SigA11 = 17,
+ SigA12 = 18,
+ SigA13 = 19,
+ SigA14 = 20,
+ SigA15 = 21,
+ SigA16 = 22,
+ SigA17 = 23,
+ SigCs0N = 24,
+ SigCs1N = 25,
+ SigCs2N = 26,
+ SigCs3N = 27,
+ SigCs4N = 28,
+ SigCs5N = 29,
+ SigCs6N = 30,
+ SigCs7N = 31,
+ SigCs8N = 32,
+ SigCs9N = 33,
+ SigCke0 = 34,
+ SigCke1 = 35,
+ SigCke2 = 36,
+ SigCke3 = 37,
+ SigCke4 = 38,
+ SigCke5 = 39,
+ SigOdt0 = 40, //could also be used for CA-ODT for LP4
+ SigOdt1 = 41, //could also be used for CA-ODT for LP4
+ SigOdt2 = 42,
+ SigOdt3 = 43,
+ SigOdt4 = 44,
+ SigOdt5 = 45,
+ SigPar = 46,
+ SigAlertN = 47,
+ SigBg0 = 48,
+ SigBg1 = 49,
+ SigActN = 50,
+ SigCid0 = 51,
+ SigCid1 = 52,
+ SigCid2 = 53,
+ SigCk0 = 54,
+ SigCk1 = 55,
+ SigCk2 = 56,
+ SigCk3 = 57,
+ SigCk4 = 58,
+ SigCk5 = 59,
+ SigGnt0 = 60,
+ SigGnt1 = 61,
+ SigErid00 = 62,
+ SigErid01 = 63,
+ SigErid10 = 64,
+ SigErid11 = 65,
+ SigErr0 = 66,
+ SigErr1 = 67,
+ SigCa00 = 68, // First instantiation of the CA bus for a given channel
+ SigCa01 = 69,
+ SigCa02 = 70,
+ SigCa03 = 71,
+ SigCa04 = 72,
+ SigCa05 = 73,
+ SigCa10 = 74, // Second instantiation of the CA bus for a given channel
+ SigCa11 = 75,
+ SigCa12 = 76,
+ SigCa13 = 77,
+ SigCa14 = 78,
+ SigCa15 = 79,
+ GsmCsnMax,
+ GsmCsnDelim = INT32_MAX
+} GSM_CSN;
+
+
+#endif // _MrcCommonTypes_h_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcInterface.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcInterface.h new file mode 100644 index 0000000000..87ad005f03 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcInterface.h @@ -0,0 +1,1756 @@ +/** @file
+ This file includes all the data structures that the MRC considers "global data".
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MrcInterface_h_
+#define _MrcInterface_h_
+#include "MrcTypes.h"
+#include "ConfigBlock.h"
+
+#define MAX_CPU_SOCKETS (1) ///< The maximum number of CPUs per system.
+#define MAX_CONTROLLERS (1) ///< The maximum number of memory controllers per CPU socket.
+#define MAX_CHANNEL (2) ///< The maximum number of channels per memory controller.
+#define MAX_DIMMS_IN_CHANNEL (2) ///< The maximum number of DIMMs per channel.
+#define MAX_RANK_IN_DIMM (2) ///< The maximum number of ranks per DIMM.
+#define MAX_RANK_IN_CHANNEL (MAX_DIMMS_IN_CHANNEL * MAX_RANK_IN_DIMM) ///< The maximum number of ranks per channel.
+#define MAX_SDRAM_IN_DIMM (9) ///< The maximum number of SDRAMs per DIMM when ECC is enabled.
+#define MAX_MR_IN_DIMM (7) ///< Maximum number of mode registers in a DIMM.
+#define MAX_DEVICES_IN_DDR4 (8) ///< The maximum number of SDRAMs per DDR4 DIMM.
+#define MAX_BITS (8) ///< BITS per byte.
+#define MAX_STROBE (18) ///< Number of strobe groups.
+#define MAX_DQ (72) ///< Number of Dq bits used by the rank.
+#define CHAR_BITS (8) ///< Number of bits in a char.
+#define PSMI_SIZE_MB (64) ///< Define the max size of PSMI needed in MB
+#define BCLK_DEFAULT (100 * 1000 * 1000) ///< BCLK default value, in Hertz.
+#define MAX_COMMAND_GROUPS (2)
+#define MAX_EDGES (2) ///< Maximum number of edges.
+#define SUPPORT_DDR3 SUPPORT ///< SUPPORT means that DDR3 is supported by the MRC.
+#define ULT_SUPPORT_LPDDR3 SUPPORT ///< SUPPORT means that LPDDR3 is supported by the MRC.
+#define TRAD_SUPPORT_LPDDR3 /*UN*/SUPPORT ///< SUPPORT means that LPDDR3 is supported by the MRC.
+#define BDW_SUPPORT_LPDDR3 SUPPORT ///< SUPPORT means that LPDDR3 is supported by the MRC.
+#define JEDEC_SUPPORT_LPDDR SUPPORT ///< SUPPORT means that JEDEC SPD Spec for LPDDR3 is supported by the MRC.
+#define SUPPORT_DDR4 SUPPORT ///< SUPPORT means that DDR4 is supported by the MRC.
+#define SUPPORT_LPDDR3 (ULT_SUPPORT_LPDDR3 || TRAD_SUPPORT_LPDDR3 || BDW_SUPPORT_LPDDR3 || JEDEC_SUPPORT_LPDDR)
+#define MRC_ALL_DDR_SUPPORTED ((SUPPORT_DDR4 == SUPPORT) && ((SUPPORT_DDR3 == SUPPORT) && (SUPPORT_LPDDR3 == SUPPORT)))
+#define MRC_DDR3_LPDDR_SUPPORTED ((SUPPORT_DDR3 == SUPPORT) || (SUPPORT_LPDDR3 == SUPPORT))
+#define SPD3_MANUF_START 117 ///< The starting point for the SPD manufacturing data.
+#define SPD3_MANUF_END 127 ///< The ending point for the SPD manufacturing data.
+#if (SUPPORT_DDR4 == SUPPORT)
+#define SPD4_MANUF_START 320 ///< The starting point for the SPD manufacturing data.
+#define SPD4_MANUF_END 328 ///< The ending point for the SPD manufacturing data.
+#endif
+#if (JEDEC_SUPPORT_LPDDR == SUPPORT)
+#define SPDLP_MANUF_START 320 ///< The starting point for the SPD manufacturing data.
+#define SPDLP_MANUF_END 328 ///< The ending point for the SPD manufacturing data.
+#endif
+
+#include "CpuRegs.h"
+#include "MrcSpdData.h"
+#include "MrcRmtData.h"
+#include "MrcCommonTypes.h"
+#pragma pack (push, 1)
+
+
+///
+//////////////////////////////////////////////////////////////////////////////////////
+/// OEM platform routines and types //
+//////////////////////////////////////////////////////////////////////////////////////
+///
+/// define the oem check points the OEM can define more point and locate them in the code.
+///
+typedef enum {
+ OemFastBootPermitted, ///< before fast boot.
+ OemRestoreNonTraining,
+ OemPrintInputParameters, ///< before printing input parameters
+ OemSpdProcessingRun, ///< before spd processing code
+ OemSetOverridePreSpd, ///< before set overrides pre spd
+ OemSetOverride, ///< before set overrides
+ OemMcCapability, ///< before MC capability
+ OemMcInitRun, ///< before mc init code
+ OemMcMemoryMap, ///< before memory map
+ OemMcResetRun, ///< before jedec reset
+ OemPreTraining, ///< before the training.
+ OemMcTrainingRun, ///< before training code
+ OemEarlyCommandTraining, ///< before Early Command training
+ OemJedecInitLpddr3, ///< before Jedec Init Lpddr3
+ OemSenseAmpTraining, ///< before Sense Amp Training
+ OemReadMprTraining, ///< before Read MPR Training
+ OemReceiveEnable, ///< before Read Leveling
+ OemJedecWriteLeveling, ///< before Jedec Write Leveling
+ OemLpddrLatencySetB, ///< before LPDDR Latency Set B
+ OemWriteDqDqs, ///< before Write Timing Centering
+ OemWriteVoltage, ///< before Write Voltage Centering
+ OemEarlyWriteDqDqs2D, ///< before Early Write Timing Centering 2D
+ OemEarlyWrDsEq, ///< before Early Write Drive Strength / Equalization
+ OemEarlyReadDqDqs2D, ///< before Early Read Timing Centering 2D
+ OemEarlyReadMprDqDqs2D, ///< before Early MPR Read Timing Centering 2D
+ OemReadDqDqs, ///< before Read Timing Centering
+ OemDdr4Map, ///< before DDR4 PDA Mapping
+ OemDimmRonTraining, ///< before DIMM Ron Training
+ OemDimmODTTraining, ///< before DIMM ODT Training
+ OemWriteDriveStrengthEq, ///< before Write Drive Strength/Equalization 2D Training
+ OemWriteDriveUpDn, ///< before Write Drive Strength Up/Dn 2D Training
+ OemWriteSlewRate, ///< before Write Slew Rate Training
+ OemReadODTTraining, ///< before Read ODT algorithm.
+ OemReadEQTraining, ///< before Read Equalization Training
+ OemReadAmplifierPower, ///< before Read Amplifier Power
+ OemOptimizeComp, ///< before Comp Optimization Training
+ OemPowerSavingMeter, ///< before PowerSavingMeter step
+ OemWriteDqDqs2D, ///< before Write Timing Centering 2D
+ OemReadDqDqs2D, ///< before Read Timing Centering 2D
+ OemCmdVoltCenterPreLct, ///< before Command Voltage Centering that runs pre-LCT
+ OemCmdSlewRate, ///< before CMD Slew Rate
+ OemCmdVoltCentering, ///< before Command Voltage Centering
+ OemCmdDriveStrengthEq, ///< before Command Drive Strength Equalization
+ OemWriteVoltCentering2D, ///< before Write Voltage Centering 2D
+ OemReadVoltCentering2D, ///< before Read Voltage Centering 2D
+ OemLateCommandTraining, ///< before Late Command training
+ OemCmdNormalization, ///< before CMD Normalization
+ OemRoundTripLatency, ///< before Round Trip Latency Traiing
+ OemTurnAroundTimes, ///< before Turn Aorund Times.
+ OemRcvEnCentering1D, ///< before Receive Enable Centring
+ OemSaveMCValues, ///< before saving memory controller values
+ OemRmt, ///< before RMT crosser tool.
+ OemMemTest, ///< before Memory testing
+ OemRestoreTraining, ///< before Restoring Training Values
+ OemJedecResetDdr4Fast, ///< before JEDEC reset for DDR4 in Fast flow
+ OemSelfRefreshExit, ///< before Self Refresh Exit
+ OemNormalMode, ///< before Normal Mode on non-cold boots.
+ OemTxtAliasCheck, ///< before TxT Alias Check Call.
+ OemAliasCheck, ///< before alias checking on cold boots.
+ OemHwMemInit,
+
+ OemPostTraining, ///< after the training.
+ OemForceOltm, ///< before MrcForceOltm
+ OemMrcActivate, ///< before MrcActivate call.
+ OemMrcRhPrevention, ///< before MrcRhPrevention
+ OemSaGvSwitch, ///< before SA GV switch
+ OemEngPerfGain, ///< before Energy Performance Gain.
+ OemMrcDone, ///< call to MrcOemCheckPoint when MRC was done.
+ OemFrequencySet, ///< do operation before frequency set.
+ OemFrequencySetDone, ///< do operation after frequency set.
+ OemStartMemoryConfiguration,
+ OemBeforeNormalMode, ///< call to MrcOemCheckPoint before normal mode is enalbed
+ OemAfterNormalMode, ///< call to MrcOemCheckPoint after normal mode is enalbed
+ OemMrcFillRmt,
+ OemRetrainMarginCheck,
+ OemSsaStopPoint, ///< Call to SSA stop point
+ ///
+ ///*********************************************************************************
+ ///
+ OemNumOfCommands ///< Should always be last in the list!
+} MrcOemStatusCommand;
+
+typedef UINT8 MrcIteration; ///< Mrc invocation sequence number, start with 0 and increment by one each time MRC library is called.
+#define MRC_ITERATION_MAX ((1 << ((sizeof (MrcIteration) * 8) - 1)) + ((1 << ((sizeof (MrcIteration) * 8) - 1)) - 1))
+
+#define MAX_RCOMP (3)
+#define MAX_RCOMP_TARGETS (5)
+
+///
+/// Thermal Options
+///
+typedef struct {
+ UINT8 RaplLim2WindX; ///< Offset 110 - Power Limit 2 Time Window X value: 0=Minimal, 3=Maximum, <b>1=Default</b>
+ UINT8 RaplLim2WindY; ///< Offset 111 - Power Limit 2 Time Window Y value: 0=Minimal, 3=Maximum, <b>1=Default</b>
+ UINT8 RaplLim1WindX; ///< Offset 112 - Power Limit 1 Time Window X value: <b>0=Minimal</b>, 3=Maximum
+ UINT8 RaplLim1WindY; ///< Offset 113 - Power Limit 1 Time Window Y value: <b>0=Minimal</b>, 31=Maximum
+ UINT16 RaplLim2Pwr; ///< Offset 114 - Power Limit 2: 0=Minimal, 16383=Maximum, <b>222=Default</b>
+ UINT16 RaplLim1Pwr; ///< Offset 116 - Power Limit 1: <b>0=Minimal</b>, 16383=Maximum
+ UINT8 WarmThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 118 - Warm Threshold (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 122 - Hot Threshold (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 WarmBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 126 - Warm Budget (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 HotBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 130 - Hot Budget (Channel 0, Dimm 0): 0=Minimal, <b>255=Maximum</b>
+ UINT8 IdleEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+ UINT8 PdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+ UINT8 ActEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+ UINT8 RdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+ UINT8 WrEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL];
+} ThermalMngmtEn;
+
+
+typedef struct {
+ UINT8 GdxcEnable; ///< GDXC MOT enable
+ UINT8 GdxcIotSize; ///< IOT size in multiples of 8MEG
+ UINT8 GdxcMotSize; ///< MOT size in multiples of 8MEG
+} MrcGdxc;
+
+typedef struct {
+ UINT32 ECT : 1; ///< BIT0 - Early Command Training
+ UINT32 SOT : 1; ///< BIT1 - Sense Amp Offset Training
+ UINT32 ERDMPRTC2D : 1; ///< BIT2 - Early ReadMPR Timing Centering 2D
+ UINT32 RDMPRT : 1; ///< BIT3 - Read MPR Training
+ UINT32 RCVET : 1; ///< BIT4 - Read Leveling Training (RcvEn)
+ UINT32 JWRL : 1; ///< BIT5 - Jedec Write Leveling
+ UINT32 EWRTC2D : 1; ///< BIT6 - Early Write Time Centering 2D
+ UINT32 ERDTC2D : 1; ///< BIT7 - Early Read Time Centering 2D
+ UINT32 WRTC1D : 1; ///< BIT8 - Write Timing Centering 1D
+ UINT32 WRVC1D : 1; ///< BIT9 - Write Voltage Centering 1D
+ UINT32 RDTC1D : 1; ///< BIT10 - Read Timing Centering 1D
+ UINT32 DIMMODTT : 1; ///< BIT11 - Dimm ODT Training
+ UINT32 DIMMRONT : 1; ///< BIT12 - Dimm Ron Training
+ UINT32 WRDSEQT : 1; ///< BIT13 - Write Drive Strength / Equalization Training 2D
+ UINT32 WRSRT : 1; ///< BIT14 - Write Slew Rate Training
+ UINT32 RDODTT : 1; ///< BIT15 - Read ODT Training
+ UINT32 RDEQT : 1; ///< BIT16 - Read Equalization Training
+ UINT32 RDAPT : 1; ///< BIT17 - Read Amplifier Power Training
+ UINT32 WRTC2D : 1; ///< BIT18 - Write Timing Centering 2D
+ UINT32 RDTC2D : 1; ///< BIT19 - Read Timing Centering 2D
+ UINT32 WRVC2D : 1; ///< BIT20 - Write Voltage Centering 2D
+ UINT32 RDVC2D : 1; ///< BIT21 - Read Voltage Centering 2D
+ UINT32 CMDVC : 1; ///< BIT22 - Command Voltage Centering
+ UINT32 LCT : 1; ///< BIT23 - Late Command Training
+ UINT32 RTL : 1; ///< BIT24 - Round Trip latency
+ UINT32 TAT : 1; ///< BIT25 - Turn Around Timing
+ UINT32 RMT : 1; ///< BIT26 - RMT Tool
+ UINT32 MEMTST : 1; ///< BIT27 - Memory Test
+ UINT32 ALIASCHK: 1; ///< BIT28 - SPD Alias Check
+ UINT32 RCVENC1D: 1; ///< BIT29 - Receive Enable Centering 1D
+ UINT32 RMC : 1; ///< BIT30 - Retrain Margin Check
+ UINT32 WRDSUDT : 1; ///< BIT31 - Write Drive Strength Up/Dn independently
+} TrainingStepsEn;
+
+typedef struct {
+ UINT32 CMDSR : 1; ///< BIT0 - CMD Slew Rate Training
+ UINT32 CMDDSEQ : 1; ///< BIT1 - CMD Drive Strength and Tx Equalization
+ UINT32 CMDNORM : 1; ///< BIT2 - CMD Normalization
+ UINT32 EWRDSEQ : 1; ///< BIT3 - Early DQ Write Drive Strength and Equalization Training
+ UINT32 RsvdBits :28;
+} TrainingStepsEn2;
+
+///
+/// Defines whether the MRC is executing in full or mini BIOS mode.
+///
+typedef enum {
+ MrcModeFull, ///< Select full BIOS MRC execution.
+ MrcModeMini, ///< Select mini BIOS MRC execution.
+ MrcModeMaximum ///< Delimiter.
+} MrcMode;
+
+typedef enum {
+ MrcTmPower,
+ MrcTmMargin,
+ MrcTmMax
+} TrainingModeType;
+
+typedef enum {
+ LastRxV,
+ LastRxT,
+ LastTxV,
+ LastTxT,
+ LastRcvEna,
+ LastWrLevel,
+ LastCmdT,
+ LastCmdV,
+ MAX_RESULT_TYPE
+} MrcMarginResult;
+
+typedef enum {
+ MSG_LEVEL_NEVER,
+ MSG_LEVEL_ERROR,
+ MSG_LEVEL_WARNING,
+ MSG_LEVEL_NOTE,
+ MSG_LEVEL_EVENT,
+ MSG_LEVEL_ALGO,
+ MSG_LEVEL_MMIO,
+ MSG_LEVEL_CSV,
+ MSG_LEVEL_TIME,
+ MSG_LEVEL_ALL = MRC_INT32_MAX
+} MrcDebugMsgLevel;
+
+///
+/// Define the frequencies that may be possible in the memory controller.
+/// Note that not all these values may be supported.
+///
+#define fNoInit (0)
+#define f800 (800)
+#define f1000 (1000)
+#define f1100 (1100)
+#define f1067 (1067)
+#define f1200 (1200)
+#define f1300 (1300)
+#define f1333 (1333)
+#define f1400 (1400)
+#define f1467 (1467)
+#define f1500 (1500)
+#define f1600 (1600)
+#define f1700 (1700)
+#define f1733 (1733)
+#define f1800 (1800)
+#define f1867 (1867)
+#define f1900 (1900)
+#define f2000 (2000)
+#define f2100 (2100)
+#define f2133 (2133)
+#define f2200 (2200)
+#define f2267 (2267)
+#define f2300 (2300)
+#define f2400 (2400)
+#define f2500 (2500)
+#define f2533 (2533)
+#define f2600 (2600)
+#define f2667 (2667)
+#define f2700 (2700)
+#define f2800 (2800)
+#define f2900 (2900)
+#define f2933 (2933)
+#define f3000 (3000)
+#define f3067 (3067)
+#define f3100 (3100)
+#define f3200 (3200)
+#define f3333 (3333)
+#define f3467 (3467)
+#define f3600 (3600)
+#define f3733 (3733)
+#define f3867 (3867)
+#define f4000 (4000)
+#define f4133 (4133)
+#define fInvalid (0x7FFFFFFF)
+typedef UINT32 MrcFrequency;
+
+//
+// Max supported frequency in OC mode
+// RefClk133: 15*266 + 100 = 4133 (using Odd ratio mode)
+// RefClk100: 15*200 + 100 = 3100 (using Odd ratio mode)
+//
+#define MAX_FREQ_OC_133 f4133
+#define MAX_FREQ_OC_100 f3100
+
+//
+// tCK value in femtoseconds for various frequencies
+// If Freq is in MHz, then tCK[fs] = 10^9 * 1/(Freq/2)
+//
+#define MRC_DDR_800_TCK_MIN 2500000
+#define MRC_DDR_1000_TCK_MIN 2000000
+#define MRC_DDR_1067_TCK_MIN 1875000
+#define MRC_DDR_1100_TCK_MIN 1818182
+#define MRC_DDR_1200_TCK_MIN 1666667
+#define MRC_DDR_1300_TCK_MIN 1538462
+#define MRC_DDR_1333_TCK_MIN 1500000
+#define MRC_DDR_1400_TCK_MIN 1428571
+#define MRC_DDR_1467_TCK_MIN 1363636
+#define MRC_DDR_1500_TCK_MIN 1333333
+#define MRC_DDR_1600_TCK_MIN 1250000
+#define MRC_DDR_1700_TCK_MIN 1176471
+#define MRC_DDR_1733_TCK_MIN 1153846
+#define MRC_DDR_1800_TCK_MIN 1111111
+#define MRC_DDR_1867_TCK_MIN 1071429
+#define MRC_DDR_1900_TCK_MIN 1052632
+#define MRC_DDR_2000_TCK_MIN 1000000
+#define MRC_DDR_2100_TCK_MIN 952381
+#define MRC_DDR_2133_TCK_MIN 938000
+#define MRC_DDR_2200_TCK_MIN 909091
+#define MRC_DDR_2267_TCK_MIN 882353
+#define MRC_DDR_2300_TCK_MIN 869565
+#define MRC_DDR_2400_TCK_MIN 833333
+#define MRC_DDR_2500_TCK_MIN 800000
+#define MRC_DDR_2533_TCK_MIN 789474
+#define MRC_DDR_2600_TCK_MIN 769231
+#define MRC_DDR_2667_TCK_MIN 750000
+#define MRC_DDR_2700_TCK_MIN 740741
+#define MRC_DDR_2800_TCK_MIN 714286
+#define MRC_DDR_2900_TCK_MIN 689655
+#define MRC_DDR_2933_TCK_MIN 681818
+#define MRC_DDR_3000_TCK_MIN 666667
+#define MRC_DDR_3067_TCK_MIN 652174
+#define MRC_DDR_3100_TCK_MIN 645161
+#define MRC_DDR_3200_TCK_MIN 625000
+#define MRC_DDR_3333_TCK_MIN 600000
+#define MRC_DDR_3467_TCK_MIN 576923
+#define MRC_DDR_3600_TCK_MIN 555556
+#define MRC_DDR_3733_TCK_MIN 535714
+#define MRC_DDR_3867_TCK_MIN 517241
+#define MRC_DDR_4000_TCK_MIN 500000
+#define MRC_DDR_4133_TCK_MIN 483871
+
+///
+/// Define the memory nominal voltage (VDD).
+/// Note that not all these values may be supported.
+///
+typedef enum {
+ VDD_INVALID,
+ VDD_1_00 = 1000,
+ VDD_1_05 = 1050,
+ VDD_1_10 = 1100,
+ VDD_1_15 = 1150,
+ VDD_1_20 = 1200,
+ VDD_1_25 = 1250,
+ VDD_1_30 = 1300,
+ VDD_1_35 = 1350,
+ VDD_1_40 = 1400,
+ VDD_1_45 = 1450,
+ VDD_1_50 = 1500,
+ VDD_1_55 = 1550,
+ VDD_1_60 = 1600,
+ VDD_1_65 = 1650,
+ VDD_1_70 = 1700,
+ VDD_1_75 = 1750,
+ VDD_1_80 = 1800,
+ VDD_1_85 = 1850,
+ VDD_1_90 = 1900,
+ VDD_1_95 = 1950,
+ VDD_2_00 = 2000,
+ VDD_2_05 = 2050,
+ VDD_2_10 = 2100,
+ VDD_2_15 = 2150,
+ VDD_2_20 = 2200,
+ VDD_2_25 = 2250,
+ VDD_2_30 = 2300,
+ VDD_2_35 = 2350,
+ VDD_2_40 = 2400,
+ VDD_2_45 = 2450,
+ VDD_2_50 = 2500,
+ VDD_2_55 = 2550,
+ VDD_2_60 = 2600,
+ VDD_2_65 = 2650,
+ VDD_2_70 = 2700,
+ VDD_2_75 = 2750,
+ VDD_2_80 = 2800,
+ VDD_2_85 = 2850,
+ VDD_2_90 = 2900,
+ VDD_2_95 = 2950,
+ VDD_MAXIMUM = 0x7FFFFFFF
+} MrcVddSelect;
+
+///
+/// SA GV points
+///
+typedef enum {
+ MrcSaGvPointLow,
+ MrcSaGvPointHigh,
+} MrcSaGvPoint;
+
+///
+/// SA GV modes
+/// Disabled: SA GV Disabled, run all MRC tasks
+/// FixedLow: SA GV Disabled, run only MRC tasks marked with MRC_PF_GV_LOW
+/// FixedHigh: SA GV Disabled, run only MRC tasks marked with MRC_PF_GV_HIGH
+/// Enabled: SA GV Enabled
+///
+typedef enum {
+ MrcSaGvDisabled,
+ MrcSaGvFixedLow,
+ MrcSaGvFixedHigh,
+ MrcSaGvEnabled,
+} MrcSaGv;
+
+///
+/// DIMM SPD Security Status
+///
+typedef enum {
+ MrcSpdStatusGood, ///< Memory is in a secure state.
+ MrcSpdStatusAliased, ///< Memory is aliased.
+ MrcSpdStatusLast ///< Must be last in the list
+} MrcSpdStatus;
+
+///
+/// Define the virtual channel.
+///
+typedef enum {
+ vcL, ///< Virtual channel L
+ vcS, ///< Virtual channel S
+} MrcVirtualChannel;
+
+///
+/// Define the board types.
+///
+typedef enum {
+ btCRBMB, ///< 0 - CRB Mobile
+ btCRBDT, ///< 1 - CRB Desktop
+ btUser1, ///< 2 - SV mobile
+ btUser2, ///< 3 - SV desktop
+ btUser3, ///< 4 - SV server?
+ btUser4, ///< 5 - Ult
+ btCRBEMB, ///< 6 - CRB Embedded
+ btUpServer, ///< 7 - Up Server
+ btUnknown, ///< 8 - Unknown
+ btMaximum ///< Delimiter
+} MrcBoardType;
+
+///
+/// Define the CPU family/model.
+///
+typedef enum {
+ cmSKL_ULX_ULT = CPUID_FULL_FAMILY_MODEL_SKYLAKE_ULT_ULX, ///< Skylake ULT/ULX
+ cmSKL_DT_HALO = CPUID_FULL_FAMILY_MODEL_SKYLAKE_DT_HALO, ///< Skylake DT/Halo
+ cmKBL_ULX_ULT = CPUID_FULL_FAMILY_MODEL_KABYLAKE_ULT_ULX, ///< Kabylake ULT/ULX
+ cmKBL_DT_HALO = CPUID_FULL_FAMILY_MODEL_KABYLAKE_DT_HALO ///< Kabylake DT/Halo
+} MrcCpuModel;
+
+///
+/// Define the CPU Tick/Tock.
+///
+typedef enum {
+ cfSkl = 0, ///< Skylake
+ cfKbl, ///< Kabylake
+ cfMax
+} MrcCpuFamily;
+
+///
+/// Define the CPU stepping number.
+///
+typedef enum {
+ ///
+ /// Skylake ULX/ULT
+ ///
+ csSklB0 = EnumSklB0,
+ csSklJ0 = EnumSklJ0,
+ csSklC0 = EnumSklC0,
+ csSklK0 = EnumSklK0,
+ csSklD0 = EnumSklD0,
+ csSklUlxUltLast = csSklD0,
+
+ ///
+ /// Kabylake ULX/ULT
+ ///
+ csKblG0 = EnumKblG0,
+ csKblH0 = EnumKblH0,
+ csKblJ0 = EnumKblJ0,
+ csKblY0 = EnumKblY0,
+ csKblUlxUltLast = csKblY0,
+
+ ///
+ /// Skylake DT/Halo
+ ///
+ csSklP0 = EnumSklP0,
+ csSklQ0 = EnumSklQ0,
+ csSklM0 = EnumSklM0,
+ csSklR0 = EnumSklR0,
+ csSklS0 = EnumSklS0,
+ csSklN0 = EnumSklN0,
+ csSklDtHaloLast = csSklN0,
+
+ ///
+ /// Kabylake DT/Halo
+ ///
+ csKblA0 = EnumKblA0,
+ csKblB0 = EnumKblB0,
+ csKblS0 = EnumKblS0,
+ csKblM0 = EnumKblM0,
+ csKblN0 = EnumKblN0,
+ csKblDtHaloLast = csKblN0,
+} MrcCpuStepping;
+
+typedef enum {
+ CONTROLLER_NOT_PRESENT, ///< There is no controller present in the system.
+ CONTROLLER_DISABLED, ///< There is a controller present but it is disabled.
+ CONTROLLER_PRESENT, ///< There is a controller present and it is enabled.
+ MAX_CONTROLLER_STATUS ///< Delimiter
+} MrcControllerSts;
+
+typedef enum {
+ CHANNEL_NOT_PRESENT, ///< There is no channel present on the controller.
+ CHANNEL_DISABLED, ///< There is a channel present but it is disabled.
+ CHANNEL_PRESENT, ///< There is a channel present and it is enabled.
+ MAX_CHANNEL_STATUS ///< Delimiter
+} MrcChannelSts;
+
+typedef enum {
+ DIMM_ENABLED, ///< DIMM/rank Pair is enabled, presence will be detected.
+ DIMM_DISABLED, ///< DIMM/rank Pair is disabled, regardless of presence.
+ DIMM_PRESENT, ///< There is a DIMM present in the slot/rank pair and it will be used.
+ DIMM_NOT_PRESENT, ///< There is no DIMM present in the slot/rank pair.
+ MAX_DIMM_STATUS ///< Delimiter
+} MrcDimmSts;
+
+typedef enum {
+ STD_PROFILE, ///< Standard DIMM profile select.
+ USER_PROFILE, ///< User specifies various override values.
+ XMP_PROFILE1, ///< XMP enthusiast settings select (XMP profile #1).
+ XMP_PROFILE2, ///< XMP extreme settings select (XMP profile #2).
+ MAX_PROFILE ///< Delimiter
+} MrcProfile;
+
+#define XMP_PROFILES_ENABLE (0x3)
+#define XMP1_PROFILE_ENABLE (0x1)
+#define XMP2_PROFILE_ENABLE (0x2)
+
+typedef enum {
+ MRC_REF_CLOCK_133, ///< 133MHz reference clock
+ MRC_REF_CLOCK_100, ///< 100MHz reference clock
+ MRC_REF_CLOCK_MAXIMUM ///< Delimiter
+} MrcRefClkSelect; ///< This value times the MrcClockRatio determines the MrcFrequency.
+
+typedef enum {
+ MRC_FREQ_INVALID = 0,
+ MRC_FREQ_133 = (MRC_BIT0 << MRC_REF_CLOCK_133), // Bit 0
+ MRC_FREQ_100 = (MRC_BIT0 << MRC_REF_CLOCK_100), // Bit 1
+ MRC_FREQ_133_ODD_RATIO = (MRC_BIT2 << MRC_REF_CLOCK_133), // Bit 2
+ MRC_FREQ_100_ODD_RATIO = (MRC_BIT2 << MRC_REF_CLOCK_100), // Bit 3
+ MRC_FREQ_MAX // Delimiter
+} MrcFreqFlag;
+
+typedef UINT32 MrcBClkRef; ///< Base clock, in Hertz, Default is 100MHz or leave at zero for default.
+
+//
+// This encoding matches SKL SC_GS_CFG.DRAM_technology and MAD_INTER_CHANNEL.DDR_TYPE registers
+//
+typedef enum {
+ MRC_DDR_TYPE_DDR4 = 0,
+ MRC_DDR_TYPE_DDR3 = 1,
+ MRC_DDR_TYPE_LPDDR3 = 2,
+ MRC_DDR_TYPE_UNKNOWN = 3,
+ MAX_MRC_DDR_TYPE ///< Delimiter
+} MrcDdrType;
+
+typedef enum {
+ MrcIterationClock,
+ MrcIterationCmdN,
+ MrcIterationCmdS,
+ MrcIterationCke,
+ MrcIterationCtl,
+ MrcIterationCmdV,
+ MrcIterationMax
+} MrcIterationType;
+
+typedef enum {
+ UpmLimit,
+ PowerLimit,
+ RetrainLimit,
+ MarginLimitMax
+} MRC_MARGIN_LIMIT_TYPE;
+
+
+typedef enum {
+ HardwareRhp,
+ Refresh2x
+} MrcRhpType;
+
+typedef enum {
+ OneIn2To1 = 1,
+ OneIn2To2,
+ OneIn2To3,
+ OneIn2To4,
+ OneIn2To5,
+ OneIn2To6,
+ OneIn2To7,
+ OneIn2To8,
+ OneIn2To9,
+ OneIn2To10,
+ OneIn2To11,
+ OneIn2To12,
+ OneIn2To13,
+ OneIn2To14,
+ OneIn2To15
+} MrcRhProbType;
+
+typedef enum {
+ MRC_POST_CODE,
+ MRC_POST_CODE_WRITE,
+ MRC_POST_CODE_READ,
+ MRC_POST_CODE_MAX
+} MrcDebugPostCode;
+
+typedef struct {
+ UINT32 MrcData;
+ UINT32 Stream;
+ UINT32 Start;
+ UINT32 End;
+ UINT32 Current;
+ int Level;
+ UINT16 PostCode[MRC_POST_CODE_MAX];
+ UINT32 TopStackAddr; ///< Initial stack address.
+ UINT32 LowestStackAddr; ///< Track the lowest stack address used through MrcPrintfVaList()
+} MrcDebug;
+
+typedef UINT16 MrcPostCode;
+typedef UINT8 MrcClockRatio; ///< This value times the MrcRefClkSelect determines the MrcFrequency.
+typedef UINT32 MrcGfxDataSize; ///< The size of the stolen graphics data memory, in MBytes.
+typedef UINT32 MrcGfxGttSize; ///< The size of the graphics translation table, in MBytes.
+
+
+///
+/// This data structure contains all the "DDR power saving data" values that are considered output by the MRC.
+/// The following are memory controller level definitions. All channels on a controller are set to these values.
+///
+typedef struct {
+ BOOLEAN BaseFlag; ///< Indicates if the base line of power was already calculated.
+ UINT16 BaseSavingRd; ///< Indicates the base line of power consume by the ddr on read.
+ UINT16 BaseSavingWr; ///< Indicates the base line of power consume by the ddr on write.
+ UINT16 BaseSavingCmd; ///< Indicates the base line of power consume by the ddr on command.
+ UINT16 MrcSavingRd; ///< Indicates the power consume by the ddr on read at the end of MRC.
+ UINT16 MrcSavingWr; ///< Indicates the power consume by the ddr on write at the end of MRC.
+ UINT16 MrcSavingCmd; ///< Indicates the power consume by the ddr on command at the end of MRC.
+} MrcOdtPowerSaving;
+
+///
+/// The memory controller capabilities.
+///
+typedef union {
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} MrcCapabilityIdA;
+
+typedef union {
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} MrcCapabilityIdB;
+
+typedef union {
+ UINT64 Data;
+ struct {
+ MrcCapabilityIdA A;
+ MrcCapabilityIdB B;
+ } Data32;
+} MrcCapabilityId;
+
+///
+/// MRC version description.
+///
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} MrcVersion;
+
+///
+/// Memory map configuration information.
+///
+typedef struct {
+ UINT32 TomMinusMe;
+ UINT32 ToludBase;
+ UINT32 BdsmBase;
+ UINT32 GttBase;
+ UINT32 GraphicsControlRegister;
+ UINT32 TsegBase;
+ BOOLEAN ReclaimEnable;
+ UINT32 RemapBase;
+ UINT32 RemapLimit;
+ UINT32 TouudBase;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 MeStolenBase;
+ UINT32 MeStolenSize;
+ UINT32 GdxcMotBase;
+ UINT32 GdxcMotSize;
+ UINT32 GdxcIotBase;
+ UINT32 GdxcIotSize;
+ UINT32 DprSize;
+ UINT32 PttStolenBase;
+ UINT32 PrmrrBase;
+ UINT32 LowestBase;
+} MrcMemoryMap;
+
+///
+/// Real time clock information.
+///
+typedef struct {
+ UINT8 Seconds; ///< Seconds, 0-59
+ UINT8 Minutes; ///< Minutes, 0-59
+ UINT8 Hours; ///< Hours, 0-23
+ UINT8 DayOfMonth; ///< Day of the month, 1-31
+ UINT8 Month; ///< Month of the year, 1-12
+ UINT16 Year; ///< Year, 0-65535
+} MrcBaseTime;
+
+///
+/// DIMM timings
+///
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+} MrcTiming;
+
+typedef struct {
+ INT32 Mtb; ///< Medium time base.
+ INT32 Ftb; ///< Fine time base.
+} MrcTimeBase;
+
+typedef struct {
+ UINT8 Left; ///< The left side of the timing eye.
+ UINT8 Center; ///< The center of the timing eye.
+ UINT8 Right; ///< The right side of the timing eye.
+} MrcDqTimeMargin;
+
+typedef struct {
+ UINT8 High; ///< The high side of the Vref eye.
+ UINT8 Center; ///< The center of the Vref eye.
+ UINT8 Low; ///< The low side of the Vref eye.
+} MrcDqVrefMargin;
+
+typedef struct {
+ UINT8 Left; ///< The left side of the command eye.
+ UINT8 Right; ///< The right side of the command eye.
+ UINT8 High; ///< The high side of the command eye.
+ UINT8 Low; ///< The low side of the command eye.
+} MrcCommandMargin;
+
+typedef struct {
+ UINT8 Left; ///< The left side of the receive enable eye.
+ UINT8 Right; ///< The right side of the receive enableeye.
+} MrcRecvEnMargin;
+
+typedef struct {
+ UINT8 Left; ///< The left side of the write leveling eye.
+ UINT8 Right; ///< The right side of the write leveling eye.
+} MrcWrLevelMargin;
+
+typedef struct {
+ UINT8 SpdValid[sizeof (MrcSpd) / (CHAR_BITS * sizeof (UINT8))]; ///< Each valid bit maps to SPD byte.
+ UINT8 MrcSpdString[3]; ///< The SPD data start marker. This must be located at the start of the SPD data structure. It includes this string plus the following flag.
+ union {
+ struct {
+ UINT8 DimmNumber : 4; ///< SPD zero based DIMM number.
+ UINT8 ChannelNumber : 3; ///< SPD zero based channel number.
+ UINT8 MdSocket : 1; ///< 0 = memory down, 1 = socketed.
+ } Bit;
+ UINT8 Data;
+ } Flag;
+ MrcSpd Data; ///< The SPD data for each DIMM. SPDGeneral field = 0 when absent.
+} MrcSpdData;
+
+typedef UINT8 (*MRC_IO_READ_8) (UINT32 IoAddress);
+typedef UINT16 (*MRC_IO_READ_16) (UINT32 IoAddress);
+typedef UINT32 (*MRC_IO_READ_32) (UINT32 IoAddress);
+typedef void (*MRC_IO_WRITE_8) (UINT32 IoAddress, UINT8 Value);
+typedef void (*MRC_IO_WRITE_16) (UINT32 IoAddress, UINT16 Value);
+typedef void (*MRC_IO_WRITE_32) (UINT32 IoAddress, UINT32 Value);
+typedef UINT8 (*MRC_MMIO_READ_8) (UINT32 Address);
+typedef UINT16 (*MRC_MMIO_READ_16) (UINT32 Address);
+typedef UINT32 (*MRC_MMIO_READ_32) (UINT32 Address);
+typedef UINT64 (*MRC_MMIO_READ_64) (UINT32 Address);
+typedef UINT8 (*MRC_MMIO_WRITE_8) (UINT32 Address, UINT8 Value);
+typedef UINT16 (*MRC_MMIO_WRITE_16) (UINT32 Address, UINT16 Value);
+typedef UINT32 (*MRC_MMIO_WRITE_32) (UINT32 Address, UINT32 Value);
+typedef UINT64 (*MRC_MMIO_WRITE_64) (UINT32 Address, UINT64 Value);
+typedef UINT8 (*MRC_SMBUS_READ_8) (UINT32 Address, UINT32 *Status);
+typedef UINT16 (*MRC_SMBUS_READ_16) (UINT32 Address, UINT32 *Status);
+typedef UINT8 (*MRC_SMBUS_WRITE_8) (UINT32 Address, UINT8 Value, UINT32 *Status);
+typedef UINT16 (*MRC_SMBUS_WRITE_16) (UINT32 Address, UINT16 Value, UINT32 *Status);
+typedef UINT32 (*MRC_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset);
+typedef UINT32 (*MRC_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset);
+typedef void (*MRC_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year);
+typedef UINT64 (*MRC_GET_CPU_TIME) (void *MrcData);
+typedef void * (*MRC_MEMORY_COPY) (UINT8 *Destination, UINT8 *Source, UINT32 NumBytes);
+typedef void * (*MRC_MEMORY_SET_BYTE) (UINT8 *Destination, UINT32 NumBytes, UINT8 Value);
+typedef void * (*MRC_MEMORY_SET_WORD) (UINT16 *Destination, UINT32 NumWords, UINT16 Value);
+typedef void * (*MRC_MEMORY_SET_DWORD) (UINT32 *Destination, UINT32 NumDwords, UINT32 Value);
+typedef UINT64 (*MRC_LEFT_SHIFT_64) (UINT64 Data, UINT32 NumBits);
+typedef UINT64 (*MRC_RIGHT_SHIFT_64) (UINT64 Data, UINT32 NumBits);
+typedef UINT64 (*MRC_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier);
+typedef UINT64 (*MRC_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder);
+typedef BOOLEAN (*MRC_GET_SPD_DATA) (UINT8 BootMode, UINT8 SpdAddress, UINT8 *SpdData, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize);
+typedef BOOLEAN (*MRC_GET_RANDOM_NUMBER) (UINT32 *Rand);
+typedef UINT32 (*MRC_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status);
+typedef UINT32 (*MRC_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status);
+typedef UINT32 (*MRC_GET_MEMORY_VDD) (void *MrcData, UINT32 DefaultVdd);
+typedef UINT32 (*MRC_SET_MEMORY_VDD) (void *MrcData, UINT32 DefaultVdd, UINT32 Value);
+typedef UINT32 (*MRC_CHECKPOINT) (void *MrcData, UINT32 CheckPoint, void *Scratch);
+typedef void (*MRC_DEBUG_HOOK) (void *GlobalData, UINT16 DisplayDebugNumber);
+typedef void (*MRC_PRINT_STRING) (void *String);
+typedef UINT8 (*MRC_GET_RTC_CMOS) (UINT8 Location);
+typedef UINT64 (*MRC_MSR_READ_64) (UINT32 Location);
+typedef UINT64 (*MRC_MSR_WRITE_64) (UINT32 Location, UINT64 Data);
+typedef void (*MRC_RETURN_FROM_SMC) (void *GlobalData, UINT32 MrcStatus);
+typedef void (*MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue);
+typedef void (*MRC_SET_LOCK_PRMRR) (UINT32 PrmrrBase, UINT32 PrmrrSize);
+typedef void (*MRC_TXT_ACHECK) (void);
+
+///
+/// Function calls that are called external to the MRC.
+/// This structure needs to be aligned with SA_FUNCTION_CALLS. All functions that are
+/// not apart of SA_FUNCTION_CALLS need to be at the end of the structure.
+///
+typedef struct {
+ MRC_IO_READ_8 MrcIoRead8;
+ MRC_IO_READ_16 MrcIoRead16;
+ MRC_IO_READ_32 MrcIoRead32;
+ MRC_IO_WRITE_8 MrcIoWrite8;
+ MRC_IO_WRITE_16 MrcIoWrite16;
+ MRC_IO_WRITE_32 MrcIoWrite32;
+ MRC_MMIO_READ_8 MrcMmioRead8;
+ MRC_MMIO_READ_16 MrcMmioRead16;
+ MRC_MMIO_READ_32 MrcMmioRead32;
+ MRC_MMIO_READ_64 MrcMmioRead64;
+ MRC_MMIO_WRITE_8 MrcMmioWrite8;
+ MRC_MMIO_WRITE_16 MrcMmioWrite16;
+ MRC_MMIO_WRITE_32 MrcMmioWrite32;
+ MRC_MMIO_WRITE_64 MrcMmioWrite64;
+ MRC_SMBUS_READ_8 MrcSmbusRead8;
+ MRC_SMBUS_READ_16 MrcSmbusRead16;
+ MRC_SMBUS_WRITE_8 MrcSmbusWrite8;
+ MRC_SMBUS_WRITE_16 MrcSmbusWrite16;
+ MRC_GET_PCI_DEVICE_ADDRESS MrcGetPciDeviceAddress;
+ MRC_GET_PCIE_DEVICE_ADDRESS MrcGetPcieDeviceAddress;
+ MRC_GET_RTC_TIME MrcGetRtcTime;
+ MRC_GET_CPU_TIME MrcGetCpuTime;
+ MRC_MEMORY_COPY MrcCopyMem;
+ MRC_MEMORY_SET_BYTE MrcSetMem;
+ MRC_MEMORY_SET_WORD MrcSetMemWord;
+ MRC_MEMORY_SET_DWORD MrcSetMemDword;
+ MRC_LEFT_SHIFT_64 MrcLeftShift64;
+ MRC_RIGHT_SHIFT_64 MrcRightShift64;
+ MRC_MULT_U64_U32 MrcMultU64x32;
+ MRC_DIV_U64_U64 MrcDivU64x64;
+ MRC_GET_SPD_DATA MrcGetSpdData;
+ MRC_GET_RANDOM_NUMBER MrcGetRandomNumber;
+ MRC_CPU_MAILBOX_READ MrcCpuMailboxRead;
+ MRC_CPU_MAILBOX_WRITE MrcCpuMailboxWrite;
+ MRC_GET_MEMORY_VDD MrcGetMemoryVdd;
+ MRC_SET_MEMORY_VDD MrcSetMemoryVdd;
+ MRC_CHECKPOINT MrcCheckpoint;
+ MRC_DEBUG_HOOK MrcDebugHook;
+ MRC_PRINT_STRING MrcPrintString;
+ MRC_GET_RTC_CMOS MrcRtcCmos;
+ MRC_MSR_READ_64 MrcReadMsr64;
+ MRC_MSR_WRITE_64 MrcWriteMsr64;
+ MRC_RETURN_FROM_SMC MrcReturnFromSmc;
+ MRC_DRAM_RESET MrcDramReset;
+ MRC_SET_LOCK_PRMRR MrcSetLockPrmrr;
+ MRC_TXT_ACHECK MrcTxtAcheck;
+} MRC_FUNCTION;
+
+///
+///*****************************************
+/// Output related "global data" structures.
+///*****************************************
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are SDRAM level definitions. All ranks on a rank are set to these values.
+///
+/* Commented out until needed, in order to save space.
+typedef struct {
+} MrcSdramOut;
+*/
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are rank level definitions. All ranks on a DIMM are set to these values.
+///
+typedef struct {
+//MrcSdramOut Sdram[MAX_SDRAM_IN_DIMM]; ///< The following are SDRAM level definitions.
+ UINT16 MR[MAX_MR_IN_DIMM]; ///< DRAM mode register value.
+ UINT16 MR11; ///< LPDDR3 ODT MR
+ UINT8 Ddr4PdaMr6[MAX_SDRAM_IN_DIMM]; ///< DDR4 MR6[6:0] for per-DRAM VrefDQ (PDA)
+#if (SUPPORT_DDR4 == SUPPORT)
+ UINT8 Device[MAX_SDRAM_IN_DIMM]; ///< Which Bytes are tied to which Device where BIT0 set means Byte 0
+#endif //SUPPORT_DDR4
+} MrcRankOut;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are DIMM level definitions. All ranks on a DIMM are set to these values.
+///
+typedef struct {
+ MrcDimmSts Status; ///< See MrcDimmSts for the definition of this field.
+ MrcTiming Timing[MAX_PROFILE]; ///< The DIMMs timing values.
+ MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The voltage (VDD) setting for this DIMM, per profile.
+ BOOLEAN EccSupport; ///< TRUE if ECC is enabled and supported on this DIMM.
+ BOOLEAN IgnoreNonEccDimm; ///< TRUE if a DIMM without ECC capability should be ignored.
+ BOOLEAN AddressMirrored; ///< TRUE if the DIMM is address mirrored.
+ BOOLEAN SelfRefreshTemp; ///< TRUE if the DIMM supports self refresh extended operating temperature range (SRT).
+ BOOLEAN AutoSelfRefresh; ///< TRUE if the DIMM supports automatic self refresh (ASR).
+ BOOLEAN PartialSelfRefresh; ///< TRUE if the DIMM supports Partial Array Self Refresh (PASR).
+ BOOLEAN OnDieThermalSensor; ///< TRUE if the DIMM supports On-die Thermal Sensor (ODTS) Readout.
+ BOOLEAN ExtendedTemperRange; ///< TRUE if the DIMM supports Extended Temperature Range (ETR).
+ BOOLEAN ExtendedTemperRefresh; ///< TRUE if the DIMM supports 1x Extended Temperature Refresh rate, FALSE = 2x.
+ MrcDdrType DdrType; ///< DDR type: DDR3 or LPDDR3
+ MEMORY_PACKAGE ModuleType; ///< Module type: UDIMM, SO-DIMM, etc.
+ UINT32 SdramCount; ///< The number of SDRAM components on a DIMM.
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT32 RowSize; ///< The DIMMs row address size.
+ UINT16 ColumnSize; ///< The DIMMs column address size.
+ UINT16 Crc; ///< Calculated CRC16 of the DIMM's provided SPD. Can be used to detect DIMM change.
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 Banks; ///< Number of banks the DIMM contains.
+ UINT8 BankGroups; ///< Number of bank groups the DIMM contains.
+ UINT8 PrimaryBusWidth; ///< DIMM primary bus width.
+ UINT8 SdramWidth; ///< DIMM SDRAM width.
+ UINT8 SdramWidthIndex; ///< DIMM SDRAM width index (0 = x4, 1 = x8, 2 = x16, 3 = x32).
+ UINT8 DensityIndex; ///< Total SDRAM capacity index (0 = 256Mb, 1 = 512Mb, 2 = 1Gb, etc).
+ UINT8 tMAC; ///< Maximum Activate Count for pTRR.
+ UINT8 ReferenceRawCard; ///< Indicates which JEDEC reference design raw card was used as the basis for the module assembly.
+ UINT8 ReferenceRawCardRevision; ///< Indicates which JEDEC reference design raw card revsion.
+ UINT8 XmpSupport; ///< Indicates if XMP profiles are supported. 0 = None, 1 = XMP1 only, 2 = XMP2 only, 3 = All.
+ UINT8 XmpRevision; ///< Indicates the XMP revision of this DIMM. 0 = None, 12h = 1.2, 13h = 1.3.
+ MrcRankOut Rank[MAX_RANK_IN_DIMM]; ///< The following are rank level definitions.
+} MrcDimmOut;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are channel level definitions. All DIMMs on a memory channel are set to these values.
+///
+typedef struct {
+ MrcChannelSts Status; ///< Indicates whether this channel should be used.
+ MrcVirtualChannel VirtualChannel; ///< define the virtual channel type A or B.
+ MrcTiming Timing[MAX_PROFILE]; ///< The channel timing values.
+ MrcTimeBase TimeBase[MAX_DIMMS_IN_CHANNEL][MAX_PROFILE]; ///< Medium and fine timebases for each DIMM in the channel and each memory profile.
+ UINT32 Capacity; ///< Amount of memory in this channel, in MBytes.
+ UINT32 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ UINT32 DataOffsetTrain[MAX_SDRAM_IN_DIMM]; ///< DataOffsetTrain CR
+ UINT32 DataCompOffset[MAX_SDRAM_IN_DIMM]; ///< DataCompOffset CR
+ UINT32 CkeCmdPiCode[MAX_COMMAND_GROUPS]; ///< CKE CmdPiCode CR, per group
+ UINT32 CmdsCmdPiCode[MAX_COMMAND_GROUPS]; ///< CmdS CmdPiCode CR, per group
+ UINT32 CmdnCmdPiCode[MAX_COMMAND_GROUPS]; ///< CmdN CmdPiCode CR, per group
+ UINT16 TxDqs[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxDQS PI Code
+ UINT16 TxDq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxDQ Pi Code
+ UINT16 RcvEn[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RcvEn PI Code
+ UINT16 WlDelay[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< WlDelay PI Code
+ UINT8 ClkPiCode[MAX_RANK_IN_CHANNEL]; ///< Clk Pi Code
+ UINT8 CtlPiCode[MAX_RANK_IN_CHANNEL]; ///< Ctl Pi Code
+ UINT8 CkePiCode[MAX_RANK_IN_CHANNEL]; ///< Ctl Pi Code
+ UINT8 TxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< TxEq setting
+ MrcCommandMargin Command[MAX_RANK_IN_CHANNEL]; ///< Cmd setting
+ MrcDqTimeMargin RxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Pi Code
+ MrcDqTimeMargin TxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Tx PerBit Pi Code
+ MrcDqVrefMargin RxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Vref
+ MrcDqVrefMargin TxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_BITS]; ///< Rx PerBit Vref
+ MrcRecvEnMargin ReceiveEnable[MAX_RANK_IN_CHANNEL]; ///< Receive enable per rank
+ MrcWrLevelMargin WriteLevel[MAX_RANK_IN_CHANNEL]; ///< Write leveling per rank
+ UINT8 IoLatency[MAX_RANK_IN_CHANNEL]; ///< IOLatency
+ UINT8 RTLatency[MAX_RANK_IN_CHANNEL]; ///< RoundTripLatency
+ UINT32 RTIoComp; ///< RoundTrip IO Compensation of the Channel
+ UINT8 RxVref[MAX_SDRAM_IN_DIMM]; ///< RX Vref in steps of 7.9 mv
+ UINT8 RxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RxEQ Setting
+ UINT8 RxDqsP[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RxDQSP PI Code
+ UINT8 RxDqsN[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< RxDQSN PI Code
+ UINT8 ValidRankBitMask; ///< Bit map of the populated ranks per channel
+ UINT8 ValidCkeBitMask; ///< Bit map of the used CKE pins per channel
+ MrcDimmOut Dimm[MAX_DIMMS_IN_CHANNEL]; ///< DIMM specific output variables.
+} MrcChannelOut;
+
+///
+/// This data structure contains all the "global data" values that are considered output by the MRC.
+/// The following are memory controller level definitions. All channels on a controller are set to these values.
+///
+typedef struct {
+ MrcControllerSts Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ MrcChannelOut Channel[MAX_CHANNEL]; ///< The following are channel level definitions.
+} MrcControllerOut;
+
+///
+///********************************************
+/// Saved data related "global data" structures.
+///********************************************
+///
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are DIMM level definitions.
+///
+typedef struct {
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+} MrcDimmSave;
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are channel level definitions.
+///
+typedef struct {
+ MrcChannelSts Status; ///< Indicates whether this channel should be used.
+ UINT32 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ UINT8 ValidRankBitMask; ///< Bit map of the populated ranks per channel
+ MrcTiming Timing[MAX_PROFILE]; ///< The channel timing values.
+ MrcDimmOut Dimm[MAX_DIMMS_IN_CHANNEL]; ///< Save the DIMM output characteristics.
+ MrcDimmSave DimmSave[MAX_DIMMS_IN_CHANNEL]; ///< Save SPD information needed for SMBIOS structure creation.
+} MrcChannelSave;
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are controller level definitions.
+///
+typedef struct {
+ MrcControllerSts Status; ///< Indicates whether this controller should be used.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ MrcChannelSave Channel[MAX_CHANNEL]; ///< The following are channel level definitions.
+} MrcContSave;
+
+///
+/// This data structure contains all the "global data" values that are considered to be needed
+/// by the MRC between power state transitions (S0->S3->S0) and also fast and warm boot modes.
+/// The following are system level definitions.
+///
+typedef struct {
+ UINT32 Crc; ///< The CRC-32 of the data in this structure.
+} MrcSaveHeader;
+
+//
+// ------- IMPORTANT NOTE --------
+// MRC_MC_REGISTER_COUNT in MrcInterface.h should match the table in MrcSaveRestore.c.
+// Update this define whenever you add/remove registers from this table.
+//
+#define MRC_REGISTER_COUNT_COMMON (1376 / sizeof (UINT32)) ///< The number of MC registers that need to be saved (common)
+#define MRC_REGISTER_COUNT_SAGV (1528 / sizeof (UINT32)) ///< The number of MC registers that need to be saved (per SA GV point)
+
+typedef struct {
+ MrcCapabilityId McCapId; ///< The memory controller's capabilities.
+ UINT32 RegSaveCommon[MRC_REGISTER_COUNT_COMMON]; ///< The MC registers that are common to both SA GV points
+ UINT32 RegSaveLow[MRC_REGISTER_COUNT_SAGV]; ///< The MC registers for the Low SA GV point
+ UINT32 RegSaveHigh[MRC_REGISTER_COUNT_SAGV]; ///< The MC registers for the High SA GV point, or for SA GV Disabled case
+ UINT32 MeStolenSize; ///< The managebility engine memory size, in Mbyte units.
+ MrcCpuStepping CpuStepping; ///< The last cold boot happended with this CPU stepping.
+ MrcCpuModel CpuModel; ///< The last cold boot happended with this CPU model.
+ MrcCpuFamily CpuFamily; ///< CPU is Skylake or Kabylake
+ MrcVersion Version; ///< The last cold boot happended with this MRC version.
+ UINT32 SaMemCfgCrc; ///< The CRC32 of the system agent memory configuration structure.
+ MrcContSave Controller[MAX_CONTROLLERS]; ///< The following are controller level definitions.
+ MrcFrequency Frequency; ///< The system's common memory controller frequency.
+ UINT32 MemoryClock; ///< The system's common memory controller clock, in femtoseconds.
+ BOOLEAN OddRatioModeLow; ///< If Odd Ratio Mode is enabled, QCLK frequency has an addition of 133/100 MHz. This is for SAGV Low point.
+ BOOLEAN OddRatioModeHigh; ///< If Odd Ratio Mode is enabled, QCLK frequency has an addition of 133/100 MHz. This is for SAGV High point, or SAGV disabled / fixed high / fixed low
+ MrcRefClkSelect RefClk; ///< The memory controller is going to use this reference clock.
+ MrcClockRatio Ratio; ///< Request for this memory controller to use this clock ratio.
+ MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The voltage (VDD) setting for all DIMMs in the system, per profile.
+ BOOLEAN EccSupport; ///< TRUE if ECC is enabled and supported on this controller.
+ MrcDdrType DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT32 DefaultXmptCK[MAX_PROFILE - XMP_PROFILE1]; ///< The Default XMP tCK values read from SPD.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ BOOLEAN BinnedLpddrDevices; ///< Binned LPDDR3 devices (6Gb/12Gb/etc)
+ BOOLEAN TCRSensitiveHynixDDR4; ///< TCR sensitive Hynix DDR4 in the system
+ BOOLEAN TCRSensitiveMicronDDR4; ///< TCR sensitive Micron DDR4 in the system
+ BOOLEAN LpddrEctDone; ///< Set to TRUE once Early Command Training on LPDDR is done, and we can run JEDEC Init
+ UINT8 BerEnable; ///< BER Enable (and # of Addresses)
+ UINT64 BerAddress[4]; ///< BER Addresses
+} MrcSaveData;
+
+typedef struct {
+ UINT32 Size; ///< The size of this structure, in bytes. Must be the first entry in this structure.
+ MrcDebug Debug; ///< MRC debug related variables used for serial output and debugging purposes.
+ MrcVersion Version; ///< The memory reference code version.
+ MrcFrequency FreqMax; ///< The requested maximum valid frequency.
+ MrcFrequency Frequency; ///< The system's common memory controller frequency.
+ UINT32 MemoryClockMax; ///< The system's common memory controller maximum clock, in femtoseconds.
+ UINT32 MemoryClock; ///< The system's common memory controller clock, in femtoseconds.
+ MrcRefClkSelect RefClk; ///< The memory controller is going to use this reference clock.
+ MrcClockRatio Ratio; ///< Request for this memory controller to use this clock ratio.
+ MrcMemoryMap MemoryMapData; ///< The system's memory map data.
+ MrcGfxDataSize GraphicsStolenSize; ///< Graphics Data Stolen Memory size in MB
+ MrcGfxGttSize GraphicsGttSize; ///< GTT graphics stolen memory size in MB
+ MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The currently running voltage (VDD) setting for all DIMMs in the system, per profile.
+ MrcGdxc Gdxc; ///< GDXC enable and size.
+ BOOLEAN VddVoltageDone; ///< To determine if VddVoltageDone update has been done already
+ BOOLEAN EccSupport; ///< TRUE if ECC is enabled and supported on this controller.
+ BOOLEAN EnDumRd; ///< Enable/Disable Logic Analyzer
+ BOOLEAN RestoreMRs; ///< Enable/Disable restoring
+ BOOLEAN LpddrEctDone; ///< Set to TRUE once Early Command Training on LPDDR is done, and we can run JEDEC Init
+ BOOLEAN LpddrWLUpdated; ///< Set to TRUE once LPDDR WL Memory Set has been updated
+ BOOLEAN JedecInitDone; ///< Set to TRUE once JEDEC Init on LPDDR/DDR4 is done
+ UINT32 DefaultXmptCK[MAX_PROFILE - XMP_PROFILE1]; ///< The Default XMP tCK values read from SPD.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ BOOLEAN Capable100; ///< The MC is capable of 100 reference clock (0 = no, 1 = yes).
+ BOOLEAN AutoSelfRefresh; ///< Indicates ASR is supported for all the DIMMS for 2xRefresh
+ MrcDdrType DdrType; ///< Current memory type: DDR3, DDR4, or LPDDR3
+ MrcSpdStatus SpdSecurityStatus; ///< Status variable to inform BIOS that memory contains an alias.
+ UINT32 MrcTotalChannelLimit; ///< The maximum allowed memory size per channel, in MBytes.
+ UINT8 SdramCount; ///< The number of SDRAM components on a DIMM.
+ UINT16 Qclkps; ///< Qclk period in pS
+ UINT8 DQPat; ///< Global Variables storing the current DQPat REUT Test
+ INT8 DQPatLC; ///< Global Variables storing the current DQPat Loopcount
+ UINT8 ValidRankMask; ///< Rank bit map - includes both channels
+ UINT8 ValidChBitMask; ///< Channel bit map of the populated channels
+ BOOLEAN UpmPwrRetrainFlag; ///< A flag that indicates if training with higher UPM/PWR limits.
+ UINT32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES]; ///< Stores last margin measurement.
+ BOOLEAN MarginSignReversed[MAX_RANK_IN_CHANNEL][MAX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES]; ///< Indicates if the Margin Sign is Reversed
+ MrcOdtPowerSaving OdtPowerSavingData; ///< ODT power savings data.
+ BOOLEAN TxDIMMVref[MAX_CHANNEL]; ///< Whether Write DIMM Vref is enabled based on Channel
+ UINT32 MchBarWriteCount; ///< The number of MMIO writes performed during MRC execution.
+ UINT32 MchBarReadCount; ///< The number of MMIO reads performed during MRC execution.
+ UINT8 BerEnable; ///< BER Enable (and # of Addresses)
+ UINT64 BerAddress[4]; ///< BER Addresses
+ UINT8 CmdVLoop; ///< Keeps track of the # of CmdV training step runned
+ UINT8 CmdVLoopStatus; ///< Keeps the last status of the CmdV training step
+ UINT8 tMAC; ///< Maximum Activate Count for pTRR.
+ UINT8 LpddrMemWriteLatencySet; ///< 0 = Set A (WL), 1 = Set B (WL) if supported
+ BOOLEAN Ddr4PdaEnable; ///< Current status of PDA - if true all the Mr6 operations need to use PDA mode.
+ BOOLEAN BinnedLpddrDevices; ///< Binned LPDDR3 devices (6Gb/12Gb/etc)
+ MrcControllerOut Controller[MAX_CONTROLLERS]; ///< The following are controller level definitions.
+ BOOLEAN TCRSensitiveHynixDDR4; ///< TCR sensitive Hynix DDR4 in the system
+ BOOLEAN TCRSensitiveMicronDDR4; ///< TCR sensitive Micron DDR4 in the system
+ BOOLEAN OddRatioMode; ///< If Odd Ratio Mode is enabled, QCLK frequency has an addition of 133/100 MHz
+ BOOLEAN LpddrDramOdt; ///< Indicates if LPDDR DRAM ODT is used - Only used for 2133+
+#ifdef BDAT_SUPPORT
+ union {
+ MRC_BDAT_SCHEMA_LIST_HOB *Pointer; ///< Pointer to the BDAT schema list.
+ UINT64 Data;
+ } BdatSchemasHob;
+ union {
+ BDAT_MEMORY_DATA_HOB *Pointer; ///< Pointer to the BDAT memory data HOB.
+ UINT64 Data;
+ } BdatMemoryHob[MAX_SCHEMA_LIST_LENGTH];
+#endif
+
+} MrcOutput;
+
+///
+///****************************************
+/// Input related "global data" structures.
+///****************************************
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are SDRAM level definitions. All ranks on a rank are set to these values.
+///
+/* Commented out until needed, in order to save space.
+typedef struct {
+ UINT8 Placeholder; ///< TODO: Is there anything that needs to go in here?
+} MrcSdramIn;
+*/
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are rank level definitions. All ranks on a DIMM are set to these values.
+///
+/* Commented out until needed, in order to save space.
+typedef struct {
+ MrcSdramIn Sdram[MAX_SDRAM_IN_DIMM]; ///< The following are SDRAM level definitions.
+} MrcRankIn;
+*/
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are DIMM level definitions. All ranks on a DIMM are set to these values.
+///
+typedef struct {
+ MrcDimmSts Status; ///< Indicates whether this DIMM should be used.
+ MrcSpdData Spd; ///< The SPD data for each DIMM. SPDGeneral field = 0 when absent.
+ MrcTiming Timing; ///< The DIMMs requested timing overrides.
+ UINT8 SpdAddress; ///< The SMBus address for the DIMM's SPD data.
+//MrcRankIn Rank[MAX_RANK_IN_DIMM]; ///< The following are rank level definitions.
+} MrcDimmIn;
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are channel level definitions. All DIMMs on a memory channel are set to these values.
+///
+typedef struct {
+ MrcChannelSts Status; ///< Indicates whether this channel should be used.
+ UINT32 DimmCount; ///< The maximum number of DIMMs on this channel.
+ MrcDimmIn Dimm[MAX_DIMMS_IN_CHANNEL]; ///< The following are DIMM level definitions.
+ UINT8 DqsMapCpu2Dram[8]; ///< Mapping from CPU DQS pins to SDRAM DQS pins
+ UINT8 DqMapCpu2Dram[8][MAX_BITS]; ///< Mapping from CPU DQ pins to SDRAM DQ pins
+ UINT8 DQByteMap[MrcIterationMax][2]; ///< Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side), per group
+ ///< DQByteMap[0] - ClkDQByteMap:
+ ///< If clock is per rank, program to [0xFF, 0xFF]
+ ///< If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+ ///< If clock is shared by 2 ranks but does not go to all bytes,
+ ///< Entry[i] defines which DQ bytes Group i services
+ ///< DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+ ///< DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+ ///< DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+ ///< For DDR, DQByteMap[3:1] = [0xFF, 0]
+ ///< DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+ ///< Variable only exists to make the code easier to use
+ ///< DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+ ///< Variable only exists to make the code easier to use
+} MrcChannelIn;
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are memory controller level definitions. All channels on a controller are set to these values.
+///
+typedef struct {
+ MrcControllerSts Status; ///< Indicates whether this controller should be used.
+ UINT8 ChannelCount; ///< Number of valid channels that are requested on the controller.
+ MrcChannelIn Channel[MAX_CHANNEL]; ///< The following are channel level definitions.
+} MrcControllerIn;
+
+///
+/// This data structure contains all the "global data" values that are considered input by the MRC.
+/// The following are system level definitions. All memory controllers in the system are set to these values.
+///
+typedef struct {
+ //
+ // Start of synchronization to the SA MEMORY_CONFIGURATION structure.
+ // Alignment of this block must be maintained and field offsets must match.
+ //
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 HobBufferSize; ///< Offset 28 Size of HOB buffer
+ //
+ // The following parameters are used only when SpdProfileSelected is UserDefined (CUSTOM PROFILE)
+ //
+ UINT8 MemoryProfile; ///< Offset 29 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Customized profile, 2=XMP profile 1, 3=XMP profile 2.
+ UINT16 tCL; ///< Offset 30 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
+ UINT16 tRCDtRP; ///< Offset 32 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tRAS; ///< Offset 34 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
+ UINT16 tWR; ///< Offset 36 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
+ UINT16 tRFC; ///< Offset 38 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
+ UINT16 tRRD; ///< Offset 40 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
+ UINT16 tWTR; ///< Offset 42 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRTP; ///< Offset 44 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
+ UINT16 tFAW; ///< Offset 46 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tCWL; ///< Offset 48 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
+ UINT16 tREFI; ///< Offset 50 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
+ UINT16 VddVoltage; ///< Offset 52 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT8 NModeSupport; ///< Offset 54 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
+
+ UINT8 McLock; ///< Offset 55 Enable/Disable memory configuration register locking: 0=Disable, <b>1=Enable</b>.
+ //
+ // Thermal Management
+ //
+ UINT32 ThermalManagement:1; ///< Offset 56 Memory Thermal Management Support: <b>0=Disable</b>, 1=Enable.
+ UINT32 PeciInjectedTemp:1; ///< - Enable/Disable memory temperatures to be injected to the processor via PECI: <b>0=Disable</b>, 1=Enable.
+ UINT32 ExttsViaTsOnBoard:1; ///< - Enable/Disable routing TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH: <b>0=Disable</b>, 1=Enable.
+ UINT32 ExttsViaTsOnDimm:1; ///< - Enable/Disable routing TS-on-DIMM's ALERT# to EXTTS# pin on the PCH: <b>0=Disable</b>, 1=Enable.
+ UINT32 VirtualTempSensor:1; ///< - Enable/Disable Virtual Temperature Sensor (VTS): <b>0=Disable</b>, 1=Enable.
+ UINT32 RsvdBits0:27;
+ //
+ // Training Algorithms
+ //
+ TrainingStepsEn TrainingEnables; ///< Offset 60 Options to Enable individual training steps
+
+ UINT32 MrcSafeConfig:1; ///< Offset 64 MRC Safe Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 EccSupport:1; ///< - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
+ UINT32 RemapEnable:1; ///< - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
+ UINT32 ScramblerEnable:1; ///< - Memory scrambler support: 0=Disable, <b>1=Enable</b>
+ UINT32 OddRatioMode:1; ///< - If Odd Ratio Mode is enabled, QCLK frequency has an addition of 133/100 MHz: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcTimeMeasure:1; ///< - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcFastBoot:1; ///< - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
+ UINT32 DqPinsInterleaved:1; ///< - Interleaving mode of DQ/DQS pins for HSW_ULT which depends on board routing: <b>0=Disable</b>, 1=Enable
+ UINT32 RankInterleave:1; ///< - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 EnhancedInterleave:1; ///< - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 WeaklockEn:1; ///< - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 CmdTriStateDis:1; ///< - CMD Tri-State Support: <b>0=Enable</b>, 1=Disable. Note: This should be set to 1 (Disable) if Command RTT is not present on the platform.
+ UINT32 MemoryTrace:1; ///< - Memory Trace to second DDR channel using Stacked Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 ChHashEnable:1; ///< - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 EnableExtts:1; ///< - Enable Extts: <b>0=Disable</b>, 1=Enable
+ UINT32 EnableCltm:1; ///< - Enable Closed Loop Thermal Management: <b>0=Disable</b>, 1=Enable
+ UINT32 EnableOltm:1; ///< - Enable Open Loop Thermal Management: <b>0=Disable</b>, 1=Enable
+ UINT32 EnablePwrDn:1; ///< - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 EnablePwrDnLpddr:1; ///< - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 LockPTMregs:1; ///< - Lock PCU Thermal Management registers: 0=Disable, <b>1=Enable</b>
+ UINT32 UserPowerWeightsEn:1; ///< - Allows user to explicitly set power weight, scale factor, and channel power floor values: <b>0=Disable</b>, 1=Enable
+ UINT32 RaplLim2Lock:1; ///< - Lock DDR_RAPL_LIMIT register: <b>0=Disable</b>, 1=Enable
+ UINT32 RaplLim2Ena:1; ///< - Enable Power Limit 2: <b>0=Disable</b>, 1=Enable
+ UINT32 RaplLim1Ena:1; ///< - Enable Power Limit 1: <b>0=Disable</b>, 1=Enable
+ UINT32 SrefCfgEna:1; ///< - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeatLpddr:1; ///< - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeat:1; ///< - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
+ UINT32 AutoSelfRefreshSupport:1; ///< - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
+ UINT32 ExtTemperatureSupport:1; ///< - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
+ UINT32 MobilePlatform:1; ///< - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
+ UINT32 Force1Dpc:1; ///< - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
+ UINT32 ForceSingleRank:1; ///< - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
+
+ UINT32 RhPrevention:1; ///< Offset 68 RH Prevention Enable/Disable: 0=Disable, <b>1=Enable</b>
+ UINT32 VttTermination:1; ///< - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
+ UINT32 VttCompForVsshi:1; ///< - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
+ UINT32 ExitOnFailure:1; ///< - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
+ UINT32 Vc1ReadMeter:1; ///< - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 DdrThermalSensor:1; ///< - Ddr Thermal Sensor: 0=Disable, <b>1=Enable</b>
+ UINT32 LpddrMemWriteLatencySet:1; ///< - LPDDR3 Write Latency Set option: 0=Set A, <b>1=Set B</b>
+ UINT32 EvLoader:1; ///< - Option to Enable EV Loader: <b>0=Disable</b>,1=Enable
+ UINT32 EvLoaderDelay:1; ///< - Option to Enable EV Loader Delay: 0=Disable, <b>1=Enable</b>
+ UINT32 Ddr4DdpSharedClock:1; ///< - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 Ddr4DdpSharedZq:1; ///< - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 RsvdBits1:21;
+
+ UINT32 BClkFrequency; ///< Offset 72 - Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
+ UINT16 DdrFreqLimit; ///< Offset 76 Memory Frequency Limit: <b>0=Auto (limited by SPD/CPU capability)</b>, for valid values see MrcFrequency in MrcInterface.h
+ /**
+ Selects the DDR base reference clock\n
+ <b>0x00 = 133MHz</b>
+ 0x01 = 100MHz
+ **/
+ UINT8 RefClk; ///< Offset 78
+ /**
+ Selects the ratio to multiply the reference clock by for the DDR frequency\n
+ When RefClk is 133MHz\n
+ <b>0x00 = Auto</b>, 0x03 through 0x0C are valid values, all others are invalid\n
+ When RefClk is 100MHz\n
+ <b>0x00 = Auto</b>, 0x06 through 0x10 are valid values, all others are invalid\n
+ **/
+ UINT8 Ratio; ///< Offset 79
+ MrcGdxc Gdxc; ///< Offset 80 GDXC enable and size.
+ /**
+ - Channel Hash Enable.\n
+ NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8\n
+ 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
+ **/
+ UINT8 ChHashInterleaveBit; ///< Offset 83
+ UINT16 ChHashMask; ///< Offset 84 - Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ /**
+ Disables a DIMM slot in the channel even if a DIMM is present\n
+ Array index represents the channel number (0 = channel 0, 1 = channel 1)\n
+ <b>0x0 = DIMM 0 and DIMM 1 enabled</b>\n
+ 0x1 = DIMM 0 disabled, DIMM 1 enabled\n
+ 0x2 = DIMM 0 enabled, DIMM 1 disabled\n
+ 0x3 = DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n
+ **/
+ UINT8 DisableDimmChannel[MAX_CHANNEL];///< Offset 86
+ ThermalMngmtEn ThermalEnables; ///< Offset 88
+
+ UINT16 SrefCfgIdleTmr; ///< Offset 132 - Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
+ UINT8 MaxRttWr; ///< Offset 134 - Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
+ UINT8 ThrtCkeMinTmr; ///< Offset 135 - Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x30=Default</b>
+ UINT8 ThrtCkeMinTmrLpddr; ///< Offset 136 - Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x40=Default</b>
+
+ UINT8 EnergyScaleFact; ///< Offset 137 - Energy Scale Factor. 0=Minimal, 7=Maximum, <b>4=Default</b>
+ UINT8 RaplPwrFlCh1; ///< Offset 138 - Power Channel 1 Floor value: <b>0=Minimal</b>, 255=Maximum
+ UINT8 RaplPwrFlCh0; ///< Offset 139 - Power Channel 0 Floor value: <b>0=Minimal</b>, 255=Maximum
+ UINT8 PowerDownMode; ///< Offset 140 - CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
+ UINT8 PwdwnIdleCounter; ///< Offset 141 - CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
+ UINT8 CkeRankMapping; ///< Offset 142 - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies which rank CKE[i] goes to.
+ UINT8 BerEnable; ///< Offset 143 - BER Enable and # of Addresses passed in: <b>0=Minimal</b>, 8=Maximum
+ UINT64 BerAddress[4]; ///< Offset 144 - BER Address(es): <b>0=Minimal</b>, 0xFFFFFFFFFFFFFFFF=Maximum (step is 0x40)
+ UINT16 PciIndex; ///< Offset 176 - Pci index register address: <b>0xCF8=Default</b>
+ UINT16 PciData; ///< Offset 178 - Pci data register address: <b>0xCFC=Default</b>
+
+ UINT8 StrongWkLeaker; ///< Offset 180 - Strong Weak Leaker: 1=Minimal, <b>7=Maximum</b>
+ UINT8 CaVrefConfig; ///< Offset 181 0=VREF_CA goes to both CH_A and CH_B, 1=VREF_CA to CH_A, VREF_DQ_A to CH_B, <b>2=VREF_CA to CH_A, VREF_DQ_B to CH_B</b>
+ UINT16 FreqSaGvLow; ///< Offset 182 SA GV Low: 0 is Auto/default, otherwise holds the frequency value: <b>0=Default</b>, 1067, 1200, 1333, 1400, 1600, 1800, 1867. NOTE: must be below or equal to the SA GV High frequency.
+ UINT32 Vc1ReadMeterTimeWindow; ///< Offset 184 - VC1 Read Meter Time Window: 0=Minimal, 0x1FFFF=Maximum, <b>0x320=Default</b>
+ UINT16 Vc1ReadMeterThreshold; ///< Offset 188 - VC1 Read Meter Threshold (within Time Window): 0=Minimal, 0xFFFF=Maximum, <b>0x118=Default</b>
+ UINT16 Idd3n; ///< Offset 190 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
+ UINT16 Idd3p; ///< Offset 192 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
+ UINT8 EpgEnable; ///< Offset 194 Enable Energy Performance Gain.
+ UINT8 RhSolution; ///< Offset 195 Type of solution to be used for RHP - 0/1 = HardwareRhp/Refresh2x
+ UINT8 RhActProbability; ///< Offset 196 Activation probability for Hardware RHP
+ UINT8 SaGv; ///< Offset 197 SA GV: <b>0=Disabled</b>, 1=FixedLow, 2=FixedHigh, 3=Enabled
+
+ UINT8 UserThresholdEnable; ///< Offset 198 - Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 UserBudgetEnable; ///< Offset 199 - Flag to manually select the Budget Regiseters for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 TsodTcritMax; ///< Offset 200 - TSOD Tcrit Maximum Value to be Configure , 0=Minimal, 128=Maximum, , <b>105=Default</b>
+ UINT8 TsodEventMode; ///< Offset 201 - Flag to Enable Event Mode Interruption in TSOD Configuration Register, 0=Disable, 1=Enable, <b>1=Default</b>
+ UINT8 TsodEventPolarity; ///< Offset 202 - Event Signal Polarity in TSOD Configuration Register, 0=Low, 1=High, <b>0=Default</b>
+ UINT8 TsodCriticalEventOnly; ///< Offset 203 - Critical Trigger Only in TSOD Configuration Register,0=Disable, 1=Enable, <b>1=Default</b>
+ UINT8 TsodEventOutputControl; ///< Offset 204 - Event Output Control in TSOD Configuration Register,0=Disable, 1=Enable, <b>1=Default</b>
+ UINT8 TsodAlarmwindowLockBit; ///< Offset 205 - Alarm Windows Lock Bit in TSOD Configuration Register,0=Unlock, 1=Lock, <b>0=Default</b>
+ UINT8 TsodCriticaltripLockBit;///< Offset 206 - Critical Trip Lock Bit in TSOD Configuration Register,0=Unlock, 1=Lock, <b>0=Default</b>
+ UINT8 TsodShutdownMode; ///< Offset 207 - Shutdown Mode TSOD Configuration Register,0=Enable, 1=Disable, <b>0=Default</b>
+ UINT8 TsodThigMax; ///< Offset 208 - Thigh Max Value In the for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 TsodManualEnable; ///< Offset 209 - Flag to manually select the TSOD Register Values , 0=Disable, 1=Enable, <b>0=Default</b>
+
+ UINT8 RetrainOnFastFail; ///< Offset 210 - Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
+ UINT8 ForceOltmOrRefresh2x; ///< Offset 211 - Force OLTM or 2X Refresh when needed. <b>0 = Force OLTM</b>, 1 = Force 2x Refresh
+ UINT8 DllBwEn0; ///< Offset 212 - DllBwEn value for 1067
+ UINT8 DllBwEn1; ///< Offset 213 - DllBwEn value for 1333
+ UINT8 DllBwEn2; ///< Offset 214 - DllBwEn value for 1600
+ UINT8 DllBwEn3; ///< Offset 215 - DllBwEn value for 1867 and up
+ UINT32 VddSettleWaitTime; ///< Offset 216 - Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
+ UINT8 EnCmdRate; ///< Offset 220 - CMD Rate Enable: 0=Disable, 1=1 CMD, 2=2 CMDs, <b>3=3 CMDs</b>, 4=4 CMDs, 5=5 CMDs, 6=6 CMDs, 7=7 CMDs
+ UINT8 Refresh2X; ///< Offset 221 - Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
+ UINT8 SmramMask; ///< Offset 222 Reserved memory ranges for SMRAM
+ UINT8 Rsvd0; ///< Offset 223 - Reserved.
+
+ TrainingStepsEn2 TrainingEnables2; ///< Offset 224 - Options to Enable individual training steps
+ //
+ // End of synchronization to the SA MEMORY_CONFIGURATION structure.
+ //
+ MrcFrequency FreqMax; ///< The requested maximum valid frequency.
+ MrcBoardType BoardType; ///< define the board type (CRBMB,CRBDT,User1,User2). the OEM can add more boards.
+ MrcCpuStepping CpuStepping; ///< define the CPU stepping.
+ MrcCpuModel CpuModel; ///< define the CPU model.
+ MrcCpuFamily CpuFamily; ///< CPU is Skylake or Kabylake
+ MrcGfxDataSize GraphicsStolenSize; ///< Graphics Data Stolen Memory size in MB
+ MrcGfxGttSize GraphicsGttSize; ///< GTT graphics stolen memory size in MB
+ MrcBaseTime BaseTime; ///< RTC base time.
+ MrcIteration Iteration; ///< Number of interations thru the MRC core call table.
+ MrcMode MrcMode; ///< The control for full or MiniBIOS MRC.
+ MrcBootMode BootMode; ///< The requested memory controller boot mode.
+ BOOLEAN TxtFlag; ///< Trusted eXecution Technology flag.
+ BOOLEAN SetRxDqs32; ///< Set DQS Delay to 32 control.
+ BOOLEAN GfxIsVersatileAcceleration; ///< iGFX engines are in Versatile Acceleration
+ BOOLEAN DDR4MAP; ///< DDR4 PDA Mapping training control.
+ UINT32 SaMemCfgAddress; ///< Starting address of the input parameters to CRC.
+ UINT32 SaMemCfgSize; ///< The size of the input parameters to CRC.
+ UINT32 PciEBaseAddress; ///< define the PciE base address.
+ UINT32 MchBarBaseAddress; ///< define the MCH bar base address.
+ UINT32 SmbusBaseAddress; ///< This field defines the smbus base address.
+ UINT32 GdxcBaseAddress; ///< This field defines the GDXC base address.
+ UINT32 HpetBaseAddress; ///< This field defines the hpet base address.
+ UINT32 MeStolenSize; ///< define the size that the ME need in MB.
+ UINT32 MmioSize; ///< define the MMIO size in MB.
+ UINT32 TsegSize; ///< TSEG size that require by the system in MB.
+ UINT32 IedSize; ///< IED size that require by the system in MB.
+ UINT32 DprSize; ///< DPR size required by system in MB.
+ UINT32 PrmrrSize; ///< Prmrr size required by the system in MB.
+ UINT32 SerialBuffer; ///< Pointer to the start of the serial buffer.
+ UINT32 SerialBufferSize; ///< The size of the serial buffer, in bytes.
+ UINT32 DebugStream; ///< The debug port pointer.
+ UINT32 MmaTestContentPtr; ///< Pointer to MMA Test Content Data. Used in FSP.
+ UINT32 MmaTestContentSize; ///< Size of MMA Test Content Data. Used in FSP.
+ UINT32 MmaTestConfigPtr; ///< Pointer to MMA Test Config Data. Used in FSP.
+ UINT32 MmaTestConfigSize; ///< Size of MMA Test Config Data. Used in FSP.
+ INT32 DebugLevel; ///< Indicates the level of debug messaging.
+ UINT16 VccIomV; ///< VccIO logic voltage in mV.
+ MrcControllerIn Controller[MAX_CONTROLLERS]; ///< The following are controller level definitions.
+ BOOLEAN RmtPerTask; ///< Option to enable RMT after major training steps
+#ifdef SSA_FLAG
+ UINT32 SsaCallbackPpi;
+#endif // SSA_FLAG
+ UINT32 HeapBase; ///< Starting address of the heap space.
+ UINT32 HeapSize; ///< Size of the heap space, in bytes.
+ UINT32 MrcStackTop; ///< Top of the stack at the beginning of MRC, for stack usage calculations.
+ BOOLEAN RmtBdatEnable; ///< Option to enable output of training results into BDAT.
+ BOOLEAN LpddrDramOdt; ///< TRUE if LPDDR DRAM ODT is used - depends on board design
+ BOOLEAN Ddr3DramOdt; ///< TRUE if DDR3 DRAM ODT is used - depends on board design
+ BOOLEAN Ddr4DramOdt; ///< TRUE if DDR4 DRAM ODT is used - depends on board design
+ BOOLEAN EnableVrefPwrDn; ///< Setting this limits VrefGen to be off only during CKEPowerDown
+ BOOLEAN TxEqDis; ///< Disable TX Equalization
+ BOOLEAN EnVttOdt; ///< Enable VTT Termination for Data ODT
+ UINT32 CpuidModel; ///< Unique CPU identifier.
+ UINT8 CpuidStepping; ///< Revision of the CPU.
+ UINT32 SiPreMemPolicyPpi;
+ TrainingModeType PowerTrainingMode; ///< 0 - Power Training. 1 - Margin Training.
+ union {
+ MRC_FUNCTION *Func; ///< External to MRC function pointers
+ UINT64 Data;
+ } Call;
+ UINT16 RcompResistor[MAX_RCOMP]; ///< Reference RCOMP resistors on motherboard
+ UINT16 RcompTarget[MAX_RCOMP_TARGETS]; ///< RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
+ UINT32 CleanMemory:1; ///< TRUE to request a memory clean
+ UINT32 RsvdBits5:31;
+ /**
+ Sets the serial debug message level\n
+ 0x00 = Disabled\n
+ 0x01 = Errors only\n
+ 0x02 = Errors and Warnings\n
+ <b>0x03 = Errors, Warnings, and Info</b>\n
+ 0x04 = Errors, Warnings, Info, and Events\n
+ 0x05 = Displays Memory Init Execution Time Summary only\n
+ **/
+ UINT8 SerialDebugLevel; ///<
+} MrcInput;
+
+typedef struct {
+ UINT32 Size; ///< The size of this structure, in bytes. Must be the first entry in this structure.
+ MrcSaveHeader Header; ///< The header portion of the MRC saved data.
+ MrcSaveData Data; ///< The data portion of the MRC saved data.
+} MrcSave;
+
+typedef struct {
+ // Global variables that will be copied to the HOB follow.
+ UINT8 MrcDataString[4]; ///< Beginning of global data marker, starts with "MRC". Must be the first entry in this structure.
+ UINT32 MrcDataSize; ///< The size of the MRC global data area, in bytes. Must be the second entry in this structure.
+ MrcSave Save; ///< System specific save variables.
+ MrcInput Inputs; ///< System specific input variables.
+ MrcOutput Outputs; ///< System specific output variables.
+
+ // Global variables that will remain internal to the MRC library follow.
+ union {
+ void *Internal; ///< System specific output variables that remain internal to the library.
+ UINT64 Data;
+ } IntOutputs;
+} MrcParameters;
+
+/**
+ This function returns the recommended MRC boot mode.
+
+ @param[in] MrcData - include all the MRC general data.
+
+ @retval bmWarm if we are in self refresh and the DISB bit is set, otherwise returns bmCold.
+**/
+extern
+MrcBootMode
+MrcGetBootMode (
+ IN MrcParameters * const MrcData
+ );
+
+/**
+ This function return the MRC version.
+
+ @param[in] MrcData - include all the MRC general data.
+ @param[out] Version - Location to store the MRC version.
+**/
+extern
+void
+MrcVersionGet (
+ IN const MrcParameters *const MrcData,
+ OUT MrcVersion *const Version
+ );
+
+/**
+ Print the MRC version to the MRC output device.
+
+ @param[in] *MrcData - Pointer to the MRC Debug structure.
+ @param[in] Version - The MRC version.
+**/
+extern
+void
+MrcVersionPrint (
+ IN MrcParameters *MrcData,
+ IN const MrcVersion *Version
+ );
+
+/**
+ Calculates a CRC-32 of the specified data buffer.
+
+ @param[in] Data - Pointer to the data buffer.
+ @param[in] DataSize - Size of the data buffer, in bytes.
+
+ @retval The CRC-32 value.
+**/
+extern
+UINT32
+MrcCalculateCrc32 (
+ IN const UINT8 *const Data,
+ IN const UINT32 DataSize
+ );
+
+/**
+ This function resets the DISB bit in General PM Configuration 2 B:D:F 0,31,0 offset 0xA2.
+
+ @param[in] MrcData - include all the MRC general data.
+**/
+extern
+void
+MrcResetDISB (
+ IN MrcParameters * const MrcData
+ );
+
+/**
+ Initializes the memory controller and DIMMs.
+
+ @param[in, out] MrcData - Include all MRC global data.
+ @param[in] Select - Specific task index to execute, or zero to run all tasks from the call table.
+ Used in the interpreter.
+
+ @retval mrcSuccess if the initialization succeeded, otherwise an error status indicating the failure.
+**/
+extern
+MrcStatus
+MrcStartMemoryConfiguration (
+ IN OUT MrcParameters *const MrcData,
+ IN UINT32 Select
+ );
+
+/**
+ Retrieve the current memory frequency and clock from the memory controller.
+
+ @param[in] MrcData - Include all MRC global data.
+ @param[in, out] MemoryClock - The current memory clock.
+ @param[in, out] Ratio - The current memory ratio setting.
+ @param[in, out] RefClk - The current memory reference clock.
+ @param[in, out] OddRatioMode - The current QCLK Odd Ratio mode.
+
+ @retval: The current memory frequency.
+**/
+MrcFrequency
+MrcGetCurrentMemoryFrequency (
+ MrcParameters * const MrcData,
+ UINT32 * const MemoryClock,
+ MrcClockRatio * const Ratio,
+ MrcRefClkSelect * const RefClk,
+ BOOLEAN * const OddRatioMode
+ );
+
+/**
+ This function get the current value of the sticky scratchpad register.
+
+ @param[in] MrcData - include all the MRC data.
+
+ @retval The current value of the sticky scratchpad register.
+
+ **/
+extern
+UINT64
+MrcWmRegGet (
+ IN MrcParameters *const MrcData
+ );
+
+/**
+ This function reads the current setting of the GDXC MOT region.
+
+ @param[in] MrcData - All the MRC global data.
+ @param[in, out] Start - The starting GDXC MOT address.
+ @param[in, out] End - The ending GDXC MOT address.
+
+ @retval Returns mrcSuccess if the value has been read.
+**/
+extern
+MrcStatus
+MrcGetGdxcMot (
+ IN MrcParameters *const MrcData,
+ IN OUT UINT32 *const Start,
+ IN OUT UINT32 *const End
+ );
+
+/**
+ This function reads the current setting of the GDXC OCLA region.
+
+ @param[in] MrcData - All the MRC global data.
+ @param[in, out] Start - The starting GDXC MOT address.
+ @param[in, out] End - The ending GDXC MOT address.
+
+ @retval Returns mrcSuccess if the value has been read.
+**/
+extern
+MrcStatus
+MrcGetGdxcOcla (
+ IN MrcParameters *const MrcData,
+ IN OUT UINT32 *const Start,
+ IN OUT UINT32 *const End
+ );
+
+/**
+ Gets pointers to functions inside of core.
+
+ @param[in] MrcData - All the MRC global data.
+ @param[out] CallMcAddressDecode - Pointer to the function MrcMcAddressDecode
+ @param[out] CallMcAddressEncode - Pointer to the function MrcMcAddressEncode
+ @param[out] CallChannelExist - Pointer to the function MrcChannelExist
+ @param[out] CallPrintf - Pointer to the function MrcPrintf
+ @param[out] CallChangeMargin - Pointer to the function ChangeMargin
+ @param[out] CallSignExtend - Pointer to the function MrcSignExtend
+ @param[out] CallShiftPIforCmdTraining - Pointer to the function ShiftPIforCmdTraining
+ @param[out] CallUpdateVrefWaitTilStable - Pointer to the function UpdateVrefWaitTilStable
+ @param[out] CallMrcThermalOverrides - Pointer to the function MrcThermalOverrides
+
+ @retval Returns mrcSuccess if the function succeeds.
+**/
+extern
+MrcStatus
+MrcGetCoreFunction (
+ IN const MrcParameters *const MrcData,
+ OUT UINT32 *CallMcAddressDecode,
+ OUT UINT32 *CallMcAddressEncode,
+ OUT UINT32 *CallChannelExist,
+ OUT UINT32 *CallPrintf,
+ OUT UINT32 *CallChangeMargin,
+ OUT UINT32 *CallSignExtend,
+ OUT UINT32 *CallShiftPIforCmdTraining,
+ OUT UINT32 *CallUpdateVrefWaitTilStable,
+ OUT UINT32 *CallMrcThermalOverrides
+ );
+
+
+/**
+ Set up the overrides required by the MiniBios execution.
+
+ @param[in] MrcData - Pointer to the MRC global data structure
+**/
+extern
+void
+MrcMiniBiosOverrides (
+ OUT MrcParameters *const MrcData
+ );
+
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcRmtData.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcRmtData.h new file mode 100644 index 0000000000..51d40ff376 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcRmtData.h @@ -0,0 +1,237 @@ +/** @file
+ Copies the memory related timing and configuration information into the
+ Compatible BIOS data (BDAT) table.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MrcRmtData_h_
+#define _MrcRmtData_h_
+
+#include "MrcTypes.h"
+
+#define VDD_1_350 1350 ///< VDD in millivolts
+#define VDD_1_500 1500 ///< VDD in millivolts
+#define PI_STEP_BASE 2048 ///< Magic number from spec
+#define PI_STEP_INTERVAL 128 ///< tCK is split into this amount of intervals
+#define PI_STEP ((PI_STEP_BASE) / (PI_STEP_INTERVAL))
+#define VREF_STEP_BASE 100 ///< Magic number from spec
+#define TX_VREF_STEP 7800 ///< TX Vref step in microvolts
+#define TX_VREF(VDD) (((TX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
+#define RX_VREF_STEP 8000 ///< TX Vref step in microvolts
+#define RX_VREF(VDD) (((RX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
+#define CA_VREF_STEP 8000 ///< TX Vref step in microvolts
+#define CA_VREF(VDD) (((CA_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
+
+#define MAX_SPD_RMT 512 ///< The maximum amount of data, in bytes, in an SPD structure.
+#define RMT_PRIMARY_VERSION 4 ///< The BDAT structure that is currently supported.
+#define RMT_SECONDARY_VERSION 0 ///< The BDAT structure that is currently supported.
+#define MAX_MODE_REGISTER 7 ///< Number of mode registers
+#define MAX_DRAM_DEVICE 9 ///< Maximum number of memory devices
+
+//
+// Warning: Bdat4.h has its own copy of this #define
+// make sure to change it in both places
+//
+#define MAX_SCHEMA_LIST_LENGTH (10)
+
+/*
+ Memory Schema GUID
+ This is private GUID used by MemoryInit internally.
+ {CE3F6794-4883-492C-8DBA-2FC098447710}
+*/
+#ifdef BDAT_SUPPORT
+extern EFI_GUID gEfiMemorySchemaGuid;
+#endif
+/*
+ GUID for Schema List HOB
+ This is private GUID used by MemoryInit internally.
+ {3047C2AC-5E8E-4C55-A1CB-EAAD0A88861B}
+*/
+extern EFI_GUID gMrcSchemaListHobGuid;
+
+
+#pragma pack(push, 1)
+
+typedef struct {
+ UINT8 RxDqLeft; ///< Units = piStep
+ UINT8 RxDqRight;
+ UINT8 TxDqLeft;
+ UINT8 TxDqRight;
+ UINT8 RxVrefLow; ///< Units = rxVrefStep
+ UINT8 RxVrefHigh;
+ UINT8 TxVrefLow; ///< Units = txVrefStep
+ UINT8 TxVrefHigh;
+} BDAT_DQ_MARGIN_STRUCTURE;
+
+typedef struct {
+ UINT8 RxDqLeft; ///< Units = piStep
+ UINT8 RxDqRight;
+ UINT8 TxDqLeft;
+ UINT8 TxDqRight;
+ UINT8 CmdLeft;
+ UINT8 CmdRight;
+ UINT8 RecvenLeft; ///< Units = recvenStep
+ UINT8 RecvenRight;
+ UINT8 WrLevelLeft; ///< Units = wrLevelStep
+ UINT8 WrLevelRight;
+ UINT8 RxVrefLow; ///< Units = rxVrefStep
+ UINT8 RxVrefHigh;
+ UINT8 TxVrefLow; ///< Units = txVrefStep
+ UINT8 TxVrefHigh;
+ UINT8 CmdVrefLow; ///< Units = caVrefStep
+ UINT8 CmdVrefHigh;
+} BDAT_RANK_MARGIN_STRUCTURE;
+
+typedef struct {
+ UINT16 RecEnDelay[MAX_STROBE];
+ UINT16 WlDelay[MAX_STROBE];
+ UINT8 RxDqDelay[MAX_STROBE];
+ UINT8 TxDqDelay[MAX_STROBE];
+ UINT8 ClkDelay;
+ UINT8 CtlDelay;
+ UINT8 CmdDelay[3];
+ UINT8 IoLatency;
+ UINT8 Roundtrip;
+} BDAT_RANK_TRAINING_STRUCTURE;
+
+typedef struct {
+ UINT16 ModeRegister[MAX_MODE_REGISTER]; ///< Mode register settings
+} BDAT_DRAM_MRS_STRUCTURE;
+
+typedef struct {
+ UINT8 RankEnabled; ///< 0 = Rank disabled
+ UINT8 RankMarginEnabled; ///< 0 = Rank margin disabled
+ UINT8 DqMarginEnabled; ///< 0 = Dq margin disabled
+ BDAT_RANK_MARGIN_STRUCTURE RankMargin; ///< Rank margin data
+ BDAT_DQ_MARGIN_STRUCTURE DqMargin[MAX_DQ]; ///< Array of Dq margin data per rank
+ BDAT_RANK_TRAINING_STRUCTURE RankTraining; ///< Rank training settings
+ BDAT_DRAM_MRS_STRUCTURE RankMRS[MAX_DRAM_DEVICE]; ///< Rank MRS settings
+} BDAT_RANK_STRUCTURE;
+
+typedef struct {
+ UINT8 SpdValid[MAX_SPD_RMT / (CHAR_BITS * sizeof (UINT8))]; ///< Each valid bit maps to SPD byte
+ UINT8 SpdData[MAX_SPD_RMT]; ///< Array of raw SPD data bytes
+} BDAT_SPD_STRUCTURE;
+
+typedef struct {
+ UINT8 DimmEnabled; ///< 0 = DIMM disabled
+ BDAT_RANK_STRUCTURE RankList[MAX_RANK_IN_DIMM]; ///< Array of ranks per DIMM
+ BDAT_SPD_STRUCTURE SpdBytes; ///< SPD data per DIMM
+} BDAT_DIMM_STRUCTURE;
+
+typedef struct {
+ UINT8 ChannelEnabled; ///< 0 = Channel disabled
+ UINT8 NumDimmSlot; ///< Number of slots per channel on the board
+ BDAT_DIMM_STRUCTURE DimmList[MAX_DIMMS_IN_CHANNEL]; ///< Array of DIMMs per channel
+} BDAT_CHANNEL_STRUCTURE;
+
+typedef struct {
+ UINT8 ControllerEnabled; ///< 0 = MC disabled
+ UINT16 ControllerDeviceId; ///< MC device Id
+ UINT8 ControllerRevisionId; ///< MC revision Id
+ UINT16 MemoryFrequency; ///< Memory frequency in units of MHz / 10
+ ///< e.g. ddrFreq = 13333 for tCK = 1.5 ns
+ UINT16 MemoryVoltage; ///< Memory Vdd in units of mV
+ ///< e.g. ddrVoltage = 1350 for Vdd = 1.35 V
+ UINT8 PiStep; ///< Step unit = piStep * tCK / 2048
+ ///< e.g. piStep = 16 for step = 11.7 ps (1/128 tCK)
+ UINT16 RxVrefStep; ///< Step unit = rxVrefStep * Vdd / 100
+ ///< e.g. rxVrefStep = 520 for step = 7.02 mV
+ UINT16 TxVrefStep; ///< Step unit = txVrefStep * Vdd / 100
+ UINT16 CaVrefStep; ///< Step unit = caVrefStep * Vdd / 100
+ UINT8 RecvenStep; ///< Step unit = recvenStep * tCK / 2048
+ UINT8 WrLevelStep; ///< Step unit = wrLevelStep * tCK / 2048
+ BDAT_CHANNEL_STRUCTURE ChannelList[MAX_CHANNEL]; ///< Array of channels per memory controller
+} BDAT_SOCKET_STRUCTURE;
+
+typedef struct {
+ union {
+ UINT32 Data32; ///< MRC version: Major.Minor.Revision.Build
+ struct {
+ UINT8 Build; ///< MRC version: Build
+ UINT8 Revision; ///< MRC version: Revision
+ UINT8 Minor; ///< MRC version: Minor
+ UINT8 Major; ///< MRC version: Major
+ } Version;
+ } RefCodeRevision; ///< Major.Minor.Revision.Build
+ UINT8 MaxController; ///< Max controllers per system, e.g. 1
+ UINT8 MaxChannel; ///< Max channels per memory controller, e.g. 2
+ UINT8 MaxDimm; ///< Max DIMM per channel, e.g. 2
+ UINT8 MaxRankDimm; ///< Max ranks per DIMM, e.g. 2
+ UINT8 MaxStrobe; ///< Number of Dqs used by the rank, e.g. 18
+ UINT8 MaxDq; ///< Number of Dq bits used by the rank, e.g. 72
+ UINT32 MarginLoopCount; ///< Units of cache line
+ BDAT_SOCKET_STRUCTURE ControllerList[MAX_CONTROLLERS]; ///< Array of memory controllers per system
+} BDAT_SYSTEM_STRUCTURE;
+
+typedef struct {
+ UINT32 Data1;
+ UINT16 Data2;
+ UINT16 Data3;
+ UINT8 Data4[8];
+} BDAT_EFI_GUID;
+
+typedef struct {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} BDAT_HOB_GENERIC_HEADER;
+
+typedef struct {
+ BDAT_HOB_GENERIC_HEADER Header;
+ BDAT_EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} BDAT_HOB_GUID_TYPE;
+
+typedef struct {
+ BDAT_EFI_GUID SchemaId; ///< The GUID uniquely identifies the format of the data contained within the structure.
+ UINT32 DataSize; ///< The total size of the memory block, including both the header as well as the schema specific data.
+ UINT16 Crc16; ///< Crc16 is computed in the same manner as the field in the BDAT_HEADER_STRUCTURE.
+} MRC_BDAT_SCHEMA_HEADER_STRUCTURE;
+
+typedef struct {
+ MRC_BDAT_SCHEMA_HEADER_STRUCTURE SchemaHeader; ///< The schema header.
+ union {
+ UINT32 Data; ///< MRC version: Major.Minor.Revision.Build
+ struct {
+ UINT8 Build; ///< MRC version: Build
+ UINT8 Revision; ///< MRC version: Revision
+ UINT8 Minor; ///< MRC version: Minor
+ UINT8 Major; ///< MRC version: Major
+ } Version;
+ } RefCodeRevision; ///< Major.Minor.Revision.Build
+ UINT8 MaxController; ///< Max controllers per system, e.g. 1
+ UINT8 MaxChannel; ///< Max channels per memory controller, e.g. 2
+ UINT8 MaxDimm; ///< Max DIMM per channel, e.g. 2
+ UINT8 MaxRankDimm; ///< Max ranks per DIMM, e.g. 2
+ UINT8 MaxStrobe; ///< Number of Dqs used by the rank, e.g. 18
+ UINT8 MaxDq; ///< Number of Dq bits used by the rank, e.g. 72
+ UINT32 MarginLoopCount; ///< Units of cache line
+ BDAT_SOCKET_STRUCTURE ControllerList[MAX_CONTROLLERS]; ///< Array of memory controllers per system
+} BDAT_MEMORY_DATA_STRUCTURE;
+
+typedef struct {
+ BDAT_HOB_GUID_TYPE HobGuidType;
+ BDAT_MEMORY_DATA_STRUCTURE MemorySchema;
+} BDAT_MEMORY_DATA_HOB;
+
+#pragma pack (pop)
+
+typedef struct {
+ BDAT_HOB_GUID_TYPE HobGuidType;
+ UINT16 SchemaHobCount;
+ UINT16 Reserved;
+ BDAT_EFI_GUID SchemaHobGuids[MAX_SCHEMA_LIST_LENGTH];
+} MRC_BDAT_SCHEMA_LIST_HOB;
+
+#endif //_MrcRmtData_h_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcSpdData.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcSpdData.h new file mode 100644 index 0000000000..cbfeb1cd0a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcSpdData.h @@ -0,0 +1,1173 @@ +/** @file
+ SPD data format header file.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MrcSpdData_h_
+#define _MrcSpdData_h_
+#pragma pack (push, 1)
+
+#include "MrcTypes.h"
+
+#define MAX_XMP_PROFILES (2)
+#define SPD3_MANUF_SIZE (SPD3_MANUF_END - SPD3_MANUF_START + 1) ///< The size of the SPD manufacturing data.
+#define SPD4_MANUF_SIZE (SPD4_MANUF_END - SPD4_MANUF_START + 1) ///< The size of the SPD manufacturing data.
+#define SPDLP_MANUF_SIZE (SPDLP_MANUF_END - SPDLP_MANUF_START + 1) ///< The size of the SPD manufacturing data
+
+typedef union {
+ struct {
+ UINT8 BytesUsed : 4; ///< Bits 3:0
+ UINT8 BytesTotal : 3; ///< Bits 6:4
+ UINT8 CrcCoverage : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_DEVICE_DESCRIPTION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Minor : 4; ///< Bits 3:0
+ UINT8 Major : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_REVISION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Type : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_DRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ModuleType : 4; ///< Bits 3:0
+ UINT8 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_MODULE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Density : 4; ///< Bits 3:0
+ UINT8 BankAddress : 3; ///< Bits 6:4
+ UINT8 : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ColumnAddress : 3; ///< Bits 2:0
+ UINT8 RowAddress : 3; ///< Bits 5:3
+ UINT8 : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_SDRAM_ADDRESSING_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 OperationAt1_50 : 1; ///< Bits 0:0
+ UINT8 OperationAt1_35 : 1; ///< Bits 1:1
+ UINT8 OperationAt1_25 : 1; ///< Bits 2:2
+ UINT8 : 5; ///< Bits 7:3
+ } Bits;
+ UINT8 Data;
+} SPD_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SdramDeviceWidth : 3; ///< Bits 2:0
+ UINT8 RankCount : 3; ///< Bits 5:3
+ UINT8 : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_MODULE_ORGANIZATION_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 PrimaryBusWidth : 3; ///< Bits 2:0
+ UINT8 BusWidthExtension : 2; ///< Bits 4:3
+ UINT8 : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Divisor : 4; ///< Bits 3:0
+ UINT8 Dividend : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_FINE_TIMEBASE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Dividend : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Divisor : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT;
+
+typedef struct {
+ SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend
+ SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor
+} SPD_MEDIUM_TIMEBASE;
+
+typedef union {
+ struct {
+ UINT8 tCKmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TCK_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 CL4 : 1; ///< Bits 0:0
+ UINT16 CL5 : 1; ///< Bits 1:1
+ UINT16 CL6 : 1; ///< Bits 2:2
+ UINT16 CL7 : 1; ///< Bits 3:3
+ UINT16 CL8 : 1; ///< Bits 4:4
+ UINT16 CL9 : 1; ///< Bits 5:5
+ UINT16 CL10 : 1; ///< Bits 6:6
+ UINT16 CL11 : 1; ///< Bits 7:7
+ UINT16 CL12 : 1; ///< Bits 8:8
+ UINT16 CL13 : 1; ///< Bits 9:9
+ UINT16 CL14 : 1; ///< Bits 10:10
+ UINT16 CL15 : 1; ///< Bits 11:11
+ UINT16 CL16 : 1; ///< Bits 12:12
+ UINT16 CL17 : 1; ///< Bits 13:13
+ UINT16 CL18 : 1; ///< Bits 14:14
+ UINT16 : 1; ///< Bits 15:15
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tAAmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TAA_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWRmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TWR_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRCD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRRDmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRRD_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRP_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPab : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRP_AB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPabFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TRP_AB_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRPpb : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRP_PB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPpbFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TRP_PB_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tRFCab : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_TRFC_AB_MTB_STRUCT;
+
+typedef union {
+struct {
+ UINT16 tRFCpb : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_TRFC_PB_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRASminUpper : 4; ///< Bits 3:0
+ UINT8 tRCminUpper : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_TRAS_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRASmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRAS_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRCmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tRFCmin : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_TRFC_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tWTRmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TWTR_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tRTPmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TRTP_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tFAWminUpper : 4; ///< Bits 3:0
+ UINT8 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_TFAW_MIN_MTB_UPPER_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tFAWmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TFAW_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCWLmin : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_TCWL_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 NMode : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_SYSTEM_COMMAND_RATE_STRUCT;
+
+typedef union {
+ struct {
+ UINT16 tREFImin : 16; ///< Bits 15:0
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_TREFI_MIN_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 RZQ6 : 1; ///< Bits 0:0
+ UINT8 RZQ7 : 1; ///< Bits 1:1
+ UINT8 : 5; ///< Bits 6:2
+ UINT8 DllOff : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_SDRAM_OPTIONAL_FEATURES_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0
+ UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1
+ UINT8 AutoSelfRefresh : 1; ///< Bits 2:2
+ UINT8 OnDieThermalSensor : 1; ///< Bits 3:3
+ UINT8 : 3; ///< Bits 6:4
+ UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0
+ UINT8 ThermalSensorPresence : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_MODULE_THERMAL_SENSOR_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 NonStandardDeviceDescription : 7; ///< Bits 6:0
+ UINT8 SdramDeviceType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_SDRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_AUTO_SELF_REFRESH_PERF_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TCK_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tAAminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TAA_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TRCD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRPminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TRP_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRCminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TRC_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tMACencoding : 4; ///< Bits 3:0
+ UINT8 tMAWencoding : 2; ///< Bits 5:4
+ UINT8 Reserved : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_PTRR_SUPPORT_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tRRDminFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_TRRD_MIN_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_UNBUF_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_UNBUF_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 MappingRank1 : 1; ///< Bits 0:0
+ UINT8 : 7; ///< Bits 7:1
+ } Bits;
+ UINT8 Data;
+} SPD_UNBUF_ADDRESS_MAPPING;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_RDIMM_MODULE_NOMINAL_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_RDIMM_REFERENCE_RAW_CARD;
+
+typedef union {
+ struct {
+ UINT8 RegisterCount : 2; ///< Bits 1:0
+ UINT8 DramRowCount : 2; ///< Bits 3:2
+ UINT8 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_RDIMM_MODULE_ATTRIBUTES;
+
+typedef union {
+ struct {
+ UINT16 ContinuationCount : 7; ///< Bits 6:0
+ UINT16 ContinuationParity : 1; ///< Bits 7:7
+ UINT16 LastNonZeroByte : 8; ///< Bits 15:8
+ } Bits;
+ UINT16 Data;
+ UINT8 Data8[2];
+} SPD_MANUFACTURER_ID_CODE;
+
+typedef struct {
+ UINT8 Year; ///< Year represented in BCD (00h = 2000)
+ UINT8 Week; ///< Year represented in BCD (47h = week 47)
+} SPD_MANUFACTURING_DATE;
+
+typedef union {
+ UINT32 Data;
+ UINT16 SerialNumber16[2];
+ UINT8 SerialNumber8[4];
+} SPD_MANUFACTURER_SERIAL_NUMBER;
+
+typedef struct {
+ UINT8 Location; ///< Module Manufacturing Location
+} SPD_MANUFACTURING_LOCATION;
+
+typedef struct {
+ SPD_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code
+ SPD_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location
+ SPD_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
+ SPD_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number
+} SPD_UNIQUE_MODULE_ID;
+
+typedef union {
+ UINT16 Crc[1];
+ UINT8 Data8[2];
+} SPD_CYCLIC_REDUNDANCY_CODE;
+
+typedef union {
+ struct {
+ UINT8 ProfileEnable1 : 1; ///< Bits 0:0
+ UINT8 ProfileEnable2 : 1; ///< Bits 1:1
+ UINT8 ProfileConfig1 : 2; ///< Bits 3:2
+ UINT8 ProfileConfig2 : 2; ///< Bits 5:4
+ UINT8 : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_XMP_ORG_CONFIG;
+
+typedef struct {
+ UINT16 XmpId; ///< 176-177 XMP Identification String
+ SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 178 XMP Organization & Configuration
+ SPD_REVISION_STRUCT XmpRevision; ///< 179 XMP Revision
+ SPD_MEDIUM_TIMEBASE MediumTimeBase[MAX_XMP_PROFILES]; ///< 180-183 Medium Timebase (MTB)
+ SPD_FINE_TIMEBASE_STRUCT FineTimeBase; ///< 184 Fine Timebase (FTB) Dividend / Divisor
+} SPD_EXTREME_MEMORY_PROFILE_HEADER;
+
+typedef union {
+ struct {
+ UINT8 Decimal : 5;
+ UINT8 Integer : 2;
+ UINT8 : 1;
+ } Bits;
+ UINT8 Data;
+} SPD_VDD_VOLTAGE_LEVEL_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Decimal : 7;
+ UINT8 Integer : 1;
+ } Bits;
+ UINT8 Data;
+} SPD_VDD_VOLTAGE_LEVEL_STRUCT_2_0;
+
+typedef union {
+ struct {
+ UINT8 Fine : 2; ///< Bits 1:0
+ UINT8 Medium : 2; ///< Bits 3:2
+ UINT8 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD4_TIMEBASE_STRUCT;
+
+typedef union {
+ struct {
+ UINT32 CL7 : 1; ///< Bits 0:0
+ UINT32 CL8 : 1; ///< Bits 1:1
+ UINT32 CL9 : 1; ///< Bits 2:2
+ UINT32 CL10 : 1; ///< Bits 3:3
+ UINT32 CL11 : 1; ///< Bits 4:4
+ UINT32 CL12 : 1; ///< Bits 5:5
+ UINT32 CL13 : 1; ///< Bits 6:6
+ UINT32 CL14 : 1; ///< Bits 7:7
+ UINT32 CL15 : 1; ///< Bits 8:8
+ UINT32 CL16 : 1; ///< Bits 9:9
+ UINT32 CL17 : 1; ///< Bits 10:10
+ UINT32 CL18 : 1; ///< Bits 11:11
+ UINT32 CL19 : 1; ///< Bits 12:12
+ UINT32 CL20 : 1; ///< Bits 13:13
+ UINT32 CL21 : 1; ///< Bits 14:14
+ UINT32 CL22 : 1; ///< Bits 15:15
+ UINT32 CL23 : 1; ///< Bits 16:16
+ UINT32 CL24 : 1; ///< Bits 17:17
+ UINT32 : 14; ///< Bits 31:18
+ } Bits;
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef struct {
+ SPD_VDD_VOLTAGE_LEVEL_STRUCT Vdd; ///< 185, 220 XMP Module VDD Voltage Level
+ SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 186, 221 XMP SDRAM Minimum Cycle Time (tCKmin)
+ SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 187, 222 XMP Minimum CAS Latency Time (tAAmin)
+ SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 188-189, 223-224 XMP CAS Latencies Supported, Least Significant Byte
+ SPD_TCWL_MIN_MTB_STRUCT tCWLmin; ///< 190, 225 XMP Minimum CAS Write Latency Time (tCWLmin)
+ SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 191, 226 XMP Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 192, 227 XMP Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 193, 228 XMP Minimum Write Recovery Time (tWRmin)
+ SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 194, 229 XMP Upper Nibbles for tRAS and tRC
+ SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 195, 230 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 196, 231 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ SPD_TREFI_MIN_MTB_STRUCT tREFImin; ///< 197-198, 232-233 XMP Maximum tREFI Time (Average Periodic Refresh Interval), Least Significant Byte
+ SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 199-200, 234-235 XMP Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte
+ SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 201, 236 XMP Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+ SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 202, 237 XMP Minimum Row Active to Row Active Delay Time (tRRDmin)
+ SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 203, 238 XMP Upper Nibble for tFAW
+ SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 204, 239 XMP Minimum Four Activate Window Delay Time (tFAWmin)
+ SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 205, 240 XMP Minimum Internal Write to Read Command Delay Time (tWTRmin)
+ UINT8 Reserved1[207 - 206 + 1]; ///< 206-207, 241-242 XMP Reserved
+ SPD_SYSTEM_COMMAND_RATE_STRUCT SystemCmdRate; ///< 208, 243 XMP System ADD/CMD Rate (1N or 2N mode)
+ SPD_AUTO_SELF_REFRESH_PERF_STRUCT AsrPerf; ///< 209, 244 XMP SDRAM Auto Self Refresh Performance (Sub 1x Refresh and IDD6 impact)
+ UINT8 VoltageLevel; ///< 210, 245 XMP Memory Controller Voltage Level
+ SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 211, 246 XMP Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 212, 247 XMP Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 213, 248 XMP Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 214, 249 XMP Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 215, 250 XMP Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ UINT8 Reserved2[218 - 216 + 1]; ///< 216-218, 251-253 XMP Reserved
+ UINT8 VendorPersonality; ///< 219, 254 XMP Vendor Personality
+} SPD_EXTREME_MEMORY_PROFILE_DATA;
+
+typedef struct {
+ SPD_EXTREME_MEMORY_PROFILE_HEADER Header; ///< 176-184 XMP header
+ SPD_EXTREME_MEMORY_PROFILE_DATA Data[MAX_XMP_PROFILES]; ///< 185-254 XMP profiles
+} SPD_EXTREME_MEMORY_PROFILE;
+
+typedef struct {
+ UINT16 XmpId; ///< 384-385 XMP Identification String
+ SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 386 XMP Organization & Configuration
+ SPD_REVISION_STRUCT XmpRevision; ///< 387 XMP Revision
+ SPD4_TIMEBASE_STRUCT TimeBase[MAX_XMP_PROFILES]; ///< 388-389 Medium and Fine Timebase
+ UINT8 Reserved[392 - 390 + 1]; ///< 390-392 Reserved
+} SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0;
+
+typedef struct {
+ SPD_VDD_VOLTAGE_LEVEL_STRUCT_2_0 Vdd; ///< 393, 440 XMP Module VDD Voltage Level
+ UINT8 Reserved1[395 - 394 + 1]; ///< 394-395, 441-442 XMP Reserved
+ SPD_TCK_MIN_MTB_STRUCT tCKAVGmin; ///< 396, 443 XMP SDRAM Minimum Cycle Time (tCKAVGmin)
+ SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 397-400, 444-447 XMP CAS Latencies Supported
+ SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 401, 448 XMP Minimum CAS Latency Time (tAAmin)
+ SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 402, 449 XMP Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 403, 450 XMP Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 404, 451 XMP Upper Nibbles for tRAS and tRC
+ SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 405, 452 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 406, 453 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 407-408, 454-455 XMP Minimum Refresh Recovery Delay Time (tRFC1min)
+ SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 409-410, 456-457 XMP Minimum Refresh Recovery Delay Time (tRFC2min)
+ SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 411-412, 458-459 XMP Minimum Refresh Recovery Delay Time (tRFC4min)
+ SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 413, 460 Upper Nibble for tFAW
+ SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 414, 461 Minimum Four Activate Window Delay Time (tFAWmin)
+ SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 415, 462 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
+ SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 416, 463 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
+ UINT8 Reserved2[424 - 417 + 1]; ///< 417-424, 464-471 XMP Reserved
+ SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 425, 472 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
+ SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 426, 473 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
+ SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 427, 474 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 428, 475 Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 429, 476 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 430, 477 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD_TCK_MIN_FTB_STRUCT tCKAVGminFine; ///< 431, 478 Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmin)
+ UINT8 Reserved3[439 - 432 + 1]; ///< 432-439, 479-486 XMP Reserved
+} SPD_EXTREME_MEMORY_PROFILE_DATA_2_0;
+
+typedef struct {
+ SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 Header; ///< 384-392 XMP header
+ SPD_EXTREME_MEMORY_PROFILE_DATA_2_0 Data[MAX_XMP_PROFILES]; ///< 393-486 XMP profiles
+} SPD_EXTREME_MEMORY_PROFILE_2_0;
+
+typedef struct {
+ SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision
+ SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
+ SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
+ SPD_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
+ SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
+ SPD_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD
+ SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization
+ SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width
+ SPD_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor
+ SPD_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend
+ SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)
+ UINT8 Reserved1; ///< 13 Reserved
+ SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported
+ SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)
+ SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)
+ SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+ SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC
+ SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)
+ SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+ SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+ SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW
+ SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)
+ SPD_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features
+ SPD_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAMThermalAndRefreshOptions
+ SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor
+ SPD_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type
+ SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ SPD_TRP_AB_MTB_STRUCT tRPab; ///< 39 Minimum Row Precharge Delay Time for all banks (tRPab)
+ SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 40 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab)
+ SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 41 - pTRR support with TMAC value
+ UINT8 Reserved3[59 - 42 + 1]; ///< 42 - 59 Reserved
+} SPD_GENERAL_SECTION;
+
+typedef struct {
+ SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
+ SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
+ SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
+ SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM
+ UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved
+} SPD_MODULE_UNBUFFERED;
+
+typedef struct {
+ SPD_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height
+ SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness
+ SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used
+ SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes
+ UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved
+} SPD_MODULE_REGISTERED;
+
+typedef union {
+ SPD_MODULE_UNBUFFERED Unbuffered;
+ SPD_MODULE_REGISTERED Registered;
+} SPD_MODULE_SPECIFIC;
+
+typedef struct {
+ UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number
+} SPD_MODULE_PART_NUMBER;
+
+typedef struct {
+ UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code
+} SPD_MODULE_REVISION_CODE;
+
+typedef struct {
+ UINT8 ManufactureSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data
+} SPD_MANUFACTURE_SPECIFIC;
+
+///
+/// DDR3 Serial Presence Detect structure
+///
+typedef struct {
+ SPD_GENERAL_SECTION General; ///< 0-59 General Section
+ SPD_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section
+ SPD_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
+ SPD_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number
+ SPD_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code
+ SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code
+ SPD_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 150-175 Manufacturer's Specific Data
+ SPD_EXTREME_MEMORY_PROFILE Xmp; ///< 176-254 Intel(r) Extreme Memory Profile support
+ UINT8 Reserved; ///< 255 Reserved
+} MrcSpdDdr3;
+
+typedef union {
+ struct {
+ UINT8 Density : 4; ///< Bits 3:0
+ UINT8 BankAddress : 2; ///< Bits 5:4
+ UINT8 BankGroup : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SignalLoading : 2; ///< Bits 1:0
+ UINT8 : 2; ///< Bits 3:2
+ UINT8 DieCount : 3; ///< Bits 6:4
+ UINT8 SdramDeviceType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_DEVICE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1
+ UINT8 : 6; ///< Bits 7:2
+ } Bits;
+ UINT8 Data;
+} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCKmax : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_TCK_MAX_MTB_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKmaxFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD4_TCK_MAX_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD4_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef struct {
+ SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision
+ SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
+ SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
+ SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
+ SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
+ SPD4_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 6 SDRAM Device Type
+ SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 7 pTRR support with TMAC value
+ SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options
+ UINT8 Reserved0[10 - 9 + 1]; ///< 9-10 Reserved
+ SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD
+ SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization
+ SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width
+ SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor
+ UINT8 Reserved1[16 - 15 + 1]; ///< 15-16 Reserved
+ SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases
+ SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
+ SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
+ SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported
+ SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)
+ SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC
+ SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
+ SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
+ SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)
+ SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)
+ SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)
+ SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW
+ SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)
+ SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
+ SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
+ UINT8 Reserved2[117 - 40 + 1]; ///< 40-117 Reserved
+ SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
+ SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
+ SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
+ SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Minimum Row Precharge Delay Time (tRPmin)
+ SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
+ SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
+} SPD4_BASE_SECTION;
+
+typedef struct {
+ SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM
+ UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_UNBUFFERED;
+
+typedef struct {
+ SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes
+ UINT8 Reserved[253 - 132 + 1]; ///< 253-132 Reserved
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD4_MODULE_REGISTERED;
+
+typedef union {
+ SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types
+ SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types
+} SPD4_MODULE_SPECIFIC;
+
+typedef struct {
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
+} SPD4_MODULE_PART_NUMBER;
+
+typedef struct {
+ UINT8 ManufactureSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
+} SPD4_MANUFACTURE_SPECIFIC;
+
+typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code
+typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping
+
+typedef struct {
+ SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID
+ SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number
+ SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code
+ SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code
+ SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping
+ SPD4_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-381 Manufacturer's Specific Data
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 382-383 Cyclical Redundancy Code (CRC)
+} SPD4_MANUFACTURING_DATA;
+
+typedef union {
+ SPD_EXTREME_MEMORY_PROFILE_2_0 Xmp; ///< 384-463 Intel(r) Extreme Memory Profile support
+ UINT8 Reserved0[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types
+} SPD4_END_USER_SECTION;
+
+///
+/// DDR4 Serial Presence Detect structure
+///
+typedef struct {
+ SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters
+ SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section
+ UINT8 Reserved0[319 - 256 + 1]; ///< 256-319 Reserved
+ SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information
+ SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable
+} MrcSpdDdr4;
+
+typedef union {
+ struct {
+ UINT8 Fine : 2; ///< Bits 1:0
+ UINT8 Medium : 2; ///< Bits 3:2
+ UINT8 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TIMEBASE_STRUCT;
+
+typedef union {
+ struct {
+ UINT32 CL3 : 1; ///< Bits 0:0
+ UINT32 CL6 : 1; ///< Bits 1:1
+ UINT32 CL8 : 1; ///< Bits 2:2
+ UINT32 CL9 : 1; ///< Bits 3:3
+ UINT32 CL10 : 1; ///< Bits 4:4
+ UINT32 CL11 : 1; ///< Bits 5:5
+ UINT32 CL12 : 1; ///< Bits 6:6
+ UINT32 CL14 : 1; ///< Bits 7:7
+ UINT32 CL16 : 1; ///< Bits 8:8
+ UINT32 : 1; ///< Bits 9:9
+ UINT32 CL20 : 1; ///< Bits 10:10
+ UINT32 CL22 : 1; ///< Bits 11:11
+ UINT32 CL24 : 1; ///< Bits 12:12
+ UINT32 : 1; ///< Bits 13:13
+ UINT32 CL28 : 1; ///< Bits 14:14
+ UINT32 : 1; ///< Bits 15:15
+ UINT32 CL32 : 1; ///< Bits 16:16
+ UINT32 : 1; ///< Bits 17:17
+ UINT32 CL36 : 1; ///< Bits 18:18
+ UINT32 : 1; ///< Bits 19:19
+ UINT32 CL40 : 1; ///< Bits 20:20
+ UINT32 : 11; ///< Bits 31:21
+ } Bits;
+ UINT32 Data;
+ UINT16 Data16[2];
+ UINT8 Data8[4];
+} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Density : 4; ///< Bits 3:0
+ UINT8 BankAddress : 2; ///< Bits 5:4
+ UINT8 BankGroup : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 SignalLoading : 2; ///< Bits 1:0
+ UINT8 ChannelsPerDie : 2; ///< Bits 3:2
+ UINT8 DieCount : 3; ///< Bits 6:4
+ UINT8 SdramPackageType : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 OperationAt1_20 : 1; ///< Bits 0:0
+ UINT8 EndurantAt1_20 : 1; ///< Bits 1:1
+ UINT8 OperationAt1_10 : 1; ///< Bits 2:2
+ UINT8 EndurantAt1_10 : 1; ///< Bits 3:3
+ UINT8 OperationAtTBD2V : 1; ///< Bits 4:4
+ UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5
+ UINT8 : 2; ///< Bits 7:6
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 tCKmax : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_TCK_MAX_MTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 ReadLatencyMode : 2; ///< Bits 1:0
+ UINT8 WriteLatencySet : 2; ///< Bits 3:2
+ UINT8 : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;
+
+typedef union {
+ struct {
+ INT8 tCKmaxFine : 8; ///< Bits 7:0
+ } Bits;
+ INT8 Data;
+} SPD_LPDDR_TCK_MAX_FTB_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 : 8; ///< Bits 7:0
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_UNBUF_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_RDIMM_MODULE_NOMINAL_HEIGHT;
+
+typedef struct {
+ SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
+ SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision
+ SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type
+ SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type
+ SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks
+ SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing
+ SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type
+ SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 7 pTRR support with TMAC value - SDRAM Optional Features
+ SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options
+ UINT8 Reserved0[10 - 9 + 1]; ///< 9-10 Reserved
+ SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD
+ SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization
+ SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width
+ SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor
+ UINT8 Reserved1[16 - 15 + 1]; ///< 15-16 Reserved
+ SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases
+ SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
+ SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
+ SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported
+ SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)
+ SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options
+ SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks
+ SPD_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank
+ SPD_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
+ SPD_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
+ UINT8 Reserved2[119 - 33 + 1]; ///< 33-119 Reserved
+ SPD_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
+ SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
+ SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+ SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
+ SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
+ SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)
+} SPD_LPDDR_BASE_SECTION;
+
+typedef union {
+ struct {
+ UINT8 FrontThickness : 4; ///< Bits 3:0
+ UINT8 BackThickness : 4; ///< Bits 7:4
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;
+
+typedef union {
+ struct {
+ UINT8 Height : 5; ///< Bits 4:0
+ UINT8 RawCardExtension : 3; ///< Bits 7:5
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;
+
+typedef union {
+ struct {
+ UINT8 Card : 5; ///< Bits 4:0
+ UINT8 Revision : 2; ///< Bits 6:5
+ UINT8 Extension : 1; ///< Bits 7:7
+ } Bits;
+ UINT8 Data;
+} SPD_LPDDR_REFERENCE_RAW_CARD;
+
+typedef struct {
+ SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height
+ SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness
+ SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used
+ UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved
+ SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)
+} SPD_LPDDR_MODULE_LPDIMM;
+
+typedef union {
+ SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types
+} SPD_LPDDR_MODULE_SPECIFIC;
+
+typedef struct {
+ UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
+} SPD_LPDDR_MODULE_PART_NUMBER;
+
+typedef struct {
+ UINT8 ManufactureSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
+} SPD_LPDDR_MANUFACTURE_SPECIFIC;
+
+typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code
+typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping
+
+typedef struct {
+ SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID
+ SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number
+ SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code
+ SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code
+ SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping
+ SPD_LPDDR_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-381 Manufacturer's Specific Data
+ UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved
+} SPD_LPDDR_MANUFACTURING_DATA;
+
+typedef union {
+ UINT8 Reserved0[511 - 384 + 1]; ///< 384-511 End User Programmable
+} SPD_LPDDR_END_USER_SECTION;
+
+typedef struct {
+ SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters
+ SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section
+ UINT8 Reserved0[319 - 256 + 1]; ///< 256-319 Reserved
+ SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information
+ SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable
+} MrcSpdLpDdr;
+
+typedef union {
+ MrcSpdDdr3 Ddr3;
+ MrcSpdDdr4 Ddr4;
+ MrcSpdLpDdr Lpddr;
+} MrcSpd;
+
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE (sizeof (SPD_MANUFACTURER_ID_CODE) + \
+ sizeof (SPD_MANUFACTURING_LOCATION) + \
+ sizeof (SPD_MANUFACTURING_DATE) + \
+ sizeof (SPD_MANUFACTURER_SERIAL_NUMBER) + \
+ sizeof (SPD4_MODULE_PART_NUMBER))
+#endif
+
+#pragma pack (pop)
+#endif // _MrcSpdData_h_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcTypes.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcTypes.h new file mode 100644 index 0000000000..5bb771089d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcTypes.h @@ -0,0 +1,237 @@ +/** @file
+
+ Include the the general MRC types
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _MRC_TYPES_H
+#define _MRC_TYPES_H
+
+#ifdef MRC_MINIBIOS_BUILD
+#include "MrcMiniBiosEfiDefs.h"
+#else
+#include <Base.h>
+#endif // MRC_MINIBIOS_BUILD
+
+//
+// Data Types
+//
+typedef union {
+ struct {
+ UINT32 Low;
+ UINT32 High;
+ } Data32;
+ UINT64 Data;
+} UINT64_STRUCT;
+
+typedef union {
+ struct {
+ INT32 Low;
+ INT32 High;
+ } Data32;
+ INT64 Data;
+} INT64_STRUCT;
+
+#define UNSUPPORT 0
+#define SUPPORT 1
+
+typedef enum {
+ mrcSuccess,
+ mrcFail,
+ mrcWrongInputParameter,
+ mrcCasError,
+ mrcTimingError,
+ mrcSenseAmpErr,
+ mrcReadMPRErr,
+ mrcReadLevelingError,
+ mrcWriteLevelingError,
+ mrcDataTimeCentering1DErr,
+ mrcWriteVoltage2DError,
+ mrcReadVoltage2DError,
+ mrcMiscTrainingError,
+ mrcWrError,
+ mrcDimmNotSupport,
+ mrcChannelNotSupport,
+ mrcPiSettingError,
+ mrcDqsPiSettingError,
+ mrcDeviceBusy,
+ mrcFrequencyChange,
+ mrcReutSequenceError,
+ mrcCrcError,
+ mrcFrequencyError,
+ mrcDimmNotExist,
+ mrcColdBootRequired,
+ mrcRoundTripLatencyError,
+ mrcMixedDimmSystem,
+ mrcAliasDetected,
+ mrcRetrain,
+ mrcRtpError,
+ mrcUnsupportedTechnology,
+ mrcMappingError,
+ mrcSocketNotSupported,
+ mrcControllerNotSupported,
+ mrcRankNotSupported,
+ mrcTurnAroundTripError
+} MrcStatus;
+
+//
+// general macros
+//
+#ifndef MIN
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#ifndef MAX
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+
+#ifndef ABS
+#define ABS(x) (((x) < 0) ? (-(x)) : (x))
+#endif
+
+//
+// Make sure x is inside the range of [a..b]
+//
+#ifndef RANGE
+#define RANGE(x, a, b) (MIN ((b), MAX ((x), (a))))
+#endif
+
+#ifndef DIVIDECEIL
+#define DIVIDECEIL(a, b) (((a) + (b) - 1) / (b))
+#endif
+
+#ifndef DIVIDEROUND
+#define DIVIDEROUND(a, b) (((a) * (b) > 0) ? ((a) + (b) / 2) / (b) : ((a) - (b) / 2) / (b))
+#endif
+
+#ifndef DIVIDEFLOOR
+#define DIVIDEFLOOR(a, b) ((a) / (b))
+#endif
+
+//
+// Number of elements in a 1D array
+//
+#ifndef ARRAY_COUNT
+#define ARRAY_COUNT(a) (sizeof (a) / sizeof (a[0]))
+#endif
+
+//
+// use for ignore parames
+//
+// #define MRC_IGNORE_PARAM(x) ((x) = (x))
+//
+#if _MSC_EXTENSIONS
+//
+// Disable warning that make it impossible to compile at /W4
+// This only works for Microsoft* tools
+//
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning (disable : 4214)
+//
+// Unreferenced formal parameter - We are object oriented, so we pass parameters even
+// if we don't need them.
+//
+#pragma warning (disable : 4100)
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so supress this warning
+//
+#pragma warning(disable : 4127)
+//
+// The given function was selected for inline expansion, but the compiler did not perform the inlining.
+//
+#pragma warning(disable : 4710)
+
+#endif // _MSC_EXTENSIONS
+#define MRC_BIT0 0x00000001
+#define MRC_BIT1 0x00000002
+#define MRC_BIT2 0x00000004
+#define MRC_BIT3 0x00000008
+#define MRC_BIT4 0x00000010
+#define MRC_BIT5 0x00000020
+#define MRC_BIT6 0x00000040
+#define MRC_BIT7 0x00000080
+#define MRC_BIT8 0x00000100
+#define MRC_BIT9 0x00000200
+#define MRC_BIT10 0x00000400
+#define MRC_BIT11 0x00000800
+#define MRC_BIT12 0x00001000
+#define MRC_BIT13 0x00002000
+#define MRC_BIT14 0x00004000
+#define MRC_BIT15 0x00008000
+#define MRC_BIT16 0x00010000
+#define MRC_BIT17 0x00020000
+#define MRC_BIT18 0x00040000
+#define MRC_BIT19 0x00080000
+#define MRC_BIT20 0x00100000
+#define MRC_BIT21 0x00200000
+#define MRC_BIT22 0x00400000
+#define MRC_BIT23 0x00800000
+#define MRC_BIT24 0x01000000
+#define MRC_BIT25 0x02000000
+#define MRC_BIT26 0x04000000
+#define MRC_BIT27 0x08000000
+#define MRC_BIT28 0x10000000
+#define MRC_BIT29 0x20000000
+#define MRC_BIT30 0x40000000
+#define MRC_BIT31 0x80000000
+#define MRC_BIT32 0x100000000ULL
+#define MRC_BIT33 0x200000000ULL
+#define MRC_BIT34 0x400000000ULL
+#define MRC_BIT35 0x800000000ULL
+#define MRC_BIT36 0x1000000000ULL
+#define MRC_BIT37 0x2000000000ULL
+#define MRC_BIT38 0x4000000000ULL
+#define MRC_BIT39 0x8000000000ULL
+#define MRC_BIT40 0x10000000000ULL
+#define MRC_BIT41 0x20000000000ULL
+#define MRC_BIT42 0x40000000000ULL
+#define MRC_BIT43 0x80000000000ULL
+#define MRC_BIT44 0x100000000000ULL
+#define MRC_BIT45 0x200000000000ULL
+#define MRC_BIT46 0x400000000000ULL
+#define MRC_BIT47 0x800000000000ULL
+#define MRC_BIT48 0x1000000000000ULL
+#define MRC_BIT49 0x2000000000000ULL
+#define MRC_BIT50 0x4000000000000ULL
+#define MRC_BIT51 0x8000000000000ULL
+#define MRC_BIT52 0x10000000000000ULL
+#define MRC_BIT53 0x20000000000000ULL
+#define MRC_BIT54 0x40000000000000ULL
+#define MRC_BIT55 0x80000000000000ULL
+#define MRC_BIT56 0x100000000000000ULL
+#define MRC_BIT57 0x200000000000000ULL
+#define MRC_BIT58 0x400000000000000ULL
+#define MRC_BIT59 0x800000000000000ULL
+#define MRC_BIT60 0x1000000000000000ULL
+#define MRC_BIT61 0x2000000000000000ULL
+#define MRC_BIT62 0x4000000000000000ULL
+#define MRC_BIT63 0x8000000000000000ULL
+
+#define MRC_DEADLOOP() { volatile int __iii; __iii = 1; while (__iii); }
+
+#ifndef ASM
+#define ASM __asm
+#endif
+
+///
+/// Type Max/Min Values
+///
+#define MRC_INT32_MAX (0x7FFFFFFF)
+#define MRC_INT32_MIN (0x80000000)
+#define MRC_INT64_MAX (0x7FFFFFFFFFFFFFFFLL)
+#define MRC_INT64_MIN (0x8000000000000000LL)
+#define MRC_UINT32_MAX (0xFFFFFFFF)
+#define MRC_UINT64_MAX (0xFFFFFFFFFFFFFFFFULL)
+#define MRC_UINT_MIN (0x0)
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.c new file mode 100644 index 0000000000..1d438e3c85 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.c @@ -0,0 +1,73 @@ +/** @file
+ DXE driver for Initializing SystemAgent Graphics ACPI table initialization.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "GraphicsInit.h"
+
+extern SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL mSaGlobalNvsAreaProtocol;
+
+
+/**
+Initialize GT ACPI tables
+
+ @param[in] ImageHandle - Handle for the image of this driver
+ @param[in] SaPolicy - SA DXE Policy protocol
+
+ @retval EFI_SUCCESS - GT ACPI initialization complete
+ @retval EFI_NOT_FOUND - Dxe System Table not found.
+ @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully.
+**/
+EFI_STATUS
+GraphicsInit (
+ IN EFI_HANDLE ImageHandle,
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Update IGD SA Global NVS
+ ///
+ DEBUG ((DEBUG_INFO, " Update Igd SA Global NVS Area.\n"));
+
+ mSaGlobalNvsAreaProtocol.Area->AlsEnable = GraphicsDxeConfig->AlsEnable;
+ ///
+ /// Initialize IGD state by checking if IGD Device 2 Function 0 is enabled in the chipset
+ ///
+ if (MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_DEVEN) & B_SA_DEVEN_D2EN_MASK) {
+ mSaGlobalNvsAreaProtocol.Area->IgdState = 1;
+ } else {
+ mSaGlobalNvsAreaProtocol.Area->IgdState = 0;
+ }
+
+ mSaGlobalNvsAreaProtocol.Area->BrightnessPercentage = 100;
+ mSaGlobalNvsAreaProtocol.Area->IgdBootType = GraphicsDxeConfig->IgdBootType;
+ mSaGlobalNvsAreaProtocol.Area->IgdPanelType = GraphicsDxeConfig->IgdPanelType;
+ mSaGlobalNvsAreaProtocol.Area->IgdPanelScaling = GraphicsDxeConfig->IgdPanelScaling;
+ ///
+ /// Get SFF power mode platform data for the IGD driver. Flip the bit (bitwise xor)
+ /// since Setup value is opposite of NVS and IGD OpRegion value.
+ ///
+ mSaGlobalNvsAreaProtocol.Area->IgdDvmtMemSize = GraphicsDxeConfig->IgdDvmtMemSize;
+ mSaGlobalNvsAreaProtocol.Area->IgdFunc1Enable = 0;
+ mSaGlobalNvsAreaProtocol.Area->IgdSciSmiMode = 0;
+ mSaGlobalNvsAreaProtocol.Area->GfxTurboIMON = GraphicsDxeConfig->GfxTurboIMON;
+
+ mSaGlobalNvsAreaProtocol.Area->EdpValid = 0;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.h new file mode 100644 index 0000000000..b76f775b24 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.h @@ -0,0 +1,46 @@ +/** @file
+ Header file for initialization of GT PowerManagement
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _GRAPHICS_INIT_H_
+#define _GRAPHICS_INIT_H_
+
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/DxeServices.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Library/MmPciLib.h>
+#include <SaAccess.h>
+#include <Protocol/SaPolicy.h>
+#include "SaInitDxe.h"
+#include "SaInit.h"
+#include <PchAccess.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+
+
+/**
+ Initialize GT ACPI tables
+
+ @param[in] ImageHandle - Handle for the image of this driver
+ @param[in] SaPolicy - SA DXE Policy protocol
+
+ @retval EFI_SUCCESS - GT ACPI initialization complete
+ @retval EFI_NOT_FOUND - Dxe System Table not found.
+ @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully.
+**/
+EFI_STATUS
+GraphicsInit (
+ IN EFI_HANDLE ImageHandle,
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion.c new file mode 100644 index 0000000000..8e7ef7bc29 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion.c @@ -0,0 +1,525 @@ +/** @file
+ This is part of the implementation of an Intel Graphics drivers OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+ The code in this file will load the driver and initialize the interface
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ - OpRegion / Software SCI SPEC
+**/
+///
+/// Include files
+///
+#include "IgdOpRegion.h"
+#include "CpuRegs.h"
+#include "Library/CpuPlatformLib.h"
+#include <Library/HobLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <SiConfigHob.h>
+
+///
+/// Global variables
+///
+GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion;
+GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
+
+///
+/// Function implementations.
+///
+/**
+ Get VBT data using SaPlaformPolicy
+
+ @param[in] VbtFileBuffer Pointer to VBT data buffer.
+
+ @retval EFI_SUCCESS VBT data was returned.
+ @retval EFI_NOT_FOUND VBT data not found.
+ @exception EFI_UNSUPPORTED Invalid signature in VBT data.
+**/
+EFI_STATUS
+GetIntegratedIntelVbtPtr (
+ OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS VbtAddress;
+ UINT32 Size;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ ///
+ /// Get the SA policy.
+ ///
+ Status = gBS->LocateProtocol (
+ &gSaPolicyProtocolGuid,
+ NULL,
+ (VOID **) &mSaPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = GetConfigBlock ((VOID *) mSaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ VbtAddress = GraphicsDxeConfig->VbtAddress;
+ Size = GraphicsDxeConfig->Size;
+
+ if (VbtAddress == 0x00000000) {
+ return EFI_NOT_FOUND;
+ } else {
+ ///
+ /// Check VBT signature
+ ///
+ *VbtFileBuffer = NULL;
+ *VbtFileBuffer = (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;
+ if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) != VBT_SIGNATURE) {
+ FreePool (*VbtFileBuffer);
+ *VbtFileBuffer = NULL;
+ return EFI_UNSUPPORTED;
+ }
+ }
+ if (Size == 0) {
+ return EFI_NOT_FOUND;
+ } else {
+ ///
+ /// Check VBT size
+ ///
+ if ((*VbtFileBuffer)->HeaderVbtSize > Size) {
+ (*VbtFileBuffer)->HeaderVbtSize = (UINT16) Size;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Get a pointer to an uncompressed image of the Intel video BIOS.
+
+ Note: This function would only be called if the video BIOS at 0xC000 is
+ missing or not an Intel video BIOS. It may not be an Intel video BIOS
+ if the Intel graphic contoller is considered a secondary adapter.
+
+ @param[in] VBiosImage - Pointer to an uncompressed Intel video BIOS. This pointer must
+ be set to NULL if an uncompressed image of the Intel Video BIOS
+ is not obtainable.
+
+ @retval EFI_SUCCESS - VBiosPtr is updated.
+ @exception EFI_UNSUPPORTED - No Intel video BIOS found.
+**/
+EFI_STATUS
+GetIntegratedIntelVBiosPtr (
+ OUT INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage
+ )
+{
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+ INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage;
+ ///
+ /// Set as if an umcompressed Intel video BIOS image was not obtainable.
+ ///
+ VBiosRomImage = NULL;
+
+ ///
+ /// Get all PCI IO protocols
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Find the video BIOS by checking each PCI IO handle for an Intel video
+ /// BIOS OPROM.
+ ///
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ VBiosRomImage = PciIo->RomImage;
+
+ ///
+ /// If this PCI device doesn't have a ROM image, skip to the next device.
+ ///
+ if (!VBiosRomImage) {
+ continue;
+ }
+ ///
+ /// Get pointer to PCIR structure
+ ///
+ PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosRomImage + VBiosRomImage->PcirOffset);
+
+ ///
+ /// Check if we have an Intel video BIOS OPROM.
+ ///
+ if ((VBiosRomImage->Signature == OPTION_ROM_SIGNATURE) &&
+ (PcirBlockPtr->VendorId == V_SA_MC_VID) &&
+ (PcirBlockPtr->ClassCode[0] == 0x00) &&
+ (PcirBlockPtr->ClassCode[1] == 0x00) &&
+ (PcirBlockPtr->ClassCode[2] == 0x03)
+ ) {
+ ///
+ /// Found Intel video BIOS.
+ ///
+ *VBiosImage = VBiosRomImage;
+ return EFI_SUCCESS;
+ }
+ }
+ ///
+ /// No Intel video BIOS found.
+ ///
+ ///
+ /// Free any allocated buffers
+ ///
+ FreePool (HandleBuffer);
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
+ The VBT (Video BIOS Table) is a block of customizable data that is built
+ within the video BIOS and edited by customers.
+
+ @retval EFI_SUCCESS - Video BIOS VBT information returned.
+ @exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosVbtPtr = NULL).
+**/
+EFI_STATUS
+GetVBiosVbtEndOfDxe (
+ VOID
+ )
+{
+ INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr;
+ UINT32 PcirBlockAddress;
+ UINT16 PciVenderId;
+ INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr;
+ VBIOS_VBT_STRUCTURE *VBiosVbtPtr;
+ EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;
+ EFI_STATUS Status;
+ VBIOS_VBT_STRUCTURE *VbtFileBuffer;
+ UINTN Index;
+ UINT8 LegacyVbtFound;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+ EFI_PEI_HOB_POINTERS HobPtr;
+ SI_CONFIG_HOB *SiConfigHob;
+
+ VbtFileBuffer = NULL;
+ LegacyVbtFound = 1;
+
+ ///
+ /// Get the SA policy.
+ ///
+ Status = gBS->LocateProtocol (
+ &gSaPolicyProtocolGuid,
+ NULL,
+ (VOID **) &mSaPolicy
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = GetConfigBlock ((VOID *) mSaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ LegacyBios = NULL;
+ VBiosPtr = NULL;
+ //
+ // Get Silicon Config data HOB
+ //
+ HobPtr.Guid = GetFirstGuidHob (&gSiConfigHobGuid);
+ SiConfigHob = (SI_CONFIG_HOB *)GET_GUID_HOB_DATA (HobPtr.Guid);
+ if (SiConfigHob->CsmFlag == 1) {
+ Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);
+
+ if (LegacyBios) {
+ VBiosPtr = (INTEL_VBIOS_OPTION_ROM_HEADER *) (UINTN) (VBIOS_LOCATION_PRIMARY);
+ PcirBlockAddress = VBIOS_LOCATION_PRIMARY + VBiosPtr->PcirOffset;
+ PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *) (UINTN) (PcirBlockAddress);
+ PciVenderId = PcirBlockPtr->VendorId;
+ ///
+ /// If the video BIOS is not at 0xC0000 or it is not an Intel video BIOS get
+ /// the integrated Intel video BIOS (must be uncompressed).
+ ///
+ if ((VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId != V_SA_MC_VID)) {
+ GetIntegratedIntelVBiosPtr (&VBiosPtr);
+ if (VBiosPtr != NULL) {
+ ///
+ /// Video BIOS found.
+ ///
+ PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->PcirOffset);
+ PciVenderId = PcirBlockPtr->VendorId;
+
+ if ((VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId != V_SA_MC_VID)) {
+ ///
+ /// Intel video BIOS not found.
+ ///
+ VBiosVbtPtr = NULL;
+ LegacyVbtFound = 0;
+ }
+ }
+ }
+ }
+ }
+ if ((LegacyBios == NULL) || (LegacyVbtFound == 0)) {
+ ///
+ /// No Video BIOS found, try to get VBT from FV.
+ ///
+ GetIntegratedIntelVbtPtr (&VbtFileBuffer);
+ if (VbtFileBuffer != NULL) {
+ ///
+ /// Video BIOS not found, use VBT from SaPolicy
+ ///
+ DEBUG ((DEBUG_INFO, "VBT data found\n"));
+ for (Index = 0; (GraphicsDxeConfig->GopVersion[Index] != '\0'); Index++) {
+ }
+ Index = (Index+1)*2;
+ CopyMem (mIgdOpRegion.OpRegion->Header.DVER, GraphicsDxeConfig->GopVersion, Index);
+ CopyMem (mIgdOpRegion.OpRegion->VBT.GVD1, VbtFileBuffer, VbtFileBuffer->HeaderVbtSize);
+ return EFI_SUCCESS;
+ }
+ }
+
+ if (VBiosPtr == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ DEBUG ((DEBUG_INFO, "VBIOS found at 0x%X\n", VBiosPtr));
+ VBiosVbtPtr = (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->VbtOffset);
+
+ if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) != VBT_SIGNATURE) {
+ return EFI_UNSUPPORTED;
+ }
+
+ ///
+ /// Initialize Video BIOS version with its build number.
+ ///
+ mIgdOpRegion.OpRegion->Header.VVER[0] = VBiosVbtPtr->CoreBlockBiosBuild[0];
+ mIgdOpRegion.OpRegion->Header.VVER[1] = VBiosVbtPtr->CoreBlockBiosBuild[1];
+ mIgdOpRegion.OpRegion->Header.VVER[2] = VBiosVbtPtr->CoreBlockBiosBuild[2];
+ mIgdOpRegion.OpRegion->Header.VVER[3] = VBiosVbtPtr->CoreBlockBiosBuild[3];
+ CopyMem (mIgdOpRegion.OpRegion->VBT.GVD1, VBiosVbtPtr, VBiosVbtPtr->HeaderVbtSize);
+
+ ///
+ /// Return final status
+ ///
+ return EFI_SUCCESS;
+}
+
+/**
+ Graphics OpRegion / Software SCI driver installation function.
+
+ @param[in] void - None
+ @retval EFI_SUCCESS - The driver installed without error.
+ @retval EFI_ABORTED - The driver encountered an error and could not complete
+ installation of the ACPI tables.
+**/
+EFI_STATUS
+IgdOpRegionInit (
+ VOID
+ )
+{
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+ UINT32 DwordData;
+ UINTN IgdBaseAddress;
+ UINT32 Data32;
+ UINT16 PchAcpiBaseAddress;
+ UINT16 PchTcoBaseAddress;
+ SA_POLICY_PROTOCOL *SaPolicy;
+ CPU_SKU CpuSku;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+ SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL *SaGlobalNvsArea;
+
+ CpuSku = GetCpuSku ();
+
+ ///
+ /// Get the SA policy.
+ ///
+ Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **)&SaPolicy);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+ ///
+ /// Locate the SA Global NVS Protocol.
+ ///
+ Status = gBS->LocateProtocol (
+ &gSaGlobalNvsAreaProtocolGuid,
+ NULL,
+ (VOID **) &SaGlobalNvsArea
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Allocate an ACPI NVS memory buffer as the IGD OpRegion, zero initialize
+ /// the first 1K, and set the IGD OpRegion pointer in the Global NVS
+ /// area structure.
+ ///
+ Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (IGD_OPREGION_STRUC), (VOID **) &mIgdOpRegion.OpRegion);
+ ASSERT_EFI_ERROR (Status);
+
+ SetMem (mIgdOpRegion.OpRegion, 0x2000, 0);
+ SaGlobalNvsArea->Area->IgdOpRegionAddress = (UINT32) (UINTN) (mIgdOpRegion.OpRegion);
+
+ ///
+ /// If IGD is disabled return
+ ///
+ IgdBaseAddress = MmPciBase (SA_IGD_BUS, SA_IGD_DEV, SA_IGD_FUN_0);
+ if (MmioRead32 (IgdBaseAddress + 0) == 0xFFFFFFFF) {
+ return EFI_SUCCESS;
+ }
+ ///
+ /// Initialize OpRegion Header
+ ///
+ CopyMem (mIgdOpRegion.OpRegion->Header.SIGN, HEADER_SIGNATURE, sizeof (HEADER_SIGNATURE));
+ ///
+ /// Set OpRegion Size in KBs
+ ///
+ mIgdOpRegion.OpRegion->Header.SIZE = HEADER_SIZE / 1024;
+ mIgdOpRegion.OpRegion->Header.OVER = (UINT32) (LShiftU64 (HEADER_OPREGION_VER, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));
+
+ ///
+ /// All Mailboxes are supported.
+ ///
+ mIgdOpRegion.OpRegion->Header.MBOX = HEADER_MBOX_SUPPORT;
+
+ ///
+ /// Initialize OpRegion Mailbox 1 (Public ACPI Methods).
+ ///
+ /// Note - The initial setting of mailbox 1 fields is implementation specific.
+ /// Adjust them as needed many even coming from user setting in setup.
+ ///
+ mIgdOpRegion.OpRegion->MBox1.CLID = LID_OPEN;
+
+ ///
+ /// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation).
+ ///
+ /// Note - The initial setting of mailbox 3 fields is implementation specific.
+ /// Adjust them as needed many even coming from user setting in setup.
+ ///
+ ///
+ /// Do not initialize TCHE. This field is written by the graphics driver only.
+ ///
+ ///
+ /// The ALSI field is generally initialized by ASL code by reading the embedded controller.
+ ///
+ mIgdOpRegion.OpRegion->Header.PCON = GraphicsDxeConfig->PlatformConfig;
+ if (CpuSku != EnumCpuTrad) {
+ mIgdOpRegion.OpRegion->Header.PCON = mIgdOpRegion.OpRegion->Header.PCON | 0x2;
+ }
+
+ mIgdOpRegion.OpRegion->MBox3.BCLP = BACKLIGHT_BRIGHTNESS;
+
+ mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_STRETCH);
+
+ ///
+ /// Reporting to driver for VR IMON Calibration. Bits [5-1] values supported 14A to 31A.
+ ///
+ mIgdOpRegion.OpRegion->MBox3.PCFT = (SaGlobalNvsArea->Area->GfxTurboIMON << 1) & 0x003E;
+
+ ///
+ /// Set Initial current Brightness
+ ///
+ mIgdOpRegion.OpRegion->MBox3.CBLV = (INIT_BRIGHT_LEVEL | FIELD_VALID_BIT);
+
+ ///
+ /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle Mapping Table
+ /// Possible 20 entries (example used 10), each 16 bits as follows:
+ /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+ ///
+ mIgdOpRegion.OpRegion->MBox3.BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///< 0%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///< 10%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///< 20%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///< 30%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///< 40%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT); ///< 50%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///< 60%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///< 70%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///< 80%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///< 90%
+ mIgdOpRegion.OpRegion->MBox3.BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///< 100%
+
+ mIgdOpRegion.OpRegion->MBox3.IUER = 0x00;
+
+ if (!EFI_ERROR (Status)) {
+ mIgdOpRegion.OpRegion->MBox3.IUER = GraphicsDxeConfig->IuerStatusVal;
+ }
+
+ ///
+ /// Initialize hardware state:
+ /// Set ASLS Register to the OpRegion physical memory address.
+ /// Set SWSCI register bit 15 to a "1" to activate SCI interrupts.
+ ///
+ MmioWrite32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET, (UINT32) (UINTN) (mIgdOpRegion.OpRegion));
+ MmioAndThenOr16 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET, (UINT16) ~(BIT0), BIT15);
+
+ DwordData = MmioRead32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET);
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET),
+ 1,
+ &DwordData
+ );
+ DwordData = MmioRead32 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET);
+ S3BootScriptSaveMemWrite (
+ S3BootScriptWidthUint32,
+ (UINTN) (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET),
+ 1,
+ &DwordData
+ );
+
+ PchAcpiBaseGet (&PchAcpiBaseAddress);
+ PchTcoBaseGet (&PchTcoBaseAddress);
+ ///
+ /// Clear the B_DMISCI_STS bit in R_TCO1_STS by writing a '1'.
+ ///
+ IoWrite16 ((UINTN) (PchTcoBaseAddress + R_PCH_TCO1_STS), B_PCH_TCO1_STS_DMISCI);
+
+ ///
+ /// Clear the ACPI TCO status.
+ ///
+ Data32 = B_PCH_ACPI_GPE0_STS_127_96_TC0SCI;
+ IoWrite32 ((UINTN) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0_STS_127_96), Data32);
+
+ ///
+ /// Enable ACPI TCO SCI's.
+ ///
+ IoOr16 ((UINTN) (PchAcpiBaseAddress + R_PCH_ACPI_GPE0_EN_127_96), B_PCH_ACPI_GPE0_EN_127_96_TC0SCI);
+
+ ///
+ /// Install OpRegion / Software SCI protocol
+ ///
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gIgdOpRegionProtocolGuid,
+ &mIgdOpRegion,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Return final status
+ ///
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion.h new file mode 100644 index 0000000000..40616c4b82 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion.h @@ -0,0 +1,189 @@ +/** @file
+ This is part of the implementation of an Intel Graphics drivers OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ @par Specification Reference:
+ - OpRegion / Software SCI SPEC
+**/
+#ifndef _IGD_OPREGION_H_
+#define _IGD_OPREGION_H_
+
+///
+/// Statements that include other header files.
+///
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/S3BootScriptLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/IoLib.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/LegacyBios.h>
+#include <Library/MmPciLib.h>
+#include <PchAccess.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <SaAccess.h>
+#include <IndustryStandard/Pci22.h>
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include <Protocol/SaPolicy.h>
+
+
+#include <Protocol/SaGlobalNvsArea.h>
+
+///
+/// Driver Produced Protocol Prototypes
+///
+#include <Protocol/IgdOpRegion.h>
+
+///
+///
+/// OpRegion (Miscellaneous) defines.
+///
+/// OpRegion Header defines.
+///
+typedef UINT16 STRING_REF;
+#define HEADER_SIGNATURE "IntelGraphicsMem"
+#define HEADER_SIZE 0x2000
+#define HEADER_OPREGION_VER 0x0200
+#define HEADER_OPREGION_REV 0x00
+#define HEADER_MBOX_SUPPORT (HD_MBOX5 + HD_MBOX4 + HD_MBOX3 + HD_MBOX2 + HD_MBOX1)
+#define HD_MBOX1 BIT0
+#define HD_MBOX2 BIT1
+#define HD_MBOX3 BIT2
+#define HD_MBOX4 BIT3
+#define HD_MBOX5 BIT4
+#define SVER_SIZE 32
+
+///
+/// OpRegion Mailbox 1 EQUates.
+///
+#define LID_OPEN 3
+
+///
+/// OpRegion Mailbox 3 EQUates.
+///
+#define ALS_ENABLE BIT0
+#define BLC_ENABLE BIT1
+#define BACKLIGHT_BRIGHTNESS 0xFF
+#define FIELD_VALID_BIT BIT31
+#define WORD_FIELD_VALID_BIT BIT15
+#define PFIT_ENABLE BIT2
+#define PFIT_OPRN_AUTO 0x00000000
+#define PFIT_OPRN_SCALING 0x00000007
+#define PFIT_OPRN_OFF 0x00000000
+#define PFIT_SETUP_AUTO 0
+#define PFIT_SETUP_SCALING 1
+#define PFIT_SETUP_OFF 2
+#define INIT_BRIGHT_LEVEL 0x64
+#define PFIT_STRETCH 6
+
+///
+/// Video BIOS / VBT defines
+///
+#define OPTION_ROM_SIGNATURE 0xAA55
+#define VBIOS_LOCATION_PRIMARY 0xC0000
+
+#define VBT_SIGNATURE SIGNATURE_32 ('$', 'V', 'B', 'T')
+///
+/// Typedef stuctures
+///
+#pragma pack(1)
+typedef struct {
+ UINT16 Signature; /// 0xAA55
+ UINT8 Size512;
+ UINT8 Reserved[21];
+ UINT16 PcirOffset;
+ UINT16 VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ UINT32 Signature; /// "PCIR"
+ UINT16 VendorId; /// 0x8086
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ UINT8 HeaderSignature[20];
+ UINT16 HeaderVersion;
+ UINT16 HeaderSize;
+ UINT16 HeaderVbtSize;
+ UINT8 HeaderVbtCheckSum;
+ UINT8 HeaderReserved;
+ UINT32 HeaderOffsetVbtDataBlock;
+ UINT32 HeaderOffsetAim1;
+ UINT32 HeaderOffsetAim2;
+ UINT32 HeaderOffsetAim3;
+ UINT32 HeaderOffsetAim4;
+ UINT8 DataHeaderSignature[16];
+ UINT16 DataHeaderVersion;
+ UINT16 DataHeaderSize;
+ UINT16 DataHeaderDataBlockSize;
+ UINT8 CoreBlockId;
+ UINT16 CoreBlockSize;
+ UINT16 CoreBlockBiosSize;
+ UINT8 CoreBlockBiosType;
+ UINT8 CoreBlockReleaseStatus;
+ UINT8 CoreBlockHWSupported;
+ UINT8 CoreBlockIntegratedHW;
+ UINT8 CoreBlockBiosBuild[4];
+ UINT8 CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack()
+///
+/// Driver Private Function definitions
+///
+
+/**
+ Graphics OpRegion / Software SCI driver installation function.
+
+ @retval EFI_SUCCESS - The driver installed without error.
+ @retval EFI_ABORTED - The driver encountered an error and could not complete
+ installation of the ACPI tables.
+**/
+EFI_STATUS
+IgdOpRegionInit (
+ VOID
+ );
+
+/**
+ Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
+ The VBT (Video BIOS Table) is a block of customizable data that is built
+ within the video BIOS and edited by customers.
+
+ @retval EFI_SUCCESS - Video BIOS VBT information returned.
+ @exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosVbtPtr = NULL).
+**/
+EFI_STATUS
+GetVBiosVbtEndOfDxe (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c new file mode 100644 index 0000000000..4c7fc08200 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c @@ -0,0 +1,304 @@ +/** @file
+ This is the driver that initializes the Intel System Agent.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "SaInitDxe.h"
+#include "SaInit.h"
+#include <Protocol/SaGlobalNvsArea.h>
+
+///
+/// Global Variables
+///
+GLOBAL_REMOVE_IF_UNREFERENCED SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL mSaGlobalNvsAreaProtocol;
+GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
+
+/**
+ Initialize System Agent SSDT ACPI tables
+
+ @retval EFI_SUCCESS ACPI tables are initialized successfully
+ @retval EFI_NOT_FOUND ACPI tables not found
+**/
+EFI_STATUS
+InitializeSaSsdtAcpiTables (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN i;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ INTN Instance;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINTN AcpiTableKey;
+ UINT8 *CurrPtr;
+ UINT8 *EndPtr;
+ UINT32 *Signature;
+ EFI_ACPI_DESCRIPTION_HEADER *SaAcpiTable;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ FwVol = NULL;
+ SaAcpiTable = NULL;
+
+ ///
+ /// Locate ACPI Table protocol
+ ///
+ DEBUG ((DEBUG_INFO, "Init SA SSDT table\n"));
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_WARN, "Fail to locate EfiAcpiTableProtocol.\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ ///
+ /// Locate protocol.
+ /// There is little chance we can't find an FV protocol
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+ ///
+ /// Looking for FV with ACPI storage file
+ ///
+ for (i = 0; i < NumberOfHandles; i++) {
+ ///
+ /// Get the protocol on this handle
+ /// This should not fail because of LocateHandleBuffer
+ ///
+ Status = gBS->HandleProtocol (
+ HandleBuffer[i],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// See if it has the ACPI storage file
+ ///
+ Size = 0;
+ FvStatus = 0;
+ Status = FwVol->ReadFile (
+ FwVol,
+ &gSaSsdtAcpiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ ///
+ /// If we found it, then we are done
+ ///
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+ ///
+ /// Free any allocated buffers
+ ///
+ FreePool (HandleBuffer);
+
+ ///
+ /// Sanity check that we found our data file
+ ///
+ ASSERT (FwVol != NULL);
+ if (FwVol == NULL) {
+ DEBUG ((DEBUG_INFO, "SA Global NVS table not found\n"));
+ return EFI_NOT_FOUND;
+ }
+ ///
+ /// Our exit status is determined by the success of the previous operations
+ /// If the protocol was found, Instance already points to it.
+ /// Read tables from the storage file.
+ ///
+ Instance = 0;
+ CurrentTable = NULL;
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &gSaSsdtAcpiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Check the table ID to modify the table
+ ///
+ if (((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->OemTableId == SIGNATURE_64 ('S', 'a', 'S', 's', 'd', 't', ' ', 0)) {
+ SaAcpiTable = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
+ ///
+ /// Locate the SSDT package
+ ///
+ CurrPtr = (UINT8 *) SaAcpiTable;
+ EndPtr = CurrPtr + SaAcpiTable->Length;
+
+ for (; CurrPtr <= EndPtr; CurrPtr++) {
+ Signature = (UINT32 *) (CurrPtr + 3);
+ if (*Signature == SIGNATURE_32 ('S', 'A', 'N', 'V')) {
+ ASSERT (*(UINT32 *) (CurrPtr + 3 + sizeof (*Signature) + 2) == 0xFFFF0000);
+ ASSERT (*(UINT16 *) (CurrPtr + 3 + sizeof (*Signature) + 2 + sizeof (UINT32) + 1) == 0xAA55);
+ ///
+ /// SA Global NVS Area address
+ ///
+ *(UINT32 *) (CurrPtr + 3 + sizeof (*Signature) + 2) = (UINT32) (UINTN) mSaGlobalNvsAreaProtocol.Area;
+ ///
+ /// SA Global NVS Area size
+ ///
+ *(UINT16 *) (CurrPtr + 3 + sizeof (*Signature) + 2 + sizeof (UINT32) + 1) =
+ sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA);
+
+ AcpiTableKey = 0;
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ SaAcpiTable,
+ SaAcpiTable->Length,
+ &AcpiTableKey
+ );
+ ASSERT_EFI_ERROR (Status);
+ return EFI_SUCCESS;
+ }
+ }
+ }
+ ///
+ /// Increment the instance
+ ///
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ return Status;
+
+}
+
+/**
+ This function gets registered as a callback to perform Dmar Igd
+
+ @param[in] Event - A pointer to the Event that triggered the callback.
+ @param[in] Context - A pointer to private data registered with the callback function.
+**/
+VOID
+EFIAPI
+SaAcpiEndOfDxeCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+
+ UpdateDmarEndOfDxe ();
+
+ if (MmioRead16 (MmPciBase (SA_MC_BUS, 2, 0) + R_SA_IGD_VID) != 0xFFFF) {
+ Status = GetVBiosVbtEndOfDxe ();
+ if (EFI_SUCCESS != Status) {
+ DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Op Region Error, Status = %r \n", Status));
+ }
+
+ }
+
+ return;
+}
+
+/**
+ SystemAgent Acpi Initialization.
+
+ @param[in] ImageHandle Handle for the image of this driver
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
+**/
+EFI_STATUS
+EFIAPI
+SaAcpiInit (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT EndOfDxeEvent;
+ ///
+ /// Get the platform setup policy.
+ ///
+ Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &mSaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Install System Agent Global NVS protocol
+ ///
+ DEBUG ((DEBUG_INFO, "Install SA GNVS protocol\n"));
+ Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA), (VOID **) &mSaGlobalNvsAreaProtocol.Area);
+ ASSERT_EFI_ERROR (Status);
+ ZeroMem ((VOID *) mSaGlobalNvsAreaProtocol.Area, sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA));
+ mSaGlobalNvsAreaProtocol.Area->XPcieCfgBaseAddress = (UINT32) (MmPciBase (0, 0, 0));
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gSaGlobalNvsAreaProtocolGuid,
+ &mSaGlobalNvsAreaProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+
+ ///
+ /// GtPostInit Initialization
+ ///
+ DEBUG ((DEBUG_INFO, "Initializing GT ACPI tables\n"));
+ GraphicsInit (ImageHandle, mSaPolicy);
+
+ ///
+ /// Vtd Initialization
+ ///
+ DEBUG ((DEBUG_INFO, "Initializing VT-d ACPI tables\n"));
+ VtdInit (mSaPolicy);
+
+ ///
+ /// IgdOpRegion Install Initialization
+ ///
+ DEBUG ((DEBUG_INFO, "Initializing IGD OpRegion\n"));
+ IgdOpRegionInit ();
+
+ ///
+ /// Register an end of DXE event for SA ACPI to do tasks before invoking any UEFI drivers,
+ /// applications, or connecting consoles,...
+ ///
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ SaAcpiEndOfDxeCallback,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+
+ ///
+ /// Install System Agent Global NVS ACPI table
+ ///
+ Status = InitializeSaSsdtAcpiTables ();
+
+
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h new file mode 100644 index 0000000000..7e9efc40bc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h @@ -0,0 +1,33 @@ +/** @file
+ Header file for SA Common Initialization Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_INITIALIZATION_DRIVER_H_
+#define _SA_INITIALIZATION_DRIVER_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/S3BootScriptLib.h>
+#include <Library/SaPlatformLib.h>
+#include <Guid/EventGroup.h>
+#include <CpuRegs.h>
+#include <SaAccess.h>
+#include <Library/CpuPlatformLib.h>
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c new file mode 100644 index 0000000000..6900cf8a5b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c @@ -0,0 +1,47 @@ +/** @file
+ This is the driver that initializes the Intel System Agent.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "SaInitDxe.h"
+#include "SaInit.h"
+#include <Library/MmPciLib.h>
+#include <MemInfoHob.h>
+
+/**
+ SystemAgent Dxe Initialization.
+
+ @param[in] ImageHandle Handle for the image of this driver
+ @param[in] SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
+**/
+EFI_STATUS
+EFIAPI
+SaInitEntryPointDxe (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SaInitDxe Start\n"));
+
+
+ Status = SaAcpiInit (ImageHandle);
+
+
+ DEBUG ((DEBUG_INFO, "SaInitDxe End\n"));
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h new file mode 100644 index 0000000000..55a87fef4d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h @@ -0,0 +1,102 @@ +/** @file
+ Header file for SA Initialization Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SA_INITIALIZATION_DXE_DRIVER_H_
+#define _SA_INITIALIZATION_DXE_DRIVER_H_
+
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/AcpiTable.h>
+#include "VTd.h"
+#include "IgdOpRegion.h"
+#include "GraphicsInit.h"
+#include <Library/HobLib.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <SiConfigHob.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/MmPciLib.h>
+
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include <Protocol/SaPolicy.h>
+
+extern EFI_GUID gSaSsdtAcpiTableStorageGuid;
+
+/**
+ <b>System Agent Initialization DXE Driver Entry Point</b>
+ - <b>Introduction</b> \n
+ Based on the information/data in SA_POLICY_PROTOCOL, this module performs further SA initialization in DXE phase,
+ e.g. internal devices enable/disable, SSVID/SID programming, graphic power-management, VT-d, IGD OpRegion initialization.
+ From the perspective of a PCI Express hierarchy, the Broadwell System Agent and PCH together appear as a Root Complex with root ports the number of which depends on how the 8 PCH ports and 4 System Agent PCIe ports are configured [4x1, 2x8, 1x16].
+ There is an internal link (DMI or OPI) that connects the System Agent to the PCH component. This driver includes initialization of SA DMI, PCI Express, SA & PCH Root Complex Topology.
+ For iGFX, this module implements the initialization of the Graphics Technology Power Management from the Broadwell System Agent BIOS Specification and the initialization of the IGD OpRegion/Software SCI - BIOS Specification.
+ The ASL files that go along with the driver define the IGD OpRegion mailboxes in ACPI space and implement the software SCI interrupt mechanism.
+ The IGD OpRegion/Software SCI code serves as a communication interface between system BIOS, ASL, and Intel graphics driver including making a block of customizable data (VBT) from the Intel video BIOS available.
+ Reference Code for the SCI service functions "Get BIOS Data" and "System BIOS Callback" can be found in the ASL files, those functions can be platform specific, the sample provided in the reference code are implemented for Intel CRB.
+ This module implements the VT-d functionality described in the Broadwell System Agent BIOS Specification.
+ This module publishes the LegacyRegion protocol to control the read and write accesses to the Legacy BIOS ranges.
+ E000 and F000 segments are the legacy BIOS ranges and contain pointers to the ACPI regions, SMBIOS tables and so on. This is a private protocol used by Intel Framework.
+ This module registers CallBack function that performs SA security registers lockdown at end of post as required from Broadwell Bios Spec.
+ In addition, this module publishes the SaInfo Protocol with information such as current System Agent reference code version#.
+
+ - @pre
+ - EFI_FIRMWARE_VOLUME_PROTOCOL: Documented in Firmware Volume Specification, available at the URL: http://www.intel.com/technology/framework/spec.htm
+ - SA_POLICY_PROTOCOL: A protocol published by a platform DXE module executed earlier; this is documented in this document as well.
+ - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL: Documented in the Unified Extensible Firmware Interface Specification, version 2.0, available at the URL: http://www.uefi.org/specs/
+ - EFI_BOOT_SCRIPT_SAVE_PROTOCOL: A protocol published by a platform DXE module executed earlier; refer to the Sample Code section of the Framework PCH Reference Code.
+ - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL: Documented in the Unified Extensible Firmware Interface Specification, version 2.0, available at the URL: http://www.uefi.org/specs/
+ - EFI_ACPI_TABLE_PROTOCOL : Documented in PI Specification 1.2
+ - EFI_CPU_IO_PROTOCOL: Documented in CPU I/O Protocol Specification, available at the URL: http://www.intel.com/technology/framework/spec.htm
+ - EFI_DATA_HUB_PROTOCOL: Documented in EFI Data Hub Infrastructure Specification, available at the URL: http://www.intel.com/technology/framework/spec.htm
+ - EFI_HII_PROTOCOL (or EFI_HII_DATABASE_PROTOCOL for UEFI 2.1): Documented in Human Interface Infrastructure Specification, available at the URL: http://www.intel.com/technology/framework/spec.htm
+ (For EFI_HII_DATABASE_PROTOCOL, refer to UEFI Specification Version 2.1 available at the URL: http://www.uefi.org/)
+
+ - @result
+ IGD power-management functionality is initialized; VT-d is initialized (meanwhile, the DMAR table is updated); IGD OpRegion is initialized - IGD_OPREGION_PROTOCOL installed, IGD OpRegion allocated and mailboxes initialized, chipset initialized and ready to generate Software SCI for Internal graphics events. Publishes the SA_INFO_PROTOCOL with current SA reference code version #. Publishes the EFI_LEGACY_REGION_PROTOCOL documented in the Compatibility Support Module Specification, version 0.9, available at the URL: http://www.intel.com/technology/framework/spec.htm
+
+ - <b>References</b> \n
+ IGD OpRegion/Software SCI for Broadwell
+ Advanced Configuration and Power Interface Specification Revision 4.0a.
+
+ - <b>Porting Recommendations</b> \n
+ No modification of the DXE driver should be typically necessary.
+ This driver should be executed after all related devices (audio, video, ME, etc.) are initialized to ensure correct data in DMAR table and DMA-remapping registers.
+
+ @param[in] ImageHandle Handle for the image of this driver
+ @param[in] SystemTable Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
+**/
+EFI_STATUS
+EFIAPI
+SaInitEntryPointDxe (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ SystemAgent Acpi Initialization.
+
+ @param[in] ImageHandle Handle for the image of this driver
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate
+**/
+EFI_STATUS
+EFIAPI
+SaAcpiInit (
+ IN EFI_HANDLE ImageHandle
+ );
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf new file mode 100644 index 0000000000..6b01b494cd --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf @@ -0,0 +1,109 @@ +## @file
+# Component description file for SystemAgent Initialization driver
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SaInitDxe
+FILE_GUID = DE23ACEE-CF55-4fb6-AA77-984AB53DE811
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+ENTRY_POINT = SaInitEntryPointDxe
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+
+
+[LibraryClasses]
+UefiDriverEntryPoint
+UefiLib
+UefiBootServicesTableLib
+DxeServicesTableLib
+DebugLib
+TimerLib
+PciLib
+BaseMemoryLib
+MemoryAllocationLib
+CpuPlatformLib
+IoLib
+S3BootScriptLib
+MmPciLib
+PchCycleDecodingLib
+PchP2sbLib
+GpioLib
+ConfigBlockLib
+SaPlatformLib
+HobLib
+PchPcieRpLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+KabylakeSiliconPkg/KabylakeSiliconPrivate.dec
+
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId
+gSiPkgTokenSpaceGuid.PcdMchBaseAddress
+
+[Sources]
+SaInitDxe.h
+SaInitDxe.c
+SaInit.h
+IgdOpRegion.h
+IgdOpRegion.c
+GraphicsInit.h
+GraphicsInit.c
+SaAcpi.c
+VTd.c
+VTd.h
+
+
+[Protocols]
+gEfiAcpiTableProtocolGuid ## CONSUMES
+gSaGlobalNvsAreaProtocolGuid ## PRODUCES
+gSaPolicyProtocolGuid ## CONSUMES
+gEfiCpuArchProtocolGuid ## CONSUMES
+gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES
+gEfiPciRootBridgeIoProtocolGuid ## CONSUMES
+gEfiPciIoProtocolGuid ## CONSUMES
+gEfiGlobalNvsAreaProtocolGuid ## CONSUMES
+gIgdOpRegionProtocolGuid ## PRODUCES
+gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+gEfiLegacyBiosProtocolGuid ## CONSUMES
+
+[Guids]
+gSaConfigHobGuid
+gSaAcpiTableStorageGuid
+gMiscDxeConfigGuid
+gSaSsdtAcpiTableStorageGuid
+gEfiEndOfDxeEventGroupGuid
+gSiConfigHobGuid ## CONSUMES
+gPchConfigHobGuid ## CONSUMES
+gGraphicsDxeConfigGuid
+
+[Depex]
+gEfiAcpiTableProtocolGuid AND
+gEfiFirmwareVolume2ProtocolGuid AND
+gSaPolicyProtocolGuid AND
+gEfiPciRootBridgeIoProtocolGuid AND
+gEfiPciHostBridgeResourceAllocationProtocolGuid AND # This is to ensure that PCI MMIO resource has been prepared and available for this driver to allocate.
+gEfiHiiDatabaseProtocolGuid
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.c new file mode 100644 index 0000000000..ded44b661f --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.c @@ -0,0 +1,931 @@ +/** @file
+ This code provides a initialization of intel VT-d (Virtualization Technology for Directed I/O).
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "SaInitDxe.h"
+#include "SaInit.h"
+#include "VTd.h"
+#include <CpuRegs.h>
+#include <SaConfigHob.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PchP2sbLib.h>
+#include <Library/PchInfoLib.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy;
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *mPchConfigHob;
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_SERIES mPchSeries;
+GLOBAL_REMOVE_IF_UNREFERENCED SA_CONFIG_HOB *SaConfigHob;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddI2C0Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddI2C1Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddI2C2Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddI2C3Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddI2C4Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddI2C5Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddSpi0Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddSpi1Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddUa00Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddUa01Needed;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAnddUa02Needed;
+
+/**
+ For device that specified by Device Num and Function Num,
+ mDevEnMap is used to check device presence.
+ 0x80 means use Device ID to detemine presence
+
+ The structure is used to check if device scope is valid when update DMAR table
+**/
+UINT16 mDevEnMap[][2] = {{0x0200, 0x80}, {0x1400, 0x80}, {0x1401, 0x80}};
+
+BOOLEAN mInterruptRemappingSupport;
+
+/**
+ Get the corresponding device Enable/Disable bit according DevNum and FunNum
+
+ @param[in] DevNum - Device Number
+ @param[in] FunNum - Function Number
+
+ @retval If the device is found, return disable/Enable bit in FD/Deven reigster
+ @retval If not found return 0xFF
+**/
+UINT16
+GetFunDisableBit (
+ UINT8 DevNum,
+ UINT8 FunNum
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < sizeof (mDevEnMap) / 4; Index++) {
+ if (mDevEnMap[Index][0] == ((DevNum << 0x08) | FunNum)) {
+ return mDevEnMap[Index][1];
+ }
+ }
+
+ return 0xFF;
+}
+
+/**
+ Update the DRHD structure
+
+ @param[in, out] DrhdEnginePtr - A pointer to DRHD structure
+**/
+VOID
+UpdateDrhd (
+ IN OUT VOID *DrhdEnginePtr
+ )
+{
+ UINT16 Length;
+ UINT16 DisableBit;
+ UINTN DeviceScopeNum;
+ BOOLEAN NeedRemove;
+ EFI_ACPI_DRHD_ENGINE1_STRUCT *DrhdEngine;
+
+ //
+ // Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE1_STRUCT Pointer
+ //
+ DrhdEngine = (EFI_ACPI_DRHD_ENGINE1_STRUCT *) DrhdEnginePtr;
+ Length = DrhdEngine->Length;
+ DeviceScopeNum = (DrhdEngine->Length - EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+ DisableBit = GetFunDisableBit (
+ DrhdEngine->DeviceScope[0].PciPath[0],
+ DrhdEngine->DeviceScope[0].PciPath[1]
+ );
+ NeedRemove = FALSE;
+ if ((DisableBit == 0xFF) ||
+ (DrhdEngine->RegisterBaseAddress == 0) ||
+ ((DisableBit == 0x80) &&
+ (MmioRead32 (MmPciBase (0, DrhdEngine->DeviceScope[0].PciPath[0], DrhdEngine->DeviceScope[0].PciPath[1]) + 0x00) == 0xFFFFFFFF))
+ ) {
+ NeedRemove = TRUE;
+ }
+ if (NeedRemove) {
+ Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+ }
+ ///
+ /// If no devicescope is left, we set the structure length as 0x00
+ ///
+ if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->Flags == 0x01)) {
+ DrhdEngine->Length = Length;
+ } else {
+ DrhdEngine->Length = 0;
+ }
+}
+
+/**
+ Get IOAPIC ID from LPC
+
+ @retval APIC ID
+**/
+UINT8
+GetIoApicId (
+ VOID
+ )
+{
+ UINT8 volatile *IoapicIndex;
+ UINT32 volatile *IoapicData;
+ UINT32 IoApicIndexAddr;
+ UINT32 IoApicDataAddr;
+ UINT32 Data32;
+
+ ///
+ /// Get IOAPIC base
+ ///
+ PchIoApicBaseGet (&IoApicIndexAddr, &IoApicDataAddr);
+ IoapicIndex = (UINT8 *) (UINTN) IoApicIndexAddr;
+ IoapicData = (UINT32 *) (UINTN) IoApicDataAddr;
+
+ ///
+ /// Get APIC ID from Identification Register (Index 0)
+ ///
+ *IoapicIndex = 0;
+ Data32 = (*IoapicData & 0x0F000000) >> 24;
+
+ return (UINT8) Data32;
+}
+
+/**
+ Initialize some data required for ANDD table generation.
+
+**/
+VOID
+AnddTablePreInit (
+ VOID
+ )
+{
+ /*
+ For Serial IO devices, they do not appear in PCI space, use platform policy or SPT SKU to determine existence
+ - I2C0 (D21: F0)
+ - I2C1 (D21: F1)
+ - I2C2 (D21: F2) (LP Only)
+ - I2C3 (D21: F3) (LP Only)
+ - I2C4 (D25: F2) (LP Only)
+ - I2C5 (D25: F1) (LP Only)
+ - SPI0 (D30: F2)
+ - SPI1 (D30: F3)
+ - UART0 (D30: F0)
+ - UART1 (D30: F1)
+ - UART2 (D25: F0)
+ - PEMC (D30: F4) (LP Only) (PCI mode only)
+ - PSDO (D30: F5) (LP Only) (Deprecated)
+ - PSDC (D30: F6) (LP Only) (PCI mode only)
+ */
+ mAnddI2C0Needed = TRUE;
+ mAnddI2C1Needed = TRUE;
+ mAnddI2C2Needed = TRUE;
+ mAnddI2C3Needed = TRUE;
+ mAnddI2C4Needed = TRUE;
+ mAnddI2C5Needed = TRUE;
+ mAnddSpi0Needed = TRUE;
+ mAnddSpi1Needed = TRUE;
+ mAnddUa00Needed = TRUE;
+ mAnddUa01Needed = TRUE;
+ mAnddUa02Needed = TRUE;
+
+ if (mPchConfigHob->SerialIo.DevMode[0] != 2) {
+ mAnddI2C0Needed = FALSE;
+ if (mPchConfigHob->SerialIo.DevMode[0] == 0) {
+ //
+ // Function 0 disabled so no sub-functions
+ //
+ mAnddI2C1Needed = FALSE;
+ mAnddI2C2Needed = FALSE;
+ mAnddI2C3Needed = FALSE;
+ }
+ }
+ if (mPchConfigHob->SerialIo.DevMode[1] != 2) {
+ mAnddI2C1Needed = FALSE;
+ }
+ if ((mPchSeries != PchLp) || (mPchConfigHob->SerialIo.DevMode[2] != 2)) {
+ mAnddI2C2Needed = FALSE;
+ }
+ if ((mPchSeries != PchLp) || (mPchConfigHob->SerialIo.DevMode[3] != 2)) {
+ mAnddI2C3Needed = FALSE;
+ }
+ if ((mPchSeries != PchLp) || (mPchConfigHob->SerialIo.DevMode[4] != 2)) {
+ mAnddI2C4Needed = FALSE;
+ }
+ if ((mPchSeries != PchLp) || (mPchConfigHob->SerialIo.DevMode[5] != 2)) {
+ mAnddI2C5Needed = FALSE;
+ }
+ if (mPchConfigHob->SerialIo.DevMode[6] != 2) {
+ mAnddSpi0Needed = FALSE;
+ }
+ if (mPchConfigHob->SerialIo.DevMode[7] != 2) {
+ mAnddSpi1Needed = FALSE;
+ }
+ if (mPchConfigHob->SerialIo.DevMode[8] != 2) {
+ mAnddUa00Needed = FALSE;
+ if (mPchConfigHob->SerialIo.DevMode[8] == 0) {
+ //
+ // Function 0 disabled so no sub-functions
+ //
+ mAnddUa01Needed = FALSE;
+ mAnddSpi0Needed = FALSE;
+ mAnddSpi1Needed = FALSE;
+ }
+ }
+ if (mPchConfigHob->SerialIo.DevMode[9] != 2) {
+ mAnddUa01Needed = FALSE;
+ }
+ if (mPchConfigHob->SerialIo.DevMode[10] != 2) {
+ mAnddUa02Needed = FALSE;
+ if (mPchConfigHob->SerialIo.DevMode[10] == 0) {
+ //
+ // Function 0 disabled so no sub-functions
+ //
+ mAnddI2C4Needed = FALSE;
+ mAnddI2C5Needed = FALSE;
+ }
+ }
+}
+
+/**
+ Update the second DRHD structure
+
+ @param[in, out] DrhdEnginePtr - A pointer to DRHD structure
+**/
+VOID
+UpdateDrhd2 (
+ IN OUT VOID *DrhdEnginePtr
+ )
+{
+ UINT16 Length;
+ UINTN DeviceScopeNum;
+ UINTN ValidDeviceScopeNum;
+ UINT16 Data16;
+ UINT16 Index;
+ UINT8 Bus;
+ UINT8 Path[2];
+ BOOLEAN NeedRemove;
+ EFI_ACPI_DRHD_ENGINE2_STRUCT *DrhdEngine;
+
+ ///
+ /// Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE2_STRUCT Pointer
+ ///
+ DrhdEngine = (EFI_ACPI_DRHD_ENGINE2_STRUCT *) DrhdEnginePtr;
+
+ Length = DrhdEngine->Length;
+ DeviceScopeNum = (DrhdEngine->Length - EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+ Data16 = 0;
+ Bus = 0;
+ ValidDeviceScopeNum = 0;
+ Path[0] = 0;
+ Path[1] = 0;
+
+ AnddTablePreInit ();
+
+ for (Index = 0; Index < DeviceScopeNum; Index++) {
+ NeedRemove = FALSE;
+ /**
+ For HPET and APIC, update device scope if Interrupt remapping is supported. remove device scope
+ if interrupt remapping is not supported.
+ - Index = 0 - IOAPIC
+ - Index = 1 - HPET
+ **/
+ if (mInterruptRemappingSupport) {
+ if (Index == 0) {
+ ///
+ /// Update source id for IoApic's device scope entry
+ ///
+ PchP2sbCfgGet16 (R_PCH_P2SB_IBDF, &Data16);
+ Bus = (UINT8) (Data16 >> 8);
+ if (Bus != 0x00) {
+ Path[0] = (UINT8) ((Data16 & 0xff) >> 3);
+ Path[1] = (UINT8) (Data16 & 0x7);
+ } else {
+ DEBUG ((DEBUG_WARN, "P2SB APIC Bus, Device and Function numbers were not programmed yet or invalid, use hardcoding values instead!\n"));
+ Bus = 0xF0;
+ Path[0] = 0x1F;
+ Path[1] = 0x0;
+ }
+ DrhdEngine->DeviceScope[Index].StartBusNumber = Bus;
+ DrhdEngine->DeviceScope[Index].PciPath[0] = Path[0];
+ DrhdEngine->DeviceScope[Index].PciPath[1] = Path[1];
+ //
+ // Update APIC ID
+ //
+ DrhdEngine->DeviceScope[Index].EnumId = GetIoApicId ();
+ }
+ if (Index == 1) {
+ ///
+ /// Update source id for HPET's device scope entry
+ ///
+ PchP2sbCfgGet16 (R_PCH_P2SB_HBDF, &Data16);
+ Bus = (UINT8) (Data16 >> 8);
+ Path[0] = (UINT8) ((Data16 & 0xFF) >> 3);
+ Path[1] = (UINT8) (Data16 & 0x7);
+ DrhdEngine->DeviceScope[Index].StartBusNumber = Bus;
+ DrhdEngine->DeviceScope[Index].PciPath[0] = Path[0];
+ DrhdEngine->DeviceScope[Index].PciPath[1] = Path[1];
+ }
+ } else {
+ if ((Index == 0) || (Index == 1)) {
+ NeedRemove = TRUE;
+ }
+ }
+
+ switch (Index) {
+ case 0:
+ case 1:
+ break;
+ case 2:
+ if (mAnddI2C0Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 3:
+ if (mAnddI2C1Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 4:
+ if (mAnddI2C2Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 5:
+ if (mAnddI2C3Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 6:
+ if (mAnddI2C4Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 7:
+ if (mAnddI2C5Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 8:
+ if (mAnddSpi0Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 9:
+ if (mAnddSpi1Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 10:
+ if (mAnddUa00Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 11:
+ if (mAnddUa01Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ case 12:
+ if (mAnddUa02Needed == FALSE) {
+ NeedRemove = TRUE;
+ }
+ break;
+ default:
+ NeedRemove = TRUE;
+ break;
+ }
+
+ CopyMem (
+ &DrhdEngine->DeviceScope[ValidDeviceScopeNum],
+ &DrhdEngine->DeviceScope[Index],
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE)
+ );
+ if (NeedRemove) {
+ Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+ } else {
+ ValidDeviceScopeNum++;
+ }
+ }
+ ///
+ /// If no devicescope is left, we set the structure length as 0x00
+ ///
+ if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->Flags == 0x01)) {
+ DrhdEngine->Length = Length;
+ } else {
+ DrhdEngine->Length = 0;
+ }
+}
+
+/**
+ Update the RMRR structure
+
+ @param[in, out] RmrrPtr - A pointer to RMRR structure
+**/
+VOID
+UpdateRmrr (
+ IN OUT VOID *RmrrPtr
+ )
+{
+ UINT16 Length;
+ UINT16 DisableBit;
+ UINTN DeviceScopeNum;
+ UINTN ValidDeviceScopeNum;
+ UINTN Index;
+ BOOLEAN NeedRemove;
+ EFI_ACPI_RMRR_USB_STRUC *Rmrr;
+
+ ///
+ /// To make sure all devicescope can be checked,
+ /// we convert the RmrrPtr to EFI_ACPI_RMRR_USB_STRUC pointer
+ ///
+ Rmrr = (EFI_ACPI_RMRR_USB_STRUC *) RmrrPtr;
+
+ Length = Rmrr->Length;
+ ValidDeviceScopeNum = 0;
+ DeviceScopeNum = (Rmrr->Length - EFI_ACPI_RMRR_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+ for (Index = 0; Index < DeviceScopeNum; Index++) {
+ DisableBit = GetFunDisableBit (
+ Rmrr->DeviceScope[Index].PciPath[0],
+ Rmrr->DeviceScope[Index].PciPath[1]
+ );
+ NeedRemove = FALSE;
+ if ((DisableBit == 0xFF) ||
+ ((DisableBit == 0x80) &&
+ (MmioRead32 (MmPciBase (0, Rmrr->DeviceScope[Index].PciPath[0], Rmrr->DeviceScope[Index].PciPath[1]) + 0x00) == 0xFFFFFFFF))
+ ) {
+ NeedRemove = TRUE;
+ }
+ CopyMem (
+ &Rmrr->DeviceScope[ValidDeviceScopeNum],
+ &Rmrr->DeviceScope[Index],
+ sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE)
+ );
+
+ if (Rmrr->RmrLimitAddress == 0x0) {
+ NeedRemove = TRUE;
+ }
+
+ if (NeedRemove) {
+ Length -= sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE);
+ } else {
+ ValidDeviceScopeNum++;
+ }
+ }
+ ///
+ /// If No deviceScope is left, set length as 0x00
+ ///
+ if (Length > EFI_ACPI_RMRR_HEADER_LENGTH) {
+ Rmrr->Length = Length;
+ } else {
+ Rmrr->Length = 0;
+ }
+}
+
+/**
+ Update the DMAR table
+
+ @param[in, out] TableHeader - The table to be set
+ @param[in, out] Version - Version to publish
+**/
+VOID
+DmarTableUpdate (
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ EFI_ACPI_DMAR_TABLE *DmarTable;
+ EFI_ACPI_DMAR_TABLE TempDmarTable;
+ UINTN Offset;
+ UINTN StructureLen;
+ UINTN McD0BaseAddress;
+ UINT32 MchBar;
+ UINT16 IgdMode;
+ UINT16 GttMode;
+ UINT32 IgdMemSize;
+ UINT32 GttMemSize;
+ EFI_STATUS Status;
+ MISC_DXE_CONFIG *MiscDxeConfig;
+ CPU_GENERATION CpuGeneration;
+ UINT64 OemTableId;
+
+ IgdMemSize = 0;
+ GttMemSize = 0;
+ DmarTable = (EFI_ACPI_DMAR_TABLE *) TableHeader;
+ CpuGeneration = GetCpuGeneration ();
+ //
+ // The Default OEM Table ID is "KBL "
+ //
+ OemTableId = KBL_OEM_TABLE_ID;
+
+ Status = GetConfigBlock ((VOID *) mSaPolicy, &gMiscDxeConfigGuid, (VOID *)&MiscDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Set INTR_REMAP bit (BIT 0) if interrupt remapping is supported
+ ///
+ if (mInterruptRemappingSupport) {
+ DmarTable->Flags |= BIT0;
+ }
+
+ if (SaConfigHob->VtdData.X2ApicOptOut == 1) {
+ DmarTable->Flags |= BIT1;
+ } else {
+ DmarTable->Flags &= 0xFD;
+ }
+
+ ///
+ /// Get OemId
+ ///
+ CopyMem (DmarTable->Header.OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (DmarTable->Header.OemId));
+
+ if (CpuGeneration == EnumSklCpu) {
+ //
+ // Use "SKL " as OEM Table ID if the CpuGeneration is SKL
+ //
+ OemTableId = SKL_OEM_TABLE_ID;
+ }
+ //
+ // Update OEM Table ID
+ //
+ DmarTable->Header.OemTableId = OemTableId;
+
+ ///
+ /// Calculate IGD memsize
+ ///
+ McD0BaseAddress = MmPciBase (SA_MC_BUS, 0, 0);
+ MchBar = (UINT32) MmioRead64 (McD0BaseAddress + R_SA_MCHBAR) & ~BIT0;
+ IgdMode = ((MmioRead16 (McD0BaseAddress + R_SA_GGC) & B_SKL_SA_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF;
+ if (IgdMode < 0xF0) {
+ IgdMemSize = IgdMode * 32 * (1024) * (1024);
+ } else {
+ IgdMemSize = 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024);
+ }
+ ///
+ /// Calculate GTT mem size
+ ///
+ GttMemSize = 0;
+ GttMode = (MmioRead16 (McD0BaseAddress + R_SA_GGC) & B_SKL_SA_GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET;
+ if (GttMode <= V_SKL_SA_GGC_GGMS_8MB) {
+ GttMemSize = (1 << GttMode) * (1024) * (1024);
+ }
+
+ DmarTable->RmrrIgd.RmrBaseAddress = (MmioRead32 (McD0BaseAddress + R_SA_TOLUD) & ~(0x01)) - IgdMemSize - GttMemSize;
+ DmarTable->RmrrIgd.RmrLimitAddress = DmarTable->RmrrIgd.RmrBaseAddress + IgdMemSize + GttMemSize - 1;
+ DEBUG ((DEBUG_INFO, "RMRR Base address IGD %016lX\n", DmarTable->RmrrIgd.RmrBaseAddress));
+ DEBUG ((DEBUG_INFO, "RMRR Limit address IGD %016lX\n", DmarTable->RmrrIgd.RmrLimitAddress));
+
+ DmarTable->RmrrUsb.RmrBaseAddress = MiscDxeConfig->RmrrUsbBaseAddress[0];
+ DmarTable->RmrrUsb.RmrLimitAddress = MiscDxeConfig->RmrrUsbBaseAddress[1];
+
+ ///
+ /// Convert to 4KB alignment.
+ ///
+ if (DmarTable->RmrrUsb.RmrLimitAddress != 0x0) {
+ DmarTable->RmrrUsb.RmrBaseAddress &= (EFI_PHYSICAL_ADDRESS) ~0xFFF;
+ DmarTable->RmrrUsb.RmrLimitAddress &= (EFI_PHYSICAL_ADDRESS) ~0xFFF;
+ DmarTable->RmrrUsb.RmrLimitAddress += 0x1000-1;
+ }
+
+ DEBUG ((DEBUG_INFO, "RMRR Base address USB %016lX\n", DmarTable->RmrrUsb.RmrBaseAddress));
+ DEBUG ((DEBUG_INFO, "RMRR Limit address USB %016lX\n", DmarTable->RmrrUsb.RmrLimitAddress));
+
+ if (DmarTable->RmrrUsb.RmrBaseAddress == 0) {
+ DEBUG ((DEBUG_WARN, "WARNING: RmrrUsb.RmrBaseAddress is 0.\n"));
+ }
+ ///
+ /// Update DRHD structures of DmarTable
+ ///
+ DmarTable->DrhdEngine1.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1);
+ DmarTable->DrhdEngine2.RegisterBaseAddress = (MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1);
+
+ DEBUG ((DEBUG_INFO, "VTD base address1 %x\n", DmarTable->DrhdEngine1.RegisterBaseAddress));
+ DEBUG ((DEBUG_INFO, "VTD base address2 %x\n", DmarTable->DrhdEngine2.RegisterBaseAddress));
+ ///
+ /// copy DmarTable to TempDmarTable to be processed
+ ///
+ CopyMem (&TempDmarTable, DmarTable, sizeof (EFI_ACPI_DMAR_TABLE));
+
+ UpdateDrhd (&TempDmarTable.DrhdEngine1);
+ UpdateDrhd2 (&TempDmarTable.DrhdEngine2);
+
+ ///
+ /// Update RMRR structures of temp DMAR table
+ ///
+ UpdateRmrr ((VOID *) &TempDmarTable.RmrrUsb);
+ UpdateRmrr ((VOID *) &TempDmarTable.RmrrIgd);
+
+ ///
+ /// Remove unused device scope or entire DRHD structures
+ ///
+ Offset = (UINTN) (&TempDmarTable.DrhdEngine1);
+ if (TempDmarTable.DrhdEngine1.Length != 0) {
+ Offset += TempDmarTable.DrhdEngine1.Length;
+ }
+ if (TempDmarTable.DrhdEngine2.Length != 0) {
+ StructureLen = TempDmarTable.DrhdEngine2.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.DrhdEngine2, TempDmarTable.DrhdEngine2.Length);
+ Offset += StructureLen;
+ }
+ ///
+ /// Remove unused device scope or entire RMRR structures
+ ///
+ if (TempDmarTable.RmrrUsb.Length != 0) {
+ StructureLen = TempDmarTable.RmrrUsb.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrUsb, TempDmarTable.RmrrUsb.Length);
+ Offset += StructureLen;
+ }
+ if (TempDmarTable.RmrrIgd.Length != 0) {
+ StructureLen = TempDmarTable.RmrrIgd.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrIgd, TempDmarTable.RmrrIgd.Length);
+ Offset += StructureLen;
+ }
+
+ ///
+ /// Include necessary ANDD structures for SPT
+ ///
+ if (mAnddI2C0Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddI2C0.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C0, TempDmarTable.AnddI2C0.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddI2C1Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddI2C1.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C1, TempDmarTable.AnddI2C1.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddI2C2Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddI2C2.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C2, TempDmarTable.AnddI2C2.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddI2C3Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddI2C3.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C3, TempDmarTable.AnddI2C3.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddI2C4Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddI2C4.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C4, TempDmarTable.AnddI2C4.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddI2C5Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddI2C5.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddI2C5, TempDmarTable.AnddI2C5.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddSpi0Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddSpi0.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddSpi0, TempDmarTable.AnddSpi0.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddSpi1Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddSpi1.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddSpi1, TempDmarTable.AnddSpi1.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddUa00Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddUa00.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddUa00, TempDmarTable.AnddUa00.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddUa01Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddUa01.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddUa01, TempDmarTable.AnddUa01.Length);
+ Offset += StructureLen;
+ }
+ if (mAnddUa02Needed == TRUE) {
+ StructureLen = TempDmarTable.AnddUa02.Length;
+ CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.AnddUa02, TempDmarTable.AnddUa02.Length);
+ Offset += StructureLen;
+ }
+
+ Offset = Offset - (UINTN) &TempDmarTable;
+ ///
+ /// Re-calculate DMAR table check sum
+ ///
+ TempDmarTable.Header.Checksum = (UINT8) (TempDmarTable.Header.Checksum + TempDmarTable.Header.Length - Offset);
+ ///
+ /// Set DMAR table length
+ ///
+ TempDmarTable.Header.Length = (UINT32) Offset;
+ ///
+ /// Replace DMAR table with rebuilt table TempDmarTable
+ ///
+ CopyMem ((VOID *) DmarTable, (VOID *) &TempDmarTable, TempDmarTable.Header.Length);
+}
+
+/**
+ EndOfDxe routine for update DMAR
+**/
+VOID
+UpdateDmarEndOfDxe (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN i;
+ INTN Instance;
+ EFI_ACPI_TABLE_VERSION Version;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINTN AcpiTableHandle;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_DESCRIPTION_HEADER *VtdAcpiTable;
+ STATIC BOOLEAN Triggered = FALSE;
+ EFI_PEI_HOB_POINTERS HobPtr;
+ if (Triggered) {
+ return;
+ }
+
+ Triggered = TRUE;
+
+ FwVol = NULL;
+ AcpiTable = NULL;
+ VtdAcpiTable = NULL;
+
+ ///
+ /// Locate PCH Policy HOB and PCH series to support feature enabling/disabling
+ ///
+ //
+ // Get PCH Config HOB.
+ //
+ HobPtr.Guid = GetFirstGuidHob (&gPchConfigHobGuid);
+ ASSERT (HobPtr.Guid != NULL);
+ mPchConfigHob = GET_GUID_HOB_DATA (HobPtr.Guid);
+
+ mPchSeries = GetPchSeries ();
+
+ ///
+ /// Locate ACPI support protocol
+ ///
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+
+ ///
+ /// Locate protocol.
+ /// There is little chance we can't find an FV protocol
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Looking for FV with ACPI storage file
+ ///
+ for (i = 0; i < NumberOfHandles; i++) {
+ ///
+ /// Get the protocol on this handle
+ /// This should not fail because of LocateHandleBuffer
+ ///
+ Status = gBS->HandleProtocol (
+ HandleBuffer[i],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// See if it has the ACPI storage file
+ ///
+ Size = 0;
+ FvStatus = 0;
+ Status = FwVol->ReadFile (
+ FwVol,
+ &gSaAcpiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ ///
+ /// If we found it, then we are done
+ ///
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+ ///
+ /// Our exit status is determined by the success of the previous operations
+ /// If the protocol was found, Instance already points to it.
+ ///
+ ///
+ /// Free any allocated buffers
+ ///
+ FreePool (HandleBuffer);
+
+ ///
+ /// Sanity check that we found our data file
+ ///
+ ASSERT (FwVol);
+ if (FwVol == NULL) {
+ return;
+ }
+ ///
+ /// By default, a table belongs in all ACPI table versions published.
+ ///
+ Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
+
+ ///
+ /// Read tables from the storage file.
+ ///
+ Instance = 0;
+ CurrentTable = NULL;
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &gSaAcpiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Check the Signature ID to modify the table
+ ///
+ switch (((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Signature) {
+
+ case EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE:
+ VtdAcpiTable = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
+ DmarTableUpdate (VtdAcpiTable, &Version);
+ break;
+
+ default:
+ break;
+ }
+ ///
+ /// Increment the instance
+ ///
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+ ///
+ /// Update the VTD table in the ACPI tables.
+ ///
+ AcpiTableHandle = 0;
+ if (VtdAcpiTable != NULL) {
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ VtdAcpiTable,
+ VtdAcpiTable->Length,
+ &AcpiTableHandle
+ );
+ FreePool (VtdAcpiTable);
+ }
+}
+
+/**
+ Locate the VT-d ACPI tables data file and read ACPI SSDT tables.
+ Publish the appropriate SSDT based on current configuration and capabilities.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+
+ @retval EFI_SUCCESS - Vtd initialization complete
+ @exception EFI_UNSUPPORTED - Vtd is not enabled by policy
+**/
+EFI_STATUS
+VtdInit (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ UINTN McD0BaseAddress;
+
+ mInterruptRemappingSupport = FALSE;
+ SaConfigHob = NULL;
+ SaConfigHob = GetFirstGuidHob (&gSaConfigHobGuid);
+ if (SaConfigHob != NULL) {
+ mInterruptRemappingSupport = SaConfigHob->VtdData.InterruptRemappingSupport;
+ }
+
+ McD0BaseAddress = MmPciBase (SA_MC_BUS, 0, 0);
+ mSaPolicy = SaPolicy;
+
+ if (((SaConfigHob != NULL) && (SaConfigHob->VtdData.VtdDisable)) || (MmioRead32 (McD0BaseAddress + R_SA_MC_CAPID0_A_OFFSET) & BIT23)) {
+ DEBUG ((DEBUG_WARN, "VTd disabled or no capability!\n"));
+ return EFI_UNSUPPORTED;
+ }
+ ///
+ /// Check SA supports VTD and VTD is enabled in setup menu
+ ///
+ DEBUG ((DEBUG_INFO, "VTd enabled\n"));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.h new file mode 100644 index 0000000000..fc84a7c41e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.h @@ -0,0 +1,61 @@ +/** @file
+ This code provides a initialization of intel VT-d (Virtualization Technology for Directed I/O).
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _VT_D_H_
+#define _VT_D_H_
+
+///
+/// Include files
+///
+#include <DmaRemappingTable.h>
+#include <SaAccess.h>
+#include <PchAccess.h>
+#include <Uefi.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Protocol/AcpiTable.h>
+#include <Library/MmPciLib.h>
+#include <Protocol/SaPolicy.h>
+#include <SiConfigHob.h>
+#include <PchConfigHob.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+
+
+#define VTD_ECAP_REG 0x10
+#define IR BIT3
+
+#define KBL_OEM_TABLE_ID 0x204C424B ///< "KBL "
+#define SKL_OEM_TABLE_ID 0x204C4B53 ///< "SKL "
+
+/**
+ Locate the VT-d ACPI tables data file and read ACPI SSDT tables.
+ Publish the appropriate SSDT based on current configuration and capabilities.
+
+ @param[in] SaPolicy SA DXE Policy protocol
+
+ @retval EFI_SUCCESS - Vtd initialization complete
+ @retval Other - No Vtd function initiated
+**/
+EFI_STATUS
+VtdInit (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+/**
+ EndOfDxe routine for update DMAR
+**/
+VOID
+UpdateDmarEndOfDxe (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccess.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccess.inf new file mode 100644 index 0000000000..150716529c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccess.inf @@ -0,0 +1,55 @@ +## @file
+# Component description file for the SmmAccess module
+#
+# {1323C7F8-DAD5-4126-A54B-7A05FBF4151}
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SmmAccess
+FILE_GUID = 1323C7F8-DAD5-4126-A54B-7A05FBF41515
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+ENTRY_POINT = SmmAccessDriverEntryPoint
+
+
+[LibraryClasses]
+UefiDriverEntryPoint
+BaseLib
+BaseMemoryLib
+DebugLib
+HobLib
+
+[Packages]
+MdePkg/MdePkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+SmmAccessDriver.h
+SmmAccessDriver.c
+
+
+[Protocols]
+gEfiPciRootBridgeIoProtocolGuid ## CONSUMES
+gEfiSmmAccess2ProtocolGuid ## PRODUCES
+
+
+[Guids]
+gEfiSmmPeiSmramMemoryReserveGuid
+
+
+[Depex]
+gEfiPciRootBridgeIoProtocolGuid
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.c b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.c new file mode 100644 index 0000000000..3e8fd96484 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.c @@ -0,0 +1,434 @@ +/** @file
+ This is the driver that publishes the SMM Access Protocol
+ instance for System Agent.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "SmmAccessDriver.h"
+
+static SMM_ACCESS_PRIVATE_DATA mSmmAccess;
+
+
+/**
+ This is the standard EFI driver point that
+ installs an SMM Access Protocol
+
+ @param[in] ImageHandle - Handle for the image of this driver
+ @param[in] SystemTable - Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS - Protocol was installed successfully
+ @exception EFI_UNSUPPORTED - Protocol was not installed
+ @retval EFI_NOT_FOUND - Protocol can't be found.
+ @retval EFI_OUT_OF_RESOURCES - Protocol does not have enough resources to initialize the driver.
+**/
+EFI_STATUS
+EFIAPI
+SmmAccessDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ UINTN Index;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;
+ EFI_PEI_HOB_POINTERS *Hob;
+
+ ///
+ /// --cr-- INITIALIZE_SCRIPT (ImageHandle, SystemTable);
+ ///
+ /// Initialize Global variables
+ ///
+ ZeroMem (&mSmmAccess, sizeof (mSmmAccess));
+
+ Status = gBS->LocateProtocol (
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ (VOID **) &PciRootBridgeIo
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Could not locate PCI Root Bridge IO Protocol\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ mSmmAccess.Signature = SMM_ACCESS_PRIVATE_DATA_SIGNATURE;
+ mSmmAccess.Handle = NULL;
+ mSmmAccess.PciRootBridgeIo = PciRootBridgeIo;
+
+ ///
+ /// Get Hob list
+ ///
+ Hob = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);
+ if (Hob == NULL) {
+ DEBUG ((DEBUG_ERROR, "SmramMemoryReserve HOB not found\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ DescriptorBlock = (VOID *) ((UINT8 *) Hob + sizeof (EFI_HOB_GUID_TYPE));
+
+ ///
+ /// Alloc space for mSmmAccess.SmramDesc
+ ///
+ mSmmAccess.SmramDesc = AllocateZeroPool ((DescriptorBlock->NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));
+ if (mSmmAccess.SmramDesc == NULL) {
+ DEBUG ((DEBUG_ERROR, "Alloc mSmmAccess.SmramDesc fail.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DEBUG ((DEBUG_INFO, "Alloc mSmmAccess.SmramDesc success.\n"));
+
+ ///
+ /// Use the HOB to publish SMRAM capabilities
+ ///
+ for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ mSmmAccess.SmramDesc[Index].PhysicalStart = DescriptorBlock->Descriptor[Index].PhysicalStart;
+ mSmmAccess.SmramDesc[Index].CpuStart = DescriptorBlock->Descriptor[Index].CpuStart;
+ mSmmAccess.SmramDesc[Index].PhysicalSize = DescriptorBlock->Descriptor[Index].PhysicalSize;
+ mSmmAccess.SmramDesc[Index].RegionState = DescriptorBlock->Descriptor[Index].RegionState;
+ }
+
+ mSmmAccess.NumberRegions = Index;
+ mSmmAccess.SmmAccess.Open = Open;
+ mSmmAccess.SmmAccess.Close = Close;
+ mSmmAccess.SmmAccess.Lock = Lock;
+ mSmmAccess.SmmAccess.GetCapabilities = GetCapabilities;
+ mSmmAccess.SmmAccess.LockState = FALSE;
+ mSmmAccess.SmmAccess.OpenState = FALSE;
+
+ ///
+ /// Install our protocol interfaces on the device's handle
+ ///
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mSmmAccess.Handle,
+ &gEfiSmmAccess2ProtocolGuid,
+ &mSmmAccess.SmmAccess,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "InstallMultipleProtocolInterfaces returned %r\n", Status));
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine accepts a request to "open" a region of SMRAM. The
+ region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+ The use of "open" means that the memory is visible from all boot-service
+ and SMM agents.
+
+ @param[in] This - Pointer to the SMM Access Interface.
+
+ @retval EFI_SUCCESS - The region was successfully opened.
+ @retval EFI_DEVICE_ERROR - The region could not be opened because locked by
+ chipset.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+ IN EFI_SMM_ACCESS2_PROTOCOL *This
+ )
+{
+ EFI_STATUS Status;
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINT64 Address;
+ UINT8 SmramControl;
+ UINTN DescriptorIndex;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+ for (DescriptorIndex = 0; DescriptorIndex < SmmAccess->NumberRegions; DescriptorIndex++) {
+ if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ }
+
+ ///
+ /// BEGIN CHIPSET SPECIFIC CODE
+ ///
+ ///
+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+ ///
+ Address = EFI_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+
+ Status = SmmAccess->PciRootBridgeIo->Pci.Read (
+ SmmAccess->PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &SmramControl
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SmmAccess->PciRootBridgeIo->Pci.Read returned %r\n", Status));
+ return Status;
+ }
+ ///
+ /// Is SMRAM locked?
+ ///
+ for (DescriptorIndex = 0; DescriptorIndex < SmmAccess->NumberRegions; DescriptorIndex++) {
+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+ ///
+ /// Cannot Open a locked region
+ ///
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ }
+ ///
+ /// Open SMRAM region
+ ///
+ SmramControl |= B_SA_SMRAMC_D_OPEN_MASK;
+ SmramControl &= ~(B_SA_SMRAMC_D_CLS_MASK);
+
+ Status = SmmAccess->PciRootBridgeIo->Pci.Write (
+ SmmAccess->PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &SmramControl
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SmmAccess->PciRootBridgeIo->Pci.Write returned %r\n", Status));
+ return Status;
+ }
+ ///
+ /// END CHIPSET SPECIFIC CODE
+ ///
+ for (DescriptorIndex = 0; DescriptorIndex < SmmAccess->NumberRegions; DescriptorIndex++) {
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;
+ }
+ SmmAccess->SmmAccess.OpenState = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine accepts a request to "close" a region of SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "close" means that the memory is only visible from SMM agents,
+ not from BS or RT code.
+
+ @param[in] This - Pointer to the SMM Access Interface.
+
+ @retval EFI_SUCCESS - The region was successfully closed.
+ @retval EFI_DEVICE_ERROR - The region could not be closed because locked by chipset.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+ IN EFI_SMM_ACCESS2_PROTOCOL *This
+ )
+{
+ EFI_STATUS Status;
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINT64 Address;
+ BOOLEAN OpenState;
+ UINT8 Index;
+ UINT8 SmramControl;
+ UINTN DescriptorIndex;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+ for (DescriptorIndex = 0; DescriptorIndex < SmmAccess->NumberRegions; DescriptorIndex++) {
+ if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));
+ continue;
+ }
+
+ ///
+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+ ///
+ Address = EFI_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+
+ Status = SmmAccess->PciRootBridgeIo->Pci.Read (
+ SmmAccess->PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &SmramControl
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SmmAccess->PciRootBridgeIo->Pci.Read returned %r\n", Status));
+ return Status;
+ }
+ ///
+ /// Is SMRAM locked?
+ ///
+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+ ///
+ /// Cannot Close a locked region
+ ///
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// Close SMRAM region
+ ///
+ SmramControl &= ~(B_SA_SMRAMC_D_OPEN_MASK);
+
+ Status = SmmAccess->PciRootBridgeIo->Pci.Write (
+ SmmAccess->PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &SmramControl
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SmmAccess->PciRootBridgeIo->Pci.Write returned %r\n", Status));
+ return Status;
+ }
+ ///
+ /// END CHIPSET SPECIFIC CODE
+ ///
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~EFI_SMRAM_OPEN;
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) (EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+ }
+
+ ///
+ /// Find out if any regions are still open
+ ///
+ OpenState = FALSE;
+ for (Index = 0; Index < mSmmAccess.NumberRegions; Index++) {
+ if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) == EFI_SMRAM_OPEN) {
+ OpenState = TRUE;
+ }
+ }
+
+ SmmAccess->SmmAccess.OpenState = OpenState;
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine accepts a request to "lock" SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "lock" means that the memory can no longer be opened
+ to BS state..
+
+ @param[in] This - Pointer to the SMM Access Interface.
+
+ @retval EFI_SUCCESS - The region was successfully locked.
+ @retval EFI_DEVICE_ERROR - The region could not be locked because at least
+ one range is still open.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+ IN EFI_SMM_ACCESS2_PROTOCOL *This
+ )
+{
+ EFI_STATUS Status;
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINT64 Address;
+ UINT8 SmramControl;
+ UINTN DescriptorIndex;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+ if (SmmAccess->SmmAccess.OpenState) {
+ DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ for (DescriptorIndex = 0; DescriptorIndex < SmmAccess->NumberRegions; DescriptorIndex++) {
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= EFI_SMRAM_LOCKED;
+ }
+ SmmAccess->SmmAccess.LockState = TRUE;
+
+ ///
+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+ ///
+ Address = EFI_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+
+ Status = SmmAccess->PciRootBridgeIo->Pci.Read (
+ SmmAccess->PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &SmramControl
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SmmAccess->PciRootBridgeIo->Pci.Read returned %r\n", Status));
+ return Status;
+ }
+ ///
+ /// Lock the SMRAM
+ ///
+ SmramControl |= B_SA_SMRAMC_D_LCK_MASK;
+
+ Status = SmmAccess->PciRootBridgeIo->Pci.Write (
+ SmmAccess->PciRootBridgeIo,
+ EfiPciWidthUint8,
+ Address,
+ 1,
+ &SmramControl
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "SmmAccess->PciRootBridgeIo->Pci.Write returned %r\n", Status));
+ return Status;
+ }
+ ///
+ /// END CHIPSET SPECIFIC CODE
+ ///
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine services a user request to discover the SMRAM
+ capabilities of this platform. This will report the possible
+ ranges that are possible for SMRAM access, based upon the
+ memory controller capabilities.
+
+ @param[in] This - Pointer to the SMRAM Access Interface.
+ @param[in] SmramMapSize - Pointer to the variable containing size of the
+ buffer to contain the description information.
+ @param[in] SmramMap - Buffer containing the data describing the Smram
+ region descriptors.
+
+ @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.
+ @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+ IN CONST EFI_SMM_ACCESS2_PROTOCOL *This,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ )
+{
+ EFI_STATUS Status;
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINTN NecessaryBufferSize;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+
+ NecessaryBufferSize = SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);
+
+ if (*SmramMapSize < NecessaryBufferSize) {
+ DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n"));
+ Status = EFI_BUFFER_TOO_SMALL;
+ } else {
+ CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);
+ Status = EFI_SUCCESS;
+ }
+
+ *SmramMapSize = NecessaryBufferSize;
+
+ return Status;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.h b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.h new file mode 100644 index 0000000000..69e9e89b24 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriver.h @@ -0,0 +1,171 @@ +/** @file
+ Header file for SMM Access Driver.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SMM_ACCESS_DRIVER_H_
+#define _SMM_ACCESS_DRIVER_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#include <Guid/SmramMemoryReserve.h>
+#include <Protocol/SmmAccess2.h>
+#include <IndustryStandard/Pci22.h>
+#include <SaAccess.h>
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// Private data
+///
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ EFI_SMM_ACCESS2_PROTOCOL SmmAccess;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+
+ ///
+ /// Local Data for SMM Access interface goes here
+ ///
+ UINTN NumberRegions;
+ EFI_SMRAM_DESCRIPTOR *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+ CR (a, \
+ SMM_ACCESS_PRIVATE_DATA, \
+ SmmAccess, \
+ SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+ )
+
+//
+// Prototypes
+// Driver model protocol interface
+//
+/**
+ <b>SMM Access Driver Entry Point</b>
+ This driver installs an SMM Access Protocol
+ - <b>Introduction</b> \n
+ This module publishes the SMM access protocol. The protocol is used by the SMM Base driver to access the SMRAM region when the processor is not in SMM.
+ The SMM Base driver uses the services provided by the SMM access protocol to open SMRAM during post and copy the SMM handler.
+ SMM access protocol is also used to close the SMRAM region once the copying is done.
+ Finally, the SMM access protocol provides services to "Lock" the SMRAM region.
+ Please refer the SMM Protocols section in the attached SMM CIS Specification version 0.9 for further details.
+ This driver is required if SMM is supported. Proper configuration of SMM registers is recommended even if SMM is not supported.
+
+ - @pre
+ - _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL: Documented in the Unified Extensible Firmware Interface Specification, version 2.0, available at the URL: http://www.uefi.org/specs/
+
+ - @result
+ Publishes the _EFI_SMM_ACCESS_PROTOCOL: Documented in the System Management Mode Core Interface Specification, available at the URL: http://www.intel.com/technology/framework/spec.htm
+
+ - <b>Porting Recommendations</b> \n
+ No modification of this module is recommended. Any modification should be done in compliance with the _EFI_SMM_ACCESS_PROTOCOL protocol definition.
+
+ @param[in] ImageHandle - Handle for the image of this driver
+ @param[in] SystemTable - Pointer to the EFI System Table
+
+ @retval EFI_SUCCESS - Protocol was installed successfully
+ @exception EFI_UNSUPPORTED - Protocol was not installed
+**/
+EFI_STATUS
+EFIAPI
+SmmAccessDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ This routine accepts a request to "open" a region of SMRAM. The
+ region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+ The use of "open" means that the memory is visible from all boot-service
+ and SMM agents.
+
+ @param[in] This - Pointer to the SMM Access Interface.
+
+ @retval EFI_SUCCESS - The region was successfully opened.
+ @retval EFI_DEVICE_ERROR - The region could not be opened because locked by
+ chipset.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+ IN EFI_SMM_ACCESS2_PROTOCOL *This
+ );
+
+/**
+ This routine accepts a request to "close" a region of SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "close" means that the memory is only visible from SMM agents,
+ not from BS or RT code.
+
+ @param[in] This - Pointer to the SMM Access Interface.
+
+ @retval EFI_SUCCESS - The region was successfully closed.
+ @retval EFI_DEVICE_ERROR - The region could not be closed because locked by
+ chipset.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+ IN EFI_SMM_ACCESS2_PROTOCOL *This
+ );
+
+/**
+ This routine accepts a request to "lock" SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "lock" means that the memory can no longer be opened
+ to BS state..
+
+ @param[in] This - Pointer to the SMM Access Interface.
+
+ @retval EFI_SUCCESS - The region was successfully locked.
+ @retval EFI_DEVICE_ERROR - The region could not be locked because at least
+ one range is still open.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+ IN EFI_SMM_ACCESS2_PROTOCOL *This
+ );
+
+/**
+ This routine services a user request to discover the SMRAM
+ capabilities of this platform. This will report the possible
+ ranges that are possible for SMRAM access, based upon the
+ memory controller capabilities.
+
+ @param[in] This - Pointer to the SMRAM Access Interface.
+ @param[in] SmramMapSize - Pointer to the variable containing size of the
+ buffer to contain the description information.
+ @param[in] SmramMap - Buffer containing the data describing the Smram
+ region descriptors.
+
+ @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.
+ @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+ IN CONST EFI_SMM_ACCESS2_PROTOCOL *This,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ );
+#endif
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