diff options
Diffstat (limited to 'Silicon/Intel/LewisburgPkg')
143 files changed, 31264 insertions, 0 deletions
diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/GpioDefine.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/GpioDefine.asl new file mode 100644 index 0000000000..39c3a8688d --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/GpioDefine.asl @@ -0,0 +1,790 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Definition for GPIO groups and pads +// +#ifndef GPIO_DEFINE_ASL +#define GPIO_DEFINE_ASL + +#include "GpioPinsSklLp.h" +#include "GpioPinsSklH.h" +#include "Register/PchRegsGpio.h" + +// +// SKL-PCH GPIO Community address +// +#define PCH_GPIO_COM0 0x00af0000 // PID_GPIOCOM0 = 0xAF +#define PCH_GPIO_COM1 0x00ae0000 // PID_GPIOCOM1 = 0xAE +#define PCH_GPIO_COM2 0x00ad0000 // PID_GPIOCOM2 = 0xAD +#define PCH_GPIO_COM3 0x00ac0000 // PID_GPIOCOM3 = 0xAC + +// +// SKL-PCH-LP GPIO pin list for driver usage +// +#define GPIO_SKL_LP_DRIVER_GPP_A_00 0 +#define GPIO_SKL_LP_DRIVER_GPP_A_01 1 +#define GPIO_SKL_LP_DRIVER_GPP_A_02 2 +#define GPIO_SKL_LP_DRIVER_GPP_A_03 3 +#define GPIO_SKL_LP_DRIVER_GPP_A_04 4 +#define GPIO_SKL_LP_DRIVER_GPP_A_05 5 +#define GPIO_SKL_LP_DRIVER_GPP_A_06 6 +#define GPIO_SKL_LP_DRIVER_GPP_A_07 7 +#define GPIO_SKL_LP_DRIVER_GPP_A_08 8 +#define GPIO_SKL_LP_DRIVER_GPP_A_09 9 +#define GPIO_SKL_LP_DRIVER_GPP_A_10 10 +#define GPIO_SKL_LP_DRIVER_GPP_A_11 11 +#define GPIO_SKL_LP_DRIVER_GPP_A_12 12 +#define GPIO_SKL_LP_DRIVER_GPP_A_13 13 +#define GPIO_SKL_LP_DRIVER_GPP_A_14 14 +#define GPIO_SKL_LP_DRIVER_GPP_A_15 15 +#define GPIO_SKL_LP_DRIVER_GPP_A_16 16 +#define GPIO_SKL_LP_DRIVER_GPP_A_17 17 +#define GPIO_SKL_LP_DRIVER_GPP_A_18 18 +#define GPIO_SKL_LP_DRIVER_GPP_A_19 19 +#define GPIO_SKL_LP_DRIVER_GPP_A_20 20 +#define GPIO_SKL_LP_DRIVER_GPP_A_21 21 +#define GPIO_SKL_LP_DRIVER_GPP_A_22 22 +#define GPIO_SKL_LP_DRIVER_GPP_A_23 23 + +#define GPIO_SKL_LP_DRIVER_GPP_B_00 24 +#define GPIO_SKL_LP_DRIVER_GPP_B_01 25 +#define GPIO_SKL_LP_DRIVER_GPP_B_02 26 +#define GPIO_SKL_LP_DRIVER_GPP_B_03 27 +#define GPIO_SKL_LP_DRIVER_GPP_B_04 28 +#define GPIO_SKL_LP_DRIVER_GPP_B_05 29 +#define GPIO_SKL_LP_DRIVER_GPP_B_06 30 +#define GPIO_SKL_LP_DRIVER_GPP_B_07 31 +#define GPIO_SKL_LP_DRIVER_GPP_B_08 32 +#define GPIO_SKL_LP_DRIVER_GPP_B_09 33 +#define GPIO_SKL_LP_DRIVER_GPP_B_10 34 +#define GPIO_SKL_LP_DRIVER_GPP_B_11 35 +#define GPIO_SKL_LP_DRIVER_GPP_B_12 36 +#define GPIO_SKL_LP_DRIVER_GPP_B_13 37 +#define GPIO_SKL_LP_DRIVER_GPP_B_14 38 +#define GPIO_SKL_LP_DRIVER_GPP_B_15 39 +#define GPIO_SKL_LP_DRIVER_GPP_B_16 40 +#define GPIO_SKL_LP_DRIVER_GPP_B_17 41 +#define GPIO_SKL_LP_DRIVER_GPP_B_18 42 +#define GPIO_SKL_LP_DRIVER_GPP_B_19 43 +#define GPIO_SKL_LP_DRIVER_GPP_B_20 44 +#define GPIO_SKL_LP_DRIVER_GPP_B_21 45 +#define GPIO_SKL_LP_DRIVER_GPP_B_22 46 +#define GPIO_SKL_LP_DRIVER_GPP_B_23 47 + +#define GPIO_SKL_LP_DRIVER_GPP_C_00 48 +#define GPIO_SKL_LP_DRIVER_GPP_C_01 49 +#define GPIO_SKL_LP_DRIVER_GPP_C_02 50 +#define GPIO_SKL_LP_DRIVER_GPP_C_03 51 +#define GPIO_SKL_LP_DRIVER_GPP_C_04 52 +#define GPIO_SKL_LP_DRIVER_GPP_C_05 53 +#define GPIO_SKL_LP_DRIVER_GPP_C_06 54 +#define GPIO_SKL_LP_DRIVER_GPP_C_07 55 +#define GPIO_SKL_LP_DRIVER_GPP_C_08 56 +#define GPIO_SKL_LP_DRIVER_GPP_C_09 57 +#define GPIO_SKL_LP_DRIVER_GPP_C_10 58 +#define GPIO_SKL_LP_DRIVER_GPP_C_11 59 +#define GPIO_SKL_LP_DRIVER_GPP_C_12 60 +#define GPIO_SKL_LP_DRIVER_GPP_C_13 61 +#define GPIO_SKL_LP_DRIVER_GPP_C_14 62 +#define GPIO_SKL_LP_DRIVER_GPP_C_15 63 +#define GPIO_SKL_LP_DRIVER_GPP_C_16 64 +#define GPIO_SKL_LP_DRIVER_GPP_C_17 65 +#define GPIO_SKL_LP_DRIVER_GPP_C_18 66 +#define GPIO_SKL_LP_DRIVER_GPP_C_19 67 +#define GPIO_SKL_LP_DRIVER_GPP_C_20 68 +#define GPIO_SKL_LP_DRIVER_GPP_C_21 69 +#define GPIO_SKL_LP_DRIVER_GPP_C_22 70 +#define GPIO_SKL_LP_DRIVER_GPP_C_23 71 + +#define GPIO_SKL_LP_DRIVER_GPP_D_00 72 +#define GPIO_SKL_LP_DRIVER_GPP_D_01 73 +#define GPIO_SKL_LP_DRIVER_GPP_D_02 74 +#define GPIO_SKL_LP_DRIVER_GPP_D_03 75 +#define GPIO_SKL_LP_DRIVER_GPP_D_04 76 +#define GPIO_SKL_LP_DRIVER_GPP_D_05 77 +#define GPIO_SKL_LP_DRIVER_GPP_D_06 78 +#define GPIO_SKL_LP_DRIVER_GPP_D_07 79 +#define GPIO_SKL_LP_DRIVER_GPP_D_08 80 +#define GPIO_SKL_LP_DRIVER_GPP_D_09 81 +#define GPIO_SKL_LP_DRIVER_GPP_D_10 82 +#define GPIO_SKL_LP_DRIVER_GPP_D_11 83 +#define GPIO_SKL_LP_DRIVER_GPP_D_12 84 +#define GPIO_SKL_LP_DRIVER_GPP_D_13 85 +#define GPIO_SKL_LP_DRIVER_GPP_D_14 86 +#define GPIO_SKL_LP_DRIVER_GPP_D_15 87 +#define GPIO_SKL_LP_DRIVER_GPP_D_16 88 +#define GPIO_SKL_LP_DRIVER_GPP_D_17 89 +#define GPIO_SKL_LP_DRIVER_GPP_D_18 90 +#define GPIO_SKL_LP_DRIVER_GPP_D_19 91 +#define GPIO_SKL_LP_DRIVER_GPP_D_20 92 +#define GPIO_SKL_LP_DRIVER_GPP_D_21 93 +#define GPIO_SKL_LP_DRIVER_GPP_D_22 94 +#define GPIO_SKL_LP_DRIVER_GPP_D_23 95 + +#define GPIO_SKL_LP_DRIVER_GPP_E_00 96 +#define GPIO_SKL_LP_DRIVER_GPP_E_01 97 +#define GPIO_SKL_LP_DRIVER_GPP_E_02 98 +#define GPIO_SKL_LP_DRIVER_GPP_E_03 99 +#define GPIO_SKL_LP_DRIVER_GPP_E_04 100 +#define GPIO_SKL_LP_DRIVER_GPP_E_05 101 +#define GPIO_SKL_LP_DRIVER_GPP_E_06 102 +#define GPIO_SKL_LP_DRIVER_GPP_E_07 103 +#define GPIO_SKL_LP_DRIVER_GPP_E_08 104 +#define GPIO_SKL_LP_DRIVER_GPP_E_09 105 +#define GPIO_SKL_LP_DRIVER_GPP_E_10 106 +#define GPIO_SKL_LP_DRIVER_GPP_E_11 107 +#define GPIO_SKL_LP_DRIVER_GPP_E_12 108 +#define GPIO_SKL_LP_DRIVER_GPP_E_13 109 +#define GPIO_SKL_LP_DRIVER_GPP_E_14 110 +#define GPIO_SKL_LP_DRIVER_GPP_E_15 111 +#define GPIO_SKL_LP_DRIVER_GPP_E_16 112 +#define GPIO_SKL_LP_DRIVER_GPP_E_17 113 +#define GPIO_SKL_LP_DRIVER_GPP_E_18 114 +#define GPIO_SKL_LP_DRIVER_GPP_E_19 115 +#define GPIO_SKL_LP_DRIVER_GPP_E_20 116 +#define GPIO_SKL_LP_DRIVER_GPP_E_21 117 +#define GPIO_SKL_LP_DRIVER_GPP_E_22 118 +#define GPIO_SKL_LP_DRIVER_GPP_E_23 119 + +#define GPIO_SKL_LP_DRIVER_GPP_F_00 120 +#define GPIO_SKL_LP_DRIVER_GPP_F_01 121 +#define GPIO_SKL_LP_DRIVER_GPP_F_02 122 +#define GPIO_SKL_LP_DRIVER_GPP_F_03 123 +#define GPIO_SKL_LP_DRIVER_GPP_F_04 124 +#define GPIO_SKL_LP_DRIVER_GPP_F_05 125 +#define GPIO_SKL_LP_DRIVER_GPP_F_06 126 +#define GPIO_SKL_LP_DRIVER_GPP_F_07 127 +#define GPIO_SKL_LP_DRIVER_GPP_F_08 128 +#define GPIO_SKL_LP_DRIVER_GPP_F_09 129 +#define GPIO_SKL_LP_DRIVER_GPP_F_10 130 +#define GPIO_SKL_LP_DRIVER_GPP_F_11 131 +#define GPIO_SKL_LP_DRIVER_GPP_F_12 132 +#define GPIO_SKL_LP_DRIVER_GPP_F_13 133 +#define GPIO_SKL_LP_DRIVER_GPP_F_14 134 +#define GPIO_SKL_LP_DRIVER_GPP_F_15 135 +#define GPIO_SKL_LP_DRIVER_GPP_F_16 136 +#define GPIO_SKL_LP_DRIVER_GPP_F_17 137 +#define GPIO_SKL_LP_DRIVER_GPP_F_18 138 +#define GPIO_SKL_LP_DRIVER_GPP_F_19 139 +#define GPIO_SKL_LP_DRIVER_GPP_F_20 140 +#define GPIO_SKL_LP_DRIVER_GPP_F_21 141 +#define GPIO_SKL_LP_DRIVER_GPP_F_22 142 +#define GPIO_SKL_LP_DRIVER_GPP_F_23 143 + +#define GPIO_SKL_LP_DRIVER_GPP_G_00 144 +#define GPIO_SKL_LP_DRIVER_GPP_G_01 145 +#define GPIO_SKL_LP_DRIVER_GPP_G_02 146 +#define GPIO_SKL_LP_DRIVER_GPP_G_03 147 +#define GPIO_SKL_LP_DRIVER_GPP_G_04 148 +#define GPIO_SKL_LP_DRIVER_GPP_G_05 149 +#define GPIO_SKL_LP_DRIVER_GPP_G_06 150 +#define GPIO_SKL_LP_DRIVER_GPP_G_07 151 + +// +// SPT H GPIO pin list for driver usage +// +#define GPIO_SKL_H_DRIVER_GPP_A_00 0 +#define GPIO_SKL_H_DRIVER_GPP_A_01 1 +#define GPIO_SKL_H_DRIVER_GPP_A_02 2 +#define GPIO_SKL_H_DRIVER_GPP_A_03 3 +#define GPIO_SKL_H_DRIVER_GPP_A_04 4 +#define GPIO_SKL_H_DRIVER_GPP_A_05 5 +#define GPIO_SKL_H_DRIVER_GPP_A_06 6 +#define GPIO_SKL_H_DRIVER_GPP_A_07 7 +#define GPIO_SKL_H_DRIVER_GPP_A_08 8 +#define GPIO_SKL_H_DRIVER_GPP_A_09 9 +#define GPIO_SKL_H_DRIVER_GPP_A_10 10 +#define GPIO_SKL_H_DRIVER_GPP_A_11 11 +#define GPIO_SKL_H_DRIVER_GPP_A_12 12 +#define GPIO_SKL_H_DRIVER_GPP_A_13 13 +#define GPIO_SKL_H_DRIVER_GPP_A_14 14 +#define GPIO_SKL_H_DRIVER_GPP_A_15 15 +#define GPIO_SKL_H_DRIVER_GPP_A_16 16 +#define GPIO_SKL_H_DRIVER_GPP_A_17 17 +#define GPIO_SKL_H_DRIVER_GPP_A_18 18 +#define GPIO_SKL_H_DRIVER_GPP_A_19 19 +#define GPIO_SKL_H_DRIVER_GPP_A_20 20 +#define GPIO_SKL_H_DRIVER_GPP_A_21 21 +#define GPIO_SKL_H_DRIVER_GPP_A_22 22 +#define GPIO_SKL_H_DRIVER_GPP_A_23 23 + +#define GPIO_SKL_H_DRIVER_GPP_B_00 24 +#define GPIO_SKL_H_DRIVER_GPP_B_01 25 +#define GPIO_SKL_H_DRIVER_GPP_B_02 26 +#define GPIO_SKL_H_DRIVER_GPP_B_03 27 +#define GPIO_SKL_H_DRIVER_GPP_B_04 28 +#define GPIO_SKL_H_DRIVER_GPP_B_05 29 +#define GPIO_SKL_H_DRIVER_GPP_B_06 30 +#define GPIO_SKL_H_DRIVER_GPP_B_07 31 +#define GPIO_SKL_H_DRIVER_GPP_B_08 32 +#define GPIO_SKL_H_DRIVER_GPP_B_09 33 +#define GPIO_SKL_H_DRIVER_GPP_B_10 34 +#define GPIO_SKL_H_DRIVER_GPP_B_11 35 +#define GPIO_SKL_H_DRIVER_GPP_B_12 36 +#define GPIO_SKL_H_DRIVER_GPP_B_13 37 +#define GPIO_SKL_H_DRIVER_GPP_B_14 38 +#define GPIO_SKL_H_DRIVER_GPP_B_15 39 +#define GPIO_SKL_H_DRIVER_GPP_B_16 40 +#define GPIO_SKL_H_DRIVER_GPP_B_17 41 +#define GPIO_SKL_H_DRIVER_GPP_B_18 42 +#define GPIO_SKL_H_DRIVER_GPP_B_19 43 +#define GPIO_SKL_H_DRIVER_GPP_B_20 44 +#define GPIO_SKL_H_DRIVER_GPP_B_21 45 +#define GPIO_SKL_H_DRIVER_GPP_B_22 46 +#define GPIO_SKL_H_DRIVER_GPP_B_23 47 + +#define GPIO_SKL_H_DRIVER_GPP_C_00 48 +#define GPIO_SKL_H_DRIVER_GPP_C_01 49 +#define GPIO_SKL_H_DRIVER_GPP_C_02 50 +#define GPIO_SKL_H_DRIVER_GPP_C_03 51 +#define GPIO_SKL_H_DRIVER_GPP_C_04 52 +#define GPIO_SKL_H_DRIVER_GPP_C_05 53 +#define GPIO_SKL_H_DRIVER_GPP_C_06 54 +#define GPIO_SKL_H_DRIVER_GPP_C_07 55 +#define GPIO_SKL_H_DRIVER_GPP_C_08 56 +#define GPIO_SKL_H_DRIVER_GPP_C_09 57 +#define GPIO_SKL_H_DRIVER_GPP_C_10 58 +#define GPIO_SKL_H_DRIVER_GPP_C_11 59 +#define GPIO_SKL_H_DRIVER_GPP_C_12 60 +#define GPIO_SKL_H_DRIVER_GPP_C_13 61 +#define GPIO_SKL_H_DRIVER_GPP_C_14 62 +#define GPIO_SKL_H_DRIVER_GPP_C_15 63 +#define GPIO_SKL_H_DRIVER_GPP_C_16 64 +#define GPIO_SKL_H_DRIVER_GPP_C_17 65 +#define GPIO_SKL_H_DRIVER_GPP_C_18 66 +#define GPIO_SKL_H_DRIVER_GPP_C_19 67 +#define GPIO_SKL_H_DRIVER_GPP_C_20 68 +#define GPIO_SKL_H_DRIVER_GPP_C_21 69 +#define GPIO_SKL_H_DRIVER_GPP_C_22 70 +#define GPIO_SKL_H_DRIVER_GPP_C_23 71 + +#define GPIO_SKL_H_DRIVER_GPP_D_00 72 +#define GPIO_SKL_H_DRIVER_GPP_D_01 73 +#define GPIO_SKL_H_DRIVER_GPP_D_02 74 +#define GPIO_SKL_H_DRIVER_GPP_D_03 75 +#define GPIO_SKL_H_DRIVER_GPP_D_04 76 +#define GPIO_SKL_H_DRIVER_GPP_D_05 77 +#define GPIO_SKL_H_DRIVER_GPP_D_06 78 +#define GPIO_SKL_H_DRIVER_GPP_D_07 79 +#define GPIO_SKL_H_DRIVER_GPP_D_08 80 +#define GPIO_SKL_H_DRIVER_GPP_D_09 81 +#define GPIO_SKL_H_DRIVER_GPP_D_10 82 +#define GPIO_SKL_H_DRIVER_GPP_D_11 83 +#define GPIO_SKL_H_DRIVER_GPP_D_12 84 +#define GPIO_SKL_H_DRIVER_GPP_D_13 85 +#define GPIO_SKL_H_DRIVER_GPP_D_14 86 +#define GPIO_SKL_H_DRIVER_GPP_D_15 87 +#define GPIO_SKL_H_DRIVER_GPP_D_16 88 +#define GPIO_SKL_H_DRIVER_GPP_D_17 89 +#define GPIO_SKL_H_DRIVER_GPP_D_18 90 +#define GPIO_SKL_H_DRIVER_GPP_D_19 91 +#define GPIO_SKL_H_DRIVER_GPP_D_20 92 +#define GPIO_SKL_H_DRIVER_GPP_D_21 93 +#define GPIO_SKL_H_DRIVER_GPP_D_22 94 +#define GPIO_SKL_H_DRIVER_GPP_D_23 95 + +#define GPIO_SKL_H_DRIVER_GPP_E_00 96 +#define GPIO_SKL_H_DRIVER_GPP_E_01 97 +#define GPIO_SKL_H_DRIVER_GPP_E_02 98 +#define GPIO_SKL_H_DRIVER_GPP_E_03 99 +#define GPIO_SKL_H_DRIVER_GPP_E_04 100 +#define GPIO_SKL_H_DRIVER_GPP_E_05 101 +#define GPIO_SKL_H_DRIVER_GPP_E_06 102 +#define GPIO_SKL_H_DRIVER_GPP_E_07 103 +#define GPIO_SKL_H_DRIVER_GPP_E_08 104 +#define GPIO_SKL_H_DRIVER_GPP_E_09 105 +#define GPIO_SKL_H_DRIVER_GPP_E_10 106 +#define GPIO_SKL_H_DRIVER_GPP_E_11 107 +#define GPIO_SKL_H_DRIVER_GPP_E_12 108 +#define GPIO_SKL_H_DRIVER_GPP_E_13 109 + +#define GPIO_SKL_H_DRIVER_GPP_F_00 120 +#define GPIO_SKL_H_DRIVER_GPP_F_01 121 +#define GPIO_SKL_H_DRIVER_GPP_F_02 122 +#define GPIO_SKL_H_DRIVER_GPP_F_03 123 +#define GPIO_SKL_H_DRIVER_GPP_F_04 124 +#define GPIO_SKL_H_DRIVER_GPP_F_05 125 +#define GPIO_SKL_H_DRIVER_GPP_F_06 126 +#define GPIO_SKL_H_DRIVER_GPP_F_07 127 +#define GPIO_SKL_H_DRIVER_GPP_F_08 128 +#define GPIO_SKL_H_DRIVER_GPP_F_09 129 +#define GPIO_SKL_H_DRIVER_GPP_F_10 130 +#define GPIO_SKL_H_DRIVER_GPP_F_11 131 +#define GPIO_SKL_H_DRIVER_GPP_F_12 132 +#define GPIO_SKL_H_DRIVER_GPP_F_13 133 +#define GPIO_SKL_H_DRIVER_GPP_F_14 134 +#define GPIO_SKL_H_DRIVER_GPP_F_15 135 +#define GPIO_SKL_H_DRIVER_GPP_F_16 136 +#define GPIO_SKL_H_DRIVER_GPP_F_17 137 +#define GPIO_SKL_H_DRIVER_GPP_F_18 138 +#define GPIO_SKL_H_DRIVER_GPP_F_19 139 +#define GPIO_SKL_H_DRIVER_GPP_F_20 140 +#define GPIO_SKL_H_DRIVER_GPP_F_21 141 +#define GPIO_SKL_H_DRIVER_GPP_F_22 142 +#define GPIO_SKL_H_DRIVER_GPP_F_23 143 + +#define GPIO_SKL_H_DRIVER_GPP_G_00 144 +#define GPIO_SKL_H_DRIVER_GPP_G_01 145 +#define GPIO_SKL_H_DRIVER_GPP_G_02 146 +#define GPIO_SKL_H_DRIVER_GPP_G_03 147 +#define GPIO_SKL_H_DRIVER_GPP_G_04 148 +#define GPIO_SKL_H_DRIVER_GPP_G_05 149 +#define GPIO_SKL_H_DRIVER_GPP_G_06 150 +#define GPIO_SKL_H_DRIVER_GPP_G_07 151 +#define GPIO_SKL_H_DRIVER_GPP_G_08 152 +#define GPIO_SKL_H_DRIVER_GPP_G_09 153 +#define GPIO_SKL_H_DRIVER_GPP_G_10 154 +#define GPIO_SKL_H_DRIVER_GPP_G_11 155 +#define GPIO_SKL_H_DRIVER_GPP_G_12 156 +#define GPIO_SKL_H_DRIVER_GPP_G_13 157 +#define GPIO_SKL_H_DRIVER_GPP_G_14 158 +#define GPIO_SKL_H_DRIVER_GPP_G_15 159 +#define GPIO_SKL_H_DRIVER_GPP_G_16 160 +#define GPIO_SKL_H_DRIVER_GPP_G_17 161 +#define GPIO_SKL_H_DRIVER_GPP_G_18 162 +#define GPIO_SKL_H_DRIVER_GPP_G_19 163 +#define GPIO_SKL_H_DRIVER_GPP_G_20 164 +#define GPIO_SKL_H_DRIVER_GPP_G_21 165 +#define GPIO_SKL_H_DRIVER_GPP_G_22 166 +#define GPIO_SKL_H_DRIVER_GPP_G_23 167 + +#define GPIO_SKL_H_DRIVER_GPP_H_00 168 +#define GPIO_SKL_H_DRIVER_GPP_H_01 169 +#define GPIO_SKL_H_DRIVER_GPP_H_02 170 +#define GPIO_SKL_H_DRIVER_GPP_H_03 171 +#define GPIO_SKL_H_DRIVER_GPP_H_04 172 +#define GPIO_SKL_H_DRIVER_GPP_H_05 173 +#define GPIO_SKL_H_DRIVER_GPP_H_06 174 +#define GPIO_SKL_H_DRIVER_GPP_H_07 175 +#define GPIO_SKL_H_DRIVER_GPP_H_08 176 +#define GPIO_SKL_H_DRIVER_GPP_H_09 177 +#define GPIO_SKL_H_DRIVER_GPP_H_10 178 +#define GPIO_SKL_H_DRIVER_GPP_H_11 179 +#define GPIO_SKL_H_DRIVER_GPP_H_12 180 +#define GPIO_SKL_H_DRIVER_GPP_H_13 181 +#define GPIO_SKL_H_DRIVER_GPP_H_14 182 +#define GPIO_SKL_H_DRIVER_GPP_H_15 183 +#define GPIO_SKL_H_DRIVER_GPP_H_16 184 +#define GPIO_SKL_H_DRIVER_GPP_H_17 185 +#define GPIO_SKL_H_DRIVER_GPP_H_18 186 +#define GPIO_SKL_H_DRIVER_GPP_H_19 187 +#define GPIO_SKL_H_DRIVER_GPP_H_20 188 +#define GPIO_SKL_H_DRIVER_GPP_H_21 189 +#define GPIO_SKL_H_DRIVER_GPP_H_22 190 +#define GPIO_SKL_H_DRIVER_GPP_H_23 191 + +#define PCH_I_GPIO_DRIVER_GPP_I_00 192 +#define PCH_I_GPIO_DRIVER_GPP_I_01 193 +#define PCH_I_GPIO_DRIVER_GPP_I_02 194 +#define PCH_I_GPIO_DRIVER_GPP_I_03 195 +#define PCH_I_GPIO_DRIVER_GPP_I_04 196 +#define PCH_I_GPIO_DRIVER_GPP_I_05 197 +#define PCH_I_GPIO_DRIVER_GPP_I_06 198 +#define PCH_I_GPIO_DRIVER_GPP_I_07 199 +#define PCH_I_GPIO_DRIVER_GPP_I_08 200 +#define PCH_I_GPIO_DRIVER_GPP_I_09 201 +#define PCH_I_GPIO_DRIVER_GPP_I_10 202 + +// +// SPT GPIO IOxAPIC interrupts +// +// SPT-LP: +#define GPIO_SKL_LP_IOAPIC_GPP_A_00 0x18 +#define GPIO_SKL_LP_IOAPIC_GPP_A_01 0x19 +#define GPIO_SKL_LP_IOAPIC_GPP_A_02 0x1a +#define GPIO_SKL_LP_IOAPIC_GPP_A_03 0x1b +#define GPIO_SKL_LP_IOAPIC_GPP_A_04 0x1c +#define GPIO_SKL_LP_IOAPIC_GPP_A_05 0x1d +#define GPIO_SKL_LP_IOAPIC_GPP_A_06 0x1e +#define GPIO_SKL_LP_IOAPIC_GPP_A_07 0x1f +#define GPIO_SKL_LP_IOAPIC_GPP_A_08 0x20 +#define GPIO_SKL_LP_IOAPIC_GPP_A_09 0x21 +#define GPIO_SKL_LP_IOAPIC_GPP_A_10 0x22 +#define GPIO_SKL_LP_IOAPIC_GPP_A_11 0x23 +#define GPIO_SKL_LP_IOAPIC_GPP_A_12 0x24 +#define GPIO_SKL_LP_IOAPIC_GPP_A_13 0x25 +#define GPIO_SKL_LP_IOAPIC_GPP_A_14 0x26 +#define GPIO_SKL_LP_IOAPIC_GPP_A_15 0x27 +#define GPIO_SKL_LP_IOAPIC_GPP_A_16 0x28 +#define GPIO_SKL_LP_IOAPIC_GPP_A_17 0x29 +#define GPIO_SKL_LP_IOAPIC_GPP_A_18 0x2a +#define GPIO_SKL_LP_IOAPIC_GPP_A_19 0x2b +#define GPIO_SKL_LP_IOAPIC_GPP_A_20 0x2c +#define GPIO_SKL_LP_IOAPIC_GPP_A_21 0x2d +#define GPIO_SKL_LP_IOAPIC_GPP_A_22 0x2e +#define GPIO_SKL_LP_IOAPIC_GPP_A_23 0x2f + +#define GPIO_SKL_LP_IOAPIC_GPP_B_00 0x30 +#define GPIO_SKL_LP_IOAPIC_GPP_B_01 0x31 +#define GPIO_SKL_LP_IOAPIC_GPP_B_02 0x32 +#define GPIO_SKL_LP_IOAPIC_GPP_B_03 0x33 +#define GPIO_SKL_LP_IOAPIC_GPP_B_04 0x34 +#define GPIO_SKL_LP_IOAPIC_GPP_B_05 0x35 +#define GPIO_SKL_LP_IOAPIC_GPP_B_06 0x36 +#define GPIO_SKL_LP_IOAPIC_GPP_B_07 0x37 +#define GPIO_SKL_LP_IOAPIC_GPP_B_08 0x38 +#define GPIO_SKL_LP_IOAPIC_GPP_B_09 0x39 +#define GPIO_SKL_LP_IOAPIC_GPP_B_10 0x3a +#define GPIO_SKL_LP_IOAPIC_GPP_B_11 0x3b +#define GPIO_SKL_LP_IOAPIC_GPP_B_12 0x3c +#define GPIO_SKL_LP_IOAPIC_GPP_B_13 0x3d +#define GPIO_SKL_LP_IOAPIC_GPP_B_14 0x3e +#define GPIO_SKL_LP_IOAPIC_GPP_B_15 0x3f +#define GPIO_SKL_LP_IOAPIC_GPP_B_16 0x40 +#define GPIO_SKL_LP_IOAPIC_GPP_B_17 0x41 +#define GPIO_SKL_LP_IOAPIC_GPP_B_18 0x42 +#define GPIO_SKL_LP_IOAPIC_GPP_B_19 0x43 +#define GPIO_SKL_LP_IOAPIC_GPP_B_20 0x44 +#define GPIO_SKL_LP_IOAPIC_GPP_B_21 0x45 +#define GPIO_SKL_LP_IOAPIC_GPP_B_22 0x46 +#define GPIO_SKL_LP_IOAPIC_GPP_B_23 0x47 + +#define GPIO_SKL_LP_IOAPIC_GPP_C_00 0x48 +#define GPIO_SKL_LP_IOAPIC_GPP_C_01 0x49 +#define GPIO_SKL_LP_IOAPIC_GPP_C_02 0x4a +#define GPIO_SKL_LP_IOAPIC_GPP_C_03 0x4b +#define GPIO_SKL_LP_IOAPIC_GPP_C_04 0x4c +#define GPIO_SKL_LP_IOAPIC_GPP_C_05 0x4d +#define GPIO_SKL_LP_IOAPIC_GPP_C_06 0x4e +#define GPIO_SKL_LP_IOAPIC_GPP_C_07 0x4f +#define GPIO_SKL_LP_IOAPIC_GPP_C_08 0x50 +#define GPIO_SKL_LP_IOAPIC_GPP_C_09 0x51 +#define GPIO_SKL_LP_IOAPIC_GPP_C_10 0x52 +#define GPIO_SKL_LP_IOAPIC_GPP_C_11 0x53 +#define GPIO_SKL_LP_IOAPIC_GPP_C_12 0x54 +#define GPIO_SKL_LP_IOAPIC_GPP_C_13 0x55 +#define GPIO_SKL_LP_IOAPIC_GPP_C_14 0x56 +#define GPIO_SKL_LP_IOAPIC_GPP_C_15 0x57 +#define GPIO_SKL_LP_IOAPIC_GPP_C_16 0x58 +#define GPIO_SKL_LP_IOAPIC_GPP_C_17 0x59 +#define GPIO_SKL_LP_IOAPIC_GPP_C_18 0x5a +#define GPIO_SKL_LP_IOAPIC_GPP_C_19 0x5b +#define GPIO_SKL_LP_IOAPIC_GPP_C_20 0x5c +#define GPIO_SKL_LP_IOAPIC_GPP_C_21 0x5d +#define GPIO_SKL_LP_IOAPIC_GPP_C_22 0x5e +#define GPIO_SKL_LP_IOAPIC_GPP_C_23 0x5f + +#define GPIO_SKL_LP_IOAPIC_GPP_D_00 0x60 +#define GPIO_SKL_LP_IOAPIC_GPP_D_01 0x61 +#define GPIO_SKL_LP_IOAPIC_GPP_D_02 0x62 +#define GPIO_SKL_LP_IOAPIC_GPP_D_03 0x63 +#define GPIO_SKL_LP_IOAPIC_GPP_D_04 0x64 +#define GPIO_SKL_LP_IOAPIC_GPP_D_05 0x65 +#define GPIO_SKL_LP_IOAPIC_GPP_D_06 0x66 +#define GPIO_SKL_LP_IOAPIC_GPP_D_07 0x67 +#define GPIO_SKL_LP_IOAPIC_GPP_D_08 0x68 +#define GPIO_SKL_LP_IOAPIC_GPP_D_09 0x69 +#define GPIO_SKL_LP_IOAPIC_GPP_D_10 0x6a +#define GPIO_SKL_LP_IOAPIC_GPP_D_11 0x6b +#define GPIO_SKL_LP_IOAPIC_GPP_D_12 0x6c +#define GPIO_SKL_LP_IOAPIC_GPP_D_13 0x6d +#define GPIO_SKL_LP_IOAPIC_GPP_D_14 0x6e +#define GPIO_SKL_LP_IOAPIC_GPP_D_15 0x6f +#define GPIO_SKL_LP_IOAPIC_GPP_D_16 0x70 +#define GPIO_SKL_LP_IOAPIC_GPP_D_17 0x71 +#define GPIO_SKL_LP_IOAPIC_GPP_D_18 0x72 +#define GPIO_SKL_LP_IOAPIC_GPP_D_19 0x73 +#define GPIO_SKL_LP_IOAPIC_GPP_D_20 0x74 +#define GPIO_SKL_LP_IOAPIC_GPP_D_21 0x75 +#define GPIO_SKL_LP_IOAPIC_GPP_D_22 0x76 +#define GPIO_SKL_LP_IOAPIC_GPP_D_23 0x77 + +#define GPIO_SKL_LP_IOAPIC_GPP_E_00 0x18 +#define GPIO_SKL_LP_IOAPIC_GPP_E_01 0x19 +#define GPIO_SKL_LP_IOAPIC_GPP_E_02 0x1a +#define GPIO_SKL_LP_IOAPIC_GPP_E_03 0x1b +#define GPIO_SKL_LP_IOAPIC_GPP_E_04 0x1c +#define GPIO_SKL_LP_IOAPIC_GPP_E_05 0x1d +#define GPIO_SKL_LP_IOAPIC_GPP_E_06 0x1e +#define GPIO_SKL_LP_IOAPIC_GPP_E_07 0x1f +#define GPIO_SKL_LP_IOAPIC_GPP_E_08 0x20 +#define GPIO_SKL_LP_IOAPIC_GPP_E_09 0x21 +#define GPIO_SKL_LP_IOAPIC_GPP_E_10 0x22 +#define GPIO_SKL_LP_IOAPIC_GPP_E_11 0x23 +#define GPIO_SKL_LP_IOAPIC_GPP_E_12 0x24 +#define GPIO_SKL_LP_IOAPIC_GPP_E_13 0x25 +#define GPIO_SKL_LP_IOAPIC_GPP_E_14 0x26 +#define GPIO_SKL_LP_IOAPIC_GPP_E_15 0x27 +#define GPIO_SKL_LP_IOAPIC_GPP_E_16 0x28 +#define GPIO_SKL_LP_IOAPIC_GPP_E_17 0x29 +#define GPIO_SKL_LP_IOAPIC_GPP_E_18 0x2a +#define GPIO_SKL_LP_IOAPIC_GPP_E_19 0x2b +#define GPIO_SKL_LP_IOAPIC_GPP_E_20 0x2c +#define GPIO_SKL_LP_IOAPIC_GPP_E_21 0x2d +#define GPIO_SKL_LP_IOAPIC_GPP_E_22 0x2e +#define GPIO_SKL_LP_IOAPIC_GPP_E_23 0x2f + +#define GPIO_SKL_LP_IOAPIC_GPP_F_00 0x30 +#define GPIO_SKL_LP_IOAPIC_GPP_F_01 0x31 +#define GPIO_SKL_LP_IOAPIC_GPP_F_02 0x32 +#define GPIO_SKL_LP_IOAPIC_GPP_F_03 0x33 +#define GPIO_SKL_LP_IOAPIC_GPP_F_04 0x34 +#define GPIO_SKL_LP_IOAPIC_GPP_F_05 0x35 +#define GPIO_SKL_LP_IOAPIC_GPP_F_06 0x36 +#define GPIO_SKL_LP_IOAPIC_GPP_F_07 0x37 +#define GPIO_SKL_LP_IOAPIC_GPP_F_08 0x38 +#define GPIO_SKL_LP_IOAPIC_GPP_F_09 0x39 +#define GPIO_SKL_LP_IOAPIC_GPP_F_10 0x3a +#define GPIO_SKL_LP_IOAPIC_GPP_F_11 0x3b +#define GPIO_SKL_LP_IOAPIC_GPP_F_12 0x3c +#define GPIO_SKL_LP_IOAPIC_GPP_F_13 0x3d +#define GPIO_SKL_LP_IOAPIC_GPP_F_14 0x3e +#define GPIO_SKL_LP_IOAPIC_GPP_F_15 0x3f +#define GPIO_SKL_LP_IOAPIC_GPP_F_16 0x40 +#define GPIO_SKL_LP_IOAPIC_GPP_F_17 0x41 +#define GPIO_SKL_LP_IOAPIC_GPP_F_18 0x42 +#define GPIO_SKL_LP_IOAPIC_GPP_F_19 0x43 +#define GPIO_SKL_LP_IOAPIC_GPP_F_20 0x44 +#define GPIO_SKL_LP_IOAPIC_GPP_F_21 0x45 +#define GPIO_SKL_LP_IOAPIC_GPP_F_22 0x46 +#define GPIO_SKL_LP_IOAPIC_GPP_F_23 0x47 + +#define GPIO_SKL_LP_IOAPIC_GPP_G_00 0x48 +#define GPIO_SKL_LP_IOAPIC_GPP_G_01 0x49 +#define GPIO_SKL_LP_IOAPIC_GPP_G_02 0x4a +#define GPIO_SKL_LP_IOAPIC_GPP_G_03 0x4b +#define GPIO_SKL_LP_IOAPIC_GPP_G_04 0x4c +#define GPIO_SKL_LP_IOAPIC_GPP_G_05 0x4d +#define GPIO_SKL_LP_IOAPIC_GPP_G_06 0x4e +#define GPIO_SKL_LP_IOAPIC_GPP_G_07 0x4f + +#define GPIO_SKL_LP_IOAPIC_GPD_00 0x50 +#define GPIO_SKL_LP_IOAPIC_GPD_01 0x51 +#define GPIO_SKL_LP_IOAPIC_GPD_02 0x52 +#define GPIO_SKL_LP_IOAPIC_GPD_03 0x53 +#define GPIO_SKL_LP_IOAPIC_GPD_04 0x54 +#define GPIO_SKL_LP_IOAPIC_GPD_05 0x55 +#define GPIO_SKL_LP_IOAPIC_GPD_06 0x56 +#define GPIO_SKL_LP_IOAPIC_GPD_07 0x57 +#define GPIO_SKL_LP_IOAPIC_GPD_08 0x58 +#define GPIO_SKL_LP_IOAPIC_GPD_09 0x59 +#define GPIO_SKL_LP_IOAPIC_GPD_10 0x5a +#define GPIO_SKL_LP_IOAPIC_GPD_11 0x5b + +//SPT-H: +#define GPIO_SKL_H_IOAPIC_GPP_A_00 0x18 +#define GPIO_SKL_H_IOAPIC_GPP_A_01 0x19 +#define GPIO_SKL_H_IOAPIC_GPP_A_02 0x1a +#define GPIO_SKL_H_IOAPIC_GPP_A_03 0x1b +#define GPIO_SKL_H_IOAPIC_GPP_A_04 0x1c +#define GPIO_SKL_H_IOAPIC_GPP_A_05 0x1d +#define GPIO_SKL_H_IOAPIC_GPP_A_06 0x1e +#define GPIO_SKL_H_IOAPIC_GPP_A_07 0x1f +#define GPIO_SKL_H_IOAPIC_GPP_A_08 0x20 +#define GPIO_SKL_H_IOAPIC_GPP_A_09 0x21 +#define GPIO_SKL_H_IOAPIC_GPP_A_10 0x22 +#define GPIO_SKL_H_IOAPIC_GPP_A_11 0x23 +#define GPIO_SKL_H_IOAPIC_GPP_A_12 0x24 +#define GPIO_SKL_H_IOAPIC_GPP_A_13 0x25 +#define GPIO_SKL_H_IOAPIC_GPP_A_14 0x26 +#define GPIO_SKL_H_IOAPIC_GPP_A_15 0x27 +#define GPIO_SKL_H_IOAPIC_GPP_A_16 0x28 +#define GPIO_SKL_H_IOAPIC_GPP_A_17 0x29 +#define GPIO_SKL_H_IOAPIC_GPP_A_18 0x2a +#define GPIO_SKL_H_IOAPIC_GPP_A_19 0x2b +#define GPIO_SKL_H_IOAPIC_GPP_A_20 0x2c +#define GPIO_SKL_H_IOAPIC_GPP_A_21 0x2d +#define GPIO_SKL_H_IOAPIC_GPP_A_22 0x2e +#define GPIO_SKL_H_IOAPIC_GPP_A_23 0x2f + +#define GPIO_SKL_H_IOAPIC_GPP_B_00 0x30 +#define GPIO_SKL_H_IOAPIC_GPP_B_01 0x31 +#define GPIO_SKL_H_IOAPIC_GPP_B_02 0x32 +#define GPIO_SKL_H_IOAPIC_GPP_B_03 0x33 +#define GPIO_SKL_H_IOAPIC_GPP_B_04 0x34 +#define GPIO_SKL_H_IOAPIC_GPP_B_05 0x35 +#define GPIO_SKL_H_IOAPIC_GPP_B_06 0x36 +#define GPIO_SKL_H_IOAPIC_GPP_B_07 0x37 +#define GPIO_SKL_H_IOAPIC_GPP_B_08 0x38 +#define GPIO_SKL_H_IOAPIC_GPP_B_09 0x39 +#define GPIO_SKL_H_IOAPIC_GPP_B_10 0x3a +#define GPIO_SKL_H_IOAPIC_GPP_B_11 0x3b +#define GPIO_SKL_H_IOAPIC_GPP_B_12 0x3c +#define GPIO_SKL_H_IOAPIC_GPP_B_13 0x3d +#define GPIO_SKL_H_IOAPIC_GPP_B_14 0x3e +#define GPIO_SKL_H_IOAPIC_GPP_B_15 0x3f +#define GPIO_SKL_H_IOAPIC_GPP_B_16 0x40 +#define GPIO_SKL_H_IOAPIC_GPP_B_17 0x41 +#define GPIO_SKL_H_IOAPIC_GPP_B_18 0x42 +#define GPIO_SKL_H_IOAPIC_GPP_B_19 0x43 +#define GPIO_SKL_H_IOAPIC_GPP_B_20 0x44 +#define GPIO_SKL_H_IOAPIC_GPP_B_21 0x45 +#define GPIO_SKL_H_IOAPIC_GPP_B_22 0x46 +#define GPIO_SKL_H_IOAPIC_GPP_B_23 0x47 + +#define GPIO_SKL_H_IOAPIC_GPP_C_00 0x48 +#define GPIO_SKL_H_IOAPIC_GPP_C_01 0x49 +#define GPIO_SKL_H_IOAPIC_GPP_C_02 0x4a +#define GPIO_SKL_H_IOAPIC_GPP_C_03 0x4b +#define GPIO_SKL_H_IOAPIC_GPP_C_04 0x4c +#define GPIO_SKL_H_IOAPIC_GPP_C_05 0x4d +#define GPIO_SKL_H_IOAPIC_GPP_C_06 0x4e +#define GPIO_SKL_H_IOAPIC_GPP_C_07 0x4f +#define GPIO_SKL_H_IOAPIC_GPP_C_08 0x50 +#define GPIO_SKL_H_IOAPIC_GPP_C_09 0x51 +#define GPIO_SKL_H_IOAPIC_GPP_C_10 0x52 +#define GPIO_SKL_H_IOAPIC_GPP_C_11 0x53 +#define GPIO_SKL_H_IOAPIC_GPP_C_12 0x54 +#define GPIO_SKL_H_IOAPIC_GPP_C_13 0x55 +#define GPIO_SKL_H_IOAPIC_GPP_C_14 0x56 +#define GPIO_SKL_H_IOAPIC_GPP_C_15 0x57 +#define GPIO_SKL_H_IOAPIC_GPP_C_16 0x58 +#define GPIO_SKL_H_IOAPIC_GPP_C_17 0x59 +#define GPIO_SKL_H_IOAPIC_GPP_C_18 0x5a +#define GPIO_SKL_H_IOAPIC_GPP_C_19 0x5b +#define GPIO_SKL_H_IOAPIC_GPP_C_20 0x5c +#define GPIO_SKL_H_IOAPIC_GPP_C_21 0x5d +#define GPIO_SKL_H_IOAPIC_GPP_C_22 0x5e +#define GPIO_SKL_H_IOAPIC_GPP_C_23 0x5f + +#define GPIO_SKL_H_IOAPIC_GPP_D_00 0x60 +#define GPIO_SKL_H_IOAPIC_GPP_D_01 0x61 +#define GPIO_SKL_H_IOAPIC_GPP_D_02 0x62 +#define GPIO_SKL_H_IOAPIC_GPP_D_03 0x63 +#define GPIO_SKL_H_IOAPIC_GPP_D_04 0x64 +#define GPIO_SKL_H_IOAPIC_GPP_D_05 0x65 +#define GPIO_SKL_H_IOAPIC_GPP_D_06 0x66 +#define GPIO_SKL_H_IOAPIC_GPP_D_07 0x67 +#define GPIO_SKL_H_IOAPIC_GPP_D_08 0x68 +#define GPIO_SKL_H_IOAPIC_GPP_D_09 0x69 +#define GPIO_SKL_H_IOAPIC_GPP_D_10 0x6a +#define GPIO_SKL_H_IOAPIC_GPP_D_11 0x6b +#define GPIO_SKL_H_IOAPIC_GPP_D_12 0x6c +#define GPIO_SKL_H_IOAPIC_GPP_D_13 0x6d +#define GPIO_SKL_H_IOAPIC_GPP_D_14 0x6e +#define GPIO_SKL_H_IOAPIC_GPP_D_15 0x6f +#define GPIO_SKL_H_IOAPIC_GPP_D_16 0x70 +#define GPIO_SKL_H_IOAPIC_GPP_D_17 0x71 +#define GPIO_SKL_H_IOAPIC_GPP_D_18 0x72 +#define GPIO_SKL_H_IOAPIC_GPP_D_19 0x73 +#define GPIO_SKL_H_IOAPIC_GPP_D_20 0x74 +#define GPIO_SKL_H_IOAPIC_GPP_D_21 0x75 +#define GPIO_SKL_H_IOAPIC_GPP_D_22 0x76 +#define GPIO_SKL_H_IOAPIC_GPP_D_23 0x77 + +#define GPIO_SKL_H_IOAPIC_GPP_E_00 0x18 +#define GPIO_SKL_H_IOAPIC_GPP_E_01 0x19 +#define GPIO_SKL_H_IOAPIC_GPP_E_02 0x1a +#define GPIO_SKL_H_IOAPIC_GPP_E_03 0x1b +#define GPIO_SKL_H_IOAPIC_GPP_E_04 0x1c +#define GPIO_SKL_H_IOAPIC_GPP_E_05 0x1d +#define GPIO_SKL_H_IOAPIC_GPP_E_06 0x1e +#define GPIO_SKL_H_IOAPIC_GPP_E_07 0x1f +#define GPIO_SKL_H_IOAPIC_GPP_E_08 0x20 +#define GPIO_SKL_H_IOAPIC_GPP_E_09 0x21 +#define GPIO_SKL_H_IOAPIC_GPP_E_10 0x22 +#define GPIO_SKL_H_IOAPIC_GPP_E_11 0x23 +#define GPIO_SKL_H_IOAPIC_GPP_E_12 0x24 + +#define GPIO_SKL_H_IOAPIC_GPP_F_00 0x25 +#define GPIO_SKL_H_IOAPIC_GPP_F_01 0x26 +#define GPIO_SKL_H_IOAPIC_GPP_F_02 0x27 +#define GPIO_SKL_H_IOAPIC_GPP_F_03 0x28 +#define GPIO_SKL_H_IOAPIC_GPP_F_04 0x29 +#define GPIO_SKL_H_IOAPIC_GPP_F_05 0x2a +#define GPIO_SKL_H_IOAPIC_GPP_F_06 0x2b +#define GPIO_SKL_H_IOAPIC_GPP_F_07 0x2c +#define GPIO_SKL_H_IOAPIC_GPP_F_08 0x2d +#define GPIO_SKL_H_IOAPIC_GPP_F_09 0x2e +#define GPIO_SKL_H_IOAPIC_GPP_F_10 0x2f +#define GPIO_SKL_H_IOAPIC_GPP_F_11 0x30 +#define GPIO_SKL_H_IOAPIC_GPP_F_12 0x31 +#define GPIO_SKL_H_IOAPIC_GPP_F_13 0x32 +#define GPIO_SKL_H_IOAPIC_GPP_F_14 0x33 +#define GPIO_SKL_H_IOAPIC_GPP_F_15 0x34 +#define GPIO_SKL_H_IOAPIC_GPP_F_16 0x35 +#define GPIO_SKL_H_IOAPIC_GPP_F_17 0x36 +#define GPIO_SKL_H_IOAPIC_GPP_F_18 0x37 +#define GPIO_SKL_H_IOAPIC_GPP_F_19 0x38 +#define GPIO_SKL_H_IOAPIC_GPP_F_20 0x39 +#define GPIO_SKL_H_IOAPIC_GPP_F_21 0x3a +#define GPIO_SKL_H_IOAPIC_GPP_F_22 0x3b +#define GPIO_SKL_H_IOAPIC_GPP_F_23 0x3c + +#define GPIO_SKL_H_IOAPIC_GPP_G_00 0x3d +#define GPIO_SKL_H_IOAPIC_GPP_G_01 0x3e +#define GPIO_SKL_H_IOAPIC_GPP_G_02 0x3f +#define GPIO_SKL_H_IOAPIC_GPP_G_03 0x40 +#define GPIO_SKL_H_IOAPIC_GPP_G_04 0x41 +#define GPIO_SKL_H_IOAPIC_GPP_G_05 0x42 +#define GPIO_SKL_H_IOAPIC_GPP_G_06 0x43 +#define GPIO_SKL_H_IOAPIC_GPP_G_07 0x44 +#define GPIO_SKL_H_IOAPIC_GPP_G_08 0x45 +#define GPIO_SKL_H_IOAPIC_GPP_G_09 0x46 +#define GPIO_SKL_H_IOAPIC_GPP_G_10 0x47 +#define GPIO_SKL_H_IOAPIC_GPP_G_11 0x48 +#define GPIO_SKL_H_IOAPIC_GPP_G_12 0x49 +#define GPIO_SKL_H_IOAPIC_GPP_G_13 0x4a +#define GPIO_SKL_H_IOAPIC_GPP_G_14 0x4b +#define GPIO_SKL_H_IOAPIC_GPP_G_15 0x4c +#define GPIO_SKL_H_IOAPIC_GPP_G_16 0x4d +#define GPIO_SKL_H_IOAPIC_GPP_G_17 0x4e +#define GPIO_SKL_H_IOAPIC_GPP_G_18 0x4f +#define GPIO_SKL_H_IOAPIC_GPP_G_19 0x50 +#define GPIO_SKL_H_IOAPIC_GPP_G_20 0x51 +#define GPIO_SKL_H_IOAPIC_GPP_G_21 0x52 +#define GPIO_SKL_H_IOAPIC_GPP_G_22 0x53 +#define GPIO_SKL_H_IOAPIC_GPP_G_23 0x54 + +#define GPIO_SKL_H_IOAPIC_GPP_H_00 0x55 +#define GPIO_SKL_H_IOAPIC_GPP_H_01 0x56 +#define GPIO_SKL_H_IOAPIC_GPP_H_02 0x57 +#define GPIO_SKL_H_IOAPIC_GPP_H_03 0x58 +#define GPIO_SKL_H_IOAPIC_GPP_H_04 0x59 +#define GPIO_SKL_H_IOAPIC_GPP_H_05 0x5a +#define GPIO_SKL_H_IOAPIC_GPP_H_06 0x5b +#define GPIO_SKL_H_IOAPIC_GPP_H_07 0x5c +#define GPIO_SKL_H_IOAPIC_GPP_H_08 0x5d +#define GPIO_SKL_H_IOAPIC_GPP_H_09 0x5e +#define GPIO_SKL_H_IOAPIC_GPP_H_10 0x5f +#define GPIO_SKL_H_IOAPIC_GPP_H_11 0x60 +#define GPIO_SKL_H_IOAPIC_GPP_H_12 0x61 +#define GPIO_SKL_H_IOAPIC_GPP_H_13 0x62 +#define GPIO_SKL_H_IOAPIC_GPP_H_14 0x63 +#define GPIO_SKL_H_IOAPIC_GPP_H_15 0x64 +#define GPIO_SKL_H_IOAPIC_GPP_H_16 0x65 +#define GPIO_SKL_H_IOAPIC_GPP_H_17 0x66 +#define GPIO_SKL_H_IOAPIC_GPP_H_18 0x67 +#define GPIO_SKL_H_IOAPIC_GPP_H_19 0x68 +#define GPIO_SKL_H_IOAPIC_GPP_H_20 0x69 +#define GPIO_SKL_H_IOAPIC_GPP_H_21 0x6a +#define GPIO_SKL_H_IOAPIC_GPP_H_22 0x6b +#define GPIO_SKL_H_IOAPIC_GPP_H_23 0x6c + +#define GPIO_SKL_H_IOAPIC_GPP_I_00 0x6d +#define GPIO_SKL_H_IOAPIC_GPP_I_01 0x6e +#define GPIO_SKL_H_IOAPIC_GPP_I_02 0x6f +#define GPIO_SKL_H_IOAPIC_GPP_I_03 0x70 +#define GPIO_SKL_H_IOAPIC_GPP_I_04 0x71 +#define GPIO_SKL_H_IOAPIC_GPP_I_05 0x72 +#define GPIO_SKL_H_IOAPIC_GPP_I_06 0x73 +#define GPIO_SKL_H_IOAPIC_GPP_I_07 0x74 +#define GPIO_SKL_H_IOAPIC_GPP_I_08 0x75 +#define GPIO_SKL_H_IOAPIC_GPP_I_09 0x76 +#define GPIO_SKL_H_IOAPIC_GPP_I_10 0x77 + +#define GPIO_SKL_H_IOAPIC_GPD_00 0x18 +#define GPIO_SKL_H_IOAPIC_GPD_01 0x19 +#define GPIO_SKL_H_IOAPIC_GPD_02 0x1a +#define GPIO_SKL_H_IOAPIC_GPD_03 0x1b +#define GPIO_SKL_H_IOAPIC_GPD_04 0x1c +#define GPIO_SKL_H_IOAPIC_GPD_05 0x1d +#define GPIO_SKL_H_IOAPIC_GPD_06 0x1e +#define GPIO_SKL_H_IOAPIC_GPD_07 0x1f +#define GPIO_SKL_H_IOAPIC_GPD_08 0x20 +#define GPIO_SKL_H_IOAPIC_GPD_09 0x21 +#define GPIO_SKL_H_IOAPIC_GPD_10 0x22 +#define GPIO_SKL_H_IOAPIC_GPD_11 0x23 + +#endif // GPIO_DEFINE_ASL diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/GpioLib.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/GpioLib.asl new file mode 100644 index 0000000000..3d8b01af76 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/GpioLib.asl @@ -0,0 +1,1030 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// GPIO Access Library +// +Scope(\_SB) +{ + +#define PCH_LP_PKG_INDEX 0 +#define PCH_H_PKG_INDEX 1 + + // + // GPIO Community address for each group + // + Name(GCOM, Package(){ + Package(){ //SPT-LP + PCH_GPIO_COM0, //SPT-LP GPP_A + PCH_GPIO_COM0, //SPT-LP GPP_B + PCH_GPIO_COM1, //SPT-LP GPP_C + PCH_GPIO_COM1, //SPT-LP GPP_D + PCH_GPIO_COM1, //SPT-LP GPP_E + PCH_GPIO_COM3, //SPT-LP GPP_F + PCH_GPIO_COM3, //SPT-LP GPP_G + PCH_GPIO_COM2, //SPT-LP GPD + }, + Package(){ //SPT-H + PCH_GPIO_COM0, //SPT-H GPP_A + PCH_GPIO_COM0, //SPT-H GPP_B + PCH_GPIO_COM1, //SPT-H GPP_C + PCH_GPIO_COM1, //SPT-H GPP_D + PCH_GPIO_COM1, //SPT-H GPP_E + PCH_GPIO_COM1, //SPT-H GPP_F + PCH_GPIO_COM1, //SPT-H GPP_G + PCH_GPIO_COM1, //SPT-H GPP_H + PCH_GPIO_COM3, //SPT-H GPP_I + PCH_GPIO_COM2 //SPT-H GPD + } + }) + + // + // Number of GPIO pads per group + // + Name(GPPG, Package(){ + Package(){ //SPT-LP + V_PCH_GPIO_GPP_A_PAD_MAX, // SPT-LP GPP_A + V_PCH_GPIO_GPP_B_PAD_MAX, // SPT-LP GPP_B + V_PCH_GPIO_GPP_C_PAD_MAX, // SPT-LP GPP_C + V_PCH_GPIO_GPP_D_PAD_MAX, // SPT-LP GPP_D + V_PCH_LP_GPIO_GPP_E_PAD_MAX, // SPT-LP GPP_E + V_PCH_GPIO_GPP_F_PAD_MAX, // SPT-LP GPP_F + V_PCH_LP_GPIO_GPP_G_PAD_MAX, // SPT-LP GPP_G + V_PCH_GPIO_GPD_PAD_MAX // SPT-LP GPD + }, + Package(){ //SPT-H + V_PCH_GPIO_GPP_A_PAD_MAX, // SPT-H GPP_A + V_PCH_GPIO_GPP_B_PAD_MAX, // SPT-H GPP_B + V_PCH_GPIO_GPP_C_PAD_MAX, // SPT-H GPP_C + V_PCH_GPIO_GPP_D_PAD_MAX, // SPT-H GPP_D + V_PCH_H_GPIO_GPP_E_PAD_MAX, // SPT-H GPP_E + V_PCH_GPIO_GPP_F_PAD_MAX, // SPT-H GPP_F + V_PCH_H_GPIO_GPP_G_PAD_MAX, // SPT-H GPP_G + V_PCH_H_GPIO_GPP_H_PAD_MAX, // SPT_H GPP_H + V_PCH_H_GPIO_GPP_I_PAD_MAX, // SPT_H GPP_I + V_PCH_GPIO_GPD_PAD_MAX // SPT-H GPD + } + }) + + // + // GPIO Pad Configuration offset + // + Name(PCFG, Package(){ + Package(){ //SPT-LP + R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, // SPT-LP GPP_A + R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, // SPT-LP GPP_B + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, // SPT-LP GPP_C + R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, // SPT-LP GPP_D + R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET, // SPT-LP GPP_G + R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, // SPT-H GPP_A + R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, // SPT-H GPP_B + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, // SPT-H GPP_C + R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, // SPT-H GPP_D + R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET, // SPT_H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET, // SPT_H GPP_I + R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET // SPT-H GPD + } + }) + + // + // GPIO Host Software Pad Ownership offset + // + Name(HOWN, Package(){ + Package(){ //SPT-LP + R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN, // SPT-LP GPP_A + R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN, // SPT-LP GPP_B + R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN, // SPT-LP GPP_C + R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN, // SPT-LP GPP_D + R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN, // SPT-LP GPP_G + R_PCH_PCR_GPIO_GPD_HOSTSW_OWN // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN, // SPT-H GPP_A + R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN, // SPT-H GPP_B + R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN, // SPT-H GPP_C + R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN, // SPT-H GPP_D + R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN, // SPT-H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN, // SPT-H GPP_I + R_PCH_PCR_GPIO_GPD_HOSTSW_OWN // SPT-H GPD + } + }) + + // + // GPIO Pad Ownership offset + // + Name(POWN, Package(){ + Package(){ //SPT-LP + R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN, // SPT-LP GPP_A + R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN, // SPT-LP GPP_B + R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN, // SPT-LP GPP_C + R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN, // SPT-LP GPP_D + R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN, // SPT-LP GPP_G + R_PCH_LP_PCR_GPIO_GPD_PAD_OWN // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN, // SPT-H GPP_A + R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN, // SPT-H GPP_B + R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN, // SPT-H GPP_C + R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN, // SPT-H GPP_D + R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN, // SPT-H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN, // SPT-H GPP_I + R_PCH_H_PCR_GPIO_GPD_PAD_OWN // SPT-H GPD + } + }) + + // + // GPIO GPI_GPE_STS Offset + // + Name(GPEO, Package(){ + Package(){ //SPT-LP + R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, // SPT-LP GPP_A + R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, // SPT-LP GPP_B + R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, // SPT-LP GPP_C + R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, // SPT-LP GPP_D + R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, // SPT-LP GPP_E + R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS, // SPT-LP GPP_F + R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS, // SPT-LP GPP_G + R_PCH_PCR_GPIO_GPD_GPI_GPE_STS // SPT-LP GPD + }, + Package(){ //SPT-H + R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, // SPT-H GPP_A + R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, // SPT-H GPP_B + R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, // SPT-H GPP_C + R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, // SPT-H GPP_D + R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, // SPT-H GPP_E + R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS, // SPT-H GPP_F + R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS, // SPT-H GPP_G + R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS, // SPT-H GPP_H + R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS, // SPT-H GPP_I + R_PCH_PCR_GPIO_GPD_GPI_GPE_STS // SPT-H GPD + } + }) + + // + // GPE Enable and Status object. Each bit within one value + // equals to 0 (1-tier) or And(GPE_EN,GPE_STS) (2-tier) and represents + // one pad in selected group. + // + Name(GPES, Package(){ + 0x00000000, // GPP_A + 0x00000000, // GPP_B + 0x00000000, // GPP_C + 0x00000000, // GPP_D + 0x00000000, // GPP_E + 0x00000000, // GPP_F + 0x00000000, // GPP_G + 0x00000000, // GPP_H + 0x00000000, // GPP_I + 0x00000000 // GPD + }) + + // + // Object for storing RX Level/Edge Configuration for all pads. + // Each pad needs 2-bits. + // 00b = Level + // 01b = Edge (RxInv=0 for rising edge; 1 for falling edge) + // 10b = Disabled + // 11b = Either rising edge or falling edge + // + Name(RXEV, Package(){ + 0xFFFFFFFFFFFFFFFF, // GPP_A + 0xFFFFFFFFFFFFFFFF, // GPP_B + 0xFFFFFFFFFFFFFFFF, // GPP_C + 0xFFFFFFFFFFFFFFFF, // GPP_D + 0xFFFFFFFFFFFFFFFF, // GPP_E + 0xFFFFFFFFFFFFFFFF, // GPP_F + 0xFFFFFFFFFFFFFFFF, // GPP_G + 0xFFFFFFFFFFFFFFFF, // GPP_H + 0xFFFFFFFFFFFFFFFF, // GPP_I + 0xFFFFFFFFFFFFFFFF // GPD + }) + + // + // Get GPIO absolute number for selected GpioPad + // + Method(GNUM, 0x1, NotSerialized) + { + // + // Arg0 - GpioPad + // + + // Local1 - Gpio pad number + Store (GNMB(Arg0), Local1) + // Local2 - Gpio group index for GpioPad + Store (GGRP(Arg0), Local2) + + Return (Add(Local1,Multiply(Local2, 24))) + } + + // + // Get interrupt number for for selected GpioPad + // + Method(INUM, 0x1, NotSerialized) + { + // + // Arg0 - GpioPad + // + + If(LEqual(PCHS, 0x2)) { // SPT-LP + Store(PCH_LP_PKG_INDEX, Local0) + } Else { //SPT-H + Store(PCH_H_PKG_INDEX,Local0) + } + // Local1 - Gpio pad number + Store (GNMB(Arg0), Local1) + // Local2 - Gpio group index for GpioPad + Store (GGRP(Arg0), Local2) + // Local3 - Group index used in a loop + Store (0 , Local3) + + While(LLess (Local3, Local2)) { + Add( DeRefOf( Index (DeRefOf(Index (GPPG, Local0)),Local3)),Local1,Local1) + Increment(Local3) + } + + return(Add(24,Mod(Local1,96))) + } + + // + // Get GPIO group index for GpioPad + // + Method(GGRP,1,serialized) { + // + // Arg0 - GpioPad + // + ShiftRight( And(Arg0,0x00FF0000), 16, Local0) + return (Local0) + } + + // + // Get GPIO pin number for GpioPad + // + Method(GNMB,1,serialized) { + // + // Arg0 - GpioPad + // + return (And(Arg0,0x0000FFFF)) + } + + // + // GPEM (part of PCH NVS) is an object for informing how GPIO groups are mapped to GPE. + // Mapping for GPP_x is evaluated from (GPEM >> (GroupNumber*2)) & 0x3 + // Possible values for each group: + // 00b - 2-tier + // 01b - 1-tier, GPE_DW0 + // 10b - 1-tier, GPE_DW1 + // 11b - 1-tier, GPE_DW2 + // + + // + // Get GPE number for selected GpioPad + // + Method(GGPE, 0x1, NotSerialized) + { + // + // Arg0 - GPIO pad + // + + //Local0 - GPIO group index (GPP_A - 0, GPP_B - 1 ... ) + Store (GGRP(Arg0), Local0) + //Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // + // Get mapping for certain group + // Local2 = (GPEM >> (Local0*2)) & 0x3 + // + Store(And(ShiftRight(GPEM,Multiply(Local0,2)),0x3),Local2) + + If (LEqual(Local2,0x0)) { + // + // Pads mapped to 2-tier GPE will all generate GPE_111 + // + Return (0x6F) + } Else { + // + // For 1-tier GPE calculate GPE number + // GPE number = (Local2 - 1)*32 + Local1 + // + Return (Add(Multiply(Subtract(Local2,1),32),Local1)) + } + } + + // + // Get GPIO register address + // + Method(GADR, 0x2, NotSerialized) + { + // + // Arg0 - GPIO Group index + // Arg1 - Package with registers offsets for GPIO groups + // + + If(LEqual(PCHS, 0x2)) { // SPT-LP + Store(PCH_LP_PKG_INDEX, Local0) + } Else { //SPT-H + Store(PCH_H_PKG_INDEX, Local0) + } + //Local1 = GpioCommunityAddress + Store( Add( DeRefOf(Index (DeRefOf( Index(GCOM,Local0)),Arg0)),SBRG),Local1) + + //Local2 = Register Offset + Store( DeRefOf(Index (DeRefOf( Index(Arg1,Local0)),Arg0)),Local2) + + Return( Add (Local1, Local2)) + } + + // + // Get Pad Configuration DW0 register value + // + Method(GPC0, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Return(TEMP) + } + + // + // Set Pad Configuration DW0 register value + // + Method(SPC0, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for DW0 register + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Store(Arg1,TEMP) + } + + // + // Get Pad Configuration DW1 register value + // + Method(GPC1, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + 0x4 + Store( Add( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),0x4),Local2) + OperationRegion(PDW1, SystemMemory, Local2, 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Return(TEMP) + } + + // + // Set Pad Configuration DW1 register value + // + Method(SPC1, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for DW1 register + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local0 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + 0x4 + Store( Add( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),0x4),Local2) + OperationRegion(PDW1, SystemMemory, Local2, 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + Store(Arg1,TEMP) + } + + // + // Set RX Override + // + Method(SRXO, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - 0=no override, 1=drive RX to 1 internally + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + ,28, + TEMP,1, + ,3 + } + Store(Arg1,TEMP) + } + + // + // Get GPI Input Value + // + Method(GGIV, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 1, + TEMP,1, + , 30 + } + Return(TEMP) + } + + // + // Get GPO Output Value + // + Method(GGOV, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,1, + , 31 + } + Return(TEMP) + } + + // + // Set GPO Output Value + // + Method(SGOV, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value of GPIO Tx State + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,1, + , 31 + } + Store(Arg1,TEMP) + } + + // + // Get GPI Input Invert Bit + // + Method(GGII, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 23, + TEMP,1, + , 8 + } + Return(TEMP) + } + + // + // Set GPI Input Invert Bit + // + Method(SGII, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value of RXINV bit for selected pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 23, + TEMP,1, + , 8 + } + Store(Arg1,TEMP) + } + + // + // Get GPIO Pad Mode + // + Method(GPMV, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 10, + TEMP,3, + , 19 + } + Return(TEMP) + } + + // + // Set GPIO Pad Mode + // + Method(SPMV, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for Pad Mode for selected pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 10, + TEMP,3, + , 19 + } + Store(Arg1,TEMP) + } + + // + // Get GPIO Host Software Pad Ownership + // + Method(GHPO, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + OperationRegion(PREG, SystemMemory, GADR(Local0,HOWN), 4) + Field(PREG, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + // HostSwOwnValue = (TEMP >> Local1) & 0x1 + Return( And( ShiftRight(TEMP,Local1),0x1)) + } + + // + // Set GPIO Host Software Pad Ownership + // + Method(SHPO, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for GPIO Host Software Pad Ownership + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + OperationRegion(PREG, SystemMemory, GADR(Local0,HOWN), 4) + Field(PREG, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + // TEMP = (TEMP & (~(1 << PadNumber))) | (HostSwOwnValue << PadNumber) + Or(And(TEMP, Not(ShiftLeft(1,Local1))),ShiftLeft(Arg1,Local1),TEMP) + } + + // + // Get GPIO Pad Ownership + // + Method(GGPO, 0x1, Serialized) + { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = GpioCommunityAddress + PadOwnOffset + (PadNumber >> 3) * 0x4 + Store( Add( GADR(Local0,POWN) , Multiply( ShiftRight(Local1,3),0x4)),Local2) + OperationRegion(PREG, SystemMemory, Local2, 4) + Field(PREG, AnyAcc, NoLock, Preserve) { + Offset(0x0), + TEMP,32 + } + // PadOwnValue = (TEMP >> ((Local1 & 0x7) * 4)) & 0x3 + Return( And( ShiftRight(TEMP,Multiply(And(Local1,0x7),0x4)),0x3)) + } + + // + // Set GPIO GPIRoutIOxAPIC value + // + Method(SGRA, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for GPIRoutIOxAPIC + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 20, + TEMP,1, + , 11 + } + Store(Arg1,TEMP) + } + + // + // Set GPIO weak pull-up/down value + // + Method(SGWP, 0x2, Serialized) + { + // + // Arg0 - GPIO pad + // Arg1 - Value for weak pull-up/down + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + 0x4 + (GPIn * 0x08) + Store( Add( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),0x4),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 10, + TEMP,4, + , 18 + } + Store(Arg1,TEMP) + } + + // + // UGPS, ISME and CGPS methods are used to properly handle 2-tier GPE + // Example: + /* + Method(_L6F, 0) // Method which is called for all 2-tier GPE, must be within _GPE scope + { + \_SB.UGPS() // Update information on GPIO mapping to 1 and 2 tier GPE + If (\_SB.ISME(GpioPad)) + { + \_SB.DeviceXYZ.GPEH() // Custom function to handle GPE for certain GPIO pad + } + \_SB.CGPS() //Clear STS here + } + */ + + // + // Update one group entry in GPES object + // This method is used by UGPS() + // + Method(UGP1, 0x1, Serialized) + { + // + // Arg0 - GPIO group index + // + OperationRegion(GPPX, SystemMemory, GADR(Arg0,GPEO), 36) + Field(GPPX, AnyAcc, NoLock, Preserve) { + Offset(0x0), + STSX,32, + Offset(0x20), + GENX,32 + } + //Check if 2-tier + If(LEqual(And(ShiftRight(GPEM,Multiply(Arg0,2)),0x3),0x0)) { + //Store result of GPI_GPE_EN&GPI_GPE_STS in GPES object + Store ( And(STSX,GENX), Index (GPES, Arg0)) + } Else { + // If 1-tier store 0 in GPES object + Store ( 0x0, Index (GPES, Arg0)) + } + } + + // + // Update GPES object + // + Method(UGPS, 0x0, Serialized) + { + //Local0 - GPIO group index + If(LEqual(PCHS, 0x1)) { // SPT-H + Store(V_PCH_H_GPIO_GROUP_MAX,Local0) + } Else { //SPT-LP + Store(V_PCH_LP_GPIO_GROUP_MAX,Local0) + } + + While(Local0) { + Decrement(Local0) + UGP1(Local0) + } + } + + // + // Clear GPE status for one group from 2-tier + // This method is used by CGPS() + // + Method(CGP1, 0x2, Serialized) { + // + // Arg0 - GPIO group index + // Arg1 - Mask of bits (GpioPads) for which status should be cleared + // + //Check if 2-tier + If(LEqual(And(ShiftRight(GPEM,Multiply(Arg0,2)),0x3),0x0)) { + //Get GPI_GPE_STS for GPP_x + OperationRegion(GPPX, SystemMemory, GADR(Arg0,GPEO), 4) + Field(GPPX, AnyAcc, NoLock, Preserve) { + Offset(0x0), + STSX,32, + } + //Clear status + Store (Arg1, STSX) + } + } + + // + // Clear all GPE status for 2-tier + // + Method(CGPS, 0x0, Serialized) { + //Local0 - GPIO group index + If(LEqual(PCHS, 0x1)) { // SPT-H + Store(V_PCH_H_GPIO_GROUP_MAX,Local0) + } Else { //SPT-LP + Store(V_PCH_LP_GPIO_GROUP_MAX,Local0) + } + + While(Local0) { + Decrement(Local0) + CGP1(Local0, 0xFFFFFFFF) + } + } + + // + // Clear all GPE status for 2-tier which are level sensitive + // + Method(CGLS, 0x0, Serialized) { + //Local0 - GPIO group index + If(LEqual(PCHS, 0x1)) { // SPT-H + Store(V_PCH_H_GPIO_GROUP_MAX,Local0) + } Else { //SPT-LP + Store(V_PCH_LP_GPIO_GROUP_MAX,Local0) + } + + While(Local0) { + Decrement(Local0) + + If(LEqual(Local0,9)){Store(G2L9,Local1);} + ElseIf(LEqual(Local0,8)){Store(G2L8,Local1);} + ElseIf(LEqual(Local0,7)){Store(G2L7,Local1);} + ElseIf(LEqual(Local0,6)){Store(G2L6,Local1);} + ElseIf(LEqual(Local0,5)){Store(G2L5,Local1);} + ElseIf(LEqual(Local0,4)){Store(G2L4,Local1);} + ElseIf(LEqual(Local0,3)){Store(G2L3,Local1);} + ElseIf(LEqual(Local0,2)){Store(G2L2,Local1);} + ElseIf(LEqual(Local0,1)){Store(G2L1,Local1);} + ElseIf(LEqual(Local0,0)){Store(G2L0,Local1);} + Else {continue} + + CGP1(Local0,Local1) + } + } + + // + // Clear a particular GPE status for 2-tier + // + Method(CAGS, 0x1, Serialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + //Check if 2-tier + If(LEqual(And(ShiftRight(GPEM,Multiply(Local0,2)),0x3),0x0)) { + //Get GPI_GPE_STS for GPP_x + OperationRegion(GPPX, SystemMemory, GADR(Local0,GPEO), 4) + Field(GPPX, AnyAcc, NoLock, Preserve) { + Offset(0x0), + STSX,32, + } + //Clear status + Store (STSX, Local3) + ShiftLeft(1, Local1, Local2) + Or(STSX, Local2, STSX) // Clear GPIO status + } + } + + // + // Check GPES buffer + // + Method(ISME, 0x1, NotSerialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // return (GPES[Group]>>PadNumber) & 0x1 + Return( And( ShiftRight(DeRefOf( Index(GPES,Local0)),Local1),0x1)) + } + + // + // Do Interrupt Pin Isolation + // This method should be called before power gating external device + // + Method(DIPI, 0x1, Serialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG) , Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 9, + RDIS,1, + , 15, + RCFG,2, + , 5 + } + If(LNotEqual(RCFG,2)) { + // Save RxEvCfg state in RXEV object: + // Local3 = RXEV[Group] + // Local3 &= ~(0x3 << (PadNr*2)) + // RXEV[Group] = Local3 + Store(DeRefOf(Index (RXEV, Local0)),Local3) + And(Local3,Not(ShiftLeft(0x3,Multiply(Local1,2))),Local3) + Or(Local3,ShiftLeft(RCFG,Multiply(Local1,2)),Index(RXEV,Local0)) + // Set RxEvCfg to 2 + Store(2,RCFG) + // Set GPIORxDis to 1 + Store(1,RDIS) + } + } + + // + // Undo Interrupt Pin Isolation + // This method should be called after un-power gating external device + // + Method(UIPI, 0x1, Serialized) { + // + // Arg0 - GPIO pad + // + // Local0 - GPIO group index + Store (GGRP(Arg0), Local0) + // Local1 - GPIO pad number + Store (GNMB(Arg0), Local1) + + // Local2 = (GpioCommunityAddress + PadCfgOffset) + (GPIn * 0x08) + Store( Add( GADR(Local0,PCFG), Multiply(Local1,0x08)),Local2) + OperationRegion(PDW0, SystemMemory, Local2, 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + Offset(0x0), + , 9, + RDIS,1, + , 15, + RCFG,2, + , 5 + } + // Get RxEvCfg original value from RXEV object + // Local3 = (RXEV[Group] >> (PadNr*2)) & 0x3 + Store(And(ShiftRight(DeRefOf(Index (RXEV, Local0)),Multiply(Local1,2)),0x3),Local3) + + If(LNotEqual(Local3,2)) { + // Set GPIORxDis to 0 + Store(0,RDIS) + // Set RxEvCfg to original value + Store(Local3,RCFG) + } + } + +} // \_SB Scope + + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/IrqLink.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/IrqLink.asl new file mode 100644 index 0000000000..c39e472302 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/IrqLink.asl @@ -0,0 +1,613 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Use this information when determining the Possible IRQs that can be +// used in a given system. +// +// The following IRQs are always in use by legacy devices: +// 0 = System Timer +// 2 = 8259 PIC +// 8 = RTC +// 9 = SCI Interrupt (It may be used, we choose not to) +// 13 = Co-processor Error +// +// The following may be in use by legacy devices: +// 1 = If using PS/2 Keyboard +// 3 = If COMx Port Enabled and IRQ = 3 +// 4 = If COMx Port Enabled and IRQ = 4 +// 5 = If LPT Port Enabled and IRQ = 5 +// 6 = If FDC Enabled +// 7 = If LPT Port Enabled and IRQ = 7 +// 12 = If using PS/2 Mouse +// 14 = Primary IDE (If populated and in Compatibility Mode) +// 15 = Secondary IDE (If populated and in Compatibility Mode) +// +// The following will never be in use by legacy devices: +// 10 = Assign to PARC, PCRC, PERC, PGRC +// 11 = Assign to PBRC, PDRC, PFRC, PHRC + +Device(LNKA) // PARC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device + + Name(_UID,1) // Unique to other Link Devices + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PARC,0x80,\_SB.PARC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSA) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLA,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLA,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PARC,0x0F),IRQ0) + + Return(RTLA) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PARC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PARC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKB) // PBRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,2) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PBRC,0x80,\_SB.PBRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSB) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLB,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLB,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PBRC,0x0F),IRQ0) + + Return(RTLB) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PBRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PBRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKC) // PCRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,3) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PCRC,0x80,\_SB.PCRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSC) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLC,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLC,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PCRC,0x0F),IRQ0) + + Return(RTLC) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PCRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PCRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKD) // PDRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,4) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PDRC,0x80,\_SB.PDRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSD) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLD,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLD,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PDRC,0x0F),IRQ0) + + Return(RTLD) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PDRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PDRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKE) // PERC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,5) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PERC,0x80,\_SB.PERC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSE) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLE,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLE,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PERC,0x0F),IRQ0) + + Return(RTLE) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PERC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PERC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKF) // PFRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,6) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PFRC,0x80,\_SB.PFRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSF) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLF,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLF,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PFRC,0x0F),IRQ0) + + Return(RTLF) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PFRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PFRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKG) // PGRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,7) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PGRC,0x80,\_SB.PGRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSG) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLG,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLG,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PGRC,0x0F),IRQ0) + + Return(RTLG) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PGRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PGRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} + +Device(LNKH) // PHRC Routing Resource +{ + Name(_HID,EISAID("PNP0C0F")) + + Name(_UID,8) + + // Disable the PCI IRQ. + + Method(_DIS,0,Serialized) + { + Or(\_SB.PHRC,0x80,\_SB.PHRC) + } + + // Possible IRQ Resource Setting. + + Method (_PRS, 0, Serialized) + { + return (PRSH) + } + + // Current IRQ Resource Setting. + + Method(_CRS,0,Serialized) + { + Name(RTLH,ResourceTemplate() + { + IRQ(Level,ActiveLow,Shared) {} + }) + + // Point to specific byte. + + CreateWordField(RTLH,1,IRQ0) + + // Zero out IRQ mask bits 0-15 + + Store(Zero,IRQ0) + + ShiftLeft(1,And(\_SB.PHRC,0x0F),IRQ0) + + Return(RTLH) + } + + // Set IRQ Resource Setting. + + Method(_SRS,1,Serialized) + { + // Point to the specific byte passed in. + + CreateWordField(Arg0,1,IRQ0) + + // Determine the IRQ bit to set and store it, + + FindSetRightBit(IRQ0,Local0) + Decrement(Local0) + Store(Local0,\_SB.PHRC) + } + + // PCI IRQ Status. + + Method(_STA,0,Serialized) + { + If(And(\_SB.PHRC,0x80)) + { + Return(0x0009) + } + Else + { + Return(0x000B) + } + } +} diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/Pch.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/Pch.asl new file mode 100644 index 0000000000..35b1787833 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/Pch.asl @@ -0,0 +1,839 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Name (PNVB, 0xFFFF0000) // PCH NVS Base address +Name (PNVL, 0xAA55) // PCH NVS Length +Include ("PchNvs.asl") + + +// +// Trace Hub debug library +// Include it earlier so the debug function can be used as soon as possible +// +Include ("TraceHubDebug.asl") + +Name(SPTH,1) +Name(SPTL,2) +Method(PCHV) { + If(LEqual(PCHS, 1)) { Return (SPTH) } // series=H -> SPT-H + If(LEqual(PCHS, 2)) { Return (SPTL) } // series=LP -> SPT-LP + Return (0) +} + +// +// This PME event (PCH's GPE 6Dh) is received when any PCH internal device with +// PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. +// +Scope(\_GPE) { + Method(_L6D, 0, Serialized) { + \_SB.PC00.XHCI.GPEH() + \_SB.PC00.CAVS.GPEH() + \_SB.PC00.GBE1.GPEH() + } +} + +Scope (\_SB.PC00) { + + // + // PCH reserved resource + // + Device(PRRE) { + Name(_HID,EISAID("PNP0C02")) // motherboard resource + Name(_UID,"PCHRESV") + Name(_STA,0x3) // device present and decodes its resources, but not to be displayed in OSPM + + Method(_CRS,0,Serialized) + { + Name(BUF0,ResourceTemplate(){ + // + // PCH RESERVED MMIO RANGE + // 0xFD000000 to 0xFE7FFFFF + // to skip over address range that might be claimed by the GPIO, Intel Serial IO, Thermal, TraceHub and CIO2 devices + // need to split this into 5 ranges + // The GPIO COMM0,1,3 and SerialIO ranges will be handled by SIRC device. + // + Memory32Fixed(ReadWrite,0xFD000000,0x00AC0000) // 0xFD000000 - 0xFDABFFFF + // Skip 0xFDAC0000 - 0xFDACFFFF for GPIO_COMM3 + Memory32Fixed(ReadWrite,0xFDAD0000,0x00010000) // 0xFDAD0000 - 0xFDADFFFF, only cover GPIO_COMM2 range + // Skip 0xFDAE0000 - 0xFDAFFFFF for GPIO_COMM0 and GPIO_COMM1 + Memory32Fixed(ReadWrite,0xFDB00000,0x00500000) // 0xFDB00000 - 0xFDFFFFFF + Memory32Fixed(ReadWrite,0xFE000000,0x00010000) // 0xFE000000 - 0xFE00FFFF + Memory32Fixed(ReadWrite,0xFE011000,0x0000f000) // 0xFE011000 - 0xFE01FFFF + // Skip 0xFE020000 - 0xFE035FFF for Serial IO + Memory32Fixed(ReadWrite,0xFE036000,0x00006000) // 0xFE036000 - 0xFE03BFFF + // Skip 0xFE03C000 - 0xFE03CFFF for Thermal Device in ACPI mode + Memory32Fixed(ReadWrite,0xFE03D000,0x003C3000) // 0xFE03D000 - 0xFE3FFFFF + // Skip 0xFE400000 - 0xFE40FFFF for CIO2 in ACPI mode + Memory32Fixed(ReadWrite,0xFE410000,0x003F0000) // 0xFE410000 - 0xFE7FFFFF + }) + Return(BUF0) + } + } + Device(IOTR) { + // + // This device claims IO range reserved for IO traps + // to prevent OS from reusing it for other purposes + // + Name(_HID,EISAID("PNP0C02")) + Name(_UID,"IoTraps") + Name(BUF0,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG0) }) + Name(BUF1,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG1) }) + Name(BUF2,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG2) }) + Name(BUF3,ResourceTemplate(){ Io(Decode16,0x0,0x0,0x1,0xFF,TAG3) }) + CreateWordField(BUF0,TAG0._MIN,AMI0) + CreateWordField(BUF0,TAG0._MAX,AMA0) + CreateWordField(BUF1,TAG1._MIN,AMI1) + CreateWordField(BUF1,TAG1._MAX,AMA1) + CreateWordField(BUF2,TAG2._MIN,AMI2) + CreateWordField(BUF2,TAG2._MAX,AMA2) + CreateWordField(BUF3,TAG3._MIN,AMI3) + CreateWordField(BUF3,TAG3._MAX,AMA3) + Method(_CRS) { + Store(ResourceTemplate() { }, Local0) + Store(ITA0,AMI0);Store(ITA0,AMA0) + Store(ITA1,AMI1);Store(ITA1,AMA1) + Store(ITA2,AMI2);Store(ITA2,AMA2) + Store(ITA3,AMI3);Store(ITA3,AMA3) + if(LEqual(ITS0,1)) { ConcatenateResTemplate(Local0, BUF0, Local0) } + if(LEqual(ITS1,1)) { ConcatenateResTemplate(Local0, BUF1, Local0) } + if(LEqual(ITS2,1)) { ConcatenateResTemplate(Local0, BUF2, Local0) } + if(LEqual(ITS3,1)) { ConcatenateResTemplate(Local0, BUF3, Local0) } + return (Local0) + } + } + + + // + // LPC Bridge - Device 31, Function 0, this is only for PCH register Memory Region declare, + // it's better to be declared as early as possible since it's widely used in whole ACPI name space. + // Please add any code which needs to reference any register of it after this + // + Scope (\_SB.PC00.LPC0) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; return(0)} + + OperationRegion(LPC, PCI_Config, 0x00, 0x100) + Field(LPC, AnyAcc, NoLock, Preserve) + { + Offset(0x02), + CDID, 16, + Offset(0x08), + CRID, 8, + Offset(0x80), + IOD0, 8, + IOD1, 8, + Offset(0xA0), + , 9, + PRBL, 1, + Offset(0xAC), + , 8, + , 8, + XUSB, 1, + Offset(0xB8), + , 22, + GR0B, 2, + , 8, + Offset(0xBC), + , 2, + GR19, 2, + , 28, + Offset(0xDC), + , 2, + ESPI, 1, + } + } + + // + // PCH Power Management Controller + // + Scope(\_SB.PC00.PMC1) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; return(0)} + + OperationRegion(PMCB, PCI_Config, 0x00, 0x100) + Field(PMCB, AnyAcc, NoLock, Preserve) { + VDID, 32, + Offset(0x40), + , 8, + ACBA, 8, + Offset(0x48), + , 12, + PWBA, 20, + } + } + + // + // SMBus Controller - Device 31, Function 4 + // + Device(SBUS) { + Name(_ADR,0x001F0004) + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; return(0)} + } +} + + +Scope(\) +{ + // + // PCR Register Access Methods + // + // PCR Dword Read + // arg0: PID + // arg1: Offset + // + Method (PCRR, 2, Serialized) { + Add (ShiftLeft (arg0, 16), arg1, Local0) + Add (SBRG, Local0, Local0) + OperationRegion (PCR0, SystemMemory, Local0, 0x4) + Field(PCR0,DWordAcc,Lock,Preserve) { + Offset(0x00), + DAT0, 32 + } // End Field PCR0 + Return (DAT0) + } // End Method PCRR + + // + // PCR Dword Write + // arg0: PID + // arg1: Offset + // arg2: write data + // + Method (PCRW, 3, Serialized) { + Add (ShiftLeft (arg0, 16), arg1, Local0) + Add (SBRG, Local0, Local0) + OperationRegion (PCR0, SystemMemory, Local0, 0x4) + Field(PCR0,DWordAcc,Lock,Preserve) { + Offset(0x00), + DAT0, 32 + } // End Field PCR0 + Store (arg2, DAT0) + + // read back for PCR back to back limitation + OperationRegion (PCR1, SystemMemory, ADD (SBRG, 0x00C73418), 0x4) + Field(PCR1,DWordAcc,Lock,Preserve) { + Offset(0x00), + DAT1, 32 + } // End Field PCR1 + } // End Method PCRW + + // + // PCR Dword Or + // arg0: PID + // arg1: Offset + // arg2: Or data + // + Method (PCRO, 3, Serialized) { + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 + Store(Or(Local0,arg2),Local1) // Or data + PCRW(arg0,arg1,Local1) // Write data back + } + + // + // PCR Dword And + // arg0: PID + // arg1: Offset + // arg2: And data + // + Method (PCRA, 3, Serialized) { + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 + Store(And(Local0,arg2),Local1) // And data + PCRW(arg0,arg1,Local1) // Write data back + } + + // + // PCR Dword AndThenOr + // arg0: PID + // arg1: Offset + // arg2: And data + // arg3: Or data + // + Method (PCAO, 4, Serialized) { + Store(PCRR(arg0,arg1),Local0) // Store PCR Read data in Local0 + Store(Or(And(Local0,arg2),arg3),Local1) // AndThenOr + PCRW(arg0,arg1,Local1) // Write data back + } + + Name (PMBV, 0) // ACPI I/O base address value + Method (PMB1, 0) { + If (LEqual(PMBV, 0)) { + Store (ShiftLeft (\_SB.PC00.PMC1.ACBA, 8), PMBV) + } + Return (PMBV) + } + + Name (PWRV, 0) // PWRM base address value + Method (PWRM, 0) { + If (LEqual(PWRV, 0)) { + Store (ShiftLeft (\_SB.PC00.PMC1.PWBA, 12), PWRV) + } + Return (PWRV) + } + + + // + // Define PCH ACPIBASE I/O as an ACPI operating region. The base address + // can be found in Device 31, Function 2, Offset 40h. + // + OperationRegion(PMIO, SystemIo, PMB1, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) { + , 8, + PBSS, 1, // Power Button Status + Offset(0x40), // General Purpose Event Control + , 17, + GPEC, 1 // Software GPE Control + } + OperationRegion(PMLP, SystemIo, Add(\PMB1,0x80), 0x20) + Field(PMLP, ByteAcc, NoLock, Preserve) { + Offset(0x10), // GPE0 Enable + , 8, + GE08, 1, + , 8, + GE17, 1, + , 17, + GE35, 1, + , 9, + GE45, 1, + , 2, + GE48, 1, + , 2, + GE51, 1, + , 76, + } + Field(PMLP, ByteAcc, NoLock, WriteAsZeros) { + Offset(0x00), // GPE0 Status + , 8, + GS08, 1, + , 8, + GS17, 1, + , 17, + GS35, 1, + , 9, + GS45, 1, + , 2, + GS48, 1, + , 2, + GS51, 1, + , 2, + GS54, 1, + GS55, 1, + , 72, + } + + + + // + // PWRM register definitions + // + OperationRegion(PWMR, SystemMemory, \PWRM, 0x800) + Field(PWMR, AnyAcc, NoLock, Preserve) { + Offset(0x0E0), + , 16, + DWLE, 1, // Deep-Sx WLAN Phy Power Enable + HWLE, 1, // Host Wireless LAN Phy Power Enable + } + + // + // + OperationRegion(PMST, SystemMemory, PWRV, 0x80) + Field(PMST, DWordAcc, NoLock, Preserve) { + Offset(0x18), // Power Management Configuration Reg 1 (PM_CFG) + , 25, // + USBP, 1, // Allow USB2 PHY Core Power Gating (ALLOW_USB2_CORE_PG) + Offset(0x1C), // PCH Power Management Status (PCH_PM_STS) + , 24, // + PMFS, 1, // PMC Message Full Status (PMC_MSG_FULL_STS) + Offset(0x20), // Message to PMC (MTPMC) + MPMC, 32, // Message to PMC (MTPMC) + Offset(0x24), // PCH Power Management Status (PCH_PM_STS2) + , 20, // + UWAB, 1, // USB2 Workaround Available Bit + } + +} //end Scope(\) + +Scope (\_SB.PC00) { + Name(LTRN, 0) + Name(OBFN, 0) + + Name(LMSL, 0) + Name(LNSL, 0) + + // + // LAN Controller - Device 31, Function 6 + // + Scope(\_SB.PC00.GBE1) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; return(0)} + OperationRegion(GLBA, PCI_Config, 0,0x100) + Field(GLBA,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0xCC), + , 8, + PMEE, 1, // PME Enable + , 6, + PMES, 1, // PME Status + } + + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // can wakeup from S4 state + + Method(_DSW, 3) + { + Store(Arg0, PMEE) + } + + // + // GPE handler for GbE, this is part of _Lxx handler for bus 0 PME + // + Method(GPEH) + { + If(LEqual(DVID, 0xFFFF)) { + Return() + } + If(LAnd(PMEE, PMES)) { + Store(1, PMES) // clear PME Status + Notify(GBE1, 0x02) + } + } + } // end "GbE Controller" + +} //scope + +// +// xHCI Controller - Device 20, Function 0 +// +Include("PchXhci.asl") + +// xDCI (OTG) Controller is not used in Server +// Comment out as ifdefs don't work at Trim stage of ASL preparation + +Scope(\_SB_.PC00) { + // + // High Definition Audio Controller - Device 31, Function 3 + // + include("PchHda.asl") + + // + // PCIE Root Port #01 + // + Scope(\_SB.PC00.RP01) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR1, LTRN) + Store (PML1, LMSL) + Store (PNL1, LNSL) + Store (OBF1, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #01" + + // + // PCIE Root Port #02 + // + Scope(\_SB.PC00.RP02) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR2, LTRN) + Store (PML2, LMSL) + Store (PNL2, LNSL) + Store (OBF2, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #02" + + // + // PCIE Root Port #03 + // + Scope(\_SB.PC00.RP03) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR3, LTRN) + Store (PML3, LMSL) + Store (PNL3, LNSL) + Store (OBF3, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #03" + + // + // PCIE Root Port #04 + // + Scope(\_SB.PC00.RP04) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR4, LTRN) + Store (PML4, LMSL) + Store (PNL4, LNSL) + Store (OBF4, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #04" + + // + // PCIE Root Port #05 + // + Scope(\_SB.PC00.RP05) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR5, LTRN) + Store (PML5, LMSL) + Store (PNL5, LNSL) + Store (OBF5, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #05" + + // + // PCIE Root Port #06 + // + Scope(\_SB.PC00.RP06) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR6, LTRN) + Store (PML6, LMSL) + Store (PNL6, LNSL) + Store (OBF6, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #06" + + // + // PCIE Root Port #07 + // + Scope(\_SB.PC00.RP07) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR7, LTRN) + Store (PML7, LMSL) + Store (PNL7, LNSL) + Store (OBF7, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #07" + + // + // PCIE Root Port #08 + // + Scope(\_SB.PC00.RP08) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR8, LTRN) + Store (PML8, LMSL) + Store (PNL8, LNSL) + Store (OBF8, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #08" + + // + // PCIE Root Port #09 + // + Scope(\_SB.PC00.RP09) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTR9, LTRN) + Store (PML9, LMSL) + Store (PNL9, LNSL) + Store (OBF9, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #09" + + // + // PCIE Root Port #10 + // + Scope(\_SB.PC00.RP10) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRA, LTRN) + Store (PMLA, LMSL) + Store (PNLA, LNSL) + Store (OBFA, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #10" + + // + // PCIE Root Port #11 + // + Scope(\_SB.PC00.RP11) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRB, LTRN) + Store (PMLB, LMSL) + Store (PNLB, LNSL) + Store (OBFB, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #11" + + // + // PCIE Root Port #12 + // + Scope(\_SB.PC00.RP12) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRC, LTRN) + Store (PMLC, LMSL) + Store (PNLC, LNSL) + Store (OBFC, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #12" + + // + // PCIE Root Port #13 + // + Scope(\_SB.PC00.RP13) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRD, LTRN) + Store (PMLD, LMSL) + Store (PNLD, LNSL) + Store (OBFD, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #13" + + // + // PCIE Root Port #14 + // + Scope(\_SB.PC00.RP14) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRE, LTRN) + Store (PMLE, LMSL) + Store (PNLE, LNSL) + Store (OBFE, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #14" + + // + // PCIE Root Port #15 + // + Scope(\_SB.PC00.RP15) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRF, LTRN) + Store (PMLF, LMSL) + Store (PNLF, LNSL) + Store (OBFF, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #15" + + // + // PCIE Root Port #16 + // + Scope(\_SB.PC00.RP16) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRG, LTRN) + Store (PMLG, LMSL) + Store (PNLG, LNSL) + Store (OBFG, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #16" + + // + // PCIE Root Port #17 + // + Scope(\_SB.PC00.RP17) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRH, LTRN) + Store (PMLH, LMSL) + Store (PNLH, LNSL) + Store (OBFH, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #17" + + // + // PCIE Root Port #18 + // + Scope(\_SB.PC00.RP18) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRI, LTRN) + Store (PMLI, LMSL) + Store (PNLI, LNSL) + Store (OBFI, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #18" + + // + // PCIE Root Port #19 + // + Scope(\_SB.PC00.RP19) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRJ, LTRN) + Store (PMLJ, LMSL) + Store (PNLJ, LNSL) + Store (OBFJ, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #19" + + // + // PCIE Root Port #20 + // + Scope(\_SB.PC00.RP20) { + // + // Pass LTRx to LTRN so PchPcie.asl can be reused for PCIes. + // + Method(_INI) + { + Store (LTRK, LTRN) + Store (PMLK, LMSL) + Store (PNLK, LNSL) + Store (OBFK, OBFN) + } + Include("PchPcie.asl") + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } // end "PCIE Root Port #20" + + // + // Serial ATA Host Controller - Device 31, Function 2 + // +External(\_SB.PC00.SAT0.SDSM, MethodObj) + +Scope (\_SB.PC00.SAT1) { + Include ("PchSata.asl") + Device(PRT6) + { + Name(_ADR,0x0006FFFF) // Port 6 + } + Device(PRT7) + { + Name(_ADR,0x0007FFFF) // Port 7 + } +} +Scope (\_SB.PC00.SAT2) { + Include ("PchSata.asl") +} + //Server does not support CIO Camera I/O + + // + // Thermal Device + // + Scope(\_SB.PC00.TERM) { + Name (_HID, "INT343D") + Name (_UID, 1) + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xFE03C000, 0x00001000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , IRQ) { 18 } + }) + + CreateDWordField(RBUF,IRQ._INT,IRQN) + Method (_CRS, 0x0, NotSerialized) { + Store(TIRQ, IRQN) + + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + If(LEqual(TAEN, 0)) { Return(0x0) } // device not enabled in ACPI mode + If(LEqual(TIRQ, 0)) { Return(0x0) } // IRQ number not updated + Return(0xF) + } + } +} + +// Comment out as ifdefs don't work at Trim stage of ASL preparation + +// +// Storage and Communication Subsystems definitions +// +Include ("PchScs.asl") + + + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchAcpiTables.inf b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchAcpiTables.inf new file mode 100644 index 0000000000..85d84b6d52 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchAcpiTables.inf @@ -0,0 +1,40 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+INF_VERSION = 0x00010005
+BASE_NAME = PchAcpiTables
+FILE_GUID = 31401EE7-1600-437c-A11C-B1035D8E6070
+MODULE_TYPE = USER_DEFINED
+VERSION_STRING = 1.0
+
+[Sources]
+ Pch.asl
+ PchNvs.asl
+ PchHda.asl
+ PchSerialIo.asl
+ PchPcie.asl
+ PchSata.asl
+ PchRstPcieStorage.asl
+ UsbSbd.asl
+ PchXhci.asl
+ PchXdci.asl
+ IrqLink.asl
+ PchGpioDefine.asl
+ PchGpioLib.asl
+ TraceHubDebug.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #PCH_SPT
diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchHda.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchHda.asl new file mode 100644 index 0000000000..71220d8bda --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchHda.asl @@ -0,0 +1,312 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// Bit Difinitions +// +#ifndef BIT0 +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#endif //BIT0 + +// +// High Definition Audio Controller - Device 31, Function 3 +// +Scope(\_SB.PC00.CAVS) { + +#ifndef BIT0 +#define BIT0 0x00000001 +#endif +#ifndef BIT1 +#define BIT1 0x00000002 +#endif +#ifndef BIT2 +#define BIT2 0x00000004 +#endif +#ifndef BIT3 +#define BIT3 0x00000008 +#endif +#ifndef BIT4 +#define BIT4 0x00000010 +#endif +#ifndef BIT5 +#define BIT5 0x00000020 +#endif +#ifndef BIT6 +#define BIT6 0x00000040 +#endif +#ifndef BIT7 +#define BIT7 0x00000080 +#endif +#ifndef BIT8 +#define BIT8 0x00000100 +#endif +#ifndef BIT9 +#define BIT9 0x00000200 +#endif +#ifndef BIT10 +#define BIT10 0x00000400 +#endif +#ifndef BIT11 +#define BIT11 0x00000800 +#endif +#ifndef BIT12 +#define BIT12 0x00001000 +#endif +#ifndef BIT13 +#define BIT13 0x00002000 +#endif +#ifndef BIT14 +#define BIT14 0x00004000 +#endif +#ifndef BIT15 +#define BIT15 0x00008000 +#endif +#ifndef BIT16 +#define BIT16 0x00010000 +#endif +#ifndef BIT17 +#define BIT17 0x00020000 +#endif +#ifndef BIT18 +#define BIT18 0x00040000 +#endif +#ifndef BIT19 +#define BIT19 0x00080000 +#endif +#ifndef BIT20 +#define BIT20 0x00100000 +#endif +#ifndef BIT21 +#define BIT21 0x00200000 +#endif +#ifndef BIT22 +#define BIT22 0x00400000 +#endif +#ifndef BIT23 +#define BIT23 0x00800000 +#endif +#ifndef BIT24 +#define BIT24 0x01000000 +#endif +#ifndef BIT25 +#define BIT25 0x02000000 +#endif +#ifndef BIT26 +#define BIT26 0x04000000 +#endif +#ifndef BIT27 +#define BIT27 0x08000000 +#endif +#ifndef BIT28 +#define BIT28 0x10000000 +#endif +#ifndef BIT29 +#define BIT29 0x20000000 +#endif +#ifndef BIT30 +#define BIT30 0x40000000 +#endif +#ifndef BIT31 +#define BIT31 0x80000000 +#endif + + // + // Define a Memory Region that will allow access to the HDA PCI Configuration Space + // + OperationRegion(HDAR, PCI_Config, 0x00, 0x100) + Field(HDAR,WordAcc,NoLock,Preserve) { + VDID,32, // 0x00, VID DID + Offset(0x48), // 0x48, CGCTL - Clock Gating Control + ,6, + MBCG,1, // MISCBDCGE [BIT6] + Offset(0x54), // 0x54, Power Management Control and Status Register + ,8, + PMEE,1, + ,6, + PMES,1 // PME Status + } + + Name(_S0W, 3) // Device can wake itself from D3 in S0 + + Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable + + + Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // Can wakeup from S4 state + + // GPE handler for HDA, this is part of _Lxx handler for bus 0 PME + Method(GPEH) { + If(LEqual(VDID, 0xFFFFFFFF)) { + Return() + } + + If(LAnd(PMEE, PMES)) { + ADBG("HDAS GPEH") + Store(1, PMES) // clear PME Status + Notify(CAVS, 0x02) + } + } + + // NHLT Table memory descriptor, returned from _DSM + Name(NBUF, ResourceTemplate () { + // NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN - 1) and length (_LEN) + QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed, NonCacheable, ReadOnly, + 0x1, // AddressGranularity + 0x0000000000000000, // AddressMinimum _MIN + 0x0000000000000000, // AddressMaximum _MAX + 0x0, + 0x0, // RangeLength _LEN + , , NHLT, AddressRangeACPI,) + }) + + Method(AUWA,0,Serialized) + { + If(LEqual(PCHS, 1)) { + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-H A0 stepping (RevID = 0x0) + } else { + If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-LP A0 stepping (RevID = 0x0) + If(LEqual(\_SB.PC00.LPC0.CRID, 0x1)) { Return (1) } // Apply to SPT-LP A1 stepping (RevID = 0x1) + If(LEqual(\_SB.PC00.LPC0.CRID, 0x9)) { Return (1) } // Apply to SPT-LP A2 stepping (RevID = 0x9) + } + Return (0) + } + + Method(_INI) { + // Update resource according to NVS + ADBG("HDAS _INI") + + // Set NHLT base address and length + CreateQWordField(NBUF, ^NHLT._MIN, NBAS) + CreateQWordField(NBUF, ^NHLT._MAX, NMAS) + CreateQWordField(NBUF, ^NHLT._LEN, NLEN) + Store(NHLA, NBAS) + Add(NHLA, Subtract(NHLL, 1), NMAS) + Store(NHLL, NLEN) + + If(LEqual(AUWA(), 1)) { + Store(0, \_SB.PC00.CAVS.MBCG) + } + } + + Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + // Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer) + // Arg1 - Revision ID: 0x01 (Integer) + // Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details. + // Arg3 - Depends on Function Index - See below for details. + // Return - Depends on Function Index - See below for details. + + ADBG("HDAS _DSM") + + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + + // Verify UUID + If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) { + + Switch(ToInteger(Arg2)) { + + // Function 0: Function Support Query + // Arg2 - Function Index: 0x00 (Integer) + // Arg3: Unused + // Return: Bitmask of functions supported. (Buffer) + Case(0) { + // Supports function 0 - 3 + Return(Buffer(One) { 0x0F }) + } + + // Function 1: Query Non HD Audio Descriptor Table + // Used by the Intel Offload Engine Driver to discover the + // non HD Audio devices supported by the Audio DSP. + // Arg2 - Function Index: 0x01 (Integer) + // Arg3 - Unused + // Return - ACPI Table describing the non HD Audio links and devices supported by the ADSP (ResourceBuffer) + Case(1) { + ADBG("_DSM Fun 1 NHLT") + // NBUF - Memory Resource Descriptor buffer with address and length of NHLT + Return(NBUF) + } + + // Function 2: Query Feature Mask + // Used by the Intel Offload Engine Driver to retrieve a bitmask + // of features allowable on this platform. + // Arg2 - Function Index: 0x02 (Integer) + // Arg3: Unused + // Return: Bitmask of supported features. + Case (2) { + ADBG("_DSM Fun 2 FMSK") + // Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported + // Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported + // Bit 2 == '1', codec based VAD support allowable + // Bit 3 - 4 Reserved + // Bit 5 == '1', BT Intel HFP SCO is supported + // Bit 6 == '1', BT Intel A2DP is supported + // Bit 7 == '1', DSP based speech pre-processing disabled + // Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on Voice + // Bit 9 - 31 Reserved, shall be set to '0' + // ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy + Return(ADFM) + } + + // Function 3: Query Pre/Post Processing Module Support + // Used by the Intel Offload Engine Driver to determine if a + // specified PP Module is allowed to be supported on this platform + // Arg2 - Function Index: 0x03 (Integer) + // Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer) + // Return - TRUE if PP Module supported, else FALSE. + Case (3) { + ADBG("_DSM Fun 3 PPMS") + // ADPM - NVS AudioDSP Post-Processing Module Bit Mask updated from PchPolicy: HdaConfig->DspPpModuleMask + + // + // Example (to be updated with real GUIDs of supported 3rd party IP): + // + // 3rd Party DSP Processing Module 1 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT0) + // Check PP module with GUID AABBCCDD-EEFF-1122-3344-556677889900 + // If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-556677889900"))){ + // Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] / ADPM[BIT0] set - supported 3rd Party Processing Module 1(return true) + // } + // + // 3rd Party DSP Processing Module 5 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT5) + // Check PP module with GUID 11111111-2222-3333-4444-AABBCCDDEEFF + // If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-AABBCCDDEEFF"))){ + // Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] / ADPM[BIT5] set - supported 3rd Party Processing Module 5(return true) + // } + // + // Implement for all supported PP modules + // + Return(0) // Is not supported + } + + Default { + // Function not supported (Arg2) + ADBG("_DSM Fun NOK") + Return(Buffer(One) { 0x00 }) + } + } // Switch(Arg2) End + } // If(Arg0, UUID) End + + + // UUID not supported (Arg0) + ADBG("_DSM UUID NOK") + //Fix warning: not all control paths return a value + Return(0) + } // _DSM End + +} // end "High Definition Audio Controller" diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchHeci.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchHeci.asl new file mode 100644 index 0000000000..02eca833c3 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchHeci.asl @@ -0,0 +1,28 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0) { + // + // Management Engine Interface 1 - Device 22, Function 0 + // + Device(HECI) { + Name(_ADR, 0x00160000) + + Method(_DSM, 0x4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + //Fix warning: not all control paths return a value + Return(0) + } // End _DSM + } // Device(HECI) +} + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchIsh.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchIsh.asl new file mode 100644 index 0000000000..d05ca11667 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchIsh.asl @@ -0,0 +1,27 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Scope(\_SB.PCI0) { + // + // Integrated Sensor Hub (PCI Mode) - Device 19, Function 0 + // + Device(ISHD) { + Name(_ADR, 0x00130000) + + Method(_DSM, 0x4, NotSerialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) { + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + //Fix warning: not all control paths return a value + Return(0) + } // End _DSM + } // Device(ISHD) +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchNvs.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchNvs.asl new file mode 100644 index 0000000000..f41157f16b --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchNvs.asl @@ -0,0 +1,276 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + // + // Define PCH NVS Area operatino region. + // + + + + OperationRegion(PNVA,SystemMemory,PNVB,PNVL) + Field(PNVA,AnyAcc,Lock,Preserve) + { + Offset(0), RCRV, 32, // Offset(0), RC Revision + Offset(4), PCHS, 16, // Offset(4), PCH Series + Offset(6), PCHG, 16, // Offset(6), PCH Generation + Offset(8), RPA1, 32, // Offset(8), Root Port address 1 + Offset(12), RPA2, 32, // Offset(12), Root Port address 2 + Offset(16), RPA3, 32, // Offset(16), Root Port address 3 + Offset(20), RPA4, 32, // Offset(20), Root Port address 4 + Offset(24), RPA5, 32, // Offset(24), Root Port address 5 + Offset(28), RPA6, 32, // Offset(28), Root Port address 6 + Offset(32), RPA7, 32, // Offset(32), Root Port address 7 + Offset(36), RPA8, 32, // Offset(36), Root Port address 8 + Offset(40), RPA9, 32, // Offset(40), Root Port address 9 + Offset(44), RPAA, 32, // Offset(44), Root Port address 10 + Offset(48), RPAB, 32, // Offset(48), Root Port address 11 + Offset(52), RPAC, 32, // Offset(52), Root Port address 12 + Offset(56), RPAD, 32, // Offset(56), Root Port address 13 + Offset(60), RPAE, 32, // Offset(60), Root Port address 14 + Offset(64), RPAF, 32, // Offset(64), Root Port address 15 + Offset(68), RPAG, 32, // Offset(68), Root Port address 16 + Offset(72), RPAH, 32, // Offset(72), Root Port address 17 + Offset(76), RPAI, 32, // Offset(76), Root Port address 18 + Offset(80), RPAJ, 32, // Offset(80), Root Port address 19 + Offset(84), RPAK, 32, // Offset(84), Root Port address 20 + Offset(88), NHLA, 64, // Offset(88), HD-Audio NHLT ACPI address + Offset(96), NHLL, 32, // Offset(96), HD-Audio NHLT ACPI length + Offset(100), ADFM, 32, // Offset(100), HD-Audio DSP Feature Mask + Offset(104), SBRG, 32, // Offset(104), SBREG_BAR + Offset(108), GPEM, 32, // Offset(108), GPP_X to GPE_DWX mapping + Offset(112), G2L0, 32, // Offset(112), GPE 2-tier level edged enabled Gpio pads (Group Index 0) + Offset(116), G2L1, 32, // Offset(116), GPE 2-tier level edged enabled Gpio pads (Group Index 1) + Offset(120), G2L2, 32, // Offset(120), GPE 2-tier level edged enabled Gpio pads (Group Index 2) + Offset(124), G2L3, 32, // Offset(124), GPE 2-tier level edged enabled Gpio pads (Group Index 3) + Offset(128), G2L4, 32, // Offset(128), GPE 2-tier level edged enabled Gpio pads (Group Index 4) + Offset(132), G2L5, 32, // Offset(132), GPE 2-tier level edged enabled Gpio pads (Group Index 5) + Offset(136), G2L6, 32, // Offset(136), GPE 2-tier level edged enabled Gpio pads (Group Index 6) + Offset(140), G2L7, 32, // Offset(140), GPE 2-tier level edged enabled Gpio pads (Group Index 7) + Offset(144), G2L8, 32, // Offset(144), GPE 2-tier level edged enabled Gpio pads (Group Index 8) + Offset(148), G2L9, 32, // Offset(148), GPE 2-tier level edged enabled Gpio pads (Group Index 9) + Offset(152), G2LA, 32, // Offset(152), GPE 2-tier level edged enabled Gpio pads (Group Index 10) + Offset(156), G2LB, 32, // Offset(156), GPE 2-tier level edged enabled Gpio pads (Group Index 11) + Offset(160), G2LC, 32, // Offset(160), GPE 2-tier level edged enabled Gpio pads (Groip Index 12) + + Offset(164), PML1, 16, // Offset(164), PCIE LTR max snoop Latency 1 + Offset(166), PML2, 16, // Offset(166), PCIE LTR max snoop Latency 2 + Offset(168), PML3, 16, // Offset(168), PCIE LTR max snoop Latency 3 + Offset(170), PML4, 16, // Offset(170), PCIE LTR max snoop Latency 4 + Offset(172), PML5, 16, // Offset(172), PCIE LTR max snoop Latency 5 + Offset(174), PML6, 16, // Offset(174), PCIE LTR max snoop Latency 6 + Offset(176), PML7, 16, // Offset(176), PCIE LTR max snoop Latency 7 + Offset(178), PML8, 16, // Offset(178), PCIE LTR max snoop Latency 8 + Offset(180), PML9, 16, // Offset(180), PCIE LTR max snoop Latency 9 + Offset(182), PMLA, 16, // Offset(182), PCIE LTR max snoop Latency 10 + Offset(184), PMLB, 16, // Offset(184), PCIE LTR max snoop Latency 11 + Offset(186), PMLC, 16, // Offset(186), PCIE LTR max snoop Latency 12 + Offset(188), PMLD, 16, // Offset(188), PCIE LTR max snoop Latency 13 + Offset(190), PMLE, 16, // Offset(190), PCIE LTR max snoop Latency 14 + Offset(192), PMLF, 16, // Offset(192), PCIE LTR max snoop Latency 15 + Offset(194), PMLG, 16, // Offset(194), PCIE LTR max snoop Latency 16 + Offset(196), PMLH, 16, // Offset(196), PCIE LTR max snoop Latency 17 + Offset(198), PMLI, 16, // Offset(198), PCIE LTR max snoop Latency 18 + Offset(200), PMLJ, 16, // Offset(200), PCIE LTR max snoop Latency 19 + Offset(202), PMLK, 16, // Offset(202), PCIE LTR max snoop Latency 20 + Offset(204), PNL1, 16, // Offset(204), PCIE LTR max no snoop Latency 1 + Offset(206), PNL2, 16, // Offset(206), PCIE LTR max no snoop Latency 2 + Offset(208), PNL3, 16, // Offset(208), PCIE LTR max no snoop Latency 3 + Offset(210), PNL4, 16, // Offset(210), PCIE LTR max no snoop Latency 4 + Offset(212), PNL5, 16, // Offset(212), PCIE LTR max no snoop Latency 5 + Offset(214), PNL6, 16, // Offset(214), PCIE LTR max no snoop Latency 6 + Offset(216), PNL7, 16, // Offset(216), PCIE LTR max no snoop Latency 7 + Offset(218), PNL8, 16, // Offset(218), PCIE LTR max no snoop Latency 8 + Offset(220), PNL9, 16, // Offset(220), PCIE LTR max no snoop Latency 9 + Offset(222), PNLA, 16, // Offset(222), PCIE LTR max no snoop Latency 10 + Offset(224), PNLB, 16, // Offset(224), PCIE LTR max no snoop Latency 11 + Offset(226), PNLC, 16, // Offset(226), PCIE LTR max no snoop Latency 12 + Offset(228), PNLD, 16, // Offset(228), PCIE LTR max no snoop Latency 13 + Offset(230), PNLE, 16, // Offset(230), PCIE LTR max no snoop Latency 14 + Offset(232), PNLF, 16, // Offset(232), PCIE LTR max no snoop Latency 15 + Offset(234), PNLG, 16, // Offset(234), PCIE LTR max no snoop Latency 16 + Offset(236), PNLH, 16, // Offset(236), PCIE LTR max no snoop Latency 17 + Offset(238), PNLI, 16, // Offset(238), PCIE LTR max no snoop Latency 18 + Offset(240), PNLJ, 16, // Offset(240), PCIE LTR max no snoop Latency 19 + Offset(242), PNLK, 16, // Offset(242), PCIE LTR max no snoop Latency 20 + Offset(244), U0C0, 32, // Offset(244), SerialIo Hidden UART0 BAR 0 + Offset(248), U1C0, 32, // Offset(248), SerialIo Hidden UART1 BAR 0 + Offset(252), ADPM, 32, // Offset(252), HD-Audio DSP Post-Processing Module Mask + Offset(256), XHPC, 8, // Offset(256), Number of HighSpeed ports implemented in XHCI controller + Offset(257), XRPC, 8, // Offset(257), Number of USBR ports implemented in XHCI controller + Offset(258), XSPC, 8, // Offset(258), Number of SuperSpeed ports implemented in XHCI controller + Offset(259), XSPA, 8, // Offset(259), Address of 1st SuperSpeed port + Offset(260), HPTB, 32, // Offset(260), HPET base address + Offset(264), HPTE, 8, // Offset(264), HPET enable + //110-bytes large SerialIo block + Offset(265), SMD0, 8, // Offset(265), SerialIo controller 0 (sdma) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(266), SMD1, 8, // Offset(266), SerialIo controller 1 (i2c0) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(267), SMD2, 8, // Offset(267), SerialIo controller 2 (i2c1) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(268), SMD3, 8, // Offset(268), SerialIo controller 3 (spi0) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(269), SMD4, 8, // Offset(269), SerialIo controller 4 (spi1) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(270), SMD5, 8, // Offset(270), SerialIo controller 5 (ua00) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(271), SMD6, 8, // Offset(271), SerialIo controller 6 (ua01) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(272), SMD7, 8, // Offset(272), SerialIo controller 7 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(273), SMD8, 8, // Offset(273), SerialIo controller 8 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(274), SMD9, 8, // Offset(274), SerialIo controller 9 (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(275), SMDA, 8, // Offset(275), SerialIo controller A (shdc) mode (0: disabled, 1: pci, 2: acpi, 3: debug port) + Offset(276), SIR0, 8, // Offset(276), SerialIo controller 0 (sdma) irq number + Offset(277), SIR1, 8, // Offset(277), SerialIo controller 1 (i2c0) irq number + Offset(278), SIR2, 8, // Offset(278), SerialIo controller 2 (i2c1) irq number + Offset(279), SIR3, 8, // Offset(279), SerialIo controller 3 (spi0) irq number + Offset(280), SIR4, 8, // Offset(280), SerialIo controller 4 (spi1) irq number + Offset(281), SIR5, 8, // Offset(281), SerialIo controller 5 (ua00) irq number + Offset(282), SIR6, 8, // Offset(282), SerialIo controller 6 (ua01) irq number + Offset(283), SIR7, 8, // Offset(283), SerialIo controller 7 (shdc) irq number + Offset(284), SIR8, 8, // Offset(284), SerialIo controller 8 (shdc) irq number + Offset(285), SIR9, 8, // Offset(285), SerialIo controller 9 (shdc) irq number + Offset(286), SIRA, 8, // Offset(286), SerialIo controller A (shdc) irq number + Offset(287), SB00, 32, // Offset(287), SerialIo controller 0 (sdma) BAR0 + Offset(291), SB01, 32, // Offset(291), SerialIo controller 1 (i2c0) BAR0 + Offset(295), SB02, 32, // Offset(295), SerialIo controller 2 (i2c1) BAR0 + Offset(299), SB03, 32, // Offset(299), SerialIo controller 3 (spi0) BAR0 + Offset(303), SB04, 32, // Offset(303), SerialIo controller 4 (spi1) BAR0 + Offset(307), SB05, 32, // Offset(307), SerialIo controller 5 (ua00) BAR0 + Offset(311), SB06, 32, // Offset(311), SerialIo controller 6 (ua01) BAR0 + Offset(315), SB07, 32, // Offset(315), SerialIo controller 7 (shdc) BAR0 + Offset(319), SB08, 32, // Offset(319), SerialIo controller 8 (shdc) BAR0 + Offset(323), SB09, 32, // Offset(323), SerialIo controller 9 (shdc) BAR0 + Offset(327), SB0A, 32, // Offset(327), SerialIo controller A (shdc) BAR0 + Offset(331), SB10, 32, // Offset(331), SerialIo controller 0 (sdma) BAR1 + Offset(335), SB11, 32, // Offset(335), SerialIo controller 1 (i2c0) BAR1 + Offset(339), SB12, 32, // Offset(339), SerialIo controller 2 (i2c1) BAR1 + Offset(343), SB13, 32, // Offset(343), SerialIo controller 3 (spi0) BAR1 + Offset(347), SB14, 32, // Offset(347), SerialIo controller 4 (spi1) BAR1 + Offset(351), SB15, 32, // Offset(351), SerialIo controller 5 (ua00) BAR1 + Offset(355), SB16, 32, // Offset(355), SerialIo controller 6 (ua01) BAR1 + Offset(359), SB17, 32, // Offset(359), SerialIo controller 7 (shdc) BAR1 + Offset(363), SB18, 32, // Offset(363), SerialIo controller 8 (shdc) BAR1 + Offset(367), SB19, 32, // Offset(367), SerialIo controller 9 (shdc) BAR1 + Offset(371), SB1A, 32, // Offset(371), SerialIo controller A (shdc) BAR1 + //end of SerialIo block + Offset(375), GPEN, 8, // Offset(375), GPIO enabled + Offset(376), SGIR, 8, // Offset(376), GPIO IRQ + Offset(377), NIT1, 8, // Offset(377), RST PCIe Storage Cycle Router#1 Interface Type + Offset(378), NIT2, 8, // Offset(378), RST PCIe Storage Cycle Router#2 Interface Type + Offset(379), NIT3, 8, // Offset(379), RST PCIe Storage Cycle Router#3 Interface Type + Offset(380), NPM1, 8, // Offset(380), RST PCIe Storage Cycle Router#1 Power Management Capability Pointer + Offset(381), NPM2, 8, // Offset(381), RST PCIe Storage Cycle Router#2 Power Management Capability Pointer + Offset(382), NPM3, 8, // Offset(382), RST PCIe Storage Cycle Router#3 Power Management Capability Pointer + Offset(383), NPC1, 8, // Offset(383), RST PCIe Storage Cycle Router#1 PCIe Capabilities Pointer + Offset(384), NPC2, 8, // Offset(384), RST PCIe Storage Cycle Router#2 PCIe Capabilities Pointer + Offset(385), NPC3, 8, // Offset(385), RST PCIe Storage Cycle Router#3 PCIe Capabilities Pointer + Offset(386), NL11, 16, // Offset(386), RST PCIe Storage Cycle Router#1 L1SS Capability Pointer + Offset(388), NL12, 16, // Offset(388), RST PCIe Storage Cycle Router#2 L1SS Capability Pointer + Offset(390), NL13, 16, // Offset(390), RST PCIe Storage Cycle Router#3 L1SS Capability Pointer + Offset(392), ND21, 8, // Offset(392), RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2 + Offset(393), ND22, 8, // Offset(393), RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2 + Offset(394), ND23, 8, // Offset(394), RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2 + Offset(395), ND11, 32, // Offset(395), RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1 + Offset(399), ND12, 32, // Offset(399), RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1 + Offset(403), ND13, 32, // Offset(403), RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1 + Offset(407), NLR1, 16, // Offset(407), RST PCIe Storage Cycle Router#1 LTR Capability Pointer + Offset(409), NLR2, 16, // Offset(409), RST PCIe Storage Cycle Router#2 LTR Capability Pointer + Offset(411), NLR3, 16, // Offset(411), RST PCIe Storage Cycle Router#3 LTR Capability Pointer + Offset(413), NLD1, 32, // Offset(413), RST PCIe Storage Cycle Router#1 Endpoint LTR Data + Offset(417), NLD2, 32, // Offset(417), RST PCIe Storage Cycle Router#2 Endpoint LTR Data + Offset(421), NLD3, 32, // Offset(421), RST PCIe Storage Cycle Router#3 Endpoint LTR Data + Offset(425), NEA1, 16, // Offset(425), RST PCIe Storage Cycle Router#1 Endpoint LCTL Data + Offset(427), NEA2, 16, // Offset(427), RST PCIe Storage Cycle Router#2 Endpoint LCTL Data + Offset(429), NEA3, 16, // Offset(429), RST PCIe Storage Cycle Router#3 Endpoint LCTL Data + Offset(431), NEB1, 16, // Offset(431), RST PCIe Storage Cycle Router#1 Endpoint DCTL Data + Offset(433), NEB2, 16, // Offset(433), RST PCIe Storage Cycle Router#2 Endpoint DCTL Data + Offset(435), NEB3, 16, // Offset(435), RST PCIe Storage Cycle Router#3 Endpoint DCTL Data + Offset(437), NEC1, 16, // Offset(437), RST PCIe Storage Cycle Router#1 Endpoint DCTL2 Data + Offset(439), NEC2, 16, // Offset(439), RST PCIe Storage Cycle Router#2 Endpoint DCTL2 Data + Offset(441), NEC3, 16, // Offset(441), RST PCIe Storage Cycle Router#3 Endpoint DCTL2 Data + Offset(443), NRA1, 16, // Offset(443), RST PCIe Storage Cycle Router#1 RootPort DCTL2 Data + Offset(445), NRA2, 16, // Offset(445), RST PCIe Storage Cycle Router#2 RootPort DCTL2 Data + Offset(447), NRA3, 16, // Offset(447), RST PCIe Storage Cycle Router#3 RootPort DCTL2 Data + Offset(449), NMB1, 32, // Offset(449), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR + Offset(453), NMB2, 32, // Offset(453), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR + Offset(457), NMB3, 32, // Offset(457), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR + Offset(461), NMV1, 32, // Offset(461), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value + Offset(465), NMV2, 32, // Offset(465), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value + Offset(469), NMV3, 32, // Offset(469), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value + Offset(473), NPB1, 32, // Offset(473), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR + Offset(477), NPB2, 32, // Offset(477), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR + Offset(481), NPB3, 32, // Offset(481), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR + Offset(485), NPV1, 32, // Offset(485), RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value + Offset(489), NPV2, 32, // Offset(489), RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value + Offset(493), NPV3, 32, // Offset(493), RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value + Offset(497), , 8, // Offset(497), Flag indicating Exit Boot Service, to inform SMM + Offset(498), SXRB, 32, // Offset(498), Sx handler reserved MMIO base + Offset(502), SXRS, 32, // Offset(502), Sx handler reserved MMIO size + Offset(506), CIOE, 8, // Offset(506), Cio2 Device Enabled as ACPI device + Offset(507), CIOI, 8, // Offset(507), Cio2 Interrupt Number + Offset(508), TAEN, 8, // Offset(508), Thermal Device Acpi mode enabled + Offset(509), TIRQ, 8, // Offset(509), Thermal Device IRQ number + Offset(510), XWMB, 32, // Offset(510), XHCI memory base address + Offset(514), EMH4, 8, // Offset(514), eMMC HS400 mode enabled + Offset(515), CSKU, 8, // Offset(515), CPU SKU + Offset(516), ITA0, 16, // Offset(516), + Offset(518), ITA1, 16, // Offset(518), + Offset(520), ITA2, 16, // Offset(520), + Offset(522), ITA3, 16, // Offset(522), + Offset(524), ITS0, 8, // Offset(524), + Offset(525), ITS1, 8, // Offset(525), + Offset(526), ITS2, 8, // Offset(526), + Offset(527), ITS3, 8, // Offset(527), + Offset(528), LTR1, 8, // Offset(528), Latency Tolerance Reporting Enable + Offset(529), LTR2, 8, // Offset(529), Latency Tolerance Reporting Enable + Offset(530), LTR3, 8, // Offset(530), Latency Tolerance Reporting Enable + Offset(531), LTR4, 8, // Offset(531), Latency Tolerance Reporting Enable + Offset(532), LTR5, 8, // Offset(532), Latency Tolerance Reporting Enable + Offset(533), LTR6, 8, // Offset(533), Latency Tolerance Reporting Enable + Offset(534), LTR7, 8, // Offset(534), Latency Tolerance Reporting Enable + Offset(535), LTR8, 8, // Offset(535), Latency Tolerance Reporting Enable + Offset(536), LTR9, 8, // Offset(536), Latency Tolerance Reporting Enable + Offset(537), LTRA, 8, // Offset(537), Latency Tolerance Reporting Enable + Offset(538), LTRB, 8, // Offset(538), Latency Tolerance Reporting Enable + Offset(539), LTRC, 8, // Offset(539), Latency Tolerance Reporting Enable + Offset(540), LTRD, 8, // Offset(540), Latency Tolerance Reporting Enable + Offset(541), LTRE, 8, // Offset(541), Latency Tolerance Reporting Enable + Offset(542), LTRF, 8, // Offset(542), Latency Tolerance Reporting Enable + Offset(543), LTRG, 8, // Offset(543), Latency Tolerance Reporting Enable + Offset(544), LTRH, 8, // Offset(544), Latency Tolerance Reporting Enable + Offset(545), LTRI, 8, // Offset(545), Latency Tolerance Reporting Enable + Offset(546), LTRJ, 8, // Offset(546), Latency Tolerance Reporting Enable + Offset(547), LTRK, 8, // Offset(547), Latency Tolerance Reporting Enable + Offset(548), OBF1, 8, // Offset(548), Optimized Buffer Flush and Fill + Offset(549), OBF2, 8, // Offset(549), Optimized Buffer Flush and Fill + Offset(550), OBF3, 8, // Offset(550), Optimized Buffer Flush and Fill + Offset(551), OBF4, 8, // Offset(551), Optimized Buffer Flush and Fill + Offset(552), OBF5, 8, // Offset(552), Optimized Buffer Flush and Fill + Offset(553), OBF6, 8, // Offset(553), Optimized Buffer Flush and Fill + Offset(554), OBF7, 8, // Offset(554), Optimized Buffer Flush and Fill + Offset(555), OBF8, 8, // Offset(555), Optimized Buffer Flush and Fill + Offset(556), OBF9, 8, // Offset(556), Optimized Buffer Flush and Fill + Offset(557), OBFA, 8, // Offset(557), Optimized Buffer Flush and Fill + Offset(558), OBFB, 8, // Offset(558), Optimized Buffer Flush and Fill + Offset(559), OBFC, 8, // Offset(559), Optimized Buffer Flush and Fill + Offset(560), OBFD, 8, // Offset(560), Optimized Buffer Flush and Fill + Offset(561), OBFE, 8, // Offset(561), Optimized Buffer Flush and Fill + Offset(562), OBFF, 8, // Offset(562), Optimized Buffer Flush and Fill + Offset(563), OBFG, 8, // Offset(563), Optimized Buffer Flush and Fill + Offset(564), OBFH, 8, // Offset(564), Optimized Buffer Flush and Fill + Offset(565), OBFI, 8, // Offset(565), Optimized Buffer Flush and Fill + Offset(566), OBFJ, 8, // Offset(566), Optimized Buffer Flush and Fill + Offset(567), OBFK, 8, // Offset(567), Optimized Buffer Flush and Fill + Offset(568), ECR1, 8, // Offset(568), External Change Request + Offset(569), AG1L, 64, // Offset(569), HDA PP module custom GUID 1 - first 64bit [0-63] + Offset(577), AG1H, 64, // Offset(577), HDA PP module custom GUID 1 - second 64bit [64-127] + Offset(585), AG2L, 64, // Offset(585), HDA PP module custom GUID 2 - first 64bit [0-63] + Offset(593), AG2H, 64, // Offset(593), HDA PP module custom GUID 2 - second 64bit [64-127] + Offset(601), AG3L, 64, // Offset(601), HDA PP module custom GUID 3 - first 64bit [0-63] + Offset(609), AG3H, 64, // Offset(609), HDA PP module custom GUID 3 - second 64bit [64-127] + Offset(617), MCFG, 32 // Offset(617), PcieMmCfgBaseAddress + } diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchPcie.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchPcie.asl new file mode 100644 index 0000000000..afe2237b4c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchPcie.asl @@ -0,0 +1,208 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + OperationRegion(PXCS,PCI_Config,0x00,0x480) + Field(PXCS,AnyAcc, NoLock, Preserve) + { + Offset(0), + VDID, 32, + Offset(0x50), // LCTL - Link Control Register + L0SE, 1, // 0, L0s Entry Enabled + , 3, + LDIS, 1, + , 3, + Offset(0x52), // LSTS - Link Status Register + , 13, + LASX, 1, // 0, Link Active Status + Offset(0x5A), // SLSTS[7:0] - Slot Status Register + ABPX, 1, // 0, Attention Button Pressed + , 2, + PDCX, 1, // 3, Presence Detect Changed + , 2, + PDSX, 1, // 6, Presence Detect State + , 1, + Offset(0x60), // RSTS - Root Status Register + , 16, + PSPX, 1, // 16, PME Status + Offset(0xA4), + D3HT, 2, // Power State + Offset(0xD8), // MPC - Miscellaneous Port Configuration Register + , 30, + HPEX, 1, // 30, Hot Plug SCI Enable + PMEX, 1, // 31, Power Management SCI Enable + Offset(0xE2), // RPPGEN - Root Port Power Gating Enable + , 2, + L23E, 1, // 2, L23_Rdy Entry Request (L23ER) + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + Offset(0x324), + , 3, + LEDM, 1, // PCIEDBG.DMIL1EDM + Offset(0x420), // Offset 420h: PCIEPMECTL - PCIe PM Extension Control + , 30, + DPGE, 1, // PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane Power Gating Enable (DLSULPPGE): + } + Field(PXCS,AnyAcc, NoLock, WriteAsZeros) + { + Offset(0xDC), // SMSCS - SMI/SCI Status Register + , 30, + HPSX, 1, // 30, Hot Plug SCI Status + PMSX, 1 // 31, Power Management SCI Status + } + + + Name(LTRV, Package(){0,0,0,0}) + + // + // _DSM Device Specific Method + // + // Arg0: UUID Unique function identifier + // Arg1: Integer Revision Level + // Arg2: Integer Function Index (0 = Return Supported Functions) + // Arg3: Package Parameters + Method(_DSM, 4, Serialized) { + // + // Switch based on which unique function identifier was passed in + // + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) { + // + // _DSM Definitions for Latency Tolerance Reporting + // + // Arguments: + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D + // Arg1: Revision ID: 2 + // Arg2: Function Index: 1, 4 or 6 + // Arg3: Empty Package + // + // Return: + // A Package of four integers corresponding with the LTR encoding defined + // in the PCI Express Base Specification, as follows: + // Integer 0: Maximum Snoop Latency Scale + // Integer 1: Maximum Snoop Latency Value + // Integer 2: Maximum No-Snoop Latency Scale + // Integer 3: Maximum No-Snoop Latency Value + // These values correspond directly to the LTR Extended Capability Structure + // fields described in the PCI Express Base Specification. + // + // + // Switch by function index + // + Switch(ToInteger(Arg2)) { + // + // Function Index:0 + // Standard query - A bitmask of functions supported + // + Case (0) { + Name(OPTS,Buffer(2){0,0}) + CreateBitField(OPTS,0,FUN0) + CreateBitField(OPTS,4,FUN4) + CreateBitField(OPTS,6,FUN6) + CreateBitField(OPTS,8,FUN8) + CreateBitField(OPTS,9,FUN9) + + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + Store(1,FUN0) + if (LTRE){ + Store(1,Fun6) + } + if (OBFF){ + Store(1,Fun4) + } + if(LEqual(ECR1,1)){ + if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID: 3 + Store(1,Fun8) + Store(1,Fun9) + } + } + } + Return (OPTS) + } + // + // Function Index: 4 + // + Case(4) { + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (OBFN){ + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,8,0,0,0,0}) // OBFF capable, offset 4[08h] + } else { + Return (Buffer () {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}) + } + } + } + // + // Function Index: 6 + // LTR Extended Capability Structure + // + Case(6) { + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2 + if (LTRN){ + if (LOr(LEqual(LMSL, 0),LEqual(LNSL, 0))) + { + if (LEqual (PCHS, SPTH)) { + Store (0x0846, LMSL) + Store (0x0846, LNSL) + } elseif (LEqual (PCHS, SPTL)) { + Store (0x1003, LMSL) + Store (0x1003, LNSL) + } + } + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0)) + Store(And(LMSL,0x3FF), Index(LTRV, 1)) + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2)) + Store(And(LNSL,0x3FF), Index(LTRV, 3)) + + Return (LTRV) + } else { + Return (0) + } + } + } + Case(8) { //ECR ACPI additions for FW latency optimizations, DSM for Avoiding Power-On Reset Delay Duplication on Sx Resume + if(LEqual(ECR1,1)){ + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3 + return (1) + } + } + } + Case(9) { //ECR ACPI additions for FW latency optimizations, DSM for Specifying Device Readiness Durations + if(LEqual(ECR1,1)){ + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: 3 + return(Package(5){50000,Ones,Ones,50000,Ones}) + } + } + } + } // End of switch(Arg2) + } // End of if + return (Buffer() {0x00}) + } // End of _DSM + + Device(PXSX) + { + Name(_ADR, 0x00000000) + + // NOTE: Any PCIE Hot-Plug dependency for this port is + // specific to the CRB. Please modify the code based on + // your platform requirements. + Method(_PRW, 0) { Return(GPRW(0x09, 4)) } // can wakeup from S4 state + } + + // + // PCI_EXP_STS Handler for PCIE Root Port + // + Method(HPME,0,Serialized) { + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exists and has PME SCI Status set... + Notify (PXSX, 0x2) //notify child device; this will cause its driver to clear PME_Status from device + Store(1,PMSX) // clear rootport's PME SCI status + Store(1,PSPX) // consume one pending PME notification to prevent it from blocking the queue + } + } + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchRstPcieStorage.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchRstPcieStorage.asl new file mode 100644 index 0000000000..bef1a7e82a --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchRstPcieStorage.asl @@ -0,0 +1,222 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#define PCI_CARD_BASE_ADDR0 0x10 +#define PCI_CARD_BASE_ADDR1 0x14 +#define PCI_CARD_BASE_ADDR2 0x18 +#define PCI_CARD_BASE_ADDR3 0x1C +#define PCI_CARD_BASE_ADDR4 0x20 +#define PCI_CARD_BASE_ADDR5 0x24 + + //RST Pcie Storage Remapped Base Address Index Value + Name(PRBI, 0) + + //RST Pcie Storage Remapped Base Address Data Value + Name(PRBD, 0) + + //RST Pcie Storage Endpoint Command Data + Name(PCMD, 0) + + //RST Pcie Storage Cycle Router + Name(NCRN, 0) + + // + // Variables list to store corresponding value for different NVM device + // + Name(NITV, 0) // Interface Type + Name(NPMV, 0) // Power Management Capability Pointer + Name(NPCV, 0) // PCIe Capabilities Pointer + Name(NL1V, 0) // L1SS Capability Pointer + Name(ND2V, 0) // Endpoint L1SS Control Data2 + Name(ND1V, 0) // Endpoint L1SS Control Data1 + Name(NLRV, 0) // LTR Capability Pointer + Name(NLDV, 0) // Endpoint LTR Data + Name(NEAV, 0) // Endpoint LCTL Data + Name(NEBV, 0) // Endpoint DCTL Data + Name(NECV, 0) // Endpoint DCTL2 Data + Name(NRAV, 0) // RootPort DCTL2 Data + Name(NMBV, 0) // Endpoint unique MSI-X Table BAR + Name(NMVV, 0) // Endpoint unique MSI-X Table BAR value + Name(NPBV, 0) // Endpoint unique MSI-X PBA BAR + Name(NPVV, 0) // Endpoint unique MSI-X PBA BAR value + + Method(EPD0, 0, Serialized) // Put Remapped Device into D0 state + { + RDCA(NCRN,Add(NPMV,0x04),0xFFFFFFFC,0x0,ENDPOINT_WRITE) + } + + Method(EPD3, 0, Serialized) // Put Remapped Device into D3 state + { + RDCA(NCRN,Add(NPMV,0x04),0xFFFFFFFC,0x3,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device and Hidden Root Port + // This method is called after the endpoint is to be power ungated (D3-cold to D0 unitialized) + // + Method(CNRS, 0, Serialized) + { + // + // Return if RST Pcie Storage Remapping is disabled + // + If(LEqual(NITV,0)) + { + Return(0) + } + + // + // Clear all BARs in Remapped Device + // + RDCA(NCRN,PCI_CARD_BASE_ADDR0,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR1,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR2,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR3,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR4,0x0,0x0,ENDPOINT_WRITE) + RDCA(NCRN,PCI_CARD_BASE_ADDR5,0x0,0x0,ENDPOINT_WRITE) + + // + // Restore Endpoint CMD and remapped BAR + // + RDCA(NCRN,0x4,0xFFFFFFF8,PCMD,ENDPOINT_WRITE) + RDCA(NCRN,PRBI,0x0,PRBD,ENDPOINT_WRITE) + + // + // Restore of Remapped Device L1 Substate if this Capability is supported + // + If(LNotEqual(NL1V,0)) + { + RDCA(NCRN,Add(NL1V,0x0C),0xFFFFFF00,ND2V,ENDPOINT_WRITE) + RDCA(NCRN,Add(NL1V,0x08),0x0000000F,And(ND1V,0xFFFFFFF0),ENDPOINT_WRITE) + RDCA(NCRN,Add(NL1V,0x08),0xFFFFFFFF,ND1V,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device LTR if this Capability is supported + // + If(LNotEqual(NLRV,0)) + { + RDCA(NCRN,Add(NLRV,0x04),0xFFFFFFFF,NLDV,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device Link Control's "Enable Clock Power Management" field and "Common Clock Configuration" field + // + RDCA(NCRN,Add(NPCV,0x10),0xFFFFFEBF,And(NEAV,0xFFFC),ENDPOINT_WRITE) + + // + // Restore of Remapped Device Device Control 2 field + // + RDCA(NCRN,Add(NPCV,0x28),0xFFFFFBFF,NECV,ENDPOINT_WRITE) + + // + // Restore of Remapped Device Device Control field + // + RDCA(NCRN,Add(NPCV,0x8),0xFFFFFF1F,NEBV,ENDPOINT_WRITE) + + // + // Restore of Hidden Root Port field + // + RDCA(NCRN,0x68,0xFFFFFBFF,NRAV,ROOTPORT_WRITE) + + // + // Check CCC bit + // If this bit is 1, perform link retrain by setting the "Retrain Link" bit + // + If(LEqual(And(NEAV,0x40),0x40)) + { + RDCA(NCRN,0x50,0xFFFFFFDF,0x20,ROOTPORT_WRITE) + // + // Poll PCIe Link Active status till it is active + // + while(LEqual(And(RDCA(NCRN,0x52,0x0,0x0,ROOTPORT_READ),0x2000),0)) + { + Stall(10) + } + } + + // + // Restore of Remapped Device Link Control's "Active State Link PM Control" field + // + RDCA(NCRN,Add(NPCV,0x10),0xFFFFFFFC,And(NEAV,0x0003),ENDPOINT_WRITE) + + // + // Restore of Remapped Device related device BAR for the MSI-X Table BAR if the device supports unique MSI-X Table BAR + // + If(LNotEqual(NMVV,0)) + { + RDCA(NCRN,NMBV,0x0,NMVV,ENDPOINT_WRITE) + } + + // + // Restore of Remapped Device related device BAR for the MSI-X PBA BAR if the device supports unique MSI-X PBA BAR + // + If(LNotEqual(NPVV,0)) + { + RDCA(NCRN,NPBV,0x0,NPVV,ENDPOINT_WRITE) + } + //Fix warning: not all control paths return a value + Return(0) + } + + Method(_PS3,0,Serialized) + { + // + // Return if RST Pcie Storage Remapping is disabled + // + If(LEqual(NITV,0)) + { + //Fix warning: restricted method should not return a value + + } + + // + // Store Endpoint CMD and remapped BAR for CNRS() restoration + // + Store(RDCA(NCRN,0x4,0x0,0x0,ENDPOINT_READ),PCMD) + If(LEqual(NITV,1)) // Store BAR5 if Endpoint is AHCI Interface + { + Store(0x24,PRBI) + Store(RDCA(NCRN,0x24,0x0,0x0,ENDPOINT_READ),PRBD) + } + ElseIf(LEqual(NITV,2)) // Store BAR0 if Endpoint is NVMe Interface + { + Store(0x10,PRBI) + Store(RDCA(NCRN,0x10,0x0,0x0,ENDPOINT_READ),PRBD) + } + + EPD3() + RPD3(NCRN) + } + + Method(_PS0,0,Serialized) + { + // + // Return if RST Pcie Storage Remapping is disabled + // + If(LEqual(NITV,0)) + { + //Fix warning: restricted method should not return a value + } + RPD0(NCRN) + EPD0() + + // + // Check NSR bit in PMCS + // If this bit is 0, invoke CNRS() to perform restoration on the remapped device and hidden root port + // + Store(RDCA(NCRN,Add(NPMV,0x04),0x0,0x0,ENDPOINT_READ),Local0) + If(LEqual(And(Local0,0x8),0)) + { + CNRS() + } + } diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchSata.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchSata.asl new file mode 100644 index 0000000000..e28d8e25b7 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchSata.asl @@ -0,0 +1,227 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#define ROOTPORT_READ 0 +#define ROOTPORT_WRITE 1 +#define ENDPOINT_READ 2 +#define ENDPOINT_WRITE 3 + +// +// SDSM is Device Specific Method supporting AHCI DEVSLP +// It is not guaranteed to be available on every boot +// +// move one level up to Pch.asl + + Method(_DSM,4,serialized){ + if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }; + if(CondRefOf(\_SB.PC00.SAT0.SDSM)) { return (\_SB.PC00.SAT0.SDSM(Arg0,Arg1,Arg2,Arg3)) }; + return(0) + } + + Device(PRT0) + { + Name(_ADR,0x0000FFFF) // Port 0 + } + Device(PRT1) + { + Name(_ADR,0x0001FFFF) // Port 1 + } + Device(PRT2) + { + Name(_ADR,0x0002FFFF) // Port 2 + } + Device(PRT3) + { + Name(_ADR,0x0003FFFF) // Port 3 + } + Device(PRT4) + { + Name(_ADR,0x0004FFFF) // Port 4 + } + Device(PRT5) + { + Name(_ADR,0x0005FFFF) // Port 5 + } + + // + // Method to perform RST PCIe Storage Remapping read or write access to the remapped device / hidden root port configuration space + // This method takes 5 parameters as below: + // Arg0 - RST PCIe Storage Cycle Router# + // Arg1 - PCI Offset + // Arg2 - WriteData (AndMask) + // Arg3 - WriteData (OrMask) + // Arg4 - Access Methods: ROOTPORT_READ, ROOTPORT_WRITE, ENDPOINT_READ, ENDPOINT_WRITE + // + Method(RDCA, 5, Serialized) + { + // + // Operation Region for Sata Extended Config Space for Hidden Root Port Access + // + OperationRegion(RPAL, SystemMemory, Add(\_SB.PC00.GPCB(), Add(0xB8100,Arg1)), 0x4) + Field(RPAL,DWordAcc,Lock,Preserve) + { + RPCD, 32, + } + + // + // Operation Region for Endpoint Index-Data Pair for Remapped Device Access + // + OperationRegion(EPAC, SystemMemory, Add(\_SB.PC00.GPCB(),0xB8308), 0x8) + Field(EPAC,DWordAcc,Lock,Preserve) + { + CAIR, 32, + CADR, 32, + } + + // + // Operation Region for RST PCIe Storage Cycle Router Global configuration registers + // + OperationRegion(NCRG, SystemMemory, Add(\_SB.PC00.GPCB(),0xB8FC0), 0x4) + Field(NCRG,DWordAcc,Lock,Preserve) + { + CRGC, 32, + } + + If (LGreater(Arg0, 2)) // Return if RST PCIe Storage Cycle Router# is invalid + { + Return(0) + } + Else // Set RST PCIe Storage Cycle Router Accessibility based on Arg0 - RST PCIe Storage Cycle Router# + { + Store(Arg0,CRGC) + } + + Switch(ToInteger(Arg4)) + { + Case(ROOTPORT_READ) // Read access to the Hidden Root Port + { + Return(RPCD) + } + Case(ENDPOINT_READ) // Read access to the Remapped Device + { + Store(Arg1,CAIR) + Return(CADR) + } + Case(ROOTPORT_WRITE) // Write access to the Hidden Root Port + { + And(Arg2,RPCD,Local0) + Or(Arg3,Local0,Local0) + Store(Local0,RPCD) + } + Case(ENDPOINT_WRITE) // Write access to the Remapped Device + { + Store(Arg1,CAIR) + And(Arg2,CADR,Local0) + Or(Arg3,Local0,Local0) + Store(Local0,CADR) + } + Default + { + Return(0) + } + } + //Fix warning: not all control paths return a value + Return(0) + } + + Method(RPD0, 1, Serialized) // Put Hidden Root Port into D0 state + { + RDCA(Arg0,0xA4,0xFFFFFFFC,0x0,ROOTPORT_WRITE) + } + + Method(RPD3, 1, Serialized) // Put Hidden Root Port into D3 state + { + RDCA(Arg0,0xA4,0xFFFFFFFC,0x3,ROOTPORT_WRITE) + } + + Device(NVM1) + { + Name(_ADR,0x00C1FFFF) + + Include("PchRstPcieStorage.asl") + Method(_INI) + { + Store (NIT1, NITV) + Store (NPM1, NPMV) + Store (NPC1, NPCV) + Store (NL11, NL1V) + Store (ND21, ND2V) + Store (ND11, ND1V) + Store (NLR1, NLRV) + Store (NLD1, NLDV) + Store (NEA1, NEAV) + Store (NEB1, NEBV) + Store (NEC1, NECV) + Store (NRA1, NRAV) + Store (NMB1, NMBV) + Store (NMV1, NMVV) + Store (NPB1, NPBV) + Store (NPV1, NPVV) + Store (0, NCRN) + } + } + + Device(NVM2) + { + Name(_ADR,0x00C2FFFF) + + Include("PchRstPcieStorage.asl") + Method(_INI) + { + Store (NIT2, NITV) + Store (NPM2, NPMV) + Store (NPC2, NPCV) + Store (NL12, NL1V) + Store (ND22, ND2V) + Store (ND12, ND1V) + Store (NLR2, NLRV) + Store (NLD2, NLDV) + Store (NEA2, NEAV) + Store (NEB2, NEBV) + Store (NEC2, NECV) + Store (NRA2, NRAV) + Store (NMB2, NMBV) + Store (NMV2, NMVV) + Store (NPB2, NPBV) + Store (NPV2, NPVV) + Store (1, NCRN) + } + } + + Device(NVM3) + { + Name(_ADR,0x00C3FFFF) + + Include("PchRstPcieStorage.asl") + Method(_INI) + { + Store (NIT3, NITV) + Store (NPM3, NPMV) + Store (NPC3, NPCV) + Store (NL13, NL1V) + Store (ND23, ND2V) + Store (ND13, ND1V) + Store (NLR3, NLRV) + Store (NLD3, NLDV) + Store (NEA3, NEAV) + Store (NEB3, NEBV) + Store (NEC3, NECV) + Store (NRA3, NRAV) + Store (NMB3, NMBV) + Store (NMV3, NMVV) + Store (NPB3, NPBV) + Store (NPV3, NPVV) + Store (2, NCRN) + } + } + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchScs.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchScs.asl new file mode 100644 index 0000000000..154b2c5366 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchScs.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Storage and Communication Subsystems definitions is not supported in Server diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchSerialIo.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchSerialIo.asl new file mode 100644 index 0000000000..26cabf3ad0 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchSerialIo.asl @@ -0,0 +1,13 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchXdci.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchXdci.asl new file mode 100644 index 0000000000..0ea61b471c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchXdci.asl @@ -0,0 +1,14 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + //XDCI is not used in Server diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchXhci.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchXhci.asl new file mode 100644 index 0000000000..d304539d78 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/PchXhci.asl @@ -0,0 +1,565 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +External(\_SB.PC00.XHCI.PS0X, MethodObj) +External(\_SB.PC00.XHCI.PS3X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.PS0X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.PS2X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.PS3X, MethodObj) +External(\_SB.PC00.XHCI.RHUB.INIR, MethodObj) +External(\_SB.PC00.XHCI.XHCS, MethodObj) + + +Scope(\_SB_.PC00.XHCI) { + + OperationRegion(XPRT,PCI_Config,0x00,0x100) + Field(XPRT,AnyAcc,NoLock,Preserve) + { + DVID, 16, + Offset(0x74), + D0D3, 2, // 0x74 BIT[1:0] + , 6, + PMEE, 1, // PME Enable + , 6, + PMES, 1, // PME Status + Offset(0xA8), // SSCFG Reg for WPTLP + , 13, + MW13, 1, // 0xA8 BIT[13] + MW14, 1, // 0xA8 BIT[14] + , 17, + Offset(0xB0), // SSCFG Reg for LPTLP + , 13, + MB13, 1, // 0xB0 BIT[13] + MB14, 1, // 0xB0 BIT[14] + , 17, + Offset(0xD0), + PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register. + PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register. + PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register. + PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register + } + + // + // Variable to store the maximum D state supported in S0. + // + Name (XFLT, 0) + // + // XHCI controller won't go into D3Hot during S0 until _DSM method is evaluated by filter driver. + // + Method(_DSM,4,serialized){ + If(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } + // + // Check GUID ac340cb7-e901-45bf-b7e6-2b34ec931e23 + // + If(LEqual(Arg0, Buffer(0x10) { 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45, 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23 })) + { + // + // Only Supported value is "0x3" + // + If(LEqual(Arg1, 0x3)) + { + Store(Arg1,XFLT) + } + } + return(0) + } + + Method(_S3D, 0, NotSerialized) + { + Return(3) + } + Method(_S4D, 0, NotSerialized) + { + Return(3) + } + Method(_S3W, 0, NotSerialized) + { + Return(3) + } + Method(_S4W, 0, NotSerialized) + { + Return(3) + } + + // + // Once the filter driver is installed, D3 is allowed. + // + Method(_S0W, 0x0, NotSerialized) + { + If(LEqual(XFLT, Zero)) + { + Return(0x0) + } + Else + { + Return(0x3) + } + } + + Method(_PRW, 0) + { + Return(GPRW(0x6D, 4)) // can wakeup from S4 state + } + + Method(_DSW, 3) + { + Store(Arg0, PMEE) + } + + Method(_INI) { + // _INI for RTD3 run conditionally if implemented in platform specific code + If(CondRefOf(\_SB.PC00.XHCI.RHUB.INIR)) { // _INI for RTD3 + \_SB.PC00.XHCI.RHUB.INIR() + } + } + + // + // GPE handler for XHCI, this is part of _Lxx handler for bus 0 PME + // + Method(GPEH) + { + If(LEqual(DVID, 0xFFFF)) { + Return() + } + Store(PMES, Local0) + Store(1, PMES) // clear PME Status + If(LAnd(PMEE, Local0)) { + Notify(XHCI, 0x02) + } + } + + OperationRegion(XHCP, SystemMemory, Add(\_SB.PC00.GPCB(), 0xA0000), 0x100) + Field(XHCP,AnyAcc,Lock,Preserve) + { + Offset(0x4), + PDBM, 16, + Offset(0x10), + MEMB, 64 + } + + // + // USRA (USbR port Address), method for calculating address of first USBR port in XHCI controller + // + Method(USRA,0,Serialized) { + If(LEqual(PCHV, SPTH)) { // SPT-H + Return (15) + } Else { // SPT-LP + Return (11) + } + } + + // + // SSPA (SuperSpeed Port Address), method for calculating address of first SS port in XHCI controller + // + Method(SSPA,0,Serialized) { + If(LEqual(PCHV, SPTH)) { // SPT-H + Return (17) + } Else { // SPT-LP + Return (13) + } + } + + Name(XRST, Zero) + + Method(_PS0,0,Serialized) + { + + If(LEqual(^DVID,0xFFFF)) + { + Return() + } + + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + // + // Switch to D0 + // + Store(0,^D0D3) + + Store(\XWMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + // + // + // + + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + + // + // Call platform XHC PS0 method if present + // + If(CondRefOf(\_SB.PC00.XHCI.PS0X)) + { + \_SB.PC00.XHCI.PS0X() + } + // + // + If(LAnd(UWAB,LEqual(D0D3,0))) { + + // + // If the USB WA Bit is set and any XHCI or XDCI controller is in D0 + // + // + // USB2 PHPY Power Gating - SW WA + // + // 1. BIOS writes a new command to the MTPMC register to cause the PMC to disable power gating + Store(1,MPMC) + + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0 + // In parallel and in response to the previous command from BIOS, PMC FW will: + // * Make the USB2 force common lane PG match the BIOS policy (common lane PG disallowed) + // * Disable SUS power gating in XHCI + // * Wait for USB2 PHY side_pok to be 1 + // * Disable core power gating in USB2 PHY + // * Disable common lane power gating in USB2 PHY (probably not necessary, consider removal) + // * Wait for USB2 SUS restoration status to be set, and do USB2 SUS power gating restoration + // * Get the PHY in the correct state before allowing transition to D0. + // * Clear MSG_FULL_STS + // BIOS sees MSG_FULL_STS clear and exits the method + // + While(PMFS) { + Sleep(10) + } + } // End If(UWAB) + + } + + Method(_PS3,0,Serialized) + { + + If(LEqual(^DVID,0xFFFF)) + { + Return() + } + + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + // + // Switch back to D0 + // + Store(0,^D0D3) + + Store(\XWMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + // + // + // + + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + + // + // Switch back to D3 + // + Store(3,^D0D3) + + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + + // + // Call platform XHC PS3 method if present + // + If(CondRefOf(\_SB.PC00.XHCI.PS3X)) + { + \_SB.PC00.XHCI.PS3X() + } + If(LAnd(UWAB,LEqual(D0D3,3))) { + // + // If the USB WA Bit is set and XHCI is in D3 + // + + // 1. BIOS writes a new command to the MTPMC register to enable power gating + Store(3,MPMC) + + // 2. BIOS waits for PCH_PM_STS.MSG_FULL_STS to be 0 + // In parallel and in response to the previous command from BIOS, PMC FW will: + // * Make the USB2 force common lane PG match the BIOS policy (common lane PG allowed) + // * Enable SUS power gating in XHCI + // * Enable core power gating in USB2 PHY + // * Enable common lane power gating in the USB2 PHY + // * Clear MSG_FULL_STS + // BIOS sees MSG_FULL_STS clear and exits the method + // + While(PMFS) { + Sleep(10) + } + } // End If(UWAB) + } + + + // Apply S3 workaround. + // Arguments : + // None + // Changes 8090 Bit 10 before S3. + // + Method(XHCS,0, Serialized) { + Store(^MEMB,Local2) // Save MBAR + Store(^PDBM,Local1) // Save CMD + + And(^PDBM,Not(0x06),^PDBM) // Clear MSE/BME + + Store(\XWMB,^MEMB) // Set MBAR + Or(Local1,0x0002,^PDBM) // Set MSE + + OperationRegion(MC11,SystemMemory,\XWMB,0x9000) + Field(MC11,DWordAcc,Lock,Preserve) + { + Offset(0x8090), // HC Transfer Manager - TRM + , 10, + UCLI, 1, // CLEAR IN EP + } + + Store(0x1,UCLI) + + And(^PDBM,Not(0x02),^PDBM) // Clear MSE + + Store(Local2,^MEMB) // Restore MBAR + Store(Local1,^PDBM) // Restore CMD + + } + + // + // + // Check for XHCI switch UUID + // + // Arguments: + // Arg0 (Buffer) : UUID + // + // Returns: + // 1: It's valid UUID + // 0: Invalid UUID + // + Method(CUID,1,Serialized) { + If(LEqual(Arg0,ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { + Return(1) + } + Return(0) + } + + Device(RHUB) + { + Name(_ADR, Zero) + + // PS0 Method for xHCI Root Hub + Method(_PS0,0,Serialized) + { + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF)) + { + Return() + } + // + // Call platform XHC.RHUB PS0 method if present. + // + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS0X)) + { + \_SB.PC00.XHCI.RHUB.PS0X() + } + } + + // PS2 Method for xHCI Root Hub + Method(_PS2,0,Serialized) + { + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF)) + { + Return() + } + // + // Call platform XHC.RHUB PS2 method if present. + // + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS2X)) + { + \_SB.PC00.XHCI.RHUB.PS2X() + } + } + + // PS3 Method for xHCI Root Hub + Method(_PS3,0,Serialized) + { + If(LEqual(\_SB.PC00.XHCI.DVID,0xFFFF)) + { + Return() + } + // + // Call platform XHC.RHUB PS3 method if present. + // + If(CondRefOf(\_SB.PC00.XHCI.RHUB.PS3X)) + { + \_SB.PC00.XHCI.RHUB.PS3X() + } + } + + // + // High Speed Ports (without USBR) + // + Device(HS01) + { + Name(_ADR, 0x01) + } + + Device(HS02) + { + Name(_ADR, 0x02) + } + + Device(HS03) + { + Name(_ADR, 0x03) + } + + Device(HS04) + { + Name(_ADR, 0x04) + } + + Device(HS05) + { + Name(_ADR, 0x05) + } + + Device(HS06) + { + Name(_ADR, 0x06) + } + + Device(HS07) + { + Name(_ADR, 0x07) + } + + Device(HS08) + { + Name(_ADR, 0x08) + } + + Device(HS09) + { + Name(_ADR, 0x09) + } + + Device(HS10) + { + Name(_ADR, 0x0A) + } + + // + // USBR port will be known as USBR instead of HS09 / HS15 + // + Device(USR1) + { + Method(_ADR) { Return (Add(USRA(),0)) } + } + + // + // USBR port 2 will be known as USBR instead of xxxx + // + Device(USR2) + { + Method(_ADR) { Return (Add(USRA(),1)) } + } + + // + // Super Speed Ports + // + Device(SS01) + { + Method(_ADR) { Return (Add(SSPA(),0)) } + } + + Device(SS02) + { + Method(_ADR) { Return (Add(SSPA(),1)) } + } + + Device(SS03) + { + Method(_ADR) { Return (Add(SSPA(),2)) } + } + + Device(SS04) + { + Method(_ADR) { Return (Add(SSPA(),3)) } + } + + Device(SS05) + { + Method(_ADR) { Return (Add(SSPA(),4)) } + } + + Device(SS06) + { + Method(_ADR) { Return (Add(SSPA(),5)) } + } + + } // device rhub +} //scope + +// +// SPT-H +// + + Scope(\_SB_.PC00.XHCI.RHUB) { + + + + Device(HS11) + { + Name(_ADR, 0xB) + } + + + Device(HS12) + { + Name(_ADR, 0xC) + } + + Device(HS13) + { + Name(_ADR, 0xD) + } + + Device(HS14) + { + Name(_ADR, 0xE) + } + + Device(SS07) + { + Method(_ADR) { Return (Add(SSPA(),6)) } + } + + Device(SS08) + { + Method(_ADR) { Return (Add(SSPA(),7)) } + } + + Device(SS09) + { + Method(_ADR) { Return (Add(SSPA(),8)) } + } + + Device(SS10) + { + Method(_ADR) { Return (Add(SSPA(),9)) } + } + + } //scope + diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP01_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP01_ADR.asl new file mode 100644 index 0000000000..b02b4c5583 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP01_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA1,0)) { + Return (RPA1) + } Else { + Return (0x001C0000) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP02_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP02_ADR.asl new file mode 100644 index 0000000000..a433c1c17d --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP02_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA2,0)) { + Return (RPA2) + } Else { + Return (0x001C0001) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP03_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP03_ADR.asl new file mode 100644 index 0000000000..cbbb144020 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP03_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA3,0)) { + Return (RPA3) + } Else { + Return (0x001C0002) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP04_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP04_ADR.asl new file mode 100644 index 0000000000..6ebdaf3b68 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP04_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA4,0)) { + Return (RPA4) + } Else { + Return (0x001C0003) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP05_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP05_ADR.asl new file mode 100644 index 0000000000..83ab65b9e7 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP05_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA5,0)) { + Return (RPA5) + } Else { + Return (0x001C0004) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP06_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP06_ADR.asl new file mode 100644 index 0000000000..a64cc6af86 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP06_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA6,0)) { + Return (RPA6) + } Else { + Return (0x001C0005) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP07_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP07_ADR.asl new file mode 100644 index 0000000000..6d9507498f --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP07_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA7,0)) { + Return (RPA7) + } Else { + Return (0x001C0006) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP08_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP08_ADR.asl new file mode 100644 index 0000000000..306e439847 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP08_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA8,0)) { + Return (RPA8) + } Else { + Return (0x001C0007) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP09_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP09_ADR.asl new file mode 100644 index 0000000000..1330fbc454 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP09_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPA9,0)) { + Return (RPA9) + } Else { + Return (0x001D0000) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP10_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP10_ADR.asl new file mode 100644 index 0000000000..3320113a81 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP10_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAA,0)) { + Return (RPAA) + } Else { + Return (0x001D0001) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP11_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP11_ADR.asl new file mode 100644 index 0000000000..81c781ddad --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP11_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAB,0)) { + Return (RPAB) + } Else { + Return (0x001D0002) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP12_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP12_ADR.asl new file mode 100644 index 0000000000..21bf23efbe --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP12_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAC,0)) { + Return (RPAC) + } Else { + Return (0x001D0003) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP13_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP13_ADR.asl new file mode 100644 index 0000000000..f210d57b3b --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP13_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAD,0)) { + Return (RPAD) + } Else { + Return (0x001D0004) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP14_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP14_ADR.asl new file mode 100644 index 0000000000..28f1864d18 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP14_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAE,0)) { + Return (RPAE) + } Else { + Return (0x001D0005) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP15_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP15_ADR.asl new file mode 100644 index 0000000000..10475cecbc --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP15_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAF,0)) { + Return (RPAF) + } Else { + Return (0x001D0006) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP16_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP16_ADR.asl new file mode 100644 index 0000000000..2818ce3614 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP16_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAG,0)) { + Return (RPAG) + } Else { + Return (0x001D0007) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP17_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP17_ADR.asl new file mode 100644 index 0000000000..93fcc35ead --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP17_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAH,0)) { + Return (RPAH) + } Else { + Return (0x001B0000) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP18_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP18_ADR.asl new file mode 100644 index 0000000000..cbc5c9f3f5 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP18_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAI,0)) { + Return (RPAI) + } Else { + Return (0x001B0001) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP19_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP19_ADR.asl new file mode 100644 index 0000000000..f98acfb11a --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP19_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAJ,0)) { + Return (RPAJ) + } Else { + Return (0x001B0002) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP20_ADR.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP20_ADR.asl new file mode 100644 index 0000000000..e26cf90e3a --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/RP20_ADR.asl @@ -0,0 +1,20 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +Method (_ADR, 0) { + If (LNotEqual(RPAK,0)) { + Return (RPAK) + } Else { + Return (0x001B0003) + } +}
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/TraceHubDebug.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/TraceHubDebug.asl new file mode 100644 index 0000000000..736e76241d --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/TraceHubDebug.asl @@ -0,0 +1,148 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#define TRACE_HUB_MASTER_NUM_ASL 32 +#define TRACE_HUB_CHANNEL_NUM_ASL 22 + +// +// @note Only include register definition macros in ASL. +// GCC will leak C function definitions in to ASL +// code, causing compilation errors in some cases. +// +#include <PchReservedResources.h> +#include <Register/PchRegsTraceHub.h> + +Scope(\){ + // Check if Trace Hub is enabled + Method (THEN, 0, Serialized) { + OperationRegion (THBA, SystemMemory, PCH_TRACE_HUB_SW_BASE_ADDRESS, 0x10) + Field (THBA, DWordAcc, NoLock, Preserve) { + Offset (0x00), + DO00, 32, + } + Return (LNotEqual(DO00, 0xFFFFFFFF)) + } + + // Trace Hub debug address + // This is internal helper runtine of THDS + // Arg0 : Master number + // Arg1 : Channel number + Method (THDA, 2, Serialized) { + // Local0 = PCH_TRACE_HUB_SW_BASE_ADDRESS + 0x40 * (V_PCH_TRACE_HUB_MTB_CHLCNT * (Master - V_PCH_TRACE_HUB_MTB_STHMSTR)) + 0x40 * Channel; + Store (PCH_TRACE_HUB_SW_BASE_ADDRESS, Local0) + Add (Local0, Multiply (0x40, Multiply (V_PCH_TRACE_HUB_MTB_CHLCNT, Subtract (Arg0, V_PCH_TRACE_HUB_MTB_STHMSTR))), Local0) + Add (Local0, Multiply (0x40, Arg1), Local0) + Return (Local0) + } + + // String to raw data + // This is internal helper runtine of THDS + // Arg0 : string + // Arg1 : Index + // Arg2 : size + Method (STRD, 3, Serialized) { + If (LGreater (Add (Arg1, Arg2), SizeOf (Arg0))) { + Return (0) + } + // Local0 is return value + // Lccal1 is loop index + // Local2 is char of string + // Local3 is buffer of string + ToBuffer (Arg0, Local3) + Store (0, Local0) + Store (0, Local1) + While (LLess (Local1, Arg2)) { + Store (DeRefOf (Index (Local3, Add (Arg1, Local1))), Local2) + Add (Local0, ShiftLeft (Local2, Multiply (8, Local1)), Local0) + Increment (Local1) + } + Return (Local0) + } + + // Trace Hub debug string + // Arg0 : debug string + Method (THDS, 1, Serialized) { + // TH check if enabled. + If (LNot (THEN())) { + Return + } + + // Local0 is the length of string + // Local1 is the debug base address + Store (Sizeof (Arg0), Local0) + Store (THDA (TRACE_HUB_MASTER_NUM_ASL, TRACE_HUB_CHANNEL_NUM_ASL), Local1) + OperationRegion (THBA, SystemMemory, local1, 0x40) + Field (THBA, QWordAcc, NoLock, Preserve) { + Offset (0x00), + QO00, 64, + } + Field (THBA, DWordAcc, NoLock, Preserve) { + Offset (0x00), + DO00, 32, + Offset (0x10), + DO10, 32, + offset (0x30), + DO30, 32, + } + Field (THBA, WordAcc, NoLock, Preserve) { + Offset (0x00), + WO00, 16, + } + Field (THBA, ByteAcc, NoLock, Preserve) { + Offset (0x00), + BO00, 8, + } + + // time stamp + Store (0x01000242, DO10) + // length of string + Store (Local0, WO00) + // string + Store (0, Local6) + Store (Local0, Local7) + while (LGreaterEqual(Local7, 8)) { + Store (STRD (Arg0, Local6, 8), QO00) + Add (Local6, 8, Local6) + Subtract (Local7, 8, Local7) + } + If (LGreaterEqual(Local7, 4)) { + Store (STRD (Arg0, Local6, 4), DO00) + Add (Local6, 4, Local6) + Subtract (Local7, 4, Local7) + } + If (LGreaterEqual(Local7, 2)) { + Store (STRD (Arg0, Local6, 2), WO00) + Add (Local6, 2, Local6) + Subtract (Local7, 2, Local7) + } + If (LGreaterEqual(Local7, 1)) { + Store (STRD (Arg0, Local6, 1), BO00) + Add (Local6, 1, Local6) + Subtract (Local7, 1, Local7) + } + // flag + Store (0, DO30) + } + + // Trace Hub debug Hex string + // Arg0 : Integer, buffer + Method (THDH, 1, Serialized) { + THDS (ToHexString (Arg0)) + } + + // Trace Hub debug decimal string + // Arg0 : Integer, buffer + Method (THDD, 1, Serialized) { + THDS (ToDecimalString (Arg0)) + } +} diff --git a/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/usbsbd.asl b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/usbsbd.asl new file mode 100644 index 0000000000..2778f4247b --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/AcpiTables/Dsdt/usbsbd.asl @@ -0,0 +1,69 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// _DSM : Device Specific Method supporting USB Sideband Deferring function +// +// Arg0: UUID Unique function identifier +// Arg1: Integer Revision Level +// Arg2: Integer Function Index +// Arg3: Package Parameters +// +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) +{ + + If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8"))) + { + // + // Switch by function index + // + Switch (ToInteger(Arg2)) + { + // + // Standard query - A bitmask of functions supported + // Supports function 0-2 + // + Case (0) + { + if (LEqual(Arg1, 1)){ // test Arg1 for the revision + Return (Buffer () {0x07}) + } else { + Return (Buffer () {0}) + } + } + // + // USB Sideband Deferring Support + // 0: USB Sideband Deferring not supported on this device + // 1: USB Sideband Deferring supported + // + Case (1) + { + if (LEqual(SDGV,0xFF)){ // check for valid GPE vector + Return (0) + } else { + Return (1) + } + } + // + // GPE Vector + // Return the bit offset within the GPE block of the GPIO (HOST_ALERT) driven by this device + // + Case (2) + { + Return (SDGV) + } + } + } + + Return (0) +} diff --git a/Silicon/Intel/LewisburgPkg/Include/GpioConfig.h b/Silicon/Intel/LewisburgPkg/Include/GpioConfig.h new file mode 100644 index 0000000000..9b9420b260 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/GpioConfig.h @@ -0,0 +1,236 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig and Host Software Pad Ownership are unnecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 4; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 5; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO is in input mode. + If GPIO is set to cause an SCI then also Gpe is enabled for this pad. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 8; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 4; + + /** + GPIO Electrical Configuration + This setting controls pads termination and voltage tolerance. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 7; + + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 3; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 2; + UINT32 RsvdBits : 27; ///< Reserved bits for future extension + UINT32 RsvdBits1; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault = 0x0 +} GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +#define GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source +#define GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type + +/// +/// GPIO Power Configuration +/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified +/// Pad Register fields). +/// +typedef enum { + GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified + GpioResetPwrGood = 0x1, ///< Powergood reset + GpioResetDeep = 0x3, ///< Deep GPIO Reset + GpioResetNormal = 0x5, ///< GPIO Reset + GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) +} GPIO_RESET_CONFIG; + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with GpioTolerance1v8. +/// +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative = 0x1F, ///< Native function controls pads termination + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +#define GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value +#define GPIO_ELECTRICAL_CONFIG_1V8_TOLERANCE_MASK 0x60 ///< Mask for GPIO_ELECTRICAL_CONFIG for 1v8 tolerance setting + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and native usage). +/// The override takes place at the internal pad state directly from buffer and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/GpioPinsSklH.h b/Silicon/Intel/LewisburgPkg/Include/GpioPinsSklH.h new file mode 100644 index 0000000000..304d58741c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/GpioPinsSklH.h @@ -0,0 +1,304 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// SKL H GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPP_J 0x0109 +#define GPIO_SKL_H_GROUP_GPP_K 0x010A +#define GPIO_SKL_H_GROUP_GPP_L 0x010B +#define GPIO_SKL_H_GROUP_GPD 0x010C + +/// +/// SKL H GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPP_J0 0x01090000 +#define GPIO_SKL_H_GPP_J1 0x01090001 +#define GPIO_SKL_H_GPP_J2 0x01090002 +#define GPIO_SKL_H_GPP_J3 0x01090003 +#define GPIO_SKL_H_GPP_J4 0x01090004 +#define GPIO_SKL_H_GPP_J5 0x01090005 +#define GPIO_SKL_H_GPP_J6 0x01090006 +#define GPIO_SKL_H_GPP_J7 0x01090007 +#define GPIO_SKL_H_GPP_J8 0x01090008 +#define GPIO_SKL_H_GPP_J9 0x01090009 +#define GPIO_SKL_H_GPP_J10 0x0109000A +#define GPIO_SKL_H_GPP_J11 0x0109000B +#define GPIO_SKL_H_GPP_J12 0x0109000C +#define GPIO_SKL_H_GPP_J13 0x0109000D +#define GPIO_SKL_H_GPP_J14 0x0109000E +#define GPIO_SKL_H_GPP_J15 0x0109000F +#define GPIO_SKL_H_GPP_J16 0x01090010 +#define GPIO_SKL_H_GPP_J17 0x01090011 +#define GPIO_SKL_H_GPP_J18 0x01090012 +#define GPIO_SKL_H_GPP_J19 0x01090013 +#define GPIO_SKL_H_GPP_J20 0x01090014 +#define GPIO_SKL_H_GPP_J21 0x01090015 +#define GPIO_SKL_H_GPP_J22 0x01090016 +#define GPIO_SKL_H_GPP_J23 0x01090017 +#define GPIO_SKL_H_GPP_K0 0x010A0000 +#define GPIO_SKL_H_GPP_K1 0x010A0001 +#define GPIO_SKL_H_GPP_K2 0x010A0002 +#define GPIO_SKL_H_GPP_K3 0x010A0003 +#define GPIO_SKL_H_GPP_K4 0x010A0004 +#define GPIO_SKL_H_GPP_K5 0x010A0005 +#define GPIO_SKL_H_GPP_K6 0x010A0006 +#define GPIO_SKL_H_GPP_K7 0x010A0007 +#define GPIO_SKL_H_GPP_K8 0x010A0008 +#define GPIO_SKL_H_GPP_K9 0x010A0009 +#define GPIO_SKL_H_GPP_K10 0x010A000A +#define GPIO_SKL_H_GPP_L2 0x010B0002 +#define GPIO_SKL_H_GPP_L3 0x010B0003 +#define GPIO_SKL_H_GPP_L4 0x010B0004 +#define GPIO_SKL_H_GPP_L5 0x010B0005 +#define GPIO_SKL_H_GPP_L6 0x010B0006 +#define GPIO_SKL_H_GPP_L7 0x010B0007 +#define GPIO_SKL_H_GPP_L8 0x010B0008 +#define GPIO_SKL_H_GPP_L9 0x010B0009 +#define GPIO_SKL_H_GPP_L10 0x010B000A +#define GPIO_SKL_H_GPP_L11 0x010B000B +#define GPIO_SKL_H_GPP_L12 0x010B000C +#define GPIO_SKL_H_GPP_L13 0x010B000D +#define GPIO_SKL_H_GPP_L14 0x010B000E +#define GPIO_SKL_H_GPP_L15 0x010B000F +#define GPIO_SKL_H_GPP_L16 0x010B0010 +#define GPIO_SKL_H_GPP_L17 0x010B0011 +#define GPIO_SKL_H_GPP_L18 0x010B0012 +#define GPIO_SKL_H_GPP_L19 0x010B0013 +#define GPIO_SKL_H_GPD0 0x010C0000 +#define GPIO_SKL_H_GPD1 0x010C0001 +#define GPIO_SKL_H_GPD2 0x010C0002 +#define GPIO_SKL_H_GPD3 0x010C0003 +#define GPIO_SKL_H_GPD4 0x010C0004 +#define GPIO_SKL_H_GPD5 0x010C0005 +#define GPIO_SKL_H_GPD6 0x010C0006 +#define GPIO_SKL_H_GPD7 0x010C0007 +#define GPIO_SKL_H_GPD8 0x010C0008 +#define GPIO_SKL_H_GPD9 0x010C0009 +#define GPIO_SKL_H_GPD10 0x010C000A +#define GPIO_SKL_H_GPD11 0x010C000B + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/GpioPinsSklLp.h b/Silicon/Intel/LewisburgPkg/Include/GpioPinsSklLp.h new file mode 100644 index 0000000000..eb591da562 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/GpioPinsSklLp.h @@ -0,0 +1,207 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GPIO_PINS_SKL_LP_H_ +#define _GPIO_PINS_SKL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// SKL LP GPIO Groups +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_LP_GROUP_GPP_A 0x0200 +#define GPIO_SKL_LP_GROUP_GPP_B 0x0201 +#define GPIO_SKL_LP_GROUP_GPP_C 0x0202 +#define GPIO_SKL_LP_GROUP_GPP_D 0x0203 +#define GPIO_SKL_LP_GROUP_GPP_E 0x0204 +#define GPIO_SKL_LP_GROUP_GPP_F 0x0205 +#define GPIO_SKL_LP_GROUP_GPP_G 0x0206 +#define GPIO_SKL_LP_GROUP_GPD 0x0207 + +/// +/// SKL LP GPIO pins +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/GpioLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/GpioLib.h new file mode 100644 index 0000000000..383be789fd --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/GpioLib.h @@ -0,0 +1,783 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include <GpioConfig.h> +#include <Uefi/UefiBaseType.h> + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values. + Separate fields could be set to hardware default if it does not matter, except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those include: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +// +// Functions for setting/getting multiple GpioPad settings +// + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +// +// Functions for setting/getting single GpioPad properties +// + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ); + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ); + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ); + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group + For group which has less then 32 pads per group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ); + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ); + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ); + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ); + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get Group to GPE mapping. + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ); + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Purpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used by Smi Dispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ); + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ); + +/** + This procedure will set GPIO Input Rout SCI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSCI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSci ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will set GPIO Input Rout SMI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSmi ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will set GPI SMI Enable setting for selected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiSmiEn GPI SMI Enable setting for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiSmiPadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiSmiEn + ); + +/** + This procedure will set GPI General Purpose Event Enable setting for selected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiGpeEn GPI General Purpose Event Enable setting for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiGpePadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiGpeEn + ); + +/** + Locks GPIO pads according to GPIO_INIT_CONFIG array from + gPlatformGpioConfigGuid HOB. Only locking is applied and no other GPIO pad + configuration is changed. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_NOT_FOUND gPlatformGpioConfigGuid not found +**/ +EFI_STATUS +GpioLockGpios ( + VOID + ); + +/** + Unlocks all PCH GPIO pads + + @retval None +**/ +VOID +GpioUnlockAllGpios ( + VOID + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/GpioNativeLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/GpioNativeLib.h new file mode 100644 index 0000000000..ddeeee6490 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/GpioNativeLib.h @@ -0,0 +1,224 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GPIO_NATIVE_LIB_H_ +#define _GPIO_NATIVE_LIB_H_ + +#include <GpioConfig.h> + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ); + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT8 +GpioGetNumberOfGroups ( + VOID + ); +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ); + +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ); + +/** + This procedure will get group + + @param[in] GpioPad Gpio Pad + + @retval Value Group +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from GpioPad + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ); + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ); + +/** + This procedure will return GpioPad from GroupIndex and PadNumber + + @param[in] GroupIndex GPIO GroupIndex + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupIndexAndPadNumber ( + IN UINT32 GroupIndex, + IN UINT32 PadNumber + ); + +/** + This function sets SerialIo I2C controller pins into native mode + + @param[in] SerialIoI2cControllerNumber I2C controller + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoI2cPinsIntoNativeMode ( + IN UINT32 SerialIoI2cControllerNumber + ); + +/** + This function sets SerialIo I2C controller pins tolerance + + @param[in] SerialIoI2CControllerNumber I2C controller + @param[in] Pad1v8Tolerance TRUE: Enable 1v8 Pad tolerance + FALSE: Disable 1v8 Pad tolerance + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoI2CPinsTolerance ( + IN UINT32 SerialIoI2CControllerNumber, + IN BOOLEAN Pad1v8Tolerance + ); + +/** + This function sets SerialIo UART controller pins into native mode + + @param[in] SerialIoI2CControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoUartPinsIntoNativeMode ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl + ); + +/** + This function sets SerialIo SPI controller pins into native mode + + @param[in] SerialIoI2CControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioSetSerialIoSpiPinsIntoNativeMode ( + IN UINT32 SerialIoUartControllerNumber + ); + +/** + This function checks if GPIO pin for SATA reset port is in GPIO MODE + + @param[in] SataPort SATA port number + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsSataResetPortInGpioMode ( + IN UINTN SataPort + ); + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad + ); + +#endif // _GPIO_NATIVE_LIB_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchCycleDecodingLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchCycleDecodingLib.h new file mode 100644 index 0000000000..ac6e7fb0aa --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchCycleDecodingLib.h @@ -0,0 +1,350 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_CYCLE_DECODING_LIB_H_ +#define _PCH_CYCLE_DECODING_LIB_H_ + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes alignment, and it is IO space, so must not exceed 0xFFFF. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [7] to diable ACPI base address first before changing base address. + 2. program PMC PCI offset 40h [15:2] to ACPI base address. + 3. set PMC PCI offset 44h [7] to enable ACPI base address. + 4. program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F, PMC PCI Offset 40h bit[15:2], 1]. + 5. Program "ACPI Base Destination ID" PCR[DMI] + 27B8h[31:0] to [0x23A0]. + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH ACPI base address. + + @param[out] Address Address of ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseGet ( + OUT UINT16 *Address + ); + +/** + Set PCH PWRM base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [8] to diable PWRM base address first before changing PWRM base address. + 2. program PMC PCI offset 48h [31:16] to PM base address. + 3. set PMC PCI offset 44h [8] to enable PWRM base address. + 4. program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the PWRMBASE to be 64KB aligned. + program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the memory allocated to PWRMBASE to be 64KB in size. + 5. program "PM Base Control" PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0]. + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseSet ( + IN UINT32 Address + ); + +/** + Get PCH PWRM base address. + + @param[out] Address Address of PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseGet ( + OUT UINT32 *Address + ); + +/** + Set PCH TCO base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1]. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseGet ( + OUT UINT16 *Address + ); + +/// +/// structure of LPC general IO range register +/// It contains base address, address mask, and enable status. +/// +typedef struct { + UINT32 BaseAddr :16; + UINT32 Length :15; + UINT32 Enable : 1; +} PCH_LPC_GEN_IO_RANGE; + +#define PCH_LPC_GEN_IO_RANGE_MAX 4 +/// +/// structure of LPC general IO range register list +/// It lists all LPC general IO ran registers supported by PCH. +/// +typedef struct { + PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX]; +} PCH_LPC_GEN_IO_RANGE_LIST; + +/** + Set PCH LPC generic IO range. + For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length aligned. + This function basically checks the address and length, which should not overlap with all other generic ranges. + If no more generic range register available, it returns out of resource error. + This cycle decoding is allowed to set when DMIC.SRL is 0. + The IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be skipped except 0x80-0x8F. + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h. + + @param[in] Address Address for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + , IN UINT8 SlaveDevice + ); + +/** + Get PCH LPC generic IO range list. + This function returns a list of base address, length, and enable for all LPC generic IO range regsiters. + + @param[out] LpcGenIoRangeList Return all LPC generic IO range register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + , IN UINT8 SlaveDevice + ); + +/** + Set PCH LPC memory range decoding. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program LPC/eSPI PCI 98h [0] to [0] to disable memory decoding first before changing base address. + 2. Program LPC/eSPI PCI 98h [31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h. + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + , IN UINT8 SlaveDevice + ); + +/** + Get PCH LPC memory range decoding address. + + @param[out] Address Address of LPC memory decoding base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + OUT UINT32 *Address + , IN UINT8 SlaveDevice + ); + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable. + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ); + +/** + Set PCH LPC IO decode ranges. + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h. + Please check EDS for detail of Lpc IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC IO enable decoding. + Setup LPC I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of Lpc IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding Lpc IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + , IN UINT8 SlaveDevice + ); + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that + the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12]) + before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default + IO range values. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO. + 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ); + +/** + Get IO APIC regsiters base address. + It returns IO APIC INDEX, DATA, and EOI regsiter address once the parameter is not NULL. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] IoApicIndex Buffer of IO APIC INDEX regsiter address + @param[out] IoApicData Buffer of IO APIC DATA regsiter address + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OPTIONAL OUT UINT32 *IoApicIndex, + OPTIONAL OUT UINT32 *IoApicData + ); + +/** + Get HPET base address. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ); + +#endif // _PCH_CYCLE_DECODING_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchGbeLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchGbeLib.h new file mode 100644 index 0000000000..4630547f72 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchGbeLib.h @@ -0,0 +1,64 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_GBE_LIB_H_ +#define _PCH_GBE_LIB_H_ + +/** + Check whether GbE region is valid + Check SPI region directly since GBE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ); + +/** + Returns GbE over PCIe port number based on a soft strap. + + @return Root port number (1-based) + @retval 0 GbE over PCIe disabled +**/ +UINT32 +PchGetGbePortNumber ( + VOID + ); + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ); + +/** + Check whether LAN controller is enabled in the platform. + + @deprecated Use PchIsGbePresent instead. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbeAvailable ( + VOID + ); + +#endif // _PCH_GBE_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchInfoLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..cfdbc44fa9 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchInfoLib.h @@ -0,0 +1,237 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include <PchAccess.h> + +typedef enum { + PchH = 1, + PchLp, + PchUnknownSeries +} PCH_SERIES; + +typedef enum { + SklPch = 1, + PchUnknownGeneration +} PCH_GENERATION; + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +EFIAPI +PchStepping ( + VOID + ); + +/** + Determine if PCH is supported + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported +**/ +BOOLEAN +IsPchSupported ( + VOID + ); + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +EFIAPI +GetPchSeries ( + VOID + ); + +/** + Return Pch Generation + + @retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +EFIAPI +GetPchGeneration ( + VOID + ); + +/** + Get Pch Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +EFIAPI +GetPchMaxPciePortNum ( + VOID + ); + +/** + Get Pch Maximum Sata Port Number + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +EFIAPI +GetPchMaxSataPortNum ( + VOID + ); + +/** + Get Pch Usb Maximum Physical Port Number + + @retval Pch Usb Maximum Physical Port Number +**/ +UINT8 +EFIAPI +GetPchUsbMaxPhysicalPortNum ( + VOID + ); + +/** + Get Pch Maximum Usb2 Port Number of XHCI Controller + + @retval Pch Maximum Usb2 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb2PortNum ( + VOID + ); + +/** + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @retval Pch Maximum Usb3 Port Number of XHCI Controller +**/ +UINT8 +EFIAPI +GetPchXhciMaxUsb3PortNum ( + VOID + ); + +/** + Return TRUE if Server Sata is present + + @retval BOOLEAN TRUE if sSata device is present +**/ +BOOLEAN +EFIAPI +GetIsPchsSataPresent ( + VOID + ); + +/** + Get Pch Maximum sSata Port Number + + @param[in] None + + @retval Pch Maximum sSata Port Number +**/ +UINT8 +EFIAPI +GetPchMaxsSataPortNum ( + VOID + ); + +/** + Get Pch Maximum sSata Controller Number + + @param[in] None + + @retval Pch Maximum sSata Controller Number +**/ +UINT8 +EFIAPI +GetPchMaxsSataControllerNum ( + VOID + ); + +/** + Return Pch Lpc Device Id + + @retval UINT16 Pch DeviceId +**/ +UINT16 +EFIAPI +GetPchLpcDeviceId ( + VOID + ); + +/** + Get PCH stepping ASCII string + The return string is zero terminated. + + @param [in] PchStep Pch stepping + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + IN PCH_STEPPING PchStep, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get PCH series ASCII string + The return string is zero terminated. + + @param [in] PchSeries Pch series + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSeriesStr ( + IN PCH_SERIES PchSeries, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @param [in] LpcDid LPC device id + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSkuStr ( + IN UINT16 LpcDid, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ); + +#endif // _PCH_INFO_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchP2sbLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchP2sbLib.h new file mode 100644 index 0000000000..f7502238d0 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchP2sbLib.h @@ -0,0 +1,160 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_P2SB_LIB_H_ +#define _PCH_P2SB_LIB_H_ + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet32 ( + IN UINTN Offset, + OUT UINT32 *OutData + ); + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet16 ( + IN UINTN Offset, + OUT UINT16 *OutData + ); + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 1byte. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet8 ( + IN UINTN Offset, + OUT UINT8 *OutData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet32 ( + IN UINTN Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet16 ( + IN UINTN Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 1bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet8 ( + IN UINTN Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controller. + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ); + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not after. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controller. + @param[out] OrgStatus Original P2SB hidding/unhidden status + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ); + +#endif // _PCH_P2SB_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchPcrLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchPcrLib.h new file mode 100644 index 0000000000..085295cab4 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchPcrLib.h @@ -0,0 +1,196 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_PCR_LIB_H_ +#define _PCH_PCR_LIB_H_ + +#include <PchAccess.h> + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +#endif // _PCH_PCR_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchPmcLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchPmcLib.h new file mode 100644 index 0000000000..87d10e3074 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchPmcLib.h @@ -0,0 +1,62 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_PMC_LIB_H_ +#define _PCH_PMC_LIB_H_ + +typedef enum { + PchWarmBoot = 1, + PchColdBoot, + PwrFlr, + PwrFlrSys, + PwrFlrPch, + PchPmStatusMax +} PCH_PM_STATUS; + +/** + Query PCH to determine the Pm Status + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Status TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ); + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ); + +/** + Funtion to check if DWR occurs + + @reval TRUE DWR occurs + @reval FALSE Normal boot flow +**/ +BOOLEAN +EFIAPI +PchIsDwrFlow ( + VOID + ); + +#endif // _PCH_PMC_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchPolicyLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchPolicyLib.h new file mode 100644 index 0000000000..20266bc1dd --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchPolicyLib.h @@ -0,0 +1,72 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_PCH_POLICY_LIB_H_ +#define _PEI_PCH_POLICY_LIB_H_ + +#include <Ppi/PchPolicy.h> + +/** + Print whole PCH_POLICY_PPI and serial out. + + @param[in] PchPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +PchPrintPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ); + +/** + PchCreatePolicyDefaults creates the default setting of PCH Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] PchPolicyPpi The pointer to get PCH Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchCreatePolicyDefaults ( + OUT PCH_POLICY_PPI **PchPolicyPpi + ); + +/** + PchInstallPolicyPpi installs PchPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ); + +/* + Apply RVP3 PCH specific default settings + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance +*/ +VOID +EFIAPI +PchRvp3DefaultPolicy ( + IN PCH_POLICY_PPI *PchPolicy + ); + +#endif // _PEI_PCH_POLICY_LIB_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchSbiAccessLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchSbiAccessLib.h new file mode 100644 index 0000000000..92fd63daa7 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchSbiAccessLib.h @@ -0,0 +1,162 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_SBI_ACCESS_LIB_H_ +#define _PCH_SBI_ACCESS_LIB_H_ + +/** + PCH SBI Register structure +**/ +typedef struct { + UINT32 SbiAddr; + UINT32 SbiExtAddr; + UINT32 SbiData; + UINT16 SbiStat; + UINT16 SbiRid; +} PCH_SBI_REGISTER_STRUCT; + +/** + PCH SBI opcode definitions +**/ +typedef enum { + MemoryRead = 0x0, + MemoryWrite = 0x1, + PciConfigRead = 0x4, + PciConfigWrite = 0x5, + PrivateControlRead = 0x6, + PrivateControlWrite = 0x7, + GpioLockUnlock = 0x13 +} PCH_SBI_OPCODE; + +/** + PCH SBI response status definitions +**/ +typedef enum { + SBI_SUCCESSFUL = 0, + SBI_UNSUCCESSFUL = 1, + SBI_POWERDOWN = 2, + SBI_MIXED = 3, + SBI_INVALID_RESPONSE +} PCH_SBI_RESPONSE; + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ); + +#endif // _PCH_SBI_ACCESS_LIB_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/PchSerialIoLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/PchSerialIoLib.h new file mode 100644 index 0000000000..b88bc0f0bf --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/PchSerialIoLib.h @@ -0,0 +1,218 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_SERIAL_IO_LIB_H_ +#define _PCH_SERIAL_IO_LIB_H_ + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSpi0, + PchSerialIoIndexSpi1, + PchSerialIoIndexUart0, + PchSerialIoIndexUart1, + PchSerialIoIndexUart2, + PchSerialIoIndexMax +} PCH_SERIAL_IO_CONTROLLER; + +typedef enum { + PchSerialIoDisabled, + PchSerialIoAcpi, + PchSerialIoPci, + PchSerialIoAcpiHidden, + PchSerialIoLegacyUart, + PchSerialIoSkipInit +} PCH_SERIAL_IO_MODE; + +enum PCH_LP_SERIAL_IO_VOLTAGE_SEL { + PchSerialIoIs33V = 0, + PchSerialIoIs18V +}; +enum PCH_LP_SERIAL_IO_CS_POLARITY { + PchSerialIoCsActiveLow = 0, + PchSerialIoCsActiveHigh = 1 +}; +enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL { + PchSerialIoHwFlowCtrlDisabled = 0, + PchSerialIoHwFlowControlEnabled = 1 +}; + +#define SERIALIO_HID_LENGTH 8 // including null terminator +#define SERIALIO_UID_LENGTH 1 +#define SERIALIO_CID_LENGTH 1 +#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+SERIALIO_CID_LENGTH + +/** + Returns index of the last i2c controller + + @param[in] Number Number of SerialIo controller + + @retval Index of I2C controller +**/ +PCH_SERIAL_IO_CONTROLLER +GetMaxI2cNumber ( + ); + +/** + Returns string with AcpiHID assigned to selected SerialIo controller + + @param[in] Number Number of SerialIo controller + + @retval pointer to 8-byte string +**/ +CHAR8* +GetSerialIoAcpiHID ( + IN PCH_SERIAL_IO_CONTROLLER Number + ); + +/** + Checks if Device with given PciDeviceId is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Number is not updated + + @param[in] PciDevId Device ID + @param[out] Number Number of SerialIo controller + + @retval TRUE Yes it is a SerialIo controller + @retval FALSE No it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoPciDevId ( + IN UINT16 PciDevId, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Checks if Device with given AcpiHID string is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Number is not updated + + @param[in] AcpiHid String + @param[out] Number Number of SerialIo controller + + @retval TRUE yes it is a SerialIo controller + @retval FALSE no it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoAcpiHid ( + IN CHAR8 *AcpiHid, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Configures Serial IO Controller + + @param[in] Controller + @param[in] DeviceMode + + @retval None +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode + ); + +/** + Initializes GPIO pins used by SerialIo I2C devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] I2cVoltage + + @retval None +**/ +VOID +SerialIoI2cGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 I2cVoltage + ); + +/** + Initializes GPIO pins used by SerialIo SPI devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] SpiCsPolarity + + @retval None +**/ +VOID +SerialIoSpiGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN UINT32 SpiCsPolarity + ); + +/** + Initializes GPIO pins used by SerialIo devices + + @param[in] Controller + @param[in] DeviceMode + @param[in] HardwareFlowControl + + @retval None +**/ +VOID +SerialIoUartGpioInit ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN BOOLEAN HardwareFlowControl + ); + +/** + Finds PCI Device Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber 0=I2C0, ..., 11=UART2 + + @retval SerialIo device number +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds PCI Function Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber 0=I2C0, ..., 11=UART2 + + @retval SerialIo funciton number +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds BAR values of SerialIo devices. + SerialIo devices can be configured to not appear on PCI so traditional method of reading BAR might not work. + + @param[in] SerialIoDevice 0=I2C0, ..., 11=UART2 + @param[in] BarNumber 0=BAR0, 1=BAR1 + + @retval SerialIo Bar value +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ); + + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/Library/SpiFlashCommonLib.h b/Silicon/Intel/LewisburgPkg/Include/Library/SpiFlashCommonLib.h new file mode 100644 index 0000000000..4857564ded --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Library/SpiFlashCommonLib.h @@ -0,0 +1,102 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SPI_FLASH_COMMON_LIB_H__
+#define __SPI_FLASH_COMMON_LIB_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Silicon/Intel/LewisburgPkg/Include/PchAccess.h b/Silicon/Intel/LewisburgPkg/Include/PchAccess.h new file mode 100644 index 0000000000..830b8e5539 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/PchAccess.h @@ -0,0 +1,627 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + + +/// +/// The default PCH PCI bus number +/// +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor ID +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsystem ID +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID + +// +// Generic definitions for device enabling/disabling used by PCH code. +// +#define PCH_DEVICE_ENABLE 1 +#define PCH_DEVICE_DISABLE 0 +#define PCH_DEVICE_DEFAULT 2 + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include "Register/PchRegsThermal.h" +#include "Register/PchRegsUsb.h" +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsPsf.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" +#include "Register/PchRegsEva.h" + +// +// LPC Device ID macros +// +// +// Device IDs that are PCH-H Desktop specific +// +#define IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_0) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_1) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_2) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_3) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_4) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_5) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_6) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP(DeviceId) \ + ) + +// +// Device IDs that are PCH-H Mobile specific +// + +#define IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_0) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_1) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_2) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU) \ + ) + + +// +// Device IDs that are PCH-LP Mobile specific +// +#define IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_UNFUSE) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_0) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_1) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_2) || \ + (DeviceId == V_PCH_LP_LPC_DEVICE_ID_MB_3) \ + ) + +#define IS_PCH_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE(DeviceId) \ + ) + +// +// Device IDS that are PCH Server\Workstation specific +#define IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_SVR_0) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_SVR_1) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_SVR_2) || \ + (DeviceId == V_PCH_H_LPC_DEVICE_ID_A14B) \ + ) + + +#define IS_PCH_LPC_DEVICE_ID_SERVER(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_SERVER(DeviceId) \ + ) + +#define IS_PCH_H_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID_DESKTOP (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_MOBILE (DeviceId) || \ + IS_PCH_H_LPC_DEVICE_ID_SERVER (DeviceId) \ + ) + +#define IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID_MOBILE (DeviceId) \ + ) + +#define IS_PCH_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_LPC_DEVICE_ID(DeviceId) \ + ) + +#define IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >= V_PCH_LBG_PROD_LPC_DEVICE_ID_0) && \ + (DeviceId <= V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX) \ + ) + +#define IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >= V_PCH_LBG_LPC_DEVICE_ID_UNFUSED) && \ + (DeviceId <= V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX ) \ + ) + +#ifdef SKXD_EN +#define IS_PCH_LBG_D_SSKU_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId >= V_PCH_LBG_LPC_DEVICE_ID_SS_D1) && \ + (DeviceId <= V_PCH_LBG_LPC_DEVICE_ID_SS_D3 ) \ + ) +#endif // SKXD_EN + +#define IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS) || \ + (DeviceId == V_PCH_LBG_PROD_LPC_DEVICE_ID_T) \ + ) + +#define IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) \ + ( \ + FALSE \ + ) + +#define IS_PCH_LBG_LPC_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PROD_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_NS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_WS_LPC_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSKU_LPC_DEVICE_ID(DeviceId) \ + ) + + +// +// SATA AHCI Device ID macros +// +#define IS_PCH_LBG_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LBG_SSATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI) \ + ) + + +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_AHCI) \ + ) + +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) \ + ) + + + +// +// SATA RAID Device ID macros +// +#define IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId == V_PCH_LBG_SATA_DEVICE_ID_D_RAID1) || \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1) \ + ) + +#define IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1) || \ + (DeviceId == V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1) || \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM) || \ + (DeviceId == V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1) \ + ) + + +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE) || \ + (DeviceId == V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT) \ + ) + + +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM) || \ + (DeviceId == V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT) \ + ) + +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID(DeviceId) \ + ) + +// +// Combined SATA IDE/AHCI/RAID Device ID macros +// +#define IS_PCH_LBG_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_SSATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SSATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_RAID_DEVICE_ID (DeviceId) \ + ) +#define IS_PCH_LBG_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SSATA_DEVICE_ID (DeviceId) \ + ) + +#define IS_PCH_H_RAID_AVAILABLE(DeviceId) (TRUE) +#define IS_PCH_LP_RAID_AVAILABLE(DeviceId) (TRUE) + +#define IS_PCH_RAID_AVAILABLE(DeviceId) \ + ( \ + IS_PCH_LBG_RAID_AVAILABLE(DeviceId) \ + ) + +// +// SPI Device ID macros +// +#define IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SPI_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_SPI_DEVICE_ID) \ + ) + +#define IS_PCH_H_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_LP_SPI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_SPI_DEVICE_ID) || \ + FALSE \ + ) + +#define IS_PCH_SPI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_SPI_DEVICE_ID(DeviceId) \ + ) + +// +// USB Device ID macros +// +#define IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_USB_DEVICE_ID_XHCI_1) || \ + (DeviceId == V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_H_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_USB_DEVICE_ID_XHCI_1) \ + ) + +#define IS_PCH_LP_USB_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_USB_DEVICE_ID_XHCI_1) \ + ) +#define IS_PCH_USB_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_USB_DEVICE_ID(DeviceId) \ + ) + +// +// PCIE Device ID macros +// +#define IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId == V_PCH_LBG_PCIE_DEVICE_ID_PORT20) \ + ) + +#define IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId == V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20) \ + ) + + + +#define IS_PCH_H_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT12) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT13) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT14) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT15) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT16) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT17) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT18) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT19) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_PORT20) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_MB_SUBD) || \ + (DeviceId == V_PCH_H_PCIE_DEVICE_ID_DT_SUBD) \ + ) + +#define IS_PCH_LP_PCIE_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT1) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT2) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT3) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT4) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT5) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT6) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT7) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT8) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT9) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT10) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT11) || \ + (DeviceId == V_PCH_LP_PCIE_DEVICE_ID_PORT12) \ + ) + +#define IS_PCH_PCIE_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_PCIE_DEVICE_ID(DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID(DeviceId) \ + ) + + +// +// HD Audio Device ID macros +// +#define IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_LBG_HDA_DEVICE_ID_7) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_LBG_PROD_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_H_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_H_HDA_DEVICE_ID_7) \ + ) + +#define IS_PCH_LP_HDA_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_2) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_3) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_4) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_5) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_6) || \ + (DeviceId == V_PCH_LP_HDA_DEVICE_ID_7) \ + ) +#define IS_PCH_HDA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LBG_HDA_DEVICE_ID(DeviceId) \ + ) + + +/// +/// Any device ID that is PCH-LBG +/// +#define IS_PCH_LBG_SMBUS_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId == V_PCH_LBG_SMBUS_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_SMBUS_DEVICE_ID) \ + ) + +#define IS_PCH_LBG_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_PROD_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LBG_SMBUS_DEVICE_ID (DeviceId) || \ + (DeviceId == V_PCH_LBG_MROM_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_PROD_MROM_DEVICE_ID_0) || \ + (DeviceId == V_PCH_LBG_MROM_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_PROD_MROM_DEVICE_ID_1) || \ + (DeviceId == V_PCH_LBG_THERMAL_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_THERMAL_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_LAN_DEVICE_ID) || \ + (DeviceId == V_PCH_LBG_PROD_LAN_DEVICE_ID) \ + ) + +/// +/// Any device ID that is PCH-H +/// +#define IS_PCH_H_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_H_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_H_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_H_SPI_DEVICE_ID (DeviceId) || \ + IS_PCH_H_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId) == V_PCH_H_THERMAL_DEVICE_ID || \ + (DeviceId) == V_PCH_H_SMBUS_DEVICE_ID || \ + (DeviceId) == V_PCH_H_LAN_DEVICE_ID \ + ) + +/// +/// Any device ID that is PCH-Lp +/// +#define IS_PCH_LP_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_LPC_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_SATA_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_USB_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_PCIE_DEVICE_ID (DeviceId) || \ + IS_PCH_LP_HDA_DEVICE_ID (DeviceId) || \ + (DeviceId == V_PCH_LP_THERMAL_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SMBUS_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SPI_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_LAN_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_DMA_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_I2C0_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_I2C1_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_SPI0_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_SPI1_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_UART0_DEVICE_ID) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_UART1_DEVICE_ID ) || \ + (DeviceId == V_PCH_LP_SERIAL_IO_SDIO_DEVICE_ID) \ + ) + +/// +/// Combined any device ID that is PCH-H or PCH-LP +/// +/// +/// And any device that is PCH LBG +/// +#define IS_PCH_DEVICE_ID(DeviceId) \ + (\ + IS_PCH_LBG_DEVICE_ID(DeviceId) \ + ) + + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), Buffer, Buffer, 1, 1); + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataOr, 1, 1); + +#endif + diff --git a/Silicon/Intel/LewisburgPkg/Include/PchLimits.h b/Silicon/Intel/LewisburgPkg/Include/PchLimits.h new file mode 100644 index 0000000000..1f7e24b1ea --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/PchLimits.h @@ -0,0 +1,108 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_H_PCIE_MAX_ROOT_PORTS 20 +#define PCH_LP_PCIE_MAX_ROOT_PORTS 12 + +#define PCH_MAX_PCIE_CONTROLLERS PCH_H_PCIE_MAX_CONTROLLERS +#define PCH_PCIE_CONTROLLER_PORTS 4 +#define PCH_H_PCIE_MAX_CONTROLLERS (PCH_H_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) +#define PCH_LP_PCIE_MAX_CONTROLLERS (PCH_LP_PCIE_MAX_ROOT_PORTS / PCH_PCIE_CONTROLLER_PORTS) + +#define PCH_MAX_WM20_LANES_NUMBER 20 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS PCH_H_PCIE_MAX_ROOT_PORTS +#define PCH_LP_PCIE_MAX_CLK_REQ 6 +#define PCH_H_PCIE_MAX_CLK_REQ 16 + +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define PCH_MAX_SATA_PORTS PCH_H_AHCI_MAX_PORTS +#define PCH_MAX_SSATA_PORTS 6 +#define PCH_H_AHCI_MAX_PORTS 8 ///< Max number of sata ports in SKL PCH H +#define PCH_LP_AHCI_MAX_PORTS 3 ///< Max number of sata ports in SKL PCH LP +#define PCH_SATA_MAX_DEVICES_PER_PORT 1 ///< Max support device numner per port, Port Multiplier is not support. + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS PCH_H_XHCI_MAX_USB2_PORTS + +#define PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS 14 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R. +#define PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS 10 ///< Max Physical Connector XHCI, not counting virtual ports like USB-R. + +#define PCH_H_XHCI_MAX_USB2_PORTS 16 ///< 14 High Speed lanes + Including two ports reserved for USBr +#define PCH_LP_XHCI_MAX_USB2_PORTS 12 ///< 10 High Speed lanes + Including two ports reserved for USBr + +#define PCH_MAX_USB3_PORTS PCH_H_XHCI_MAX_USB3_PORTS + +#define PCH_H_XHCI_MAX_USB3_PORTS 10 ///< 10 Super Speed lanes +#define PCH_LP_XHCI_MAX_USB3_PORTS 6 ///< 6 Super Speed lanes + +#define PCH_XHCI_MAX_SSIC_PORT_COUNT 2 ///< 2 SSIC ports in SKL PCH-LP and SKL PCH-H + +// +// SerialIo limits +// +#define PCH_SERIALIO_MAX_CONTROLLERS 11 ///< Number of SerialIo controllers, this includes I2C, SPI and UART +#define PCH_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers +#define PCH_LP_SERIALIO_MAX_I2C_CONTROLLERS 6 ///< Number of SerialIo I2C controllers for PCH-LP +#define PCH_H_SERIALIO_MAX_I2C_CONTROLLERS 4 ///< Number of SerialIo I2C controllers for PCH-H +#define PCH_SERIALIO_MAX_SPI_CONTROLLERS 2 ///< Number of SerialIo SPI controllers +#define PCH_SERIALIO_MAX_UART_CONTROLLERS 3 ///< Number of SerialIo UART controllers + +// +// ISH limits +// +#define PCH_ISH_MAX_GP_PINS 8 +#define PCH_ISH_MAX_UART_CONTROLLERS 2 +#define PCH_ISH_MAX_I2C_CONTROLLERS 3 +#define PCH_ISH_MAX_SPI_CONTROLLERS 1 + +// +// SCS limits +// +#define PCH_SCS_MAX_CONTROLLERS 3 ///< Number of Storage and Communication Subsystem controllers, this includes eMMC, SDIO, SDCARD + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +// +// Number of eSPI slaves +// +#define PCH_ESPI_MAX_SLAVE_ID 2 + +#define PCH_PCIE_SWEQ_COEFFS_MAX 5 + +#define LBG_A0 0x30 + +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/LewisburgPkg/Include/PchPolicyCommon.h b/Silicon/Intel/LewisburgPkg/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..3e6f06ffe7 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/PchPolicyCommon.h @@ -0,0 +1,2212 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include "PchLimits.h" + +#pragma pack (push,1) +// +// ---------------------------- PCH General Config ------------------------------- +// + +typedef struct { + /** + Subsystem Vendor ID and Subsystem ID of the PCH devices. + This fields will be ignored if the value of SubSystemVendorId and SubSystemId + are both 0. + **/ + UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. Default is <b>0x8086</b> + UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. Default is <b>0x7270</b> + /** + This member describes whether or not the Compatibility Revision ID (CRID) feature + of PCH should be enabled. <b>0: Disable</b>; 1: Enable + **/ + UINT32 Crid : 1; + UINT32 EnableClockSpreadSpec : 1; + UINT32 Serm : 1; + UINT32 RsvdBits0 : 30; ///< Reserved bits + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_GENERAL_CONFIG; + + +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define PLATFORM_POR 0 +#define AUTO 0 +// +// ---------------------------- Reserved Page Config ----------------------------- +// + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +}; + +// +// ---------------------------- PCI Express Config ---------------------- +// + +enum PCH_PCIE_SPEED { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2, + PchPcieGen3 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_2, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 = 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +enum PCH_PCIE_COMPLETION_TIMEOUT { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +}; + +enum PCH_PCIE_MPL { + PchPcieMaxPayLoad128B, + PchPcieMaxPayLoad256B, + PchPcieMaxPayLoad512B, +}; + +typedef enum { + PchPcieEqDefault = 0, ///< Use reference code default (software margining) + PchPcieEqHardware = 1, ///< Hardware equalization (experimental), note this requires PCH-LP C0 or PCH-H D0 or newer + PchPcieEqSoftware = 2, ///< Use software margining flow + PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane) +} PCH_PCIE_EQ_METHOD; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. +**/ +typedef struct { + UINT32 Enable : 1; ///< Root Port enabling, 0: Disable; <b>1: Enable</b>. + UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>. + UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>. + UINT32 RsvdBits0 : 5; ///< Reserved bits. + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port. + /** + The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE. + This Number should not exceed the Maximum Available ClkReq Signals for LP and H. + **/ + UINT32 ClkReqNumber : 4; + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts + to verify CLKREQ# signal is connected by testing pad state before enabling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + <b>0: Disable</b>; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable. + /** + Max Payload Size supported, Default <b>128B</b>, see enum PCH_PCIE_MAX_PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the root port. + **/ + UINT32 MaxPayload : 2; + UINT32 RsvdBits1 : 4; ///< Reserved fields for future expansion w/o protocol change + + UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether PERST# is active <b>0: Low</b>; 1: High, See: DeviceResetPad + /** + Determines each PCIE Port speed capability. + <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + /** + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). + <b>0: Default</b>; 2: Software Search; 4: Fixed Coeficients + **/ + UINT8 Gen3EqPh3Method; + + UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>. + /** + The PCH pin assigned to device PERST# signal if available, zero otherwise. + This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices + (mainly some graphic adapters) to successfully complete the software equalization flow. + See also DeviceResetPadActiveHigh + **/ + UINT32 DeviceResetPad; + UINT32 Rsvd1; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>. + UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>. + UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable. + UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>. + UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplie by slot. Leave as 0 to set to default. Default is <b>zero</b>. + + UINT32 HsioRxSetCtleEnable : 1; ///< @deprecated, please use HsioRxSetCtleEnable from PCH_HSIO_PCIE_LANE_CONFIG + UINT32 HsioRxSetCtle : 6; ///< @deprecated, please use HsioRxSetCtle from PCH_HSIO_PCIE_LANE_CONFIG + // + // Gen3 Equaliztion settings + // + UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>5</b>. + UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>. + UINT32 RsvdBits3 : 3; ///< Reserved Bits + UINT32 Rsvd2[16]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/// +/// The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers +/// +typedef struct { + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// Pci Delay (Latency) Optimization ECR - Engineering Change Request + /// + UINT8 PciDelayOptimizationEcr; + /// + /// Pch Pcie Max Read Request Size + /// + UINT8 MaxReadRequestSize; + /// + /// Gen3 Equalization settings for physiacal PCIe lane, index 0 represents PCIe lane 1, etc. + /// Correstponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default). + /// + PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable. + /// + UINT32 EnablePort8xhDecode : 1; + /// + /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based) + /// + UINT32 PchPciePort8xhDecodePortIndex : 5; + /// + /// This member describes whether the PCI Express Clock Gating for each root port + /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable. + /// + UINT32 DisableRootPortClockGating : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable + or leaving untouched. + - <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b> + - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are + presented for maximum power savings where possible. + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device + functionality. + - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability. + **/ + UINT32 AllowNoLtrIccPllShutdown : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board. + <b>0: Disable</b>, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than 0 enabled root ports. + - <b>Enabled: One of enabled root ports get assigned to Function0.</b> + This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage + NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal, or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + + UINT32 RsvdBits0 : 21; + /** + The number of milliseconds reference code will wait for link to exit Detect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port initialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful + if device power-up seqence is controlled by BIOS or a specific device requires more time to detect. + I case of non-common clock enabled the default timout is 15ms. + <b>Default: 0</b> + **/ + UINT16 DetectTimeoutMs; + + /// + /// These are Competions Timeout settings for Uplink ports in Server PCH + /// + UINT8 PchPcieUX16CompletionTimeout; + UINT8 PchPcieUX8CompletionTimeout; + + /// + /// Max Payload Size settings for Upling ports in Server PCH + /// + UINT8 PchPcieUX16MaxPayload; + UINT8 PchPcieUX8MaxPayload; + + /// + /// Intel+ Virtual Technology for Directed I/O (VT-d) Support + /// + UINT8 VTdSupport; + UINT16 Rsvd0; ///< Reserved bytes + UINT32 Rsvd1[2]; ///< Reserved bytes +} PCH_PCIE_CONFIG; + + +/// +/// The PCH_PCIE_CONFIG2 block describes the additional configuration of the PCH PCI Express controllers +/// +typedef struct { + PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX]; ///< List of coefficients used during equalization (applicable to both software and hardware EQ) + PCH_PCIE_EQ_PARAM Rsvd0[3]; + UINT32 Rsvd1[4]; +} PCH_PCIE_CONFIG2; + +typedef struct { + UINT8 PchAdrEn; + UINT8 AdrTimerEn; + UINT8 AdrTimerVal; + UINT8 AdrMultiplierVal; + UINT8 AdrGpioSel; + UINT8 AdrHostPartitionReset; +} PCH_ADR_CONFIG; + +/** + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane +**/ +typedef struct { + // + // HSIO Rx Eq + // Refer to the EDS for recommended values. + // Note that these setting are per-lane and not per-port + // + UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved Bits + + UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 11; ///< Reserved Bits + + // + // Server specific offsets + // + UINT32 HsioIcfgAdjLimitLoEnable : 1; /// < <b>0: Disable</b>; 1: Enable Set the floor on how many ticks the autovref can take. + UINT32 HsioIcfgAdjLimitLo : 5; /// < Set the floor on how many ticks the autovref can take. (offset 0x9c) + UINT32 HsioSampOffstEvenErrSpEnable : 1; /// < <b>0: Disable</b>; 1: Enable EVEN ERR P sampler manual offset. + UINT32 HsioSampOffstEvenErrSp : 8; /// < EVEN ERR P sampler manual offset. (offset 0xA0) + UINT32 RsvdBits2 : 17; ///< Reserved Bits + + UINT32 HsioRemainingSamplerOffEnable : 1; /// < <b>0: Disable</b>; 1: Enable Remaining EVEN/ODD ERR P and N sampler manual offset. + UINT32 HsioRemainingSamplerOff : 24; /// < Remaining EVEN/ODD ERR P and N sampler manual offset. (offset 0xA4) + UINT32 HsioVgaGainCalEnable : 1; /// < <b>0: Disable</b>; 1: Enable VGA Gain CAL + UINT32 HsioVgaGainCal : 5; /// < VGA Gain Calibration Value (offset 0x1C) + UINT32 RsvdBits3 : 1; ///< Reserved Bits + + UINT32 Rsvd4[12]; ///< Reserved bytes + +} PCH_HSIO_PCIE_LANE_CONFIG; + +/// +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_CONFIG; + + +/// +/// The PCH_HSIO_PCIE_WM20_CONFIG block describes the configuration of the HSIO for PCIe lanes +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_WM20_LANES_NUMBER]; + UINT32 Rsvd0[3]; ///< Reserved bytes + +} PCH_HSIO_PCIE_WM20_CONFIG; + +// +// ---------------------------- EVA Config ----------------------------- +// + +// EVA port function hide registers. + +typedef union { + UINT32 FuncHideVal; + struct _FuncHideBits { + UINT32 PchEvaMROM0Enable : 1; ///< MROM is never hidden + UINT32 PchEvaMROM1Hidden : 1; ///< Enable/disable MROM1 funcion, 1 - hidden + UINT32 RsvdBits1 : 3; + UINT32 PchEvasSata1Hidden : 1; ///< Enable/disable sSata1, 1 - hidden + UINT32 RsvdBits2 : 25; + UINT32 PchEvaLock : 1; ///< Lock registers in EVA + + } FuncHideBits; +} +PCH_EVA_DNDEVFUNCHIDE; + + +typedef struct { + PCH_EVA_DNDEVFUNCHIDE FuncHide; + UINT8 LockDown; +} +PCH_EVA_CONFIG; +// +// ---------------------------- SATA Config ----------------------------- +// + +typedef enum { + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +typedef enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedDefault, + PchSataSpeedGen1, + PchSataSpeedGen2, + PchSataSpeedGen3 +} PCH_SATA_SPEED; + +/** + This structure configures the features, property, and capability for each SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b> + UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable + UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable + UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable + UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD + UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>. + /** + Support zero power ODD <b>0: Disable</b>, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 RsvdBits0 : 9; ///< Reserved fields for future expansion w/o protocol change + + UINT32 HsioRxEqBoostMagAdEnable : 1; ///< @deprecated, please use HsioRxGen3EqBoostMagEnable + UINT32 HsioRxEqBoostMagAd : 6; ///< @deprecated, please use HsioRxGen3EqBoostMag + + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< @deprecated, please use HsioTxGen1DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen1DownscaleAmp : 6; ///< @deprecated, please use HsioTxGen1DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< @deprecated, please use HsioTxGen2DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + UINT32 HsioTxGen2DownscaleAmp : 6; ///< @deprecated, please use HsioTxGen2DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + UINT32 Rsvd0 : 11; ///< Reserved bits + +} PCH_SATA_PORT_CONFIG; + +/** + Rapid Storage Technology settings. +**/ +typedef struct { + UINT32 RaidAlternateId : 1; ///< <b>0: Disable</b>; 1: Enable RAID Alternate ID + UINT32 Raid0 : 1; ///< 0: Disable; <b>1: Enable</b> RAID0 + UINT32 Raid1 : 1; ///< 0: Disable; <b>1: Enable</b> RAID1 + UINT32 Raid10 : 1; ///< 0: Disable; <b>1: Enable</b> RAID10 + UINT32 Raid5 : 1; ///< 0: Disable; <b>1: Enable</b> RAID5 + UINT32 Irrt : 1; ///< 0: Disable; <b>1: Enable</b> Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0: Disable; <b>1: Enable</b> OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< <b>00b: 2 secs</b>; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0: Disable; <b>1: Enable</b>. Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0: Disable; <b>1: Enable</b> RST Smart Storage caching Bit + UINT32 EfiRaidDriverLoad :1; ///< 0: Dont load EFI RST/RSTe driver; <b>1: Load EFI RST/RSTe driver + UINT32 Resvdbits : 18; ///< Reserved Bits +} PCH_SATA_RST_CONFIG; + +/** + This structure describes the details of Intel RST for PCIe Storage remapping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>) + The supported ports for PCIe Storage remapping is different depend on the platform and cycle router, the assignments are as below: + SKL PCH-LP RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8 + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12 + + SKL PCH-H RST PCIe Storage Cycle Router Assignment: + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12 + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16 + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20 + **/ + UINT32 RstPcieStoragePort : 5; + UINT32 RsvdBits0 : 2; ///< Reserved bit + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step. + Default value is <b>100ms</b>. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits1 : 16; ///< Reserved bits + + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_RST_PCIE_STORAGE_CONFIG; + +/// +/// The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers. +/// +typedef struct { + /// + /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side. + /** + eSATASpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + Please be noted, this setting could be cleared by HBA reset, which might be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should preserve the + setting before and after initialization. For support it after POST, it's dependent on + driver's behavior. + <b>0: Disable</b>; 1: Enable + **/ + UINT32 eSATASpeedLimit : 1; + UINT32 EnclosureSupport : 1; ///< 0: Disable; 1: Enable Enclosure Management Support + UINT32 Rsvdbits : 26; ///< Reserved bits + + /** + Determines the system will be configured to which SATA mode (PCH_SATA_MODE). Default is <b>PchSataModeAhci</b>. + **/ + PCH_SATA_MODE SataMode; + /** + Indicates the maximum speed the SATA controller can support + <b>0h: PchSataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1) + **/ + PCH_SATA_SPEED SpeedLimit; + /** + This member configures the features, property, and capability for each SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + PCH_SATA_RST_CONFIG Rst; ///< Setting applicable to Rapid Storage Technology + /** + This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR]; + UINT32 Rsvd0[4]; ///< Reserved fields for future expansion +} PCH_SATA_CONFIG; + + +/** + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane +**/ +typedef struct { + + // + // HSIO Rx Eq + // + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value + + // + // HSIO Tx Eq + // + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved bits + + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment + UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + + UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 4; ///< Reserved bits + + UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + UINT32 RsvdBits2 : 25; ///< Reserved bits + + UINT32 Rsvd0[8]; ///< Reserved bytes +} PCH_HSIO_SATA_PORT_LANE; + + +/// +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. +/// +typedef struct { + /// + /// These members describe the configuration of HSIO for SATA lanes. + /// + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; + UINT32 Rsvd0[8]; ///< Reserved bytes + +} PCH_HSIO_SATA_CONFIG; + +// +// --------------------------- IO APIC Config ------------------------------ +// +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can + program this field to provide a unique Bus:Device:Function number for the + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, PCH code will not program these fields if this bit is not TRUE. <b>0: Disable</b>; 1: Enable. + UINT32 RsvdBits0 : 7; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0xF0</b>. + UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x1F</b>. + UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x00</b>. + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119 + UINT32 RsvdBits1 : 7; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>. + UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is <b>0</b> + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +// +// ---------------------------- HPET Config ----------------------------- +// + +/** + The PCH_HPET_CONFIG block passes the bus/device/function value for HPET. + The address resource range of HPET must be reserved in E820 and ACPI as + system resource. +**/ +typedef struct { + /** + Determines if enable HPET timer. 0: Disable; <b>1: Enable</b>. + The HPET timer address decode is always enabled. + This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI. + While enabled, the HPET timer is started, else the HPET timer is halted. + **/ + UINT32 Enable : 1; + UINT32 BdfValid : 1; ///< Whether the BDF value is valid. <b>0: Disable</b>; 1: Enable. + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is <b>0xF0</b>. + UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is <b>0x1F</b>. + UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is <b>0x00</b>. + UINT32 RsvdBits1 : 8; ///< Reserved bits + UINT32 Base; ///< The HPET base address. Default is <b>0xFED00000</b>. +} PCH_HPET_CONFIG; + +// +// --------------------------- HD-Audio Config ------------------------------ +// +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature. +/// +#define PCH_HDAUDIO_AUTO 2 + +enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP { + PchHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers. + PchHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers. + PchHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers. +}; + +enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE { + PchHdaIoBuf33V = 0, + PchHdaIoBuf18V = 1 +}; + +enum PCH_HDAUDIO_VC_TYPE { + PchHdaVc0 = 0, + PchHdaVc1 = 1 +}; + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled = 0, + PchHdaDmic2chArray = 1, + PchHdaDmic4chArray = 2, + PchHdaDmic1chArray = 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz = 0, + PchHdaLinkFreq12MHz = 1, + PchHdaLinkFreq24MHz = 2, + PchHdaLinkFreq48MHz = 3, + PchHdaLinkFreq96MHz = 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T = 0, + PchHdaIDispMode1T = 1 +} PCH_HDAUDIO_IDISP_TMODE; + +typedef struct { + /** + This member describes whether or not Intel HD Audio (Azalia) should be enabled. + If enabled (in Auto mode) and no codec exists the reference code will automatically disable + the HD Audio device. + 0: Disable, 1: Enable, <b>2: Auto (enabled if codec detected and initialized, disabled otherwise)</b> + **/ + UINT32 Enable : 2; + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b> + UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable + UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: <b>0: HD-A Link</b>; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports + UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: <b>0: 3.3V</b>; 1: 1.8V + UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz + UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): <b>0: 2T</b>, 1: 1T + /** + Universal Audio Architecture compliance for DSP enabled system: + <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>, + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable + UINT32 RsvdBits0 : 13; ///< Reserved bits 1 + /** + Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI table: + **/ + UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; <b>2: 4ch array</b>; 3: 1ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: <b>0: Disable</b>; 1: Enable + UINT32 DspEndpointI2s : 1; ///< I2S enablement: <b>0: Disable</b>; 1: Enable + UINT32 RsvdBits1 : 28; ///< Reserved bits 2 + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation + Default is <b>zero</b>. + **/ + UINT32 DspFeatureMask; + /** + Bitmask of supported DSP Pre/Post-Processing Modules. + Specific pre/post-processing module bit position must be coherent with the ACPI implementation: + \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support. + DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable + Default is <b>zero</b>. + **/ + UINT32 DspPpModuleMask; + UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>. + UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4 +} PCH_HDAUDIO_CONFIG; + +// +// ------------------------------ LAN Config --------------------------------- +// + +/** + PCH intergrated LAN controller configuration settings. +**/ +typedef struct { + /** + Determines if enable PCH internal LAN, 0: Disable; <b>1: Enable</b>. + When Enable is changed (from disabled to enabled or from enabled to disabled), + it needs to set LAN Disable regsiter, which might be locked by FDSWL register. + So it's recommendated to issue a global reset when changing the status for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management; 1: Enabled, <b>0: Disabled</b>; + UINT32 RsvdBits0 : 4; ///< Reserved bits + UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported; 1: Enabled, <b>0: Disabled</b>; + UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReqSupported is TRUE. + UINT32 RsvdBits1 : 21; ///< Reserved bits + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LAN_CONFIG; + +// +// --------------------------- SMBUS Config ------------------------------ +// + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. +/// +typedef struct { + /** + This member describes whether or not the SMBus controller of PCH should be enabled. + 0: Disable; <b>1: Enable</b>. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating. + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_CONFIG; + +// +// --------------------------- Lock Down Config ------------------------------ +// +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH + for security requirement. +**/ +typedef struct { + /** + <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; <b>1: Enable</b>. + **/ + UINT32 GlobalSmi : 1; + /** + <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>. + **/ + UINT32 BiosInterface : 1; + /** + <b>(Test)</b> Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and lower 128-byte bank of RTC RAM. 0: Disable; <b>1: Enable</b>. + **/ + UINT32 RtcLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region can only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to take care + of BIOS modification (including SetVariable) in DXE or runtime phase after + EndOfDxe protocol is installed. <b>0: Disable</b>; 1: Enable. + **/ + UINT32 BiosLock : 1; + /** + Enable InSMM.STS (EISS) in SPI + If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also + in order to write to BIOS regions of SPI Flash. If this bit is clear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programming in + PEI phase or early DXE phase. + 0: Clear EISS bit; <b>1: Set EISS bit</b>. + **/ + UINT32 SpiEiss : 1; + /** + Lock configuration and/or state of vendor-defined set of GPIOs. + 0: Don't lock; 1: Lock + **/ + UINT32 GpioLockDown : 1; + /** + Lock TCO Base Address. + D31:F4 (SMBus Controller) Offset 54h: TCOCTL (TCO Control Register) Bit 0: TCO_BASE_LOCK (TCO Base Lock) + 0: Don't lock; 1: Lock + **/ + UINT32 TcoLock : 1; + + /** + <b>(Test)</b> Enable Lock bit for Device Function Hide Register in + MS Unit Device Function Hide Control Register (MSDEVFUNCHIDE) + 0: Disable; <b>1: Enable</b>. + **/ + UINT32 EvaLockDown : 1; + UINT32 RsvdBits0 : 24; ///< Reserved bits +} PCH_LOCK_DOWN_CONFIG; + +// +// --------------------------- Thermal Config ------------------------------------ +// +/** + This structure lists PCH supported throttling register setting for custimization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH + thermal status to the processor which is factored into the processor throttling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +/** + This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Width + UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Width + UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Width + UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Width + UINT32 RsvdBits1 : 16; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure lists PCH supported SATA thermal throttling register setting for custimization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLE; + +/** + This structure decides the settings of PCH Thermal throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. +**/ +typedef struct { + THERMAL_THROTTLE_LEVELS TTLevels; + DMI_HW_WIDTH_CONTROL DmiHaAWC; + SATA_THERMAL_THROTTLE SataTT; + SATA_THERMAL_THROTTLE sSataTT; +} PCH_THERMAL_THROTTLING; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b> + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4. + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b> + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy. + <b>0: Disable</b>; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal. +**/ +typedef struct { + /** + This field reports the status of Thermal Device. When it reports ThermalDevice + is disabled, the PCI configuration space of thermal device will be hidden by + setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST. + **/ + UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled in PCI mode</b>, 2: Enabled in ACPI mode + UINT32 TsmicLock : 1; ///< This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1: <b>Enabled</b>. + UINT32 RsvdBits0 : 29; + /** + This field decides the settings of Thermal throttling. When the Suggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + PCH_THERMAL_THROTTLING ThermalThrottling; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + This field decides the temperature, default is <b>zero</b>. + - 0x00 is the hottest + - 0x1FF is the lowest temperature + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; +} PCH_THERMAL_CONFIG; + +enum PCH_THERMAL_DEVICE { + PchThermalDeviceDisabled, + PchThermalDeviceEnabledPci, + PchThermalDeviceEnabledAcpi, + PchThermalDeviceAuto +}; + +// +// ---------------------- Power Management Config -------------------------- +// +/** + This PCH_POWER_RESET_STATUS Specifies which Power/Reset bits need to be cleared by the PCH Init Driver. + Usually platform drivers take care of these bits, but if not, let PCH Init driver clear the bits. +**/ +typedef struct { + UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>. + UINT32 MeHrstColdSts : 1; ///< Clear the ME_HRST_COLD_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>. + UINT32 MeHrstWarmSts : 1; ///< Clear the ME_HRST_WARM_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>. + UINT32 MeHostPowerDn : 1; ///< Clear the ME_HOST_PWRDN bit in the Power and Reset Status (PRSTS) register. <b>0: Disable</b>; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>. + UINT32 RsvdBits0 : 27; +} PCH_POWER_RESET_STATUS; + +/** + This PCH_GBL2HOST_EN specifes enable bits related to the "Convert Global Resets to Host Resets" (G2H) feature +**/ +typedef union { + struct { + UINT32 G2H_FEA : 1; ///< G2H Feature Enable: 0: Disable; <b>1: Enable</b>. + UINT32 LTRESET : 1; ///< LT RESET G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 PMCGBL : 1; ///< PMC FW-Initiated Global Reset G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 CPUTHRM : 1; ///< CPU Thermal Trip G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 PCHTHRM : 1; ///< PCH Internal Thermal Trip G2H Enable: Disable; <b>1: Enable</b>. + UINT32 PBO : 1; ///< Power Button Override G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 MEPBO : 1; ///< ME-Initiated Power Button Override G2H: 0: Disable; <b>1: Enable</b>. + UINT32 MEWDT : 1; ///< ME FW Watchdog Timer G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 MEGBL : 1; ///< ME-Initiated Global Reset G2H Enable: Disable; <b>1: Enable</b>. + UINT32 CTWDT : 1; ///< CPU Thermal Watchdog Timer G2H Enable: Disable; <b>1: Enable</b>. + UINT32 PMCWDT : 1; ///< PMC FW Watchdog Timer G2H Enable: Disable; <b>1: Enable</b>. + UINT32 ME_UERR : 1; ///< ME Uncorrectable Error G2H Enable: Disable; <b>1: Enable</b>. + UINT32 SYSPWR : 1; ///< SYS_PWROK Failure G2H Enable: Disable; <b>1: Enable</b>. + UINT32 OCWDT : 1; ///< Over-Clocking WDT G2H Enable: Disable; <b>1: Enable</b>. + UINT32 PMC_PARERR : 1; ///< PMC Parity Error G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 Reserved : 1; ///< Reserved + UINT32 IEPBO : 1; ///< IE-Initiated Power Button Override G2H: 0: Disable; <b>1: Enable</b>. + UINT32 IEWDT : 1; ///< IE FW Watchdog Timer G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 IEGBLN : 1; ///< IE-Initiated Global Reset G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 IE_UERRN : 1; ///< IE Uncorrectable Error G2H Enable: 0: Disable; <b>1: Enable</b>. + UINT32 ACRU_ERR_2H_EN : 1; ///< AC RU Error G2H Enable: 0: Disable; <b>1: Enable</b>. + } Bits; + UINT32 Value; +} PCH_GBL2HOST_EN; + +/** + This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>. + UINT32 Gp27WakeFromDeepSx : 1; ///< @deprecated + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>. + UINT32 RsvdBits0 : 25; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, + PchDpS3S4S5BatteryEn, + PchDpS3S4S5AlwaysEn +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s +} PCH_SLP_A_MIN_ASSERT; + +typedef enum { + PchPmGrPfetDur1us, + PchPmGrPfetDur2us, + PchPmGrPfetDur5us, + PchPmGrPfetDur20us +} PCH_PM_GR_PFET_DUR; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power management settings. + The PowerResetStatusClear field would clear the Power/Reset status bits, please + set the bits if you want PCH Init driver to clear it, if you want to check the + status later then clear the bits. +**/ +typedef struct { + /** + Specify which Power/Reset bits need to be cleared by + the PCH Init Driver. + Usually platform drivers take care of these bits, but if + not, let PCH Init driver clear the bits. + **/ + PCH_POWER_RESET_STATUS PowerResetStatusClear; + PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy + PCH_DEEP_SX_CONFIG PchDeepSxPol; ///< Deep Sx Policy. Default is <b>PchDeepSxPolDisable</b>. + PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert; ///< SLP_S3 Minimum Assertion Width Policy. Default is <b>PchSlpS350ms</b>. + PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert; ///< SLP_S4 Minimum Assertion Width Policy. Default is <b>PchSlpS44s</b>. + PCH_SLP_SUS_MIN_ASSERT PchSlpSusMinAssert; ///< SLP_SUS Minimum Assertion Width Policy. Default is <b>PchSlpSus4s</b>. + PCH_SLP_A_MIN_ASSERT PchSlpAMinAssert; ///< SLP_A Minimum Assertion Width Policy. Default is <b>PchSlpA2s</b>. + /** + This member describes whether or not the PCI ClockRun feature of PCH should + be enabled. <b>0: Disable</b>; 1: Enable + **/ + UINT32 PciClockRun : 1; + UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + <b>Default is 0: 4s</b> + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + <b>(Test)</b> + Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable. + Enery Report is must have feature. Wihtout Energy Report, the performance report + by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to try to reduce + its power by throttling, then it could try to disable Energy Report to do first debug. + This might be due to energy scaling factors are not correct or the LPM settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is <b>0:Disable</b> + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + <b>(Test)</b> + When set to true, this bit disallows host reads to PMC XRAM. + BIOS must set this bit (to disable and lock the feature) prior to passing control to OS + 0:Disable, <b>1:Enable</b> + **/ + UINT32 PmcReadDisable : 1; + /** + This determines the type of reset issued during the capsule update process by UpdateCapsule(). + The default is <b>0:S3 Resume</b>, 1:Warm reset. + **/ + UINT32 CapsuleResetType : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted. + <b>Default is FALSE.</b> + **/ + UINT32 DisableNativePowerButton : 1; + /** + Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. + When set to one SLP_S0# will be asserted in idle state. + When set to zero SLP_S0# will not toggle and is always drivern high. + 0:Disable, <b>1:Enable</b> + + Warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# being asserted. + If a platform is using SLP_S0 to lower PCH voltage the below policy must be disabled. + **/ + UINT32 SlpS0Enable : 1; + UINT32 DirtyWarmReset : 1; ///< DirtyWarmReset enable + UINT32 StallDirtyWarmReset : 1; ///< Stall during DWR + UINT32 GrPfetDurOnDef : 2; ///< Global Reset PFET duration + UINT32 Dwr_MeResetPrepDone : 1; ///< ME Reset Prep Done + UINT32 Dwr_IeResetPrepDone : 1; ///< IE Reset Prep Done + UINT32 Dwr_BmcRootPort : 8; ///< Root port where BMC is connected to + UINT32 RsvdBits0 : 6; ///< @todo ADD DESCRIPTION + + PCH_GBL2HOST_EN PchGbl2HostEn; + /** + Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where + <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. + And make sure the setting correct, which never less than the following register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is <b>0xFF: AUTO - No BIOS override</b>. + **/ + UINT8 PciePllSsc; + UINT8 Rsvd0[2]; ///< Reserved bytes + +} PCH_PM_CONFIG; + +// +// ---------------------------- DMI Config ----------------------------- +// + +/// +/// The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. +/// +typedef struct { + /** + 0: Disable; <b>1: Enable</b> ASPM on PCH side of the DMI Link. + While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value. + **/ + UINT32 DmiAspm : 1; + UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side. + BOOLEAN DmiStopAndScreamEnable : 1; + UINT32 DmiLinkDownHangBypass : 1; + UINT32 Rsvdbits : 29; + UINT32 Rsvd0[6]; ///< Reserved bytes +} PCH_DMI_CONFIG; + +// +// --------------------------- Serial IRQ Config ------------------------------ +// + +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of the PCH for Serial IRQ. +/// +typedef struct { + UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; <b>1: Enable</b>. + UINT32 RsvdBits0 : 31; ///< Reserved bits + PCH_SIRQ_MODE SirqMode; ///< Serial IRQ Mode Select. <b>0: quiet mode</b> 1: continuous mode. + PCH_START_FRAME_PULSE StartFramePulse; ///< Start Frame Pulse Width. Default is <b>PchSfpw4Clk</b>. + UINT32 Rsvd0; ///< Reserved bytes +} PCH_LPC_SIRQ_CONFIG; + + +// +// --------------------------- Port 61h Emulation in SMM ------------------------------ +// +/** + This structure is used for the emulation feature for Port61h read. The port is trapped + and the SMI handler will toggle bit4 according to the handler's internal state. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b> the emulation + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_PORT61H_SMM_CONFIG; + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< Array which stores interrupt routing for 8259 controller + UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>. + UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>. + UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>. + UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable. +} PCH_INTERRUPT_CONFIG; + +// +// --------------------- TraceHub Config ------------------------------ +// + +/// +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH. +/// +typedef struct { + UINT32 EnableMode : 2; ///< 0 = Disable <b> 2 = Host Debugger enabled </b> + UINT32 PchTraceHubHide : 1; + UINT32 RsvdBits0 : 29; ///< Reserved bits + UINT32 MemReg0Size; ///< Default is <b>0 (none)</b>. + UINT32 MemReg1Size; ///< Default is <b>0 (none)</b>. +} PCH_TRACE_HUB_CONFIG; + + +// +// ------------------- CIO2 FLIS registers Config -------------------- +// + +/// +/// The PCH_SKYCAM_CIO2_FLS_CONFIG block describes SkyCam CIO2 FLS registers configuration. +/// +typedef struct { + UINT32 PortATrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port A Clk Trim + UINT32 PortBTrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port B Clk Trim + UINT32 PortCTrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port C Clk Trim + UINT32 PortDTrimEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port D Clk Trim + UINT32 PortACtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port A Ctle + UINT32 PortBCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port B Ctle + UINT32 PortCDCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable - Enable Port C/D Ctle + UINT32 RsvdBits0 : 25; + + UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value + UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value + UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value + UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value + UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value + UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value + UINT32 RsvdBits1 : 5; + + UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value + UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value + UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value + UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value + UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value + + UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value + UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value + +} PCH_SKYCAM_CIO2_FLS_CONFIG; +// +// ---------------------------- USB Config ----------------------------- +// +/// +/// Overcurrent pins, the values match the setting of PCH EDS, please refer to PCH EDS for more details +/// +#ifndef PCH_USB_OVERCURRENT_PIN_TYPE +#define PCH_USB_OVERCURRENT_PIN_TYPE +typedef enum { + PchUsbOverCurrentPin0 = 0, + PchUsbOverCurrentPin1, + PchUsbOverCurrentPin2, + PchUsbOverCurrentPin3, + PchUsbOverCurrentPin4, + PchUsbOverCurrentPin5, + PchUsbOverCurrentPin6, + PchUsbOverCurrentPin7, + PchUsbOverCurrentPinSkip, + PchUsbOverCurrentPinMax +} PCH_USB_OVERCURRENT_PIN; +#endif + +/// +/// The location of the USB connectors. This information is use to decide eye diagram tuning value for Usb 2.0 motherboard trace. +/// +enum PCH_USB_PORT_LOCATION{ + PchUsbPortLocationBackPanel = 0, + PchUsbPortLocationFrontPanel, + PchUsbPortLocationDock, + PchUsbPortLocationMiniPciE, + PchUsbPortLocationFlex, + PchUsbPortLocationInternalTopology, + PchUsbPortLocationSkip, + PchUsbPortLocationMax +}; + + +/** + This structure configures per USB2 AFE settings. + It allows to setup the port parameters. +**/ +typedef struct { +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Petxiset; +/** Per Port HS Transmitter Bias (PERPORTTXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Txiset; +/** + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) + 00b - Emphasis OFF + 01b - De-emphasis ON + 10b - Pre-emphasis ON + 11b - Pre-emphasis & De-emphasis ON +**/ + UINT8 Predeemp; +/** + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) + 1b - half-bit pre-emphasis + 0b - full-bit pre-emphasis +**/ + UINT8 Pehalfbit; +} PCH_USB20_AFE; + +/** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures the port strength accordingly. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 2.0 Port N. + It is SW's responsibility to ensure that a given port's bit map is set only for + one OC pin Description. USB2 and USB3 on the same combo Port must use the same + OC pin (see: PCH_USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4. + PCH_USB20_AFE Afe; ///< USB2 AFE settings + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB20_PORT_CONFIG; + +/** + This structure describes whether the USB3 Port N of PCH is enabled by platform modules. +**/ +typedef struct { + UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>. + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + These members describe the specific over current pin number of USB 3.0 Port N. + It is SW's responsibility to ensure that a given port's bit map is set only for + one OC pin Description. USB2 and USB3 on the same combo Port must use the same + OC pin (see: PCH_USB_OVERCURRENT_PIN). + **/ + UINT8 OverCurrentPin; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4 + + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable. + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) + HSIO_TX_DWORD5[21:16] + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis) + **/ + UINT32 HsioTxDeEmph : 6; + + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable. + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + <b>Default = 00h</b> + **/ + UINT32 HsioTxDownscaleAmp : 6; + + UINT32 RsvdBits1 : 18; ///< Reserved bits + UINT32 Rsvd1[1]; ///< Reserved bytes +} PCH_USB30_PORT_CONFIG; + +#define PCH_XHCI_MODE_OFF 0 +#define PCH_XHCI_MODE_ON 1 + +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + /** + 0: Disable; <b>1: Enable</b> SSIC support. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits1 : 31; +} PCH_XHCI_SSIC_PORT; +/** + These members describe some settings which are related to the SSIC ports. +**/ +typedef struct { + PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT]; +} PCH_SSIC_CONFIG; + +/** + The PCH_XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be enabled. + 0: Disable; <b>1: Enable</b>. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_XDCI_CONFIG; + + +/** + This member describes the expected configuration of the PCH USB controllers, + Platform modules may need to refer Setup options, schematic, BIOS specification + to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring + the schematic. +**/ +typedef struct { + /** + This feature intends to reduce the necessary initialization time for USB HC + and devices on root ports. It is assembled by PCHInit drivers in PEI and DXE phase. + In PEI phase, the feature resets all USB HCs on PCH bus, including Intel EHCI + and XHCI. After reset USB HC, continue the system initialization without waiting + for the USB XHC reset ready. After running to DXE phase, the feature resets + those USB devices installed on each USB HC root port in parallel, including + any non USB3 speed devices on XHCI root port if XHCI is enabled. + For USB3 protocol root port, USB3 speed devices will be advanced to + enable state if link training succeeds after XHC reset. + + UsbPrecondition = Enable , Force USB Init happen in PEI as part of 2Sec Fast Boot bios optimization. + UsbPrecondition = Disable, USB Init happen in DXE just like traditionally where it happen. + Remark: With Precondition Enabled some USB2 devices which are not compliant with usb2 specification + are not being detected if installed in the system during S4/S5. + + + <b>0: Disable</b>; 1: Enable. + **/ + UINT32 UsbPrecondition : 1; + /** + This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled. + For the platform that support USB Type-C, it can disable Compliance Mode, and enable Compliance Mode when testing. + <b>0:Disable</b> , 1: Enable + **/ + UINT32 DisableComplianceMode : 1; + // Following option is now exposed since there are no restricted registers used. + UINT32 XhciOcMapEnabled : 1; ///< 0: To disable OC mapping for USB XHCI ports 1: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI Access Control Bit. + UINT32 XhciWakeOnUsb : 1; ///< 0: To disable Wake on USB connect/Disconnect 1: Enables Wake on USB connect/disconnect event. + UINT32 XhciDisMSICapability : 1; + UINT32 RsvdBits0 : 27; ///< Reserved bits + + /** + These members describe whether the USB2 Port N of PCH is enabled by platform modules. + Panel and Dock are used to describe the layout of USB port. Panel is only available for Desktop PCH. + Dock is only available for Mobile LPT. + **/ + PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by platform modules. + **/ + PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be enabled. + **/ + PCH_XDCI_CONFIG XdciConfig; + /** + These members describe some settings which are related to the SSIC ports. + **/ + PCH_SSIC_CONFIG SsicConfig; + + UINT32 Rsvd0[6]; ///< Reserved bytes +} PCH_USB_CONFIG; + +// +// --------------------------- Flash Protection Range Registers ------------------------------ +// +/** + The PCH provides a method for blocking writes and reads to specific ranges + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine, + and set the limit and base accordingly. +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; +} PCH_FLASH_PROTECTION_CONFIG; + +// +// --------------------- WatchDog (WDT) Configuration ------------------------------ +// +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable. + UINT32 RsvdBits : 31; +} PCH_WDT_CONFIG; + +// +// --------------------- P2SB Configuration ------------------------------ +// +/** + This structure contains the policies which are related to P2SB device. +**/ +typedef struct { + /** + <b>(Test)</b> + This unlock the SBI lock bit to allow SBI after post time. <b>0: Disable</b>; 1: Enable. + NOTE: Do not set this policy "SbiUnlock" unless necessary. + **/ + UINT32 SbiUnlock : 1; + /** + <b>(Test)</b> + The PSF registers will be locked before 3rd party code execution. + This policy unlock the PSF space. <b>0: Disable</b>; 1: Enable. + NOTE: Do not set this policy "PsfUnlock" unless necessary. + **/ + UINT32 PsfUnlock : 1; + /** + <b>Debug</b> + The P2SB PCIe device will be hidden at end of PEI stage. + This policy reveal P2SB PCIe device at end of EXE. <b>0: Disable (hidden)</b>; 1: Enable (visible). + NOTE: Do not set this policy "P2SbReveal" unless necessary. + **/ + UINT32 P2SbReveal : 1; + UINT32 RsvdBits : 29; +} PCH_P2SB_CONFIG; + +// +// --------------------- DCI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to Direct Connection Interface (DCI). +**/ +typedef struct { + /** + <b>(Test)</b> DCI enable (HDCIEN bit) + when Enabled, allow DCI to be enabled. When Disabled, the host control is not enabling DCI feature. + BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy. + The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature. + <b>0:Disabled</b>; 1:Enabled + **/ + UINT32 DciEn : 1; + /** + <b>(Test)</b> When set to Auto detect mode, it detects DCI being connected during BIOS post time and enable DCI. + Else it disable DCI. This policy only apply when DciEn is disabled. + NOTE: this policy should not be visible to end customer. + 0: Disable AUTO mode, <b>1: Enable AUTO mode</b> + **/ + UINT32 DciAutoDetect : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_DCI_CONFIG; + +// +// --------------------- LPC Configuration ------------------------------ +// +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00. + 0: Disable, <b>1: Enable</b> + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_LPC_CONFIG; + +// +// --------------------- SPI Configuration ------------------------------ +// +/** + This structure contains the policies which are related to SPI. +**/ +typedef struct { + /** + Force to show SPI controller. + <b>0: FALSE</b>, 1: TRUE + NOTE: For Windows OS, it MUST BE false. It's optional for other OSs. + **/ + UINT32 ShowSpiController : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_SPI_CONFIG; + +// +// --------------------------------------------------------------------- +// + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an update in the revision number +**/ +#define PCH_POLICY_REVISION 15 + +/** + The PCH Policy allows the platform code to publish a set of + configuration information that the PCH drivers will use to configure the PCH hardware. + The Revision field is used to accommodate backward compatible changes to the PPI/protocol. + The Revision should be initialized to PCH_POLICY_REVISION_X + by the PPI producer. + The BusNumber field is used for platform to assign Bus number with multiple instances. + + All reserved/unused fields must be initialized with zeros. +**/ +struct _PCH_POLICY { + /** + This member specifies the revision of the PCH policy PPI. This field is used to + indicate backwards compatible changes to the protocol. Platform code that produces + this PPI must fill with the correct revision value for the PCH reference code + to correctly interpret the content of the PPI fields. + + Revision 1: Original version + - Add DciAutoDetect policy in PCH_GENERAL_CONFIG. + - Add SbiUnlock policy in PCH_P2SB_CONFIG. + - Add the following policies in PCH_ISH_CONFIG: + - SpiGpioAssign + - Uart0GpioAssign + - Uart1GpioAssign + - I2c0GpioAssign + - I2c1GpioAssign + - I2c2GpioAssign + - Gp0GpioAssign + - Gp1GpioAssign + - Gp2GpioAssign + - Gp3GpioAssign + - Gp4GpioAssign + - Gp5GpioAssign + - Gp6GpioAssign + - Gp7GpioAssign + - Add ClkReqSupported and ClkReqDetect in PCH_PCIE_ROOT_PORT_CONFIG. + - Add the following in PCH_SKYCAM_CIO2_CONFIG + - SkyCamPortATermOvrEnable + - SkyCamPortBTermOvrEnable + - SkyCamPortCTermOvrEnable + - SkyCamPortDTermOvrEnable + - Add UartHwFlowCtrl in PCH_SERIAL_IO + - Move DciEn and DciAutoDetect to PCH_DCI_CONFIG + + + + Revision 2: Updated version + - Add Enable policy in PCH_SSIC_CONFIG + - Deprecated Target Debugger option of EnableMode in PCH_TRACE_HUB_CONFIG + - Deprecated the following policies in PCH_TRACE_HUB_CONFIG + - MemReg0WrapEnable + - MemReg1WrapEnable + - TraceDestination + - PtiMode + - PtiSpeed + - PtiTraining + - Deprecated the Usb3PinsTermination and ManualModeUsb30PerPinEnable in PCH_XHCI_CONFIG + - Redefine the Enable policy in PCH_HPET_CONFIG + - Add EnhancePort8xhDecoding in PCH_LPC_CONFIG + - Add PsfUnlock in PCH_P2SB_CONFIG + - Add AllowNoLtrIccPllShutdown in PCH_PCIE_CONFIG + - Add PdtUnlock in PCH_ISH_CONFIG + - Remove PwrmBase from policy since the base address is predefined. + - Add DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2s in PCH_HDAUDIO_CONFIG + - Add Gen3EqPh3Method abd EqPh3LaneParam in PCH_PCIE_ROOT_PORT_CONFIG/PCH_PCIE_CONFIG + - Remove SlotImplemented and PmeInterrupt from PCH_PCIE_ROOT_PORT_CONFIG + + + + Revision 3: Updated version + - Add PwrBtnOverridePeriod policy in PCH_PM_CONFIG + - Add PCH_USB20_AFE in PCH_USB20_PORT_CONFIG + - Add ClkReqSupported in PCH_LAN_CONFIG + + + + Revision 4: Updated version + - Add DeviceResetPad and DeviceResetPadActiveHigh in PCH_PCIE_ROOT_PORT_CONFIG + + + Revision 5: Updated version + - Deprecated ScsSdioMode in PCH_SCS_CONFIG + - Deprecated PchScsSdioMode (PCH_SCS_DEV_SD_MODE enum) for ScsSdSwitch in PCH_SCS_CONFIG + - Add HSIO RX and TX EQ policy for PCIe and SATA + - Add ComplianceTestMode in PCH_PCIE_CONFIG + + Revision 6: Updated version + - Add DisableEnergyReport in PCH_PM_CONFIG + + + Revision 7: Updated version + - Deprecated Enabled as Acpi device option of DeviceEnable in PCH_SKYCAM_CIO2_CONFIG + - Add PCH_SKYCAM_CIO2_FLS_CONFIG with the following elements: + - PortACtleEnable + - PortBCtleEnable + - PortCCtleEnable + - PortDCtleEnable + - PortACtleCapValue + - PortBCtleCapValue + - PortCCtleCapValue + - PortDCtleCapValue + - PortACtleResValue + - PortBCtleResValue + - PortCCtleResValue + - PortDCtleResValue + - PortATrimEnable + - PortBTrimEnable + - PortCTrimEnable + - PortDTrimEnable + - PortADataTrimValue + - PortBDataTrimValue + - PortCDataTrimValue + - PortDDataTrimValue + - PortAClkTrimValue + - PortBClkTrimValue + - PortCClkTrimValue + - PortDClkTrimValue + - Rename and reorder the policies for better understanding. + - HsioTxOutDownscaleAmpAd3GbsEnable to HsioTxGen1DownscaleAmpEnable + - HsioTxOutDownscaleAmpAd6GbsEnable to HsioTxGen2DownscaleAmpEnable + - HsioTxOutDownscaleAmpAd3Gbs to HsioTxGen2DownscaleAmp + - HsioTxOutDownscaleAmpAd6Gbs to HsioTxGen2DownscaleAmp + - Update SerialIo DevMode default to PCI mode. + + + Revision 8: Updated version + - Deprecate GP27WakeFromDeepSx and add LanWakeFromDeepSx to align EDS naming + - Add ShowSpiController policy and PCH_SPI_CONFIG. + - Add DspUaaCompliance in PCH_HDAUDIO_CONFIG + - Add PchPcieEqHardware support in PCH_PCIE_EQ_METHOD + + + Revision 9: Updated version + - Add DebugUartNumber and EnableDebugUartAfterPost in PCH_SERIAL_IO_CONFIG + - Add DetectTimeoutMs in PCH_PCIE_CONFIG + - Add PciePllSsc in PCH_PM_CONFIG + + + Revision 10: Updated version + - Add HsioTxDeEmph in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmp in PCH_USB30_PORT_CONFIG + - Add HsioTxDeEmphEnable in PCH_USB30_PORT_CONFIG + - Add HsioTxDownscaleAmpEnable in PCH_USB30_PORT_CONFIG + + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAdEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioRxEqBoostMagAd + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmpEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen1DownscaleAmp + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmpEnable + - Deprecated PCH_SATA_PORT_CONFIG.HsioTxGen2DownscaleAmp + + - Add PCH_HSIO_SATA_CONFIG HsioSataConfig in PCH_POLICY + - Add HsioRxGen1EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen1EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMagEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioRxGen2EqBoostMag in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen1DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen2DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmphEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DeEmph in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_SATA_PORT_LANE + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_SATA_PORT_LANE + + - Add PCH_HSIO_PCIE_CONFIG HsioPcieConfig in PCH_POLICY + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtleEnable + - Deprecated PCH_PCIE_ROOT_PORT_CONFIG.HsioRxSetCtle + - Add HsioRxSetCtleEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioRxSetCtle in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen3DownscaleAmpEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen3DownscaleAmp in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmphEnable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen1DeEmph in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph3p5Enable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph3p5 in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph6p0Enable in PCH_HSIO_PCIE_LANE_CONFIG + - Add HsioTxGen2DeEmph6p0 in PCH_HSIO_PCIE_LANE_CONFIG + + - Add DisableDsxAcPresentPulldown in PCH_PM_CONFIG + - Add DynamicPowerGating in PCH_SMBUS_CONFIG + - Add ZpOdd in PCH_SATA_PORT_CONFIG + - Add Uptp and Dptp in PCH_PCIE_ROOT_PORT_CONFIG + - Add PCH_PCIE_CONFIG2 PcieConfig2 in PCH_POLICY + + + Revision 11: Updated version + - Add DisableComplianceMode in PCH_USB_CONFIG + + + Revision 12: Updated version + - Add PmcReadDisable in PCH_PM_CONFIG + - Add CapsuleResetType in PCH_PM_CONFIG + - Add RpFunctionSwap in PCH_PCIE_CONFIG + + + Revision 13: Update version + - Add DisableNativePowerButton in PCH_PM_CONFIG + - Add MaxPayload in PCH_PCIE_ROOT_PORT_CONFIG + - Add IDispCodecDisconnect in PCH_HDAUDIO_CONFIG +#ifdef PCH_SERVER_BIOS_FLAG + Revision 13a: Server updates + - Add HsioIcfgAdjLimitLoEnable + - Add HsioIcfgAdjLimitLo + - Add HsioSampOffstEvenErrSpEnable + - Add HsioSampOffstEvenErrSp + - Add HsioRemainingSamplerOffEnable + - Add HsioRemainingSamplerOff + - Add HsioVgaGainCal + in PCH_HSIO_PCIE_LANE_CONFIG +#endif //PCH_SERVER_BIOS_FLAG + + **/ + UINT8 Revision; + + UINT8 Port80Route; ///< Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI. + UINT16 AcpiBase; ///< Power management I/O base address. Default is <b>0x1800</b>. + UINT32 Rsvd; + /// + /// PCH General configuration + /// + PCH_GENERAL_CONFIG PchConfig; + /// + /// This member describes PCI Express controller's related configuration. + /// + PCH_PCIE_CONFIG PcieConfig; + /** + SATA controller's related configuration. + SATA configuration that decides which Mode the SATA controller should operate in + and whether PCH SATA TEST mode is enabled. + **/ + PCH_SATA_CONFIG SataConfig; + /// + /// This member describes USB controller's related configuration. + /// + PCH_USB_CONFIG UsbConfig; + /** + This member describes IOAPIC related configuration. + Determines IO APIC ID and IO APIC Range. + **/ + PCH_IOAPIC_CONFIG IoApicConfig; + /// + /// This member describes HPET related configuration. + /// + PCH_HPET_CONFIG HpetConfig; + /// + /// This member describes the Intel HD Audio (Azalia) related configuration. + /// + PCH_HDAUDIO_CONFIG HdAudioConfig; + /// + /// LAN controller settings + /// + PCH_LAN_CONFIG LanConfig; + /// + /// This member describes SMBus related configuration. + /// + PCH_SMBUS_CONFIG SmbusConfig; + /// + /// This member describes LockDown related configuration. + /// + PCH_LOCK_DOWN_CONFIG LockDownConfig; + /// + /// This member describes Thermal related configuration. + /// + PCH_THERMAL_CONFIG ThermalConfig; + /// + /// This member describes miscellaneous platform power management configurations. + /// + PCH_PM_CONFIG PmConfig; + /// + /// This member describes DMI related configuration. + /// + PCH_DMI_CONFIG DmiConfig; + /// + /// This member describes the expected configuration of the PCH for Serial IRQ. + /// + PCH_LPC_SIRQ_CONFIG SerialIrqConfig; + /// + /// This member describes interrupt settings for PCH. + /// + PCH_INTERRUPT_CONFIG PchInterruptConfig; + /// + /// This member describes TraceHub settings for PCH. + /// + PCH_TRACE_HUB_CONFIG PchTraceHubConfig; + /// + /// This member describes the enabling of emulation for port 61h + /// + PCH_PORT61H_SMM_CONFIG Port61hSmmConfig; + /// + /// This member describes the Flash Protection related configuration + /// + PCH_FLASH_PROTECTION_CONFIG FlashProtectConfig; + /// + /// This member describes the sSata related configuration + /// + PCH_SATA_CONFIG sSataConfig; + /// + /// This member contains WDT enable configuration. + /// + PCH_WDT_CONFIG WdtConfig; + /// + /// This member contains P2SB configuration. + /// + PCH_P2SB_CONFIG P2sbConfig; + /// + /// This member contains DCI configuration. + /// + PCH_DCI_CONFIG DciConfig; + + /// + /// Platform specific common policies that used by several silicon components. + /// + /// + /// Temp Bus Number range available to be assigned to each root port and its downstream + /// devices for initialization of these devices before PCI Bus enumeration. + /// + UINT8 TempPciBusMin; + UINT8 TempPciBusMax; + /// + /// Temporary Memory Base Address for PCI devices to be used to initialize MMIO registers. + /// Minimum size is 2MB bytes + /// + UINT32 TempMemBaseAddr; + /// + /// This member contains LPC configuration. + /// + PCH_LPC_CONFIG LpcConfig; + /// + /// This member describes SkyCam CIO2 FLS registers configuration. + /// + PCH_SKYCAM_CIO2_FLS_CONFIG PchCio2FlsConfig; + /// + /// This member contains SPI configuration. + /// + PCH_SPI_CONFIG SpiConfig; + /// + /// This member describes HSIO settings for SATA controller + /// + PCH_HSIO_SATA_CONFIG HsioSataConfig; + /// + /// This member describes HSIO settings for second SATA controller + /// + PCH_HSIO_SATA_CONFIG HsiosSataConfig; + /// + /// This member describes HSIO settings for PCIe controller + /// + PCH_HSIO_PCIE_CONFIG HsioPcieConfig; + /// + /// This member describes HSIO settings for FIA WM20 PCIe + /// + PCH_HSIO_PCIE_WM20_CONFIG HsioPcieConfigFIAWM20; + /// + /// This is the extension of PCIE CONFIG + /// + PCH_PCIE_CONFIG2 PcieConfig2; + + PCH_ADR_CONFIG AdrConfig; + +}; + +#pragma pack (pop) + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/PchReservedResources.h b/Silicon/Intel/LewisburgPkg/Include/PchReservedResources.h new file mode 100644 index 0000000000..d60125b768 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/PchReservedResources.h @@ -0,0 +1,87 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** +#ifdef SERVER_BIOS_FLAG + SKX map: +#endif //SERVER_BIOS_FLAG + PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-------------------------------------------------------------------------+ + | Size | Start | End | Usage | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused | + | 256 KB | 0xFE0C0000 | 0xFE0FFFFF | TraceHub FW BAR | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub SW BAR | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address | + +-------------------------------------------------------------------------+ + +#ifdef SERVER_BIOS_FLAG + HSX map: + PCH preserved MMIO range, from 0xFC000000 to 0xFE7FFFFF + + Detailed recommended static allocation + +-------------------------------------------------------------------------+ + | Size | Start | End | Usage | + | 256 KB | 0xFC0C0000 | 0xFC0FFFFF | TraceHub FW BAR | + | 1 MB | 0xFC100000 | 0xFC1FFFFF | TraceHub MTB BAR | + | 2 MB | 0xFC200000 | 0xFC3FFFFF | TraceHub SW BAR | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode | + | 24 KB | 0xFE036000 | 0xFE03BFFF | Unused | + | 4 KB | 0xFE03C000 | 0xFE03CFFF | Thermal Device in ACPI mode | + | 524 KB | 0xFE03D000 | 0xFE0BFFFF | Unused | + | 64 KB | 0xFE400000 | 0xFE40FFFF | CIO2 MMIO BAR in ACPI mode | + | 2 MB - 64KB | 0xFE410000 | 0xFE5FFFFF | Unused | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address | + +-------------------------------------------------------------------------+ +#endif //SERVER_BIOS_FLAG +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFD000000 ///< Pch preserved MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x01800000 ///< 24MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_THERMAL_BASE_ADDRESS 0xFE03C000 ///< Thermal Device in ACPI mode +#define PCH_THERMAL_MMIO_SIZE 0x00001000 ///< 4KB + +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00040000 ///< 256KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB MMIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFE200000 ///< TraceHub SW MMIO base address +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_CIO2_BASE_ADDRESS 0xFE400000 ///< CIO2 MMIO BAR in ACPI mode +#define PCH_CIO2_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp address for misc usage +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/LewisburgPkg/Include/PcieRegs.h b/Silicon/Intel/LewisburgPkg/Include/PcieRegs.h new file mode 100644 index 0000000000..e4cf4020c8 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/PcieRegs.h @@ -0,0 +1,285 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCIE_REGS_H_ +#define _PCIE_REGS_H_ + +#include <IndustryStandard/Pci30.h> + +// +// PCI type 0 Header +// +#define R_PCI_PI_OFFSET 0x09 +#define R_PCI_SCC_OFFSET 0x0A +#define R_PCI_BCC_OFFSET 0x0B + +// +// PCI type 1 Header +// +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate Bus Number +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary Bus Number +#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary Bus Number +#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN | B_PCI_BRIDGE_BNUM_SCBN) + +#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and Limit Register + +#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base and Limit Register +#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory Limit +#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory Base + +#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable Memory Base and Limit Register +#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetchable Memory Limit +#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit Indicator +#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetchable Memory Base +#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit Indicator + +#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable Memory Base Upper 32-Bit Register +#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF + +#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable Memory Limit Upper 32-Bit Register +#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF + +// +// PCIE capabilities register +// +#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID +#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capability Capability ID Pointer + +// +// PCI Express Capability List Register (CAPID:10h) +// +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Capabilities Register (Offset 02h) +#define S_PCIE_XCAP 2 +#define B_PCIE_XCAP_SI BIT8 ///< Slot Implemented +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type +#define N_PCIE_XCAP_DT 4 + +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities Register (Offset 04h) +#define S_PCIE_DCAP 4 +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency +#define N_PCIE_DCAP_E1AL 9 +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency +#define N_PCIE_DCAP_E0AL 6 +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Supported + +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control Register (Offset 08h) +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size +#define N_PCIE_DCTL_MPS 5 +#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable +#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable +#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Error Reporting Enable +#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Error Reporting Enable + +#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status Register (Offset 0Ah) +#define B_PCIE_DSTS_TDP BIT5 ///< Transactions Pending +#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected +#define B_PCIE_DSTS_URD BIT3 ///< Unsupported Request Detected +#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected +#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Error Detected +#define B_PCIE_DSTS_CED BIT0 ///< Correctable Error Detected + +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities Register (Offset 0Ch) +#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optionality Compliance +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power Management +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency +#define N_PCIE_LCAP_EL1 15 +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s Exit Latency +#define N_PCIE_LCAP_EL0 12 +#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Management (ASPM) Support +#define B_PCIE_LCAP_APMS_L0S BIT10 +#define B_PCIE_LCAP_APMS_L1 BIT11 +#define N_PCIE_LCAP_APMS 10 +#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum Link Width +#define N_PCIE_LCAP_MLW 4 +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed +#define V_PCIE_LCAP_MLS_GEN3 3 + +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control Register (Offset 10h) +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power Management +#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link +#define B_PCIE_LCTL_LD BIT4 ///< Link Disable +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State Power Management (ASPM) Control +#define V_PCIE_LCTL_ASPM_L0S 1 +#define V_PCIE_LCTL_ASPM_L1 2 +#define V_PCIE_LCTL_ASPM_L0S_L1 3 + +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register (Offset 12h) +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link Active +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Configuration +#define B_PCIE_LSTS_LT BIT11 ///< Link Training +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link Width +#define N_PCIE_LSTS_NLW 4 +#define V_PCIE_LSTS_NLW_1 0x0010 +#define V_PCIE_LSTS_NLW_2 0x0020 +#define V_PCIE_LSTS_NLW_4 0x0040 +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed +#define V_PCIE_LSTS_CLS_GEN1 1 +#define V_PCIE_LSTS_CLS_GEN2 2 +#define V_PCIE_LSTS_CLS_GEN3 3 + +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities Register (Offset 14h) +#define S_PCIE_SLCAP 4 +#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical Slot Number +#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Power Limit Scale +#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Power Limit Value +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable +#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surprise + +#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control Register (Offset 18h) +#define S_PCIE_SLCTL 2 +#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Interrupt Enable +#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable + +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register (Offset 1Ah) +#define S_PCIE_SLSTS 2 +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State +#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed + +#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control Register (Offset 1Ch) +#define S_PCIE_RCTL 2 +#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable +#define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable +#define B_PCIE_RCTL_SNE BIT1 ///< System Error on Non-Fatal Error Enable +#define B_PCIE_RCTL_SCE BIT0 ///< System Error on Correctable Error Enable + +#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Register (Offset 20h) +#define S_PCIE_RSTS 4 + +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities 2 Register (Offset 24h) +#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBFF Supported +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported + +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2 Register (Offset 28h) +#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBFF Enable +#define N_PCIE_DCTL2_OBFFEN 13 +#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled +#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAKE# signaling +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism Enable +#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable +#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeout Value +#define V_PCIE_DCTL2_CTV_DEFAULT 0x0 +#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5 +#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6 +#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9 +#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA + +#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2 Register (Offset 30h) +#define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-emphasis (0 = -6dB, 1 = -3.5dB) +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed +#define V_PCIE_LCTL2_TLS_GEN1 1 +#define V_PCIE_LCTL2_TLS_GEN2 2 +#define V_PCIE_LCTL2_TLS_GEN3 3 + +#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 Register (Offset 32h) +#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalization Request +#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3 Successful +#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2 Successful +#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1 Successful +#define B_PCIE_LSTS2_EC BIT1 ///< Equalization Complete +#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emphasis Level + +// +// PCI Power Management Capability (CAPID:01h) +// +#define R_PCIE_PMC_OFFSET 0x02 ///< Power Management Capabilities Register +#define S_PCIE_PMC 2 +#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME Support +#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock + +#define R_PCIE_PMCS_OFFST 0x04 ///< Power Management Status/Control Register +#define S_PCIE_PMCS 4 +#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clock Control Enable +#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support +#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status +#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable +#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset +#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power State +#define V_PCIE_PMCS_PS_D0 0 +#define V_PCIE_PMCS_PS_D3H 3 + +// +// PCIE Extension Capability Register +// +#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Capability Offset +#define N_PCIE_EXCAP_NCO 20 +#define V_PCIE_EXCAP_NCO_LISTEND 0 +#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capability Version +#define N_PCIE_EXCAP_CV 16 +#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capability ID + +// +// Advanced Error Reporting Capability (CAPID:0001h) +// +#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID +#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable Error Mask Register +#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Timeout Mask +#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Completion + +// +// ACS Extended Capability (CAPID:000Dh) +// +#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID +#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability Register +//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control Register (NOTE: register size in PCIE spce is not match the PCH register size) + +// +// Secondary PCI Express Extended Capability Header (CAPID:0019h) +// +#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3 Register +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equalization +#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Status +#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan 1 Equalization Control Register (Offset 0Ch) +#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_UPL1TP 24 +#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstream Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_DPL1TP 16 +#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream Port Transmitter Preset +#define N_PCIE_EX_L01EC_UPL0TP 8 +#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstream Port Transmitter Preset +#define N_PCIE_EX_L01EC_DPL0TP 0 + +#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lane 3 Equalization Control Register (Offset 10h) +#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL3TP 24 +#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstream Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL3TP 16 +#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL2TP 8 +#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstream Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL2TP 0 + + +// +// L1 Sub-States Extended Capability Register (CAPID:001Eh) +// +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States Capabilities +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States Control 1 +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States Control 2 +#define N_PCIE_EX_L1SCTL2_POWT 3 + +// +// Base Address Offset +// +#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address Register 0 +#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address Register 1 +#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address Register 2 +#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address Register 3 +#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address Register 4 +#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address Register 5 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h new file mode 100644 index 0000000000..36451c4962 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h @@ -0,0 +1,130 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef PCH_PCIE_DEVICE_TABLE_H_ +#define PCH_PCIE_DEVICE_TABLE_H_ + + +// +// PCIe device table PPI GUID. +// +extern EFI_GUID gPchPcieDeviceTablePpiGuid; + +typedef enum { + PchPcieOverrideDisabled = 0, + PchPcieL1L2Override = 0x01, + PchPcieL1SubstatesOverride = 0x02, + PchPcieL1L2AndL1SubstatesOverride = 0x03, + PchPcieLtrOverride = 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM settings. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideConfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be override. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + UINT32 Reserved; +} PCH_PCIE_DEVICE_OVERRIDE; + +#endif // PCH_PCIE_DEVICE_TABLE_H_ + diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h new file mode 100644 index 0000000000..e994763e5e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_POLICY_PPI_H_ +#define _PCH_POLICY_PPI_H_ + +#include <PchAccess.h> +#include <PchPolicyCommon.h> + +extern EFI_GUID gPchPlatformPolicyPpiGuid; + + +typedef struct _PCH_POLICY PCH_POLICY_PPI; + +#endif // PCH_POLICY_PPI_H_ diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h new file mode 100644 index 0000000000..f7d3481f77 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h @@ -0,0 +1,99 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_RESET_PPI_H_ +#define _PCH_RESET_PPI_H_ + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchResetPpiGuid; +extern EFI_GUID gPchResetCallbackPpiGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PPI PCH_RESET_PPI; +typedef struct _PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PPI; + +// +// Related Definitions +// +// +// PCH Reset Types +// +typedef enum { + ColdReset, + WarmReset, + ShutdownReset, + PowerCycleReset, + GlobalReset, + GlobalResetWithEc, + PchResetTypeMax +} PCH_RESET_TYPE; + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PPI instance. + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_PPI_API) ( + IN PCH_RESET_PPI *This, + IN PCH_RESET_TYPE PchResetType + ); + +/** + Execute call back function for Pch Reset. + + @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset. + + @retval EFI_SUCCESS The callback function has been done successfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. Or, none of + callback ppi is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN PCH_RESET_TYPE PchResetType + ); + +/** + Interface structure to execute Pch Reset from the host controller. +**/ +struct _PCH_RESET_PPI { + PCH_RESET_PPI_API Reset; +}; + +/** + This ppi is used to execute PCH Reset from the host controller. + The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface + for DXE and PEI environments, respectively. If other drivers need to run their + callback function right before issuing the reset, they can install PCH Reset + Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that. +**/ +struct _PCH_RESET_CALLBACK_PPI { + PCH_RESET_CALLBACK ResetCallback; +}; + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h new file mode 100644 index 0000000000..44d043cf0e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h @@ -0,0 +1,31 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include <Protocol/Spi.h> + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPeiSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiService pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef EFI_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Protocol/PchReset.h b/Silicon/Intel/LewisburgPkg/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..d967de3b68 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Protocol/PchReset.h @@ -0,0 +1,118 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_RESET_H_ +#define _PCH_RESET_H_ + +#include <Ppi/PchReset.h> + +#define EFI_CAPSULE_VARIABLE_NAME L"CapsuleUpdateData" +extern EFI_GUID gEfiCapsuleVendorGuid; + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchResetProtocolGuid; +extern EFI_GUID gPchResetCallbackProtocolGuid; +extern EFI_GUID gPchPowerCycleResetGuid; +extern EFI_GUID gPchGlobalResetGuid; +extern EFI_GUID gPchGlobalResetWithEcGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL; + +typedef PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PROTOCOL; + +// +// Related Definitions +// +// +// PCH Platform Specific ResetData +// +#define PCH_POWER_CYCLE_RESET_GUID \ + { \ + 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 } \ + } + +#define PCH_GLOBAL_RESET_GUID \ + { \ + 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 } \ + } + +#define PCH_GLOBAL_RESET_WITH_EC_GUID \ + { \ + 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 } \ + } + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH sizeof (PCH_PLATFORM_SPECIFIC_RESET_STRING) + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + + +// +// Member functions +// +/** + Execute Pch Reset from the host controller. + + @param[in] This Pointer to the PCH_RESET_PROTOCOL instance. + @param[in] ResetType UEFI defined reset type. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET) ( + IN PCH_RESET_PROTOCOL *This, + IN PCH_RESET_TYPE ResetType, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ); + +/** + Retrieve PCH platform specific ResetData + + @param[in] Guid PCH platform specific reset GUID. + @param[out] DataSize The size of ResetData in bytes. + + @retval ResetData A platform specific reset that the exact type of + the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + @retval NULL If Guid is not defined in PCH platform specific reset. +**/ +typedef +VOID * +(EFIAPI *PCH_RESET_GET_RESET_DATA) ( + IN EFI_GUID *Guid, + OUT UINTN *DataSize + ); + +/** + Interface structure to execute Pch Reset from the host controller. +**/ +struct _PCH_RESET_PROTOCOL { + PCH_RESET Reset; + PCH_RESET_GET_RESET_DATA GetResetData; +}; + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Protocol/Spi.h b/Silicon/Intel/LewisburgPkg/Include/Protocol/Spi.h new file mode 100644 index 0000000000..eafedcab93 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Protocol/Spi.h @@ -0,0 +1,312 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiSpiProtocolGuid; +extern EFI_GUID gEfiSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL EFI_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionSecondaryBios, + FlashRegionuCodePatch, + FlashRegionEC, + FlashRegionDeviceExpansion2, + FlashRegionIE, + FlashRegion10Gbe_A, + FlashRegion10Gbe_B, + FlashRegion13, + FlashRegion14, + FlashRegion15, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +#define SPI_DESCR_ADDR_FLVALSIG 0x10 +#define SPI_DESCR_ADDR_FLMAP0 0x14 +#define SPI_DESCR_ADDR_FLMAP1 0x18 + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received. + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data read. + @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN EFI_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value. + If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length + It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN EFI_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations through the + Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h new file mode 100644 index 0000000000..a3dd6ed148 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDci.h @@ -0,0 +1,30 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// +#define R_PCH_PCR_DCI_ECTRL 0x04 ///< DCI Control Register +#define B_PCH_PCR_DCI_ECTRL_HDCILOCK BIT0 ///< Host DCI lock +#define B_PCH_PCR_DCI_ECTRL_HDCIEN BIT4 ///< Host DCI enable +#define R_PCH_PCR_DCI_ECKPWRCTL 0x08 ///< DCI Power Control +#define R_PCH_PCR_DCI_PCE 0x30 ///< DCI Power Control Enable Register +#define B_PCH_PCR_DCI_PCE_HAE BIT5 ///< Hardware Autonomous Enable +#define B_PCH_PCR_DCI_PCE_D3HE BIT2 ///< D3-Hot Enable +#define B_PCH_PCR_DCI_PCE_I3E BIT1 ///< I3 Enable +#define B_PCH_PCR_DCI_PCE_PMCRE BIT0 ///< PMC Request Enable + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDmi.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDmi.h new file mode 100644 index 0000000000..b7426e25fd --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsDmi.h @@ -0,0 +1,194 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_DMI_H_ +#define _PCH_REGS_DMI_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// VC Configuration (Common) +// +#define R_PCH_PCR_DMI_V0CTL 0x2014 ///< Virtual channel 0 resource control +#define B_PCH_PCR_DMI_V0CTL_EN BIT31 +#define B_PCH_PCR_DMI_V0CTL_ID (7 << 24) ///< Bit[26:24] +#define N_PCH_PCR_DMI_V0CTL_ID 24 +#define V_PCH_PCR_DMI_V0CTL_ETVM_MASK 0xFC00 +#define V_PCH_PCR_DMI_V0CTL_TVM_MASK 0x7E +#define R_PCH_PCR_DMI_V0STS 0x201A ///< Virtual channel 0 status +#define B_PCH_PCR_DMI_V0STS_NP BIT1 +#define R_PCH_PCR_DMI_V1CTL 0x2020 ///< Virtual channel 1 resource control +#define B_PCH_PCR_DMI_V1CTL_EN BIT31 +#define B_PCH_PCR_DMI_V1CTL_ID (0x0F << 24) ///< Bit[27:24] +#define N_PCH_PCR_DMI_V1CTL_ID 24 +#define V_PCH_PCR_DMI_V1CTL_ETVM_MASK 0xFC00 +#define V_PCH_PCR_DMI_V1CTL_TVM_MASK 0xFE +#define R_PCH_PCR_DMI_V1STS 0x2026 ///< Virtual channel 1 status +#define B_PCH_PCR_DMI_V1STS_NP BIT1 +#define R_PCH_PCR_DMI_VMCTL 0x2040 ///< ME Virtual Channel (VCm) resource control +#define R_PCH_PCR_DMI_VMSTS 0x2046 ///< ME Virtual Channel Resource Status +#define R_PCH_PCR_DMI_UEM 0x2088 ///< Uncorrectable Error Mask +#define R_PCH_PCR_DMI_REC 0x20AC ///< Root Error Command + +// +// Internal Link Configuration (DMI Only) +// +#define R_PCH_PCR_DMI_LCAP 0x21A4 ///< Link Capabilities +#define B_PCH_PCR_DMI_LCAP_EL1 (BIT17 | BIT16 | BIT15) +#define B_PCH_PCR_DMI_LCAP_EL0 (BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_DMI_LCAP_APMS (BIT11 | BIT10) ///< L0 is supported on DMI +#define B_PCH_PCR_DMI_LCAP_MLW 0x000003F0 +#define B_PCH_PCR_DMI_LCAP_MLS 0x0000000F +#define R_PCH_PCR_DMI_LCTL 0x21A8 ///< Link Control +#define B_PCH_PCR_DMI_LCTL_ES BIT7 +#define B_PCH_PCR_DMI_LCTL_ASPM (BIT1 | BIT0) ///< Link ASPM +#define R_PCH_PCR_DMI_LSTS 0x21AA ///< Link Status +#define R_PCH_PCR_DMI_LCTL2 0x21B0 ///< Link Control 2 +#define R_PCH_PCR_DMI_LSTS2 0x21B2 ///< Link Status 2 +#define R_PCH_PCR_DMI_L01EC 0x21BC ///< Lane 0 and Lane 1 Equalization Control +#define R_PCH_PCR_DMI_L23EC 0x21C0 ///< Lane 2 and Lane 3 Equalization Control +#define B_PCH_PCR_DMI_UPL13RPH 0x0F000000 ///< Upstream Port Lane 1/3 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL13RPH 24 ///< Upstream Port Lane 1/3 Transmitter Preset Hint value offset +#define B_PCH_PCR_DMI_UPL02RPH 0x000000F0 ///< Upstream Port Lane 0/2 Transmitter Preset Hint mask +#define N_PCH_PCR_DMI_UPL02RPH 8 ///< Upstream Port Lane 0/2 Transmitter Preset Hint value offset +#define V_PCH_PCR_DMI_UPL0RPH 7 ///< Upstream Port Lane 0 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL1RPH 7 ///< Upstream Port Lane 1 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL2RPH 7 ///< Upstream Port Lane 2 Transmitter Preset Hint value +#define V_PCH_PCR_DMI_UPL3RPH 7 ///< Upstream Port Lane 3 Transmitter Preset Hint value + + +// +// North Port Error Injection Configuration (DMI Only) +// +#define R_PCH_PCR_DMI_DMIEN 0x2230 ///< DMI Error Injection Enable + +// +// DMI Control +// +#define R_PCH_PCR_DMI_DMIC 0x2234 ///< DMI Control +#define B_PCH_PCR_DMI_DMIC_SRL BIT31 ///< Secured register lock +#define B_PCH_PCR_DMI_DMIC_ORCE (BIT25 | BIT24) ///< Offset Re-Calibration Enable +#define N_PCH_PCR_DMI_DMIC_ORCE 24 +#define V_PCH_PCR_DMI_DMIC_ORCE_EN_GEN2_GEN3 1 ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only. +#define B_PCH_PCR_DMI_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable +#define R_PCH_PCR_DMI_DMIHWAWC 0x2238 ///< DMI HW Autonomus Width Control +#define R_PCH_PCR_DMI_IOSFSBCS 0x223E ///< IOSF Sideband Control and Status +#define B_PCH_PCR_DMI_IOSFSBCS_DMICGEN (BIT6 | BIT5 | BIT3 | BIT2) ///< DMI Clock Gate Enable + +#define R_PCH_PCR_DMI_2300 0x2300 +#define R_PCH_PCR_DMI_2304 0x2304 +#define R_PCH_PCR_DMI_2310 0x2310 +#define R_PCH_PCR_DMI_2314 0x2314 +#define R_PCH_PCR_DMI_2320 0x2320 +#define R_PCH_PCR_DMI_2324 0x2324 +#define R_PCH_PCR_DMI_232C 0x232C +#define R_PCH_PCR_DMI_2334 0x2334 +#define R_PCH_PCR_DMI_2338 0x2338 +#define R_PCH_PCR_DMI_2340 0x2340 +#define R_PCH_PCR_DMI_2344 0x2344 +#define R_PCH_PCR_DMI_2348 0x2348 +#define R_PCH_PCR_DMI_234C 0x234C + +// +// Port Configuration Extension(DMI Only) +// +#define R_PCH_PCR_DMI_EQCFG1 0x2450 +#define B_PCH_PCR_DMI_EQCFG1_RTLEPCEB BIT16 +#define R_PCH_PCR_DMI_LTCO1 0x2470 ///< Local Transmitter Coefficient Override 1 +#define R_PCH_PCR_DMI_LTCO2 0x2474 ///< Local Transmitter Coefficient Override 2 +#define B_PCH_PCR_DMI_L13TCOE BIT25 ///< Lane 1/3 Transmitter Coefficient Override Enable +#define B_PCH_PCR_DMI_L02TCOE BIT24 ///< Lane 0/2 Transmitter Coefficient Override Enable +#define B_PCH_PCR_DMI_L13TPOSTCO 0x00fc0000 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L13TPOSTCO 18 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L13TPRECO 0x0003f000 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L13TPRECO 12 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L02TPOSTCO 0x00000fc0 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L02TPOSTCO 6 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset +#define B_PCH_PCR_DMI_L02TPRECO 0x0000003f ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask +#define N_PCH_PCR_DMI_L02TPRECO 0 ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset +#define R_PCH_PCR_DMI_G3L0SCTL 0x2478 ///< GEN3 L0s Control + +// +// OP-DMI Specific Registers (OP-DMI Only) +// +#define R_PCH_PCR_OPDMI_LCTL 0x2600 ///< Link Control +#define R_PCH_PCR_OPDMI_STC 0x260C ///< Sideband Timing Control +#define R_PCH_PCR_OPDMI_LPMC 0x2614 ///< Link Power Management Control +#define R_PCH_PCR_OPDMI_LCFG 0x2618 ///< Link Configuration + +// +// DMI Source Decode PCRs (Common) +// +#define R_PCH_PCR_DMI_PCIEPAR1E 0x2700 ///< PCIE Port IOxAPIC Range 1 Enable +#define R_PCH_PCR_DMI_PCIEPAR2E 0x2704 ///< PCIE Port IOxAPIC Range 2 Enable +#define R_PCH_PCR_DMI_PCIEPAR3E 0x2708 ///< PCIE Port IOxAPIC Range 3 Enable +#define R_PCH_PCR_DMI_PCIEPAR4E 0x270C ///< PCIE Port IOxAPIC Range 4 Enable +#define R_PCH_PCR_DMI_PCIEPAR1DID 0x2710 ///< PCIE Port IOxAPIC Range 1 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR2DID 0x2714 ///< PCIE Port IOxAPIC Range 2 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR3DID 0x2718 ///< PCIE Port IOxAPIC Range 3 Destination ID +#define R_PCH_PCR_DMI_PCIEPAR4DID 0x271C ///< PCIE Port IOxAPIC Range 4 Destination ID +#define R_PCH_PCR_DMI_P2SBIOR 0x2720 ///< P2SB IO Range +#define R_PCH_PCR_DMI_TTTBARB 0x2724 ///< Thermal Throttling BIOS Assigned Thermal Base Address +#define R_PCH_PCR_DMI_TTTBARBH 0x2728 ///< Thermal Throttling BIOS Assigned Thermal Base High Address +#define R_PCH_PCR_DMI_LPCLGIR1 0x2730 ///< LPC Generic I/O Range 1 +#define R_PCH_PCR_DMI_LPCLGIR2 0x2734 ///< LPC Generic I/O Range 2 +#define R_PCH_PCR_DMI_LPCLGIR3 0x2738 ///< LPC Generic I/O Range 3 +#define R_PCH_PCR_DMI_LPCLGIR4 0x273C ///< LPC Generic I/O Range 4 +#define R_PCH_PCR_DMI_LPCGMR 0x2740 ///< LPC Generic Memory Range +#define R_PCH_PCR_DMI_LPCBDE 0x2744 ///< LPC BIOS Decode Enable +#define R_PCH_PCR_DMI_UCPR 0x2748 ///< uCode Patch Region +#define B_PCH_PCR_DMI_UCPR_UPRE BIT0 ///< uCode Patch Region Enable +#define R_PCH_PCR_DMI_GCS 0x274C ///< Generic Control and Status +#define B_PCH_PCR_DMI_RPRDID 0xFFFF0000 ///< RPR Destination ID +#define B_PCH_PCR_DMI_BBS BIT10 ///< Boot BIOS Strap +#define B_PCH_PCR_DMI_RPR BIT11 ///< Reserved Page Route +#define B_PCH_PCR_DMI_BILD BIT0 ///< BIOS Interface Lock-Down +#define R_PCH_PCR_DMI_IOT1 0x2750 ///< I/O Trap Register 1 +#define R_PCH_PCR_DMI_IOT2 0x2758 ///< I/O Trap Register 2 +#define R_PCH_PCR_DMI_IOT3 0x2760 ///< I/O Trap Register 3 +#define R_PCH_PCR_DMI_IOT4 0x2768 ///< I/O Trap Register 4 +#define R_PCH_PCR_DMI_LPCIOD 0x2770 ///< LPC I/O Decode Ranges +#define R_PCH_PCR_DMI_LPCIOE 0x2774 ///< LPC I/O Enables +#define R_PCH_PCR_DMI_TCOBASE 0x2778 ///< TCO Base Address +#define B_PCH_PCR_DMI_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask +#define R_PCH_PCR_DMI_GPMR1 0x277C ///< General Purpose Memory Range 1 +#define R_PCH_PCR_DMI_GPMR1DID 0x2780 ///< General Purpose Memory Range 1 Destination ID +#define R_PCH_PCR_DMI_GPMR2 0x2784 ///< General Purpose Memory Range 2 +#define R_PCH_PCR_DMI_GPMR2DID 0x2788 ///< General Purpose Memory Range 2 Destination ID +#define R_PCH_PCR_DMI_GPMR3 0x278C ///< General Purpose Memory Range 3 +#define R_PCH_PCR_DMI_GPMR3DID 0x2790 ///< General Purpose Memory Range 3 Destination ID +#define R_PCH_PCR_DMI_GPIOR1 0x2794 ///< General Purpose I/O Range 1 +#define R_PCH_PCR_DMI_GPIOR1DID 0x2798 ///< General Purpose I/O Range 1 Destination ID +#define R_PCH_PCR_DMI_GPIOR2 0x279C ///< General Purpose I/O Range 2 +#define R_PCH_PCR_DMI_GPIOR2DID 0x27A0 ///< General Purpose I/O Range 2 Destination ID +#define R_PCH_PCR_DMI_GPIOR3 0x27A4 ///< General Purpose I/O Range 3 +#define R_PCH_PCR_DMI_GPIOR3DID 0x27A8 ///< General Purpose I/O Range 3 Destination ID +#define R_PCH_PCR_DMI_PMBASEA 0x27AC ///< PM Base Address +#define R_PCH_PCR_DMI_PMBASEC 0x27B0 ///< PM Base Control +#define R_PCH_PCR_DMI_ACPIBA 0x27B4 ///< ACPI Base Address +#define R_PCH_PCR_DMI_ACPIBDID 0x27B8 ///< ACPI Base Destination ID + + +// +// Opi PHY registers +// +#define R_PCH_PCR_OPIPHY_0110 0x0110 +#define R_PCH_PCR_OPIPHY_0118 0x0118 +#define R_PCH_PCR_OPIPHY_011C 0x011C +#define R_PCH_PCR_OPIPHY_0354 0x0354 +#define R_PCH_PCR_OPIPHY_B104 0xB104 +#define R_PCH_PCR_OPIPHY_B10C 0xB10C + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsEva.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsEva.h new file mode 100644 index 0000000000..223d630d2c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsEva.h @@ -0,0 +1,116 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_EVA_H_ +#define _PCH_REGS_EVA_H_ + +#define PCI_DEVICE_NUMBER_EVA 17 +#define PCI_FUNCTION_NUMBER_EVA_MROM0 0 +#define PCI_FUNCTION_NUMBER_EVA_MROM1 1 +#define PCI_FUNCTION_NUMBER_EVA_SSATA 5 + +/// +/// Lewisburg SKUs +/// +#define LBG_SKU_G 1 +#define LBG_SKU_X 2 +#define LBG_SKU_A 3 + +#define PCI_DEVICE_NUMBER_PCH_SSATA 17 +#define PCI_FUNCTION_NUMBER_PCH_SSATA 5 + +#define PCH_SSATA_MAX_CONTROLLERS 1 +#define PCH_SSATA_MAX_PORTS 6 // But only 4 ports are enable, BIOS needs to disable Port 4 and 5 + +#define R_PCH_LBG_SSATA_DEVICE_ID 0x02 + +/// +/// LBG Production sSATA Controller DID definition +/// +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_AHCI 0xA1D2 // LBG Production Server Secondary AHCI Mode (Ports 0-4) +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID 0xA1D4 // LBG Production Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA1D6 // LBG Production Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_PROD_SSATA_DEVICE_ID_D_RAID1 0xA1DE // LBG Production Server RAID 1/RRT + +/// +/// LBG Production (PRQ) MSUint SMBUS DID definition +/// +#define V_PCH_LBG_PROD_MROM_DEVICE_ID_0 0xA1F0 // LBG MS Unit MROM 0 PRQ DID +#define V_PCH_LBG_PROD_MROM_DEVICE_ID_1 0xA1F1 // LBG MS Unit MROM 1 PRQ DID + + +/// +/// LBG SSX (Super SKUs and Pre Production) sSATA Controller DID definition +/// +#define V_PCH_LBG_SSATA_DEVICE_ID_D_AHCI 0xA252 // LBG SSX Server Secondary AHCI Mode (Ports 0-4) +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID 0xA254 // LBG SSX Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM 0xA256 // LBG SSX Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID1 0xA25E // LBG SSX Server RAID 1/RRT + +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2823 // Server RAID 0/1/5/10 - premium - Alternate ID for RST +#define V_PCH_LBG_SSATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2827 // Server RAID 0/1/5/10 - premium - Alternate ID for RSTe + +/// +/// LBG Super SKU (SSX) MSUint DID definition +/// +#define V_PCH_LBG_MROM_DEVICE_ID_0 0xA270 // LBG NS MS Unit MROM 0 Super SKU DID +#define V_PCH_LBG_MROM_DEVICE_ID_1 0xA271 // LBG NS MS Unit MROM 1 Super SKU DID + +#define R_PCH_LBG_MROM_DEVCLKGCTL 0xE4 + +#define R_PCH_LBG_MROM_PLKCTL 0xE8 + +#define ADR_TMR_HELD_OFF_SETUP_OPTION 2 +#define R_PCH_LBG_MROM_ADRTIMERCTRL 0x180 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MASK (BIT27|BIT26|BIT25|BIT24) +#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT 24 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1 0x0 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_8 0x1 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_24 0x2 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_40 0x3 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_56 0x4 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_64 0x5 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_72 0x6 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_80 0x7 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_88 0x8 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96 0x9 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_MAX (V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_96) +#define ADR_MULT_SETUP_DEFAULT_POR 99 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_DBG_DIS BIT28 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_DIS BIT29 +#define B_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MASK (BIT30|BIT31) +#define N_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR 30 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_25US 0x0 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_50US 0x1 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US 0x2 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US 0x3 +#define V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_MAX (V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_0US) +#define ADR_TMR_SETUP_DEFAULT_POR 4 + +/// +/// MS Unit Hide Control Register +/// +#define PCH_LBG_MSUINT_FUNCS 3 +#define R_PCH_LBG_MSUINT_MSDEVFUNCHIDE 0xD4 +#define B_PCH_LBG_MSUINT_MSDEVFUNCHIDE_RSVD (BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|\ + BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|\ + BIT16|BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|\ + BIT9|BIT8|BIT7|BIT6|BIT4|BIT3|BIT2) + +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_SSATA (BIT5) + +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM1 BIT1 +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_MROM0 BIT0 +#define B_PCH_EVA_MSUNIT_MSDEVFUNCHIDE_REGLOCK BIT31 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsFia.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsFia.h new file mode 100644 index 0000000000..6ca108be67 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsFia.h @@ -0,0 +1,87 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_FIA_H_ +#define _PCH_REGS_FIA_H_ + + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. +// + +// +// PID:FIA +// +#define PCH_MAX_FIA_DRCRM 3 +#define R_PCH_PCR_FIA_CC 0 +#define B_PCH_PCR_FIA_CC_SRL BIT31 +#define B_PCH_PCR_FIA_CC_PTOCGE BIT17 +#define B_PCH_PCR_FIA_CC_OSCDCGE BIT16 +#define B_PCH_PCR_FIA_CC_SCPTCGE BIT15 + +#define R_PCH_PCR_FIA_PLLCTL 0x20 +#define R_PCH_PCR_FIA_DRCRM1 0x100 +#define R_PCH_PCR_FIA_DRCRM2 0x104 +#define R_PCH_PCR_FIA_DRCRM3 0x108 +#define S_PCH_PCR_FIA_DRCRM 4 +#define R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE 0x200 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN BIT31 +#define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28) +#define N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL 28 +#define R_PCH_PCR_FIA_PCIESATA_FUSECFG_REG_BASE 0x204 +#define R_PCH_PCR_FIA_PCIESATA_STRPCFG_REG_BASE 0x208 +#define R_PCH_PCR_FIA_PCIEUSB3_STRPFUSECFG_REG_BASE 0x20C +#define R_PCH_PCR_FIA_EXP_FUSECFG_REG_BASE 0x210 +#define R_PCH_PCR_FIA_USB3SSIC_STRPFUSECFG_REG_BASE 0x214 +#define R_PCH_PCR_FIA_CSI3_STRPFUSECFG_REG_BASE 0x218 +#define R_PCH_PCR_FIA_USB3SATA_STRPFUSECFG_REG_BASE 0x21C +#define R_PCH_PCR_FIA_UFS_STRPFUSECFG_REG_BASE 0x220 +#define R_PCH_PCR_FIA_LOS1_REG_BASE 0x250 +#define R_PCH_PCR_FIA_LOS2_REG_BASE 0x254 +#define R_PCH_PCR_FIA_LOS3_REG_BASE 0x258 +#define R_PCH_PCR_FIA_LOS4_REG_BASE 0x25C +#define V_PCH_PCR_FIA_LANE_OWN_PCIEDMI 0x0 +#define V_PCH_PCR_FIA_LANE_OWN_USB3 0x1 +#define V_PCH_PCR_FIA_LANE_OWN_SATA 0x2 +#define V_PCH_PCR_FIA_LANE_OWN_GBE 0x3 +#define V_PCH_PCR_FIA_LANE_OWN_SSIC 0x5 + +#define B_PCH_PCR_FIA_L0O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L1O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L2O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L3O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L5O (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 | BIT25 | BIT24) +#define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_PCR_FIA_L8O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L9O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L10O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L11O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L13O (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 | BIT25 | BIT24) +#define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_PCR_FIA_L16O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L17O (BIT7 | BIT6 | BIT5 | BIT4) +#define B_PCH_PCR_FIA_L18O (BIT11 | BIT10 | BIT9 | BIT8) +#define B_PCH_PCR_FIA_L19O (BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_PCR_FIA_L21O (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 | BIT25 | BIT24) +#define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_PCR_FIA_L24O (BIT3 | BIT2 | BIT1 | BIT0) +#define B_PCH_PCR_FIA_L25O (BIT7 | BIT6 | BIT5 | BIT4) + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsGpio.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsGpio.h new file mode 100644 index 0000000000..24b78d0907 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsGpio.h @@ -0,0 +1,517 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_GPIO_H_ +#define _PCH_REGS_GPIO_H_ + +#define V_PCH_GPIO_GPP_A_PAD_MAX 24 +#define V_PCH_GPIO_GPP_B_PAD_MAX 24 +#define V_PCH_GPIO_GPP_C_PAD_MAX 24 +#define V_PCH_GPIO_GPP_D_PAD_MAX 24 +#define V_PCH_LP_GPIO_GPP_E_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_E_PAD_MAX 13 +#define V_PCH_GPIO_GPP_F_PAD_MAX 24 +#define V_PCH_LP_GPIO_GPP_G_PAD_MAX 8 +#define V_PCH_H_GPIO_GPP_G_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_H_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_J_PAD_MAX 24 +#define V_PCH_H_GPIO_GPP_K_PAD_MAX 11 +#define V_PCH_H_GPIO_GPP_L_PAD_MAX 20 +#define V_PCH_H_GPIO_GPP_I_PAD_MAX 11 + +#define V_PCH_GPIO_GPD_PAD_MAX 12 + +#define V_PCH_GPIO_GROUP_MAX 13 +#define V_PCH_H_GPIO_GROUP_MAX V_PCH_GPIO_GROUP_MAX +#define V_PCH_LP_GPIO_GROUP_MAX 8 +#define V_PCH_GPIO_NUM_SUPPORTED_GPIS 261 +#define S_PCH_GPIO_GP_SMI_EN 4 +#define S_PCH_GPIO_GP_SMI_STS 4 + +/// +/// Groups mapped to 2-tier General Purpose Event will all be under +/// one master GPE_111 (0x6F) +/// +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F + + +// +// GPIO Common Private Configuration Registers +// +#define R_PCH_PCR_GPIO_REV_ID 0x00 +#define R_PCH_PCR_GPIO_CAP_LIST 0x04 +#define R_PCH_PCR_GPIO_FAMBAR 0x08 +#define R_PCH_PCR_GPIO_PADBAR 0x0C +#define B_PCH_PCR_GPIO_PADBAR 0x0000FFFF +#define R_PCH_PCR_GPIO_MISCCFG 0x10 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 16 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 12 +#define B_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PCR_GPIO_MISCCFG_GPE0_DW0 8 +#define B_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE BIT3 +#define N_PCH_PCR_GPIO_MISCCFG_IRQ_ROUTE 3 +#define B_PCH_PCR_GPIO_MISCCFG_GPDPCGEN BIT1 +#define B_PCH_PCR_GPIO_MISCCFG_GPDLCGEN BIT0 +// SKL PCH-H: +#define R_PCH_H_PCR_GPIO_MISCSECCFG 0x14 + +// +// GPIO Community 0 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_B_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_A_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_B_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX 0xAC +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_A_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_B_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX 0x74 +#define R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN 0x88 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IS 0x0108 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_IE 0x0118 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0128 +#define R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0138 +#define R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x580 + +// Common +#define R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN 0x84 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_A_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPP_B_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS 0x0124 +#define R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN 0x0134 +#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x0154 +#define R_PCH_PCR_GPIO_GPP_B_NMI_STS 0x0164 +#define R_PCH_PCR_GPIO_GPP_B_NMI_EN 0x0174 +#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 1 Private Configuration Registers +// +//SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_D_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_E_PAD_OWN 0x40 +#define R_PCH_LP_PCR_GPIO_GPP_C_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_D_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_E_GPI_VWM_EN 0x88 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK 0xB0 +#define R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX 0xB4 +//SKL PCH-H: +#define R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN 0x38 +// Server SKX PCH +#define R_PCH_H_PCR_GPIO_GPP_C_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_D_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_E_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX 0x74 +// Common +#define R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN 0x84 +#define R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN 0x88 +#define R_PCH_PCR_GPIO_GPP_C_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IS 0x0104 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IS 0x0108 +#define R_PCH_PCR_GPIO_GPP_C_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPP_D_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_E_GPI_IE 0x0114 +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS 0x0124 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS 0x0128 +#define R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN 0x0134 +#define R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN 0x0138 +#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0140 +#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0144 +#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0148 +#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x0150 +#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x0154 +#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x0158 +#define R_PCH_PCR_GPIO_GPP_C_NMI_STS 0x0160 +#define R_PCH_PCR_GPIO_GPP_D_NMI_STS 0x0164 +#define R_PCH_PCR_GPIO_GPP_E_NMI_STS 0x0168 +#define R_PCH_PCR_GPIO_GPP_C_NMI_EN 0x0170 +#define R_PCH_PCR_GPIO_GPP_D_NMI_EN 0x0174 +#define R_PCH_PCR_GPIO_GPP_E_NMI_EN 0x0178 + + +// Common: +#define R_PCH_PCR_GPIO_CAP_LIST_1_PWM 0x0200 +#define R_PCH_PCR_GPIO_PWMC 0x0204 +#define R_PCH_PCR_GPIO_CAP_LIST_2_SER_BLINK 0x0208 +#define R_PCH_PCR_GPIO_GP_SER_BLINK 0x020C +#define B_PCH_PCR_GPIO_GP_SER_BLINK 0x1F +#define R_PCH_PCR_GPIO_GP_SER_CMDSTS 0x0210 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS (BIT23 | BIT22) +#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DLS 22 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 0x003F0000 +#define N_PCH_PCR_GPIO_GP_SER_CMDSTS_DRS 16 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_BUSY BIT8 +#define B_PCH_PCR_GPIO_GP_SER_CMDSTS_GO BIT0 +#define R_PCH_PCR_GPIO_GP_SER_DATA 0x0210 +// Common: +#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 +#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 +#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 + +// +// GPIO Community 2 Private Configuration Registers +// +// SKL PCH-LP +#define R_PCH_LP_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPD_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX 0xA4 +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPD_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPD_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX 0x64 +// Common +#define R_PCH_PCR_GPIO_GPD_HOSTSW_OWN 0x80 +#define R_PCH_PCR_GPIO_GPD_GPI_IS 0x0100 +#define R_PCH_PCR_GPIO_GPD_GPI_IE 0x0110 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_STS 0x0120 +#define R_PCH_PCR_GPIO_GPD_GPI_GPE_EN 0x0130 +#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 + +// +// GPIO Community 3 Private Configuration Registers +// +// SKL PCH-LP: +#define R_PCH_LP_PCR_GPIO_GPP_F_PAD_OWN 0x20 +#define R_PCH_LP_PCR_GPIO_GPP_G_PAD_OWN 0x30 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_VWM_EN 0x80 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_VWM_EN 0x84 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK 0xA0 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX 0xA4 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK 0xA8 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX 0xAC +#define R_PCH_LP_PCR_GPIO_GPP_F_HOSTSW_OWN 0xD0 +#define R_PCH_LP_PCR_GPIO_GPP_G_HOSTSW_OWN 0xD4 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IS 0x0100 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IS 0x0104 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_IE 0x0120 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_IE 0x0124 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_STS 0x0140 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0144 +#define R_PCH_LP_PCR_GPIO_GPP_F_GPI_GPE_EN 0x0160 +#define R_PCH_LP_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0164 +#define R_PCH_LP_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 +#define R_PCH_LP_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_STS 0x0140 +#define R_PCH_H_PCR_GPIO_GPP_I_SMI_EN 0x0150 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_STS 0x0160 +#define R_PCH_H_PCR_GPIO_GPP_I_NMI_EN 0x0170 +#define R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET 0x400 + +// +// GPIO Community 4 Private Configuration Registers +// + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IS 0x0104 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_IE 0x0114 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS 0x0124 +#define R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN 0x0134 +#define R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET 0x400 +#define R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET 0x4C0 + +// +// GPIO Community 5 Private Configuration Registers +// + +// SKX Server PCH +#define R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN 0x20 +#define R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN 0x2C +#define R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN 0x38 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_VWM_EN 0x50 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_VWM_EN 0x54 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_VWM_EN 0x58 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK 0x60 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX 0x64 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK 0x68 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX 0x6C +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK 0x70 +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX 0x74 +#define R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN 0x80 +#define R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN 0x84 +#define R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN 0x88 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IS 0x0100 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IS 0x0104 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IS 0x0108 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_IE 0x0110 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_IE 0x0114 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_IE 0x0118 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS 0x0120 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS 0x0124 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_STS 0x0128 +#define R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN 0x0130 +#define R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN 0x0134 +#define R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN 0x0138 +#define R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x400 +#define R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET 0x4C0 +#define R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET 0x580 + + + + +// +// Define Pad Number +// +#define V_GPIO_PAD0 0 +#define V_GPIO_PAD1 1 +#define V_GPIO_PAD2 2 +#define V_GPIO_PAD3 3 +#define V_GPIO_PAD4 4 +#define V_GPIO_PAD5 5 +#define V_GPIO_PAD6 6 +#define V_GPIO_PAD7 7 +#define V_GPIO_PAD8 8 +#define V_GPIO_PAD9 9 +#define V_GPIO_PAD10 10 +#define V_GPIO_PAD11 11 +#define V_GPIO_PAD12 12 +#define V_GPIO_PAD13 13 +#define V_GPIO_PAD14 14 +#define V_GPIO_PAD15 15 +#define V_GPIO_PAD16 16 +#define V_GPIO_PAD17 17 +#define V_GPIO_PAD18 18 +#define V_GPIO_PAD19 19 +#define V_GPIO_PAD20 20 +#define V_GPIO_PAD21 21 +#define V_GPIO_PAD22 22 +#define V_GPIO_PAD23 23 + +// +// Host Software Pad Ownership modes +// +#define V_PCH_PCR_GPIO_HOSTSW_OWN_ACPI 0x00 +#define V_PCH_PCR_GPIO_HOSTSW_OWN_GPIO 0x01 + +// +// Pad Ownership modes +// +#define V_PCH_PCR_GPIO_PAD_OWN_HOST 0x00 +#define V_PCH_PCR_GPIO_PAD_OWN_CSME 0x01 +#define V_PCH_PCR_GPIO_PAD_OWN_ISH 0x02 + +// +// Pad Configuration Register DW0 +// + +//Pad Reset Config +#define B_PCH_GPIO_RST_CONF (BIT31 | BIT30) +#define N_PCH_GPIO_RST_CONF 30 +#define V_PCH_GPIO_RST_CONF_POW_GOOD 0x00 +#define V_PCH_GPIO_RST_CONF_DEEP_RST 0x01 +#define V_PCH_GPIO_RST_CONF_GPIO_RST 0x02 +#define V_PCH_GPIO_RST_CONF_RESUME_RST 0x03 // Only for GPD Group + +//RX Pad State Select +#define B_PCH_GPIO_RX_PAD_STATE BIT29 +#define N_PCH_GPIO_RX_PAD_STATE 29 +#define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00 +#define V_PCH_GPIO_RX_PAD_STATE_INT 0x01 + +//RX Raw Overrride to 1 +#define B_PCH_GPIO_RX_RAW1 BIT28 +#define N_PCH_GPIO_RX_RAW1 28 +#define V_PCH_GPIO_RX_RAW1_DIS 0x00 +#define V_PCH_GPIO_RX_RAW1_EN 0x01 + +//RX Level/Edge Configuration +#define B_PCH_GPIO_RX_LVL_EDG (BIT26 | BIT25) +#define N_PCH_GPIO_RX_LVL_EDG 25 +#define V_PCH_GPIO_RX_LVL_EDG_LVL 0x00 +#define V_PCH_GPIO_RX_LVL_EDG_EDG 0x01 +#define V_PCH_GPIO_RX_LVL_EDG_0 0x02 +#define V_PCH_GPIO_RX_LVL_EDG_RIS_FAL 0x03 + +//RX Invert +#define B_PCH_GPIO_RXINV BIT23 +#define N_PCH_GPIO_RXINV 23 +#define V_PCH_GPIO_RXINV_NO 0x00 +#define V_PCH_GPIO_RXINV_YES 0x01 + +//GPIO Input Route IOxAPIC +#define B_PCH_GPIO_RX_APIC_ROUTE BIT20 +#define N_PCH_GPIO_RX_APIC_ROUTE 20 +#define V_PCH_GPIO_RX_APIC_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01 + +//GPIO Input Route SCI +#define B_PCH_GPIO_RX_SCI_ROUTE BIT19 +#define N_PCH_GPIO_RX_SCI_ROUTE 19 +#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01 + +//GPIO Input Route SMI +#define B_PCH_GPIO_RX_SMI_ROUTE BIT18 +#define N_PCH_GPIO_RX_SMI_ROUTE 18 +#define V_PCH_GPIO_RX_SMI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_SMI_ROUTE_EN 0x01 + +//GPIO Input Route NMI +#define B_PCH_GPIO_RX_NMI_ROUTE BIT17 +#define N_PCH_GPIO_RX_NMI_ROUTE 17 +#define V_PCH_GPIO_RX_NMI_ROUTE_DIS 0x00 +#define V_PCH_GPIO_RX_NMI_ROUTE_EN 0x01 + +//GPIO Pad Mode +#define B_PCH_GPIO_PAD_MODE (BIT12 | BIT11 | BIT10) +#define N_PCH_GPIO_PAD_MODE 10 +#define V_PCH_GPIO_PAD_MODE_GPIO 0 +#define V_PCH_GPIO_PAD_MODE_NAT_1 1 +#define V_PCH_GPIO_PAD_MODE_NAT_2 2 +#define V_PCH_GPIO_PAD_MODE_NAT_3 3 +#define V_PCH_GPIO_PAD_MODE_NAT_4 4 // SPT-H only + +//GPIO RX Disable +#define B_PCH_GPIO_RXDIS BIT9 +#define N_PCH_GPIO_RXDIS 9 +#define V_PCH_GPIO_RXDIS_EN 0x00 +#define V_PCH_GPIO_RXDIS_DIS 0x01 + +//GPIO TX Disable +#define B_PCH_GPIO_TXDIS BIT8 +#define N_PCH_GPIO_TXDIS 8 +#define V_PCH_GPIO_TXDIS_EN 0x00 +#define V_PCH_GPIO_TXDIS_DIS 0x01 + +//GPIO RX State +#define B_PCH_GPIO_RX_STATE BIT1 +#define N_PCH_GPIO_RX_STATE 1 +#define V_PCH_GPIO_RX_STATE_LOW 0x00 +#define V_PCH_GPIO_RX_STATE_HIGH 0x01 + +//GPIO TX State +#define B_PCH_GPIO_TX_STATE BIT0 +#define N_PCH_GPIO_TX_STATE 0 +#define V_PCH_GPIO_TX_STATE_LOW 0x00 +#define V_PCH_GPIO_TX_STATE_HIGH 0x01 + +// +// Pad Configuration Register DW1 +// + +//Padtol +#define B_PCH_GPIO_PADTOL BIT25 +#define N_PCH_GPIO_PADTOL 25 +#define V_PCH_GPIO_PADTOL_NONE 0x00 +#define V_PCH_GPIO_PADTOL_CLEAR 0x00 +#define V_PCH_GPIO_PADTOL_SET 0x01 + +//Termination +#define B_PCH_GPIO_TERM (BIT13 | BIT12 | BIT11 | BIT10) +#define N_PCH_GPIO_TERM 10 +#define V_PCH_GPIO_TERM_WPD_NONE 0x00 +#define V_PCH_GPIO_TERM_WPD_5K 0x02 +#define V_PCH_GPIO_TERM_WPD_20K 0x04 +#define V_PCH_GPIO_TERM_WPU_NONE 0x08 +#define V_PCH_GPIO_TERM_WPU_1K 0x09 +#define V_PCH_GPIO_TERM_WPU_2K 0x0B +#define V_PCH_GPIO_TERM_WPU_5K 0x0A +#define V_PCH_GPIO_TERM_WPU_20K 0x0C +#define V_PCH_GPIO_TERM_WPU_1K_2K 0x0D +#define V_PCH_GPIO_TERM_NATIVE 0x0F + +//Interrupt number +#define B_PCH_GPIO_INTSEL 0x7F +#define N_PCH_GPIO_INTSEL 0 + +// +// Ownership +// +#define V_PCH_GPIO_OWN_GPIO 0x01 +#define V_PCH_GPIO_OWN_ACPI 0x00 + +// +// GPE +// +#define V_PCH_GPIO_GPE_EN 0x01 +#define V_PCH_GPIO_GPE_DIS 0x00 +// +// SMI +// +#define V_PCH_GPIO_SMI_EN 0x01 +#define V_PCH_GPIO_SMI_DIS 0x00 +// +// NMI +// +#define V_PCH_GPIO_NMI_EN 0x01 +#define V_PCH_GPIO_NMI_DIS 0x00 +// +// Reserved: RSVD1 +// +#define V_PCH_GPIO_RSVD1 0x00 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsHda.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsHda.h new file mode 100644 index 0000000000..3b7245eabf --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsHda.h @@ -0,0 +1,232 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +// +// HD-A Controller Registers (D31:F3) +// +// PCI Configuration Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_HDA 31 +#define PCI_FUNCTION_NUMBER_PCH_HDA 3 + +#define V_PCH_HDA_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_LP_HDA_DEVICE_ID_0 0x9D70 +#define V_PCH_LP_HDA_DEVICE_ID_1 0x9D71 +#define V_PCH_LP_HDA_DEVICE_ID_2 0x9D72 +#define V_PCH_LP_HDA_DEVICE_ID_3 0x9D73 +#define V_PCH_LP_HDA_DEVICE_ID_4 0x9D74 +#define V_PCH_LP_HDA_DEVICE_ID_5 0x9D75 +#define V_PCH_LP_HDA_DEVICE_ID_6 0x9D76 +#define V_PCH_LP_HDA_DEVICE_ID_7 0x9D77 +#define V_PCH_H_HDA_DEVICE_ID_0 0xA170 +#define V_PCH_H_HDA_DEVICE_ID_1 0xA171 +#define V_PCH_H_HDA_DEVICE_ID_2 0xA172 +#define V_PCH_H_HDA_DEVICE_ID_3 0xA173 +#define V_PCH_H_HDA_DEVICE_ID_4 0xA174 +#define V_PCH_H_HDA_DEVICE_ID_5 0xA175 +#define V_PCH_H_HDA_DEVICE_ID_6 0xA176 +#define V_PCH_H_HDA_DEVICE_ID_7 0xA177 +// +// LBG SSX (Super SKU) DIDs +// +#define V_PCH_LBG_HDA_DEVICE_ID_0 0xA270 +#define V_PCH_LBG_HDA_DEVICE_ID_1 0xA271 +#define V_PCH_LBG_HDA_DEVICE_ID_2 0xA272 +#define V_PCH_LBG_HDA_DEVICE_ID_3 0xA273 +#define V_PCH_LBG_HDA_DEVICE_ID_4 0xA274 +#define V_PCH_LBG_HDA_DEVICE_ID_5 0xA275 +#define V_PCH_LBG_HDA_DEVICE_ID_6 0xA276 +#define V_PCH_LBG_HDA_DEVICE_ID_7 0xA277 +// +// LBG PRODUCTION (PRQ) DIDs +// +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_0 0xA1F0 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_1 0xA1F1 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_2 0xA1F2 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_3 0xA1F3 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_4 0xA1F4 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_5 0xA1F5 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_6 0xA1F6 +#define V_PCH_LBG_PROD_HDA_DEVICE_ID_7 0xA1F7 + + +#define R_PCH_HDA_PI 0x09 +#define V_PCH_HDA_PI_ADSP_UAA 0x80 +#define R_PCH_HDA_SCC 0x0A +#define V_PCH_HDA_SCC_ADSP 0x01 +#define R_PCH_HDA_HDALBA 0x10 +#define B_PCH_HDA_HDALBA_LBA 0xFFFFC000 +#define V_PCH_HDA_HDBAR_SIZE (1 << 14) +#define R_PCH_HDA_HDAUBA 0x14 +#define B_PCH_HDA_HDAUBA_UBA 0xFFFFFFFF +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_MEMDCGE BIT0 +#define B_PCH_HDA_CGCTL_HDALDCGE BIT3 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define B_PCH_HDA_CGCTL_ODMABDCGE BIT4 +#define B_PCH_HDA_CGCTL_IDMABDCGE BIT5 +#define B_PCH_HDA_CGCTL_IOSFBDCGE BIT7 +#define B_PCH_HDA_CGCTL_IOSFSDCGE BIT8 +#define B_PCH_HDA_CGCTL_APTCGE BIT16 +#define B_PCH_HDA_CGCTL_XOTCGE BIT17 +#define B_PCH_HDA_CGCTL_SROTCGE BIT18 +#define B_PCH_HDA_CGCTL_IOSFBTCGE BIT19 +#define B_PCH_HDA_CGCTL_IOSFSTCGE BIT20 +#define B_PCH_HDA_CGCTL_FROTCGE BIT21 +#define B_PCH_HDA_CGCTL_APLLSE BIT31 +#define R_PCH_HDA_CGCTL 0x48 +#define B_PCH_HDA_CGCTL_MISCBDCGE BIT6 +#define R_PCH_HDA_PC 0x52 +#define V_PCH_HDA_PC_PMES 0x18 +#define N_PCH_HDA_PC_PMES 11 +#define R_PCH_HDA_PCS 0x54 +#define B_PCH_HDA_PCS_PMES BIT15 +#define B_PCH_HDA_PCS_PMEE BIT8 +#define B_PCH_HDA_PCS_PS (BIT1 | BIT0) +#define R_PCH_HDA_MMC 0x62 +#define B_PCH_HDA_MMC_ME BIT0 +#define R_PCH_HDA_DEVC 0x78 +#define B_PCH_HDA_DEVC_NSNPEN BIT11 +#define R_PCH_HDA_SEM1 0xC0 +#define B_PCH_HDA_SEM1_LFLCS BIT24 +#define B_PCH_HDA_SEM1_BLKC3DIS BIT17 +#define B_PCH_HDA_SEM1_TMODE BIT12 +#define B_PCH_HDA_SEM1_FIFORDYSEL (BIT10 | BIT9) +#define R_PCH_HDA_SEM2 0xC4 +#define B_PCH_HDA_SEM2_BSMT (BIT27 | BIT26) +#define V_PCH_HDA_SEM2_BSMT 0x1 +#define N_PCH_HDA_SEM2_BSMT 26 +#define B_PCH_HDA_SEM2_VC0PSNR BIT24 +#define R_PCH_HDA_SEM3L 0xC8 +#define B_PCH_HDA_SEM3L_ISL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM3L_ISL1EXT2 0x2 +#define N_PCH_HDA_SEM3L_ISL1EXT2 20 +#define R_PCH_HDA_SEM4L 0xD0 +#define B_PCH_HDA_SEM4L_OSL1EXT2 (BIT21 | BIT20) +#define V_PCH_HDA_SEM4L_OSL1EXT2 0x3 +#define N_PCH_HDA_SEM4L_OSL1EXT2 20 + +// +// Memory Space Registers +// +// +// Resides in 'HD Audio Global Registers' (0000h) +// +#define R_PCH_HDABA_GCAP 0x00 +#define R_PCH_HDABA_GCTL 0x08 +#define B_PCH_HDABA_GCTL_CRST BIT0 + +#define R_PCH_HDABA_OUTPAY 0x04 +#define R_PCH_HDABA_INPAY 0x06 +#define V_PCH_HDABA_INPAY_DEFAULT 0x1C + +#define R_PCH_HDABA_WAKEEN 0x0C +#define B_PCH_HDABA_WAKEEN_SDI_3 BIT3 +#define B_PCH_HDABA_WAKEEN_SDI_2 BIT2 +#define B_PCH_HDABA_WAKEEN_SDI_1 BIT1 +#define B_PCH_HDABA_WAKEEN_SDI_0 BIT0 + +#define R_PCH_HDABA_WAKESTS 0x0E +#define B_PCH_HDABA_WAKESTS_SDIN3 BIT3 +#define B_PCH_HDABA_WAKESTS_SDIN2 BIT2 +#define B_PCH_HDABA_WAKESTS_SDIN1 BIT1 +#define B_PCH_HDABA_WAKESTS_SDIN0 BIT0 + +// +// Resides in 'HD Audio Controller Registers' (0030h) +// +#define R_PCH_HDABA_IC 0x60 +#define R_PCH_HDABA_IR 0x64 +#define R_PCH_HDABA_ICS 0x68 +#define B_PCH_HDABA_ICS_IRV BIT1 +#define B_PCH_HDABA_ICS_ICB BIT0 + +// +// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h) +// +#define R_PCH_HDABA_PPC 0x0800 // Processing Pipe Capability Structure (Memory Space, offset 0800h) +#define R_PCH_HDABA_PPCTL (R_PCH_HDABA_PPC + 0x04) +#define B_PCH_HDABA_PPCTL_GPROCEN BIT30 + +// +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h) +// +#define V_PCH_HDA_HDALINK_INDEX 0 +#define V_PCH_HDA_IDISPLINK_INDEX 1 + +#define R_PCH_HDABA_MLC 0x0C00 // Multiple Links Capability Structure (Memory Space, offset 0C00h) +#define R_PCH_HDABA_LCTLX(x) (R_PCH_HDABA_MLC + (0x40 + (0x40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link +#define B_PCH_HDABA_LCTLX_CPA BIT23 +#define B_PCH_HDABA_LCTLX_SPA BIT16 +#define N_PCH_HDABA_LCTLX_SCF 0 +#define V_PCH_HDABA_LCTLX_SCF_6MHZ 0x0 +#define V_PCH_HDABA_LCTLX_SCF_12MHZ 0x1 +#define V_PCH_HDABA_LCTLX_SCF_24MHZ 0x2 +#define V_PCH_HDABA_LCTLX_SCF_48MHZ 0x3 +#define V_PCH_HDABA_LCTLX_SCF_96MHZ 0x4 + +// +// Resides in 'HD Audio Vendor Specific Registers' (1000h) +// +#define R_PCH_HDABA_LTRC 0x1048 +#define V_PCH_HDABA_LTRC_GB 0x29 +#define N_PCH_HDABA_LTRC_GB 0 +#define R_PCH_HDABA_PCE 0x104B +#define B_PCH_HDABA_PCE_D3HE BIT2 + +// +// Private Configuration Space Registers +// +// +// Resides in IOSF & Fabric Configuration Registers (000h) +// +#define R_PCH_PCR_HDA_TTCCFG 0xE4 +#define B_PCH_PCR_HDA_TTCCFG_HCDT BIT1 + +// +// Resides in PCI & Codec Configuration Registers (500h) +// +#define R_PCH_PCR_HDA_PCICDCCFG 0x500 // PCI & Codec Configuration Registers (PCR, offset 500h) +#define B_PCH_PCR_HDA_PCICDCCFG_ACPIIN 0x0000FF00 +#define N_PCH_PCR_HDA_PCICDCCFG_ACPIIN 8 +#define R_PCH_PCR_HDA_FNCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x30) +#define B_PCH_PCR_HDA_FNCFG_PGD BIT5 +#define B_PCH_PCR_HDA_FNCFG_BCLD BIT4 +#define B_PCH_PCR_HDA_FNCFG_CGD BIT3 +#define B_PCH_PCR_HDA_FNCFG_ADSPD BIT2 +#define B_PCH_PCR_HDA_FNCFG_HDASD BIT0 +#define R_PCH_PCR_HDA_CDCCFG (R_PCH_PCR_HDA_PCICDCCFG + 0x34) +#define B_PCH_PCR_HDA_CDCCFG_DIS_SDIN2 BIT2 + +// +// Resides in Power Management & EBB Configuration Registers (600h) +// +#define R_PCH_PCR_HDA_PWRMANCFG 0x600 // Power Management & EBB Configuration Registers (PCR, offset 600h) +#define R_PCH_PCR_HDA_APLLP0 (R_PCH_PCR_HDA_PWRMANCFG + 0x10) +#define V_PCH_PCR_HDA_APLLP0 0xFC1E0000 +#define R_PCH_PCR_HDA_APLLP1 (R_PCH_PCR_HDA_PWRMANCFG + 0x14) +#define V_PCH_PCR_HDA_APLLP1 0x00003F00 +#define R_PCH_PCR_HDA_APLLP2 (R_PCH_PCR_HDA_PWRMANCFG + 0x18) +#define V_PCH_PCR_HDA_APLLP2 0x0000011D +#define R_PCH_PCR_HDA_IOBCTL (R_PCH_PCR_HDA_PWRMANCFG + 0x1C) +#define B_PCH_PCR_HDA_IOBCTL_OSEL (BIT9 | BIT8) +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK 0 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_HDALINK_I2S 1 +#define V_PCH_PCR_HDA_IOBCTL_OSEL_I2S 3 +#define N_PCH_PCR_HDA_IOBCTL_OSEL 8 +#define B_PCH_PCR_HDA_IOBCTL_VSEL BIT1 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsHsio.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsHsio.h new file mode 100644 index 0000000000..8323c16425 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsHsio.h @@ -0,0 +1,177 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_HSIO_H_ +#define _PCH_REGS_HSIO_H_ + +#define B_PCH_HSIO_ACCESS_TYPE (BIT15 | BIT14) +#define N_PCH_HSIO_ACCESS_TYPE 14 +#define V_PCH_HSIO_ACCESS_TYPE_BDCAST (BIT15 | BIT14) +#define V_PCH_HSIO_ACCESS_TYPE_MULCAST BIT15 +#define B_PCH_HSIO_LANE_GROUP_NO (BIT13 | BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_HSIO_FUNCTION_NO (BIT8 | BIT7) +#define N_PCH_HSIO_FUNCTION_NO 7 +#define B_PCH_HSIO_REG_OFFSET (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define V_PCH_HSIO_ACCESS_TYPE_BCAST 0x03 +#define V_PCH_HSIO_ACCESS_TYPE_MCAST 0x02 +#define V_PCH_HSIO_ACCESS_TYPE_UCAST 0x00 + +#define V_PCH_HSIO_LANE_GROUP_NO_CMN_LANE 0x00 + +#define V_PCH_HSIO_FUNCTION_NO_PCS 0x00 +#define V_PCH_HSIO_FUNCTION_NO_TX 0x01 +#define V_PCH_HSIO_FUNCTION_NO_RX 0x02 + +#define V_PCH_HSIO_FUNCTION_NO_CMNDIG 0x00 +#define V_PCH_HSIO_FUNCTION_NO_CMNANA 0x01 +#define V_PCH_HSIO_FUNCTION_NO_PLL 0x02 + +#define R_PCH_HSIO_PCS_DWORD4 0x10 + +#define R_PCH_HSIO_PCS_DWORD8 0x20 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000 +#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16 +#define B_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00 +#define N_PCH_HSIO_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8 + +#define R_PCH_HSIO_PCS_DWORD9 0x24 +#define B_PCH_HSIO_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29 + +#define R_PCH_HSIO_RX_DWORD8 0x120 +#define B_PCH_HSIO_RX_DWORD8_ICFGDFETAP3_EN BIT10 + +#define R_PCH_HSIO_RX_DWORD9 0x124 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28 +#define B_PCH_HSIO_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30 + +#define R_PCH_HSIO_RX_DWORD12 0x130 +#define B_PCH_HSIO_RX_DWORD12_O_CFGEWMARGINSEL BIT14 + +#define R_PCH_HSIO_RX_DWORD20 0x150 +#define B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24 + +#define R_PCH_HSIO_RX_DWORD21 0x154 +#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8 +#define B_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define N_PCH_HSIO_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0 + +#define R_PCH_HSIO_RX_DWORD23 0x15C +#define B_PCH_HSIO_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2 +#define B_PCH_HSIO_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4 + +#define R_PCH_HSIO_RX_DWORD25 0x164 +#define B_PCH_HSIO_RX_DWORD25_RX_TAP_CFG_CTRL BIT3 +#define B_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000 +#define N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16 + +#define R_PCH_HSIO_RX_DWORD26 0x168 +#define B_PCH_HSIO_RX_DWORD26_SATA_EQ_DIS BIT16 + +#define R_PCH_HSIO_RX_DWORD34 0x188 +#define B_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | BIT12) +#define N_PCH_HSIO_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12 + +#define R_PCH_HSIO_RX_DWORD44 0x1B0 +#define B_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000 +#define N_PCH_HSIO_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16 + +#define R_PCH_HSIO_RX_DWORD56 0x1E0 +#define B_PCH_HSIO_RX_DWORD56_ICFGPIDACCFGVALID BIT16 + +#define R_PCH_HSIO_RX_DWORD57 0x1E4 +#define B_PCH_HSIO_RX_DWORD57_JIM_COURSE BIT30 +#define B_PCH_HSIO_RX_DWORD57_JIM_ENABLE BIT29 +#define B_PCH_HSIO_RX_DWORD57_JIMMODE BIT28 +#define B_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000 +#define N_PCH_HSIO_RX_DWORD57_JIMNUMCYCLES_3_0 24 +#define B_PCH_HSIO_RX_DWORD57_ICFGMARGINEN BIT0 + +#define R_PCH_HSIO_RX_DWORD59 0x1EC +#define R_PCH_HSIO_RX_DWORD60 0x1F0 + +#define R_PCH_HSIO_TX_DWORD5 0x94 +#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16 +#define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8 + +#define R_PCH_HSIO_TX_DWORD6 0x98 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8 +#define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define R_PCH_HSIO_TX_DWORD8 0xA0 +#define B_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 24 +#define B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 16 +#define B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0 8 + +#define R_PCH_HSIO_TX_DWORD19 0xCC + +#define R_PCH_LP_HSIO_LANE10_PCS_DWORD8 0x020 +#define R_PCH_LP_HSIO_LANE11_PCS_DWORD8 0x220 +#define R_PCH_LP_HSIO_LANE14_PCS_DWORD8 0x820 +#define R_PCH_LP_HSIO_LANE15_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE18_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE19_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE22_PCS_DWORD8 0x020 +#define R_PCH_H_HSIO_LANE23_PCS_DWORD8 0x220 +#define R_PCH_H_HSIO_LANE24_PCS_DWORD8 0x420 +#define R_PCH_H_HSIO_LANE25_PCS_DWORD8 0x620 +#define R_PCH_H_HSIO_LANE26_PCS_DWORD8 0x820 +#define R_PCH_H_HSIO_LANE27_PCS_DWORD8 0xA20 +#define R_PCH_H_HSIO_LANE28_PCS_DWORD8 0xC20 +#define R_PCH_H_HSIO_LANE29_PCS_DWORD8 0xE20 + +#define R_PCH_HSIO_CLANE0_CMN_ANA_DWORD2 0x8088 +#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN BIT5 +#define B_PCH_HSIO_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDEN BIT3 + +#define R_PCH_HSIO_PLL_SSC_DWORD2 0x8108 +#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16 +#define B_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN BIT10 +#define N_PCH_HSIO_PLL_SSC_DWORD2_SSCSEN 10 + +#define R_PCH_HSIO_PLL_SSC_DWORD3 0x810C +#define B_PCH_HSIO_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0 + +#define R_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12 0x8030 +#define B_PCH_PCR_MODPHY0_COM0_CMN_DIG_DWORD12_O_CFG_PWR_GATING_CTRL BIT0 + +// +// xHCI SSIC Private Configuration Register, but with opcode 4/5 for read/write access +// +#define R_PCH_PCR_MMP0_LANE_0_OFFSET 0x0 +#define R_PCH_PCR_MMP0_LANE_1_OFFSET 0x2000 +#define R_PCH_PCR_MMP0_IMPREG21 0x1050 +#define R_PCH_PCR_MMP0_IMPREG22 0x1054 +#define R_PCH_PCR_MMP0_IMPREG23 0x1058 +#define R_PCH_PCR_MMP0_IMPREG24 0x105C +#define R_PCH_PCR_MMP0_IMPREG25 0x1060 +#define R_PCH_PCR_MMP0_CMNREG4 0xF00C +#define R_PCH_PCR_MMP0_CMNREG15 0xF038 +#define R_PCH_PCR_MMP0_CMNREG16 0xF03C + +#endif //_PCH_REGS_HSIO_H_ + diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsIsh.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsIsh.h new file mode 100644 index 0000000000..ee011d84c4 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsIsh.h @@ -0,0 +1,57 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_ISH_H_ +#define _PCH_REGS_ISH_H_ + +// +// ISH Controller Registers (D19:F0) +// +// PCI Configuration Space Registers +#define PCI_DEVICE_NUMBER_PCH_ISH 19 +#define PCI_FUNCTION_NUMBER_PCH_ISH 0 +#define V_PCH_ISH_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_ISH_DEVICE_ID 0xA135 +#define V_PCH_LP_ISH_DEVICE_ID 0x9D35 + +#define R_PCH_ISH_BAR0_LOW 0x10 +#define R_PCH_ISH_BAR0_HIGH 0x14 +#define V_PCH_ISH_BAR0_SIZE 0x100000 +#define N_PCH_ISH_BAR0_ALIGNMENT 20 +#define R_PCH_ISH_BAR1_LOW 0x18 +#define R_PCH_ISH_BAR1_HIGH 0x1C +#define V_PCH_ISH_BAR1_SIZE 0x1000 +#define N_PCH_ISH_BAR1_ALIGNMENT 12 + +// +// ISH Private Configuration Space Registers (IOSF2OCP) +// (PID:ISH) +// +#define R_PCH_PCR_ISH_PMCTL 0x1D0 ///< Power Management +#define R_PCH_PCR_ISH_PCICFGCTRL 0x200 ///< PCI Configuration Control +#define B_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number +#define N_PCH_PCR_ISH_PCICFGCTR_PCI_IRQ 20 +#define B_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number +#define N_PCH_PCR_ISH_PCICFGCTR_ACPI_IRQ 12 +#define B_PCH_PCR_ISH_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin +#define N_PCH_PCR_ISH_PCICFGCTR_IPIN1 8 +#define B_PCH_PCR_ISH_PCICFGCTRL_BAR1DIS BIT7 ///< BAR1 Disable + +// +// Number of pins used by ISH controllers +// +#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2 +#define PCH_ISH_PINS_PER_UART_CONTROLLER 4 +#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsItss.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsItss.h new file mode 100644 index 0000000000..d78cc615bb --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsItss.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_ITSS_H_ +#define _PCH_REGS_ITSS_H_ + +// +// ITSS PCRs (PID:ITSS) +// +#define R_PCH_PCR_ITSS_PIRQA_ROUT 0x3100 ///< PIRQA Routing Control register +#define R_PCH_PCR_ITSS_PIRQB_ROUT 0x3101 ///< PIRQB Routing Control register +#define R_PCH_PCR_ITSS_PIRQC_ROUT 0x3102 ///< PIRQC Routing Control register +#define R_PCH_PCR_ITSS_PIRQD_ROUT 0x3103 ///< PIRQD Routing Control register +#define R_PCH_PCR_ITSS_PIRQE_ROUT 0x3104 ///< PIRQE Routing Control register +#define R_PCH_PCR_ITSS_PIRQF_ROUT 0x3105 ///< PIRQF Routing Control register +#define R_PCH_PCR_ITSS_PIRQG_ROUT 0x3106 ///< PIRQG Routing Control register +#define R_PCH_PCR_ITSS_PIRQH_ROUT 0x3107 ///< PIRQH Routing Control register +#define B_PCH_PCR_ITSS_PIRQX_ROUT_REN 0x80 ///< Interrupt Routing Enable +#define B_PCH_PCR_ITSS_PIRQX_ROUT_IR 0x0F ///< IRQ Routng +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx to IRQ3 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx to IRQ4 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx to IRQ5 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx to IRQ6 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx to IRQ7 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx to IRQ9 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx to IRQ10 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx to IRQ11 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx to IRQ12 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx to IRQ14 +#define V_PCH_PCR_ITSS_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx to IRQ15 + +#define R_PCH_PCR_ITSS_PIR0 0x3140 ///< PCI Interrupt Route 0 +#define R_PCH_PCR_ITSS_PIR1 0x3142 ///< PCI Interrupt Route 1 +#define R_PCH_PCR_ITSS_PIR2 0x3144 ///< PCI Interrupt Route 2 +#define R_PCH_PCR_ITSS_PIR3 0x3146 ///< PCI Interrupt Route 3 +#define R_PCH_PCR_ITSS_PIR4 0x3148 ///< PCI Interrupt Route 4 +#define R_PCH_PCR_ITSS_PIR5 0x314A ///< PCI Interrupt Route 5 +#define R_PCH_PCR_ITSS_PIR6 0x314C ///< PCI Interrupt Route 6 +#define R_PCH_PCR_ITSS_PIR7 0x314E ///< PCI Interrupt Route 7 +#define R_PCH_PCR_ITSS_PIR8 0x3150 ///< PCI Interrupt Route 8 +#define R_PCH_PCR_ITSS_PIR9 0x3152 ///< PCI Interrupt Route 9 +#define R_PCH_PCR_ITSS_PIR10 0x3154 ///< PCI Interrupt Route 10 +#define R_PCH_PCR_ITSS_PIR11 0x3156 ///< PCI Interrupt Route 11 +#define R_PCH_PCR_ITSS_PIR12 0x3158 ///< PCI Interrupt Route 12 + +#define R_PCH_PCR_ITSS_GIC 0x31FC ///< General Interrupt Control +#define B_PCH_PCR_ITSS_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ entry size, 1 = 24 entry size, 0 = 120 entry size +#define B_PCH_PCR_ITSS_GIC_AME BIT17 ///< Alternate Access Mode Enable +#define B_PCH_PCR_ITSS_GIC_SPS BIT16 ///< Shutdown Policy Select +#define R_PCH_PCR_ITSS_IPC0 0x3200 ///< Interrupt Polarity Control 0 +#define R_PCH_PCR_ITSS_IPC1 0x3204 ///< Interrupt Polarity Control 1 +#define R_PCH_PCR_ITSS_IPC2 0x3208 ///< Interrupt Polarity Control 2 +#define R_PCH_PCR_ITSS_IPC3 0x320C ///< Interrupt Polarity Control 3 +#define R_PCH_PCR_ITSS_ITSSPRC 0x3300 ///< ITSS Power Reduction Control +#define B_PCH_PCR_ITSS_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynamic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynamic Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_8254CGE BIT2 ///< 8254 Static Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideband Interface Clock Gating Enable +#define B_PCH_PCR_ITSS_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock Gate Enable + +#define R_PCH_PCR_ITSS_MMC 0x3334 ///< Master Message Control +#define B_PCH_PCR_ITSS_MMC_MSTRMSG_EN BIT0 ///< Master Message Enable + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsLan.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsLan.h new file mode 100644 index 0000000000..e6e89ab68f --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsLan.h @@ -0,0 +1,141 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_LAN_H_ +#define _PCH_REGS_LAN_H_ + +// +// Gigabit LAN Controller configuration registers (D31:F6) +// +#define PCI_DEVICE_NUMBER_PCH_LAN 31 +#define PCI_FUNCTION_NUMBER_PCH_LAN 6 + +#define V_PCH_LAN_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_LAN_DEVICE_ID 0x156F + +// +// LBG Production Gigabit LAN Controller Device ID +// +#define V_PCH_LBG_PROD_LAN_DEVICE_ID 0xA1A5 +// +// LBG SSX (Super SKU) Gigabit LAN Controller Device ID +// +#define V_PCH_LBG_LAN_DEVICE_ID 0xA225 + +#define V_PCH_LP_LAN_DEVICE_ID 0x156F +#define R_PCH_LAN_MBARA 0x10 +#define B_PCH_LAN_MBARA_BA 0xFFFE0000 +#define N_PCH_LAN_MBARA_ALIGN 17 +#define R_PCH_LAN_LTR_CAP 0xA8 +#define R_PCH_LAN_CLIST1 0xC8 +#define B_PCH_LAN_CLIST1_NEXT 0xFF00 +#define B_PCH_LAN_CLIST1_CID 0x00FF +#define R_PCH_LAN_PMC 0xCA +#define B_PCH_LAN_PMC_PMES 0xF800 +#define B_PCH_LAN_PMC_D2S BIT10 +#define B_PCH_LAN_PMC_D1S BIT9 +#define B_PCH_LAN_PMC_AC (BIT8 | BIT7 | BIT6) +#define B_PCH_LAN_PMC_DSI BIT5 +#define B_PCH_LAN_PMC_PMEC BIT3 +#define B_PCH_LAN_PMC_VS (BIT2 | BIT1 | BIT0) +#define R_PCH_LAN_PMCS 0xCC +#define B_PCH_LAN_PMCS_PMES BIT15 +#define B_PCH_LAN_PMCS_DSC (BIT14 | BIT13) +#define B_PCH_LAN_PMCS_DSL 0x1E00 +#define V_PCH_LAN_PMCS_DSL0 0x0000 +#define V_PCH_LAN_PMCS_DSL3 0x0600 +#define V_PCH_LAN_PMCS_DSL4 0x0800 +#define V_PCH_LAN_PMCS_DSL7 0x0E00 +#define V_PCH_LAN_PMCS_DSL8 0x1000 +#define B_PCH_LAN_PMCS_PMEE BIT8 +#define B_PCH_LAN_PMCS_PS (BIT1 | BIT0) +#define V_PCH_LAN_PMCS_PS0 0x00 +#define V_PCH_LAN_PMCS_PS3 0x03 +#define R_PCH_LAN_DR 0xCF +#define B_PCH_LAN_DR 0xFF +#define R_PCH_LAN_CLIST2 0xD0 +#define B_PCH_LAN_CLIST2_NEXT 0xFF00 +#define B_PCH_LAN_CLIST2_CID 0x00FF +#define R_PCH_LAN_MCTL 0xD2 +#define B_PCH_LAN_MCTL_CID BIT7 +#define B_PCH_LAN_MCTL_MME (BIT6 | BIT5 | BIT4) +#define B_PCH_LAN_MCTL_MMC (BIT3 | BIT2 | BIT1) +#define B_PCH_LAN_MCTL_MSIE BIT0 +#define R_PCH_LAN_MADDL 0xD4 +#define B_PCH_LAN_MADDL 0xFFFFFFFF +#define R_PCH_LAN_MADDH 0xD8 +#define B_PCH_LAN_MADDH 0xFFFFFFFF +#define R_PCH_LAN_MDAT 0xDC +#define B_PCH_LAN_MDAT 0xFFFFFFFF +#define R_PCH_LAN_FLRCAP 0xE0 +#define B_PCH_LAN_FLRCAP_NEXT 0xFF00 +#define B_PCH_LAN_FLRCAP_CID 0x00FF +#define V_PCH_LAN_FLRCAP_CID_SSEL0 0x13 +#define V_PCH_LAN_FLRCAP_CID_SSEL1 0x09 +#define R_PCH_LAN_FLRCLV 0xE2 +#define B_PCH_LAN_FLRCLV_FLRC_SSEL0 BIT9 +#define B_PCH_LAN_FLRCLV_TXP_SSEL0 BIT8 +#define B_PCH_LAN_FLRCLV_VSCID_SSEL1 0xF000 +#define B_PCH_LAN_FLRCLV_CAPVER_SSEL1 0x0F00 +#define B_PCH_LAN_FLRCLV_CAPLNG 0x00FF +#define R_PCH_LAN_DEVCTRL 0xE4 +#define B_PCH_LAN_DEVCTRL BIT0 +#define R_PCH_LAN_CPCE 0x80 +#define B_PCH_LAN_CPCE_HAE BIT5 +#define B_PCH_LAN_CPCE_SE BIT3 +#define B_PCH_LAN_CPCE_D3HE BIT2 +#define B_PCH_LAN_CPCE_I3E BIT1 +#define B_PCH_LAN_CPCE_PCMCRE BIT0 +#define R_PCH_LAN_CD0I3 0x84 +#define B_PCH_LAN_CD0I3_RR BIT3 +#define B_PCH_LAN_CD0I3_D0I3 BIT2 +#define R_PCH_LAN_CLCTL 0x94 +#define R_PCH_LAN_LANDISCTRL 0xA0 +#define B_PCH_LAN_LANDISCTRL_DISABLE BIT0 +#define R_PCH_LAN_LOCKLANDIS 0xA4 +#define B_PCH_LAN_LOCKLANDIS_LOCK BIT0 +// +// Gigabit LAN Capabilities and Status Registers (Memory space) +// +#define R_PCH_LAN_CSR_CTRL 0 +#define B_PCH_LAN_CSR_CTRL_MEHE BIT19 +#define R_PCH_LAN_CSR_STRAP 0x000C +#define B_PCH_LAN_CSR_STRAP_NVM_VALID BIT11 +#define R_PCH_LAN_CSR_FEXTNVM6 0x0010 +#define R_PCH_LAN_CSR_CTRL_EXT 0x0018 +#define B_PCH_LAN_CSR_CTRL_EXT_FORCE_SMB BIT11 +#define R_PCH_LAN_CSR_MDIC 0x0020 +#define B_PCH_LAN_CSR_MDIC_RB BIT28 +#define B_PCH_LAN_CSR_MDIC_DATA 0xFFFF +#define R_PCH_LAN_CSR_FEXT 0x002C +#define B_PCH_LAN_CSR_FEXT_WOL BIT30 +#define B_PCH_LAN_CSR_FEXT_WOL_VALID BIT31 +#define R_PCH_LAN_CSR_EXTCNF_CTRL 0x0F00 +#define B_PCH_LAN_CSR_EXTCNF_CTRL_SWFLAG BIT5 +#define B_PCH_LAN_CSR_EXTCNF_K1OFF_EN BIT8 +#define R_PCH_LAN_CSR_PHY_CTRL 0x0F10 +#define B_PCH_LAN_CSR_PHY_CTRL_GGD BIT6 +#define B_PCH_LAN_CSR_PHY_CTRL_GBEDIS BIT3 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUND BIT2 +#define B_PCH_LAN_CSR_PHY_CTRL_LPLUD BIT1 +#define R_PCH_LAN_CSR_F18 0x0F18 +#define B_PCH_LAN_CSR_F18_K1OFF_EN BIT31 +#define R_PCH_LAN_CSR_PBECCSTS 0x100C +#define B_PCH_LAN_CSR_PBECCSTS_ECC_EN BIT16 +#define R_PCH_LAN_CSR_RAL 0x5400 +#define R_PCH_LAN_CSR_RAH 0x5404 +#define B_PCH_LAN_CSR_RAH_RAH 0x0000FFFF +#define R_PCH_LAN_CSR_WUC 0x5800 +#define B_PCH_LAN_CSR_WUC_APME BIT0 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsLpc.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsLpc.h new file mode 100644 index 0000000000..4a2f8c8533 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsLpc.h @@ -0,0 +1,436 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +#include <PchLimits.h> +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +typedef enum { + PchHA0 = 0x00, + PchHB0 = 0x01, + PchHC0, + PchHD0, + PchHD1, +#ifdef SIMICS_FLAG + PchLpA0 = 0x20, +#endif + PchLpB0 = 0x23, + PchLpB1, + PchLpC0, + PchLpC1, + LbgA0 = LBG_A0, + LbgB0, + LbgB1, + LbgB2, + LbgS0, + LbgS1, +#ifdef SKXD_EN + LbgB1_D, +#endif // SKXD_EN + PchSteppingMax +} PCH_STEPPING; + +#define PCH_H_MIN_SUPPORTED_STEPPING PchHA0 +#define PCH_LP_MIN_SUPPORTED_STEPPING PchLpB0 + +#define PCH_LBG_MIN_SUPPORTED_STEPPING LbgA0 +#define V_PCH_LPC_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +// +// +// SKL PCH Server/WS LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_SVR_0 0xA149 ///< Server SKU Intel C236 Chipset +#define V_PCH_H_LPC_DEVICE_ID_SVR_1 0xA14A ///< Server SKU Intel C232 Chipset +#define V_PCH_H_LPC_DEVICE_ID_SVR_2 0xA150 ///< Server SKU Intel CM236 Chipset +#define V_PCH_H_LPC_DEVICE_ID_A14B 0xA14B ///< Super SKU Unlocked + +// +// SKL PCH-H Desktop LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU 0xA141 ///< PCH H Desktop Super SKU unlocked +#define V_PCH_H_LPC_DEVICE_ID_DT_0 0xA142 ///< PCH H Desktop Super SKU locked +#define V_PCH_H_LPC_DEVICE_ID_DT_1 0xA143 ///< PCH H Desktop H110 +#define V_PCH_H_LPC_DEVICE_ID_DT_2 0xA144 ///< PCH H Desktop H170 +#define V_PCH_H_LPC_DEVICE_ID_DT_3 0xA145 ///< PCH H Desktop Z170 +#define V_PCH_H_LPC_DEVICE_ID_DT_4 0xA146 ///< PCH H Desktop Q170 +#define V_PCH_H_LPC_DEVICE_ID_DT_5 0xA147 ///< PCH H Desktop Q150 +#define V_PCH_H_LPC_DEVICE_ID_DT_6 0xA148 ///< PCH H Desktop B150 +#define V_PCH_H_LPC_DEVICE_ID_UNFUSE 0xA140 ///< PCH-H Unfuse +// +// PCH-H Mobile LPC Device IDs +// +#define V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU 0xA141 ///< PCH H Mobile Super SKU unlocked +#define V_PCH_H_LPC_DEVICE_ID_MB_0 0xA14D ///< PCH H Mobile QM170 +#define V_PCH_H_LPC_DEVICE_ID_MB_1 0xA14E ///< PCH H Mobile HM170 +#define V_PCH_H_LPC_DEVICE_ID_MB_2 0xA14F ///< PCH H Mobile QMS170 (SFF) +// +// PCH-LP LPC Device IDs +// +#define V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU 0x9D41 ///< PCH LP Mobile Super SKU unlocked +#define V_PCH_LP_LPC_DEVICE_ID_MB_0 0x9D42 ///< PCH LP Mobile Super SKU locked +#define V_PCH_LP_LPC_DEVICE_ID_MB_1 0x9D43 ///< PCH LP Mobile (U) Base SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_2 0x9D46 ///< PCH LP Mobile (Y) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_MB_3 0x9D48 ///< PCH LP Mobile (U) Premium SKU +#define V_PCH_LP_LPC_DEVICE_ID_UNFUSE 0x9D40 ///< PCH LP Unfuse + +// +// Lewisburg Production LPC Device ID's +// +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_0 0xA1C0 ///< LBG PRQ Unfused LBG 0 SKU +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_1G 0xA1C1 ///< LBG PRQ Fused LBG 1G +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_2 0xA1C2 ///< LBG PRQ Fused LBG 2 +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_4 0xA1C3 ///< LBG PRQ Fused LBG 4 +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_E 0xA1C4 ///< LBG PRQ Fused LBG E +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_M 0xA1C5 ///< LBG PRQ Fused LBG M +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_T 0xA1C6 ///< LBG PRQ Fused LBG T (both uplinks SKU - NS) +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_LP 0xA1C7 ///< LBG PRQ Fused LBG LP + +#define V_PCH_LBG_PROD_LPC_DEVICE_ID_RESERVED_MAX 0xA1CF ///< 0xA1C8-0xA1CF reserved for future QS/PRQ SKUs + +// +// Lewisburg SSX (Super SKUs and pre production) LPC Device ID's +// +#define V_PCH_LBG_LPC_DEVICE_ID_UNFUSED 0xA240 ///< LBG SSX Unfused SKU +#define V_PCH_LBG_LPC_DEVICE_ID_SS_0 0xA241 ///< LBG SSX Super SKU 0 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD 0xA242 ///< LBG SSX Super SKU 4/SD +#define V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS 0xA243 ///< LBG SSX Super SKU T80/NS +#define V_PCH_LBG_LPC_DEVICE_ID_SS_1G 0xA244 ///< LBG SSX Super SKU 1G +#define V_PCH_LBG_LPC_DEVICE_ID_SS_T 0xA245 ///< LBG Super SKU - T +#define V_PCH_LBG_LPC_DEVICE_ID_SS_L 0xA246 ///< LBG Super SKU - L +#ifdef SKXD_EN +#define V_PCH_LBG_LPC_DEVICE_ID_SS_D1 0xA247 ///< LBG Super SKU - D co.fb.sh.1 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_D2 0xA248 ///< LBG Super SKU - D st.gp.sh.2 +#define V_PCH_LBG_LPC_DEVICE_ID_SS_D3 0xA249 ///< LBG Super SKU - D ne.gp.sh.1 +#endif // SKXD_EN + +#define V_PCH_LBG_LPC_DEVICE_ID_RESERVED_SS_MAX 0xA24F ///< 0xA247-0xA24F Super SKU reserved + + +#define V_PCH_LBG_LPC_RID_0 0x00 ///< A0 stepping +#define V_PCH_LBG_LPC_RID_1 0x01 ///< A1 stepping +#define V_PCH_LBG_LPC_RID_2 0x02 ///< B0 stepping +#define V_PCH_LBG_LPC_RID_3 0x03 ///< B1 stepping +#define V_PCH_LBG_LPC_RID_4 0x04 ///< B2 stepping +#define V_PCH_LBG_LPC_RID_8 0x08 ///< S0 stepping +#define V_PCH_LBG_LPC_RID_9 0x09 ///< S1 stepping + +#define V_PCH_LPC_RID_0 0x00 +#define V_PCH_LPC_RID_1 0x01 +#define V_PCH_LPC_RID_9 0x09 +#define V_PCH_LPC_RID_10 0x10 +#define V_PCH_LPC_RID_11 0x11 +#define V_PCH_LPC_RID_20 0x20 +#define V_PCH_LPC_RID_21 0x21 +#define V_PCH_LPC_RID_30 0x30 +#define V_PCH_LPC_RID_31 0x31 +#define R_PCH_LPC_SERIRQ_CNT 0x64 +#define B_PCH_LPC_SERIRQ_CNT_SIRQEN 0x80 +#define B_PCH_LPC_SERIRQ_CNT_SIRQMD 0x40 +#define B_PCH_LPC_SERIRQ_CNT_SIRQSZ 0x3C +#define N_PCH_LPC_SERIRQ_CNT_SIRQSZ 2 +#define B_PCH_LPC_SERIRQ_CNT_SFPW 0x03 +#define N_PCH_LPC_SERIRQ_CNT_SFPW 0 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_PCH_LPC_SERIRQ_CNT_SFPW_8CLK 0x02 +#define R_PCH_LPC_IOD 0x80 +#define B_PCH_LPC_IOD_FDD 0x1000 +#define N_PCH_LPC_IOD_FDD 12 +#define V_PCH_LPC_IOD_FDD_3F0 0 +#define V_PCH_LPC_IOD_FDD_370 1 +#define B_PCH_LPC_IOD_LPT 0x0300 +#define N_PCH_LPC_IOD_LPT 8 +#define V_PCH_LPC_IOD_LPT_378 0 +#define V_PCH_LPC_IOD_LPT_278 1 +#define V_PCH_LPC_IOD_LPT_3BC 2 +#define B_PCH_LPC_IOD_COMB 0x0070 +#define N_PCH_LPC_IOD_COMB 4 +#define V_PCH_LPC_IOD_COMB_3F8 0 +#define V_PCH_LPC_IOD_COMB_2F8 1 +#define V_PCH_LPC_IOD_COMB_220 2 +#define V_PCH_LPC_IOD_COMB_228 3 +#define V_PCH_LPC_IOD_COMB_238 4 +#define V_PCH_LPC_IOD_COMB_2E8 5 +#define V_PCH_LPC_IOD_COMB_338 6 +#define V_PCH_LPC_IOD_COMB_3E8 7 +#define B_PCH_LPC_IOD_COMA 0x0007 +#define N_PCH_LPC_IOD_COMA 0 +#define V_PCH_LPC_IOD_COMA_3F8 0 +#define V_PCH_LPC_IOD_COMA_2F8 1 +#define V_PCH_LPC_IOD_COMA_220 2 +#define V_PCH_LPC_IOD_COMA_228 3 +#define V_PCH_LPC_IOD_COMA_238 4 +#define V_PCH_LPC_IOD_COMA_2E8 5 +#define V_PCH_LPC_IOD_COMA_338 6 +#define V_PCH_LPC_IOD_COMA_3E8 7 +#define R_PCH_LPC_IOE 0x82 +#define B_PCH_LPC_IOE_ME2 BIT13 ///< Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC +#define B_PCH_LPC_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC. +#define B_PCH_LPC_IOE_ME1 BIT11 ///< Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC. +#define B_PCH_LPC_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC. +#define B_PCH_LPC_IOE_HGE BIT9 ///< High Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC. +#define B_PCH_LPC_IOE_LGE BIT8 ///< Low Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC. +#define B_PCH_LPC_IOE_FDE BIT3 ///< Floppy Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by LIOD.FDE +#define B_PCH_LPC_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT. +#define B_PCH_LPC_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB. +#define B_PCH_LPC_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA. +#define R_PCH_LPC_GEN1_DEC 0x84 +#define R_PCH_LPC_GEN2_DEC 0x88 +#define R_PCH_LPC_GEN3_DEC 0x8C +#define R_PCH_LPC_GEN4_DEC 0x90 +#define B_PCH_LPC_GENX_DEC_IODRA 0x00FC0000 +#define B_PCH_LPC_GENX_DEC_IOBAR 0x0000FFFC +#define B_PCH_LPC_GENX_DEC_EN 0x00000001 +#define R_PCH_LPC_ULKMC 0x94 +#define B_PCH_LPC_ULKMC_SMIBYENDPS BIT15 +#define B_PCH_LPC_ULKMC_TRAPBY64W BIT11 +#define B_PCH_LPC_ULKMC_TRAPBY64R BIT10 +#define B_PCH_LPC_ULKMC_TRAPBY60W BIT9 +#define B_PCH_LPC_ULKMC_TRAPBY60R BIT8 +#define B_PCH_LPC_ULKMC_SMIATENDPS BIT7 +#define B_PCH_LPC_ULKMC_PSTATE BIT6 +#define B_PCH_LPC_ULKMC_A20PASSEN BIT5 +#define B_PCH_LPC_ULKMC_USBSMIEN BIT4 +#define B_PCH_LPC_ULKMC_64WEN BIT3 +#define B_PCH_LPC_ULKMC_64REN BIT2 +#define B_PCH_LPC_ULKMC_60WEN BIT1 +#define B_PCH_LPC_ULKMC_60REN BIT0 +#define R_PCH_LPC_LGMR 0x98 +#define B_PCH_LPC_LGMR_MA 0xFFFF0000 +#define B_PCH_LPC_LGMR_LMRD_EN BIT0 +#define LPC_ESPI_FIRST_SLAVE 0 +#define ESPI_SECONDARY_SLAVE 1 + +#define R_PCH_LPC_FWH_BIOS_SEL 0xD0 +#define B_PCH_LPC_FWH_BIOS_SEL_F8 0xF0000000 +#define B_PCH_LPC_FWH_BIOS_SEL_F0 0x0F000000 +#define B_PCH_LPC_FWH_BIOS_SEL_E8 0x00F00000 +#define B_PCH_LPC_FWH_BIOS_SEL_E0 0x000F0000 +#define B_PCH_LPC_FWH_BIOS_SEL_D8 0x0000F000 +#define B_PCH_LPC_FWH_BIOS_SEL_D0 0x00000F00 +#define B_PCH_LPC_FWH_BIOS_SEL_C8 0x000000F0 +#define B_PCH_LPC_FWH_BIOS_SEL_C0 0x0000000F +#define R_PCH_LPC_FWH_BIOS_SEL2 0xD4 +#define B_PCH_LPC_FWH_BIOS_SEL2_70 0xF000 +#define B_PCH_LPC_FWH_BIOS_SEL2_60 0x0F00 +#define B_PCH_LPC_FWH_BIOS_SEL2_50 0x00F0 +#define B_PCH_LPC_FWH_BIOS_SEL2_40 0x000F +#define R_PCH_LPC_BDE 0xD8 ///< BIOS decode enable +#define B_PCH_LPC_BDE_F8 0x8000 +#define B_PCH_LPC_BDE_F0 0x4000 +#define B_PCH_LPC_BDE_E8 0x2000 +#define B_PCH_LPC_BDE_E0 0x1000 +#define B_PCH_LPC_BDE_D8 0x0800 +#define B_PCH_LPC_BDE_D0 0x0400 +#define B_PCH_LPC_BDE_C8 0x0200 +#define B_PCH_LPC_BDE_C0 0x0100 +#define B_PCH_LPC_BDE_LEG_F 0x0080 +#define B_PCH_LPC_BDE_LEG_E 0x0040 +#define B_PCH_LPC_BDE_70 0x0008 +#define B_PCH_LPC_BDE_60 0x0004 +#define B_PCH_LPC_BDE_50 0x0002 +#define B_PCH_LPC_BDE_40 0x0001 +#define R_PCH_LPC_PCC 0xE0 +#define B_PCH_LPC_PCC_CLKRUN_EN 0x0001 +#define B_PCH_LPC_FVEC0_USB_PORT_CAP 0x00000C00 +#define V_PCH_LPC_FVEC0_USB_14_PORT 0x00000000 +#define V_PCH_LPC_FVEC0_USB_12_PORT 0x00000400 +#define V_PCH_LPC_FVEC0_USB_10_PORT 0x00000800 +#define B_PCH_LPC_FVEC0_SATA_RAID_CAP 0x00000080 +#define B_PCH_LPC_FVEC0_SATA_PORT23_CAP 0x00000040 +#define B_PCH_LPC_FVEC0_SATA_PORT1_6GB_CAP 0x00000008 +#define B_PCH_LPC_FVEC0_SATA_PORT0_6GB_CAP 0x00000004 +#define B_PCH_LPC_FVEC0_PCI_CAP 0x00000002 +#define R_PCH_LPC_FVEC1 0x01 +#define B_PCH_LPC_FVEC1_USB_R_CAP 0x00400000 +#define R_PCH_LPC_FVEC2 0x02 +#define V_PCH_LPC_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_PCH_LPC_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Integrated Graphics Support Capability +#define R_PCH_LPC_FVEC3 0x03 +#define B_PCH_LPC_FVEC3_DCMI_CAP 0x00002000 ///< Data Center Manageability Interface (DCMI) Capability +#define B_PCH_LPC_FVEC3_NM_CAP 0x00001000 ///< Node Manager Capability + +#define R_PCH_LPC_MDAP 0xC0 +#define B_PCH_LPC_MDAP_POLICY_EN BIT31 +#define B_PCH_LPC_MDAP_PDMA_EN BIT30 +#define B_PCH_LPC_MDAP_VALUE 0x0001FFFF + +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +#define R_PCH_APM_STS 0xB3 + +#define R_PCH_LPC_BC 0xDC ///< Bios Control +#define S_PCH_LPC_BC 1 +#define B_PCH_LPC_BC_BILD BIT7 ///< BIOS Interface Lock-Down +#define B_PCH_LPC_BC_BBS BIT6 ///< Boot BIOS strap +#define N_PCH_LPC_BC_BBS 6 +#define V_PCH_LPC_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI +#define V_PCH_LPC_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC +#define B_PCH_LPC_BC_EISS BIT5 ///< Enable InSMM.STS +#define B_PCH_LPC_BC_TS BIT4 ///< Top Swap +#define B_PCH_LPC_BC_LE BIT1 ///< Lock Enable +#define N_PCH_LPC_BC_LE 1 +#define B_PCH_LPC_BC_WPD BIT0 ///< Write Protect Disable + +#define R_PCH_ESPI_PCBC 0xDC ///< Peripheral Channel BIOS Control +#define S_PCH_ESPI_PCBC 4 ///< Peripheral Channel BIOS Control register size +#define B_PCH_ESPI_PCBC_BWRE BIT11 ///< BIOS Write Report Enable +#define N_PCH_ESPI_PCBC_BWRE 11 ///< BIOS Write Report Enable bit position +#define B_PCH_ESPI_PCBC_BWRS BIT10 ///< BIOS Write Report Status +#define N_PCH_ESPI_PCBC_BWRS 10 ///< BIOS Write Report Status bit position +#define B_PCH_ESPI_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status +#define N_PCH_ESPI_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position +#define B_PCH_ESPI_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap +#define B_PCH_ESPI_PCBC_LE BIT1 ///< Lock Enable + +// +// Processor interface registers +// +#define R_PCH_NMI_SC 0x61 +#define B_PCH_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_NMI_EN 0x70 +#define B_PCH_NMI_EN_NMI_EN BIT7 + +// +// PCH I/O Port Defines +// +#define R_PCH_IOPORT_PCI_INDEX 0xCF8 +#define R_PCH_IOPORT_PCI_DATA 0xCFC +#define PCI_CF8_ADDR(Bus, Dev, Func, Off) \ + (((Off) & 0xFF) | (((Func) & 0x07) << 8) | (((Dev) & 0x1F) << 11) | (((Bus) & 0xFF) << 16) | (1 << 31)) + +#define PCH_LPC_CF8_ADDR(Offset) PCI_CF8_ADDR(DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, Offset) +// +// Reset Generator I/O Port +// +#define R_PCH_RST_CNT 0xCF9 +#define B_PCH_RST_CNT_FULL_RST BIT3 +#define B_PCH_RST_CNT_RST_CPU BIT2 +#define B_PCH_RST_CNT_SYS_RST BIT1 +#define V_PCH_RST_CNT_FULLRESET 0x0E +#define V_PCH_RST_CNT_HARDRESET 0x06 +#define V_PCH_RST_CNT_SOFTRESET 0x04 +#define V_PCH_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// RTC register +// +#define R_PCH_RTC_INDEX 0x70 +#define R_PCH_RTC_TARGET 0x71 +#define R_PCH_RTC_EXT_INDEX 0x72 +#define R_PCH_RTC_EXT_TARGET 0x73 +#define R_PCH_RTC_INDEX_ALT 0x74 +#define R_PCH_RTC_TARGET_ALT 0x75 +#define R_PCH_RTC_EXT_INDEX_ALT 0x76 +#define R_PCH_RTC_EXT_TARGET_ALT 0x77 +#define R_PCH_RTC_REGA 0x0A +#define B_PCH_RTC_REGA_UIP 0x80 +#define R_PCH_RTC_REGB 0x0B +#define B_PCH_RTC_REGB_SET 0x80 +#define B_PCH_RTC_REGB_PIE 0x40 +#define B_PCH_RTC_REGB_AIE 0x20 +#define B_PCH_RTC_REGB_UIE 0x10 +#define B_PCH_RTC_REGB_DM 0x04 +#define B_PCH_RTC_REGB_HOURFORM 0x02 +#define R_PCH_RTC_REGC 0x0C +#define R_PCH_RTC_REGD 0x0D + +// +// Private Configuration Register +// RTC PCRs (PID:RTC) +// +#define R_PCH_PCR_RTC_CONF 0x3400 ///< RTC Configuration register +#define S_PCH_PCR_RTC_CONF 4 +#define B_PCH_PCR_RTC_CONF_UCMOS_LOCK BIT4 +#define B_PCH_PCR_RTC_CONF_LCMOS_LOCK BIT3 +#define B_PCH_PCR_RTC_CONF_RESERVED BIT31 +#define B_PCH_PCR_RTC_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable +#define R_PCH_PCR_RTC_BUC 0x3414 ///< Backed Up Control +#define B_PCH_PCR_RTC_BUC_TS BIT0 ///< Top Swap +#define R_PCH_PCR_RTC_RTCDCG 0x3418 ///< RTC Dynamic Clock Gating Control +#define R_PCH_PCR_RTC_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ipciclk_clk (24 MHz) Dynamic Clock Gate Enable +#define R_PCH_PCR_RTC_RTCDCG_RTCROSIDEDCGEN BIT0 ///< rosc_side_clk (120 MHz) Dynamic Clock Gate Enable +#define R_PCH_PCR_RTC_3F00 0x3F00 +#define R_PCH_PCR_RTC_UIPSMI 0x3F04 ///< RTC Update In Progress SMI Control + +// +// LPC PCR Registers +// +#define R_PCH_PCR_LPC_HVMTCTL 0x3410 +#define R_PCH_PCR_LPC_GCFD 0x3418 +#define R_PCH_PCR_LPC_PCT 0x3420 +#define R_PCH_PCR_LPC_SCT 0x3424 +#define R_PCH_PCR_LPC_LPCCT 0x3428 +#define R_PCH_PCR_LPC_ULTOR 0x3500 + +// +// eSPI PCR Registers +// +#define R_PCH_PCR_ESPI_SLV_CFG_REG_CTL 0x4000 ///< Slave Configuration Register and Link Control +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRE BIT31 ///< Slave Configuration Register Access Enable +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Slave Configuration Register Access Status +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS 28 ///< Slave Configuration Register Access Status bit position +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully) +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Slave ID +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SID 19 ///< Slave ID bit position +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Slave Configuration Register Access Type +#define N_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT 16 ///< Slave Configuration Register Access Type bit position +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RD 0 ///< Slave Configuration register read from address SCRA[11:0] +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_WR 1 ///< Slave Configuration register write to address SCRA[11:0] +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_STS 2 ///< Slave Status register read +#define V_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRT_RS 3 ///< In-Band reset +#define B_PCH_PCR_ESPI_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Slave Configuration Register Address +#define R_PCH_PCR_ESPI_SLV_CFG_REG_DATA 0x4004 ///< Slave Configuration Register Data + +#define R_PCH_PCR_ESPI_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Slave 0 +#define R_PCH_PCR_ESPI_PCERR_SLV1 0x4024 ///< Peripheral Channel Error for Slave 1 +#define R_PCH_PCR_ESPI_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Slave 0 +#define R_PCH_PCR_ESPI_VWERR_SLV1 0x4034 ///< Virtual Wire Channel Error for Slave 1 +#define R_PCH_PCR_ESPI_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Slave 0 +#define B_PCH_PCR_ESPI_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits +#define N_PCH_PCR_ESPI_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position +#define V_PCH_PCR_ESPI_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI +#define B_PCH_PCR_ESPI_XERR_XNFES BIT12 ///< Fatal Error Status +#define B_PCH_PCR_ESPI_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits +#define N_PCH_PCR_ESPI_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position +#define V_PCH_PCR_ESPI_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI +#define B_PCH_PCR_ESPI_XERR_XFES BIT4 ///< Fatal Error Status +#define B_PCH_PCR_ESPI_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected +#define R_PCH_PCR_ESPI_LNKERR_SLV0 0x4050 ///< Link Error for Slave 0 +#define S_PCH_PCR_ESPI_LNKERR_SLV0 4 ///< Link Error for Slave 0 register size +#define B_PCH_PCR_ESPI_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Slave Channel Recovery Required +#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable +#define N_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position +#define V_PCH_PCR_ESPI_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI +#define B_PCH_PCR_ESPI_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status + + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsP2sb.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsP2sb.h new file mode 100644 index 0000000000..205d3ad282 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsP2sb.h @@ -0,0 +1,106 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_P2SB_H_ +#define _PCH_REGS_P2SB_H_ + +// +// PCI to P2SB Bridge Registers (D31:F1) +// +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + +#define V_PCH_P2SB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_PCH_P2SB_SBREG_BAR 0x10 +#define B_PCH_P2SB_SBREG_RBA 0xFF000000 +#define R_PCH_P2SB_SBREG_BARH 0x14 +#define B_PCH_P2SB_SBREG_RBAH 0xFFFFFFFF +#define R_PCH_P2SB_VBDF 0x50 +#define B_PCH_P2SB_VBDF_BUF 0xFF00 +#define B_PCH_P2SB_VBDF_DEV 0x00F8 +#define B_PCH_P2SB_VBDF_FUNC 0x0007 +#define R_PCH_P2SB_ESMBDF 0x52 +#define B_PCH_P2SB_ESMBDF_BUF 0xFF00 +#define B_PCH_P2SB_ESMBDF_DEV 0x00F8 +#define B_PCH_P2SB_ESMBDF_FUNC 0x0007 +#define R_PCH_P2SB_RCFG 0x54 +#define B_PCH_P2SB_RCFG_RPRID 0x0000FF00 +#define B_PCH_P2SB_RCFG_RSE BIT0 +#define R_PCH_P2SB_HPTC 0x60 +#define B_PCH_P2SB_HPTC_AE BIT7 +#define B_PCH_P2SB_HPTC_AS 0x0003 +#define N_PCH_HPET_ADDR_ASEL 12 +#define V_PCH_HPET_BASE0 0xFED00000 +#define V_PCH_HPET_BASE1 0xFED01000 +#define V_PCH_HPET_BASE2 0xFED02000 +#define V_PCH_HPET_BASE3 0xFED03000 +#define R_PCH_P2SB_IOAC 0x64 +#define B_PCH_P2SB_IOAC_AE BIT8 +#define B_PCH_P2SB_IOAC_ASEL 0x00FF +#define N_PCH_IO_APIC_ASEL 12 +#define R_PCH_IO_APIC_INDEX 0xFEC00000 +#define R_PCH_IO_APIC_DATA 0xFEC00010 +#define R_PCH_IO_APIC_EOI 0xFEC00040 +#define R_PCH_P2SB_IBDF 0x6C +#define B_PCH_P2SB_IBDF_BUF 0xFF00 +#define B_PCH_P2SB_IBDF_DEV 0x00F8 +#define B_PCH_P2SB_IBDF_FUNC 0x0007 +#define R_PCH_P2SB_HBDF 0x70 +#define B_PCH_P2SB_HBDF_BUF 0xFF00 +#define B_PCH_P2SB_HBDF_DEV 0x00F8 +#define B_PCH_P2SB_HBDF_FUNC 0x0007 +#define R_PCH_P2SB_80 0x80 +#define R_PCH_P2SB_84 0x84 +#define R_PCH_P2SB_88 0x88 +#define R_PCH_P2SB_8C 0x8C +#define R_PCH_P2SB_90 0x90 +#define R_PCH_P2SB_94 0x94 +#define R_PCH_P2SB_98 0x98 +#define R_PCH_P2SB_9C 0x9C +#define R_PCH_P2SB_DISPBDF 0xA0 +#define B_PCH_P2SB_DISPBDF_DTBLK 0x00070000 +#define B_PCH_P2SB_DISPBDF_BUF 0x0000FF00 +#define B_PCH_P2SB_DISPBDF_DEV 0x000000F8 +#define B_PCH_P2SB_DISPBDF_FUNC 0x00000007 +#define R_PCH_P2SB_ICCOS 0xA4 +#define B_PCH_P2SB_ICCOS_MODBASE 0xFF00 +#define B_PCH_P2SB_ICCOS_BUFBASE 0x00FF + +// +// Definition for SBI +// +#define R_PCH_P2SB_SBIADDR 0xD0 +#define B_PCH_P2SB_SBIADDR_DESTID 0xFF000000 +#define B_PCH_P2SB_SBIADDR_RS 0x000F0000 +#define B_PCH_P2SB_SBIADDR_OFFSET 0x0000FFFF +#define R_PCH_P2SB_SBIDATA 0xD4 +#define B_PCH_P2SB_SBIDATA_DATA 0xFFFFFFFF +#define R_PCH_P2SB_SBISTAT 0xD8 +#define B_PCH_P2SB_SBISTAT_OPCODE 0xFF00 +#define B_PCH_P2SB_SBISTAT_POSTED BIT7 +#define B_PCH_P2SB_SBISTAT_RESPONSE 0x0006 +#define N_PCH_P2SB_SBISTAT_RESPONSE 1 +#define B_PCH_P2SB_SBISTAT_INITRDY BIT0 +#define R_PCH_P2SB_SBIRID 0xDA +#define B_PCH_P2SB_SBIRID_FBE 0xF000 +#define B_PCH_P2SB_SBIRID_BAR 0x0700 +#define B_PCH_P2SB_SBIRID_FID 0x00FF +#define R_PCH_P2SB_SBIEXTADDR 0xDC +#define B_PCH_P2SB_SBIEXTADDR_ADDR 0xFFFFFFFF + +// +// Others +// +#define R_PCH_P2SB_E0 0xE0 +#define R_PCH_P2SB_F4 0xF4 +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPcie.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPcie.h new file mode 100644 index 0000000000..df40a8b703 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPcie.h @@ -0,0 +1,519 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +// +// PCH PCI Express Root Ports (D28:F0~7 & D29:F0~3) +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3 + +#define V_PCH_PCIE_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define V_PCH_H_PCIE_DEVICE_ID_PORT1 0xA110 ///< PCI Express Root Port #1, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT2 0xA111 ///< PCI Express Root Port #2, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT3 0xA112 ///< PCI Express Root Port #3, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT4 0xA113 ///< PCI Express Root Port #4, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT5 0xA114 ///< PCI Express Root Port #5, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT6 0xA115 ///< PCI Express Root Port #6, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT7 0xA116 ///< PCI Express Root Port #7, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT8 0xA117 ///< PCI Express Root Port #8, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT9 0xA118 ///< PCI Express Root Port #9, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT10 0xA119 ///< PCI Express Root Port #10, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT11 0xA11A ///< PCI Express Root Port #11, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT12 0xA11B ///< PCI Express Root Port #12, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT13 0xA11C ///< PCI Express Root Port #13, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT14 0xA11D ///< PCI Express Root Port #14, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT15 0xA11E ///< PCI Express Root Port #15, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT16 0xA11F ///< PCI Express Root Port #16, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT17 0xA167 ///< PCI Express Root Port #17, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT18 0xA168 ///< PCI Express Root Port #18, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT19 0xA169 ///< PCI Express Root Port #19, SKL PCH H +#define V_PCH_H_PCIE_DEVICE_ID_PORT20 0xA16A ///< PCI Express Root Port #20, SKL PCH H + +#define V_PCH_LP_PCIE_DEVICE_ID_PORT1 0x9D10 ///< PCI Express Root Port #1, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT2 0x9D11 ///< PCI Express Root Port #2, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT3 0x9D12 ///< PCI Express Root Port #3, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT4 0x9D13 ///< PCI Express Root Port #4, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT5 0x9D14 ///< PCI Express Root Port #5, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT6 0x9D15 ///< PCI Express Root Port #6, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT7 0x9D16 ///< PCI Express Root Port #7, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT8 0x9D17 ///< PCI Express Root Port #8, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT9 0x9D18 ///< PCI Express Root Port #9, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT10 0x9D19 ///< PCI Express Root Port #10, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT11 0x9D1A ///< PCI Express Root Port #11, SKL PCH LP PCIe Device ID +#define V_PCH_LP_PCIE_DEVICE_ID_PORT12 0x9D1B ///< PCI Express Root Port #12, SKL PCH LP PCIe Device ID + +// +// LBG Production (PRQ) PCI Express Root Ports Device ID's +// +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT1 0xA190 ///< PCI Express Root Port #1, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT2 0xA191 ///< PCI Express Root Port #2, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT3 0xA192 ///< PCI Express Root Port #3, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT4 0xA193 ///< PCI Express Root Port #4, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT5 0xA194 ///< PCI Express Root Port #5, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT6 0xA195 ///< PCI Express Root Port #6, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT7 0xA196 ///< PCI Express Root Port #7, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT8 0xA197 ///< PCI Express Root Port #8, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT9 0xA198 ///< PCI Express Root Port #9, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT10 0xA199 ///< PCI Express Root Port #10, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT11 0xA19A ///< PCI Express Root Port #11, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT12 0xA19B ///< PCI Express Root Port #12, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT13 0xA19C ///< PCI Express Root Port #13, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT14 0xA19D ///< PCI Express Root Port #14, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT15 0xA19E ///< PCI Express Root Port #15, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT16 0xA19F ///< PCI Express Root Port #16, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT17 0xA1E7 ///< PCI Express Root Port #17, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT18 0xA1E8 ///< PCI Express Root Port #18, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT19 0xA1E9 ///< PCI Express Root Port #19, LBG PRQ +#define V_PCH_LBG_PROD_PCIE_DEVICE_ID_PORT20 0xA1EA ///< PCI Express Root Port #20, LBG PRQ +// +// LBG Super SKU (SSX) PCI Express Root Ports Device ID's +// +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT1 0xA210 ///< PCI Express Root Port #1, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT2 0xA211 ///< PCI Express Root Port #2, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT3 0xA212 ///< PCI Express Root Port #3, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT4 0xA213 ///< PCI Express Root Port #4, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT5 0xA214 ///< PCI Express Root Port #5, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT6 0xA215 ///< PCI Express Root Port #6, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT7 0xA216 ///< PCI Express Root Port #7, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT8 0xA217 ///< PCI Express Root Port #8, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT9 0xA218 ///< PCI Express Root Port #9, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT10 0xA219 ///< PCI Express Root Port #10, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT11 0xA21A ///< PCI Express Root Port #11, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT12 0xA21B ///< PCI Express Root Port #12, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT13 0xA21C ///< PCI Express Root Port #13, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT14 0xA21D ///< PCI Express Root Port #14, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT15 0xA21E ///< PCI Express Root Port #15, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT16 0xA21F ///< PCI Express Root Port #16, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT17 0xA267 ///< PCI Express Root Port #17, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT18 0xA268 ///< PCI Express Root Port #18, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT19 0xA269 ///< PCI Express Root Port #19, LBG SSKU +#define V_PCH_LBG_PCIE_DEVICE_ID_PORT20 0xA26A ///< PCI Express Root Port #20, LBG SSKU + +#define R_PCH_PCIE_CLIST 0x40 +#define R_PCH_PCIE_XCAP (R_PCH_PCIE_CLIST + R_PCIE_XCAP_OFFSET) +#define R_PCH_PCIE_DCAP (R_PCH_PCIE_CLIST + R_PCIE_DCAP_OFFSET) +#define R_PCH_PCIE_DCTL (R_PCH_PCIE_CLIST + R_PCIE_DCTL_OFFSET) +#define R_PCH_PCIE_DSTS (R_PCH_PCIE_CLIST + R_PCIE_DSTS_OFFSET) +#define R_PCH_PCIE_LCAP (R_PCH_PCIE_CLIST + R_PCIE_LCAP_OFFSET) +#define B_PCH_PCIE_LCAP_PN 0xFF000000 +#define N_PCH_PCIE_LCAP_PN 24 +#define R_PCH_PCIE_LCTL (R_PCH_PCIE_CLIST + R_PCIE_LCTL_OFFSET) +#define R_PCH_PCIE_LSTS (R_PCH_PCIE_CLIST + R_PCIE_LSTS_OFFSET) +#define R_PCH_PCIE_SLCAP (R_PCH_PCIE_CLIST + R_PCIE_SLCAP_OFFSET) +#define R_PCH_PCIE_SLCTL (R_PCH_PCIE_CLIST + R_PCIE_SLCTL_OFFSET) +#define R_PCH_PCIE_SLSTS (R_PCH_PCIE_CLIST + R_PCIE_SLSTS_OFFSET) +#define R_PCH_PCIE_RCTL (R_PCH_PCIE_CLIST + R_PCIE_RCTL_OFFSET) +#define R_PCH_PCIE_RSTS (R_PCH_PCIE_CLIST + R_PCIE_RSTS_OFFSET) +#define R_PCH_PCIE_DCAP2 (R_PCH_PCIE_CLIST + R_PCIE_DCAP2_OFFSET) +#define R_PCH_PCIE_DCTL2 (R_PCH_PCIE_CLIST + R_PCIE_DCTL2_OFFSET) +#define R_PCH_PCIE_LCTL2 (R_PCH_PCIE_CLIST + R_PCIE_LCTL2_OFFSET) +#define R_PCH_PCIE_LSTS2 (R_PCH_PCIE_CLIST + R_PCIE_LSTS2_OFFSET) + + +#define R_PCH_PCIE_MID 0x80 +#define S_PCH_PCIE_MID 2 +#define R_PCH_PCIE_MC 0x82 +#define S_PCH_PCIE_MC 2 +#define R_PCH_PCIE_MA 0x84 +#define S_PCH_PCIE_MA 4 +#define R_PCH_PCIE_MD 0x88 +#define S_PCH_PCIE_MD 2 + +#define R_PCH_PCIE_SVCAP 0x90 +#define S_PCH_PCIE_SVCAP 2 +#define R_PCH_PCIE_SVID 0x94 +#define S_PCH_PCIE_SVID 4 + +#define R_PCH_PCIE_PMCAP 0xA0 +#define R_PCH_PCIE_PMCS (R_PCH_PCIE_PMCAP + R_PCIE_PMCS_OFFST) +#define R_PCH_PCIE_MPC2 0xD4 +#define S_PCH_PCIE_MPC2 4 +#define B_PCH_PCIE_MPC2_PTNFAE BIT12 +#define B_PCH_PCIE_MPC2_LSTP BIT6 +#define B_PCH_PCIE_MPC2_IEIME BIT5 +#define B_PCH_PCIE_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_MPC2_ASPMCO_L0S (1 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L1 (2 << 2) +#define V_PCH_PCIE_MPC2_ASPMCO_L0S_L1 (3 << 2) +#define B_PCH_PCIE_MPC2_EOIFD BIT1 + +#define R_PCH_PCIE_MPC 0xD8 +#define S_PCH_PCIE_MPC 4 +#define B_PCH_PCIE_MPC_PMCE BIT31 +#define B_PCH_PCIE_MPC_HPCE BIT30 +#define B_PCH_PCIE_MPC_MMBNCE BIT27 +#define B_PCH_PCIE_MPC_P8XDE BIT26 +#define B_PCH_PCIE_MPC_IRRCE BIT25 +#define B_PCH_PCIE_MPC_SRL BIT23 +#define B_PCH_PCIE_MPC_UCEL (BIT20 | BIT19 | BIT18) +#define N_PCH_PCIE_MPC_UCEL 18 +#define B_PCH_PCIE_MPC_CCEL (BIT17 | BIT16 | BIT15) +#define N_PCH_PCIE_MPC_CCEL 15 +#define B_PCH_PCIE_MPC_PCIESD (BIT14 | BIT13) +#define N_PCH_PCIE_MPC_PCIESD 13 +#define V_PCH_PCIE_MPC_PCIESD_GEN1 1 +#define V_PCH_PCIE_MPC_PCIESD_GEN2 2 +#define B_PCH_PCIE_MPC_MCTPSE BIT3 +#define B_PCH_PCIE_MPC_HPME BIT1 +#define N_PCH_PCIE_MPC_HPME 1 +#define B_PCH_PCIE_MPC_PMME BIT0 + +#define R_PCH_PCIE_SMSCS 0xDC +#define S_PCH_PCIE_SMSCS 4 +#define N_PCH_PCIE_SMSCS_LERSMIS 5 +#define N_PCH_PCIE_SMSCS_HPLAS 4 +#define N_PCH_PCIE_SMSCS_HPPDM 1 + +#define R_PCH_PCIE_RPDCGEN 0xE1 +#define S_PCH_PCIE_RPDCGEN 1 +#define B_PCH_PCIE_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6 +#define B_PCH_PCIE_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_RPDCGEN_RPDBCGEN BIT0 + + +#define R_PCH_PCIE_PWRCTL 0xE8 +#define B_PCH_PCIE_PWRCTL_LTSSMRTC BIT20 +#define B_PCH_PCIE_PWRCTL_WPDMPGEP BIT17 +#define B_PCH_PCIE_PWRCTL_DBUPI BIT15 +#define B_PCH_PCIE_PWRCTL_TXSWING BIT13 +#define B_PCH_PCIE_PWRCTL_RPL1SQPOL BIT1 +#define B_PCH_PCIE_PWRCTL_RPDTSQPOL BIT0 + +#define R_PCH_PCIE_DC 0xEC +#define B_PCH_PCIE_DC_PCIBEM BIT2 + +#define R_PCH_PCIE_PHYCTL2 0xF5 +#define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6) +#define B_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4) +#define N_PCH_PCIE_PHYCTL2_TXCFGCHGWAIT 4 +#define B_PCH_PCIE_PHYCTL2_PXPG3PLLOFFEN BIT1 +#define B_PCH_PCIE_PHYCTL2_PXPG2PLLOFFEN BIT0 + +#define R_PCH_PCIE_IOSFSBCS 0xF7 +#define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6 +#define B_PCH_PCIE_IOSFSBCS_SIID (BIT3 | BIT2) + +#define R_PCH_PCIE_STRPFUSECFG 0xFC +#define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24) +#define N_PCH_PCIE_STRPFUSECFG_PXIP 24 +#define B_PCH_PCIE_STRPFUSECFG_RPC (BIT15 | BIT14) +#define V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1 0 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1 1 +#define V_PCH_PCIE_STRPFUSECFG_RPC_2_2 2 +#define V_PCH_PCIE_STRPFUSECFG_RPC_4 3 +#define N_PCH_PCIE_STRPFUSECFG_RPC 14 +#define B_PCH_PCIE_STRPFUSECFG_MODPHYIOPMDIS BIT9 +#define B_PCH_PCIE_STRPFUSECFG_PLLSHTDWNDIS BIT8 +#define B_PCH_PCIE_STRPFUSECFG_STPGATEDIS BIT7 +#define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6 +#define B_PCH_PCIE_STRPFUSECFG_LDCGDIS BIT5 +#define B_PCH_PCIE_STRPFUSECFG_LTCGDIS BIT4 +#define B_PCH_PCIE_STRPFUSECFG_CDCGDIS BIT3 +#define B_PCH_PCIE_STRPFUSECFG_DESKTOPMOB BIT2 + +// +//PCI Express Extended Capability Registers +// + +#define R_PCH_PCIE_EXCAP_OFFSET 0x100 + +#define R_PCH_PCIE_EX_AECH 0x100 ///< Advanced Error Reporting Capability Header +#define V_PCH_PCIE_EX_AEC_CV 0x1 +#define R_PCH_PCIE_EX_UEM (R_PCH_PCIE_EX_AECH + R_PCIE_EX_UEM_OFFSET) + +#define R_PCH_PCIE_EX_CES 0x110 ///< Correctable Error Status +#define B_PCH_PCIE_EX_CES_BD BIT7 ///< Bad DLLP Status +#define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status +#define B_PCH_PCIE_EX_CES_RE BIT0 ///< Receiver Error Status + + +//CES.RE, CES.BT, CES.BD + +#define R_PCH_PCIE_EX_ACSECH 0x140 ///< ACS Extended Capability Header +#define V_PCH_PCIE_EX_ACS_CV 0x1 +#define R_PCH_PCIE_EX_ACSCAPR (R_PCH_PCIE_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET) + +#define R_PCH_PCIE_EX_L1SECH 0x200 ///< L1 Sub-States Extended Capability Header +#define V_PCH_PCIE_EX_L1S_CV 0x1 +#define R_PCH_PCIE_EX_L1SCAP (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCAP_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL1 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL1_OFFSET) +#define R_PCH_PCIE_EX_L1SCTL2 (R_PCH_PCIE_EX_L1SECH + R_PCIE_EX_L1SCTL2_OFFSET) + +#define R_PCH_PCIE_EX_SPEECH 0x220 ///< Secondary PCI Express Extended Capability Header +#define V_PCH_PCIE_EX_SPEECH_CV 0x1 + +#define R_PCH_PCIE_EX_LCTL3 (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LCTL3_OFFSET) +#define R_PCH_PCIE_EX_LES (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_LES_OFFSET) +#define R_PCH_PCIE_EX_LECTL (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET) +#define B_PCH_PCIE_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT12) +#define N_PCH_PCIE_EX_LECTL_UPTPH 12 +#define B_PCH_PCIE_EX_LECTL_UPTP 0x0F00 +#define N_PCH_PCIE_EX_LECTL_UPTP 8 +#define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_EX_LECTL_DPTPH 4 +#define B_PCH_PCIE_EX_LECTL_DPTP 0x000F +#define N_PCH_PCIE_EX_LECTL_DPTP 0 + +#define R_PCH_PCIE_EX_L01EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L01EC_OFFSET) +#define R_PCH_PCIE_EX_L23EC (R_PCH_PCIE_EX_SPEECH + R_PCIE_EX_L23EC_OFFSET) + +#define R_PCH_PCIE_PCIERTP1 0x300 +#define R_PCH_PCIE_PCIERTP2 0x304 +#define R_PCH_PCIE_PCIENFTS 0x314 +#define R_PCH_PCIE_PCIEL0SC 0x318 + +#define R_PCH_PCIE_PCIECFG2 0x320 +#define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30 +#define B_PCH_PCIE_PCIECFG2_RLLG3R BIT27 +#define B_PCH_PCIE_PCIECFG2_CROAOV BIT24 +#define B_PCH_PCIE_PCIECFG2_CROAOE BIT23 +#define B_PCH_PCIE_PCIECFG2_CRSREN BIT22 +#define B_PCH_PCIE_PCIECFG2_PMET (BIT21 | BIT20) +#define V_PCH_PCIE_PCIECFG2_PMET 1 +#define N_PCH_PCIE_PCIECFG2_PMET 20 + +#define R_PCH_PCIE_PCIEDBG 0x324 +#define B_PCH_PCIE_PCIEDBG_USSP (BIT27 | BIT26) +#define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) +#define B_PCH_PCIE_PCIEDBG_CTONFAE BIT14 +#define B_PCH_PCIE_PCIEDBG_SQOL0 BIT7 +#define B_PCH_PCIE_PCIEDBG_SPCE BIT5 +#define B_PCH_PCIE_PCIEDBG_LR BIT4 + +#define R_PCH_PCIE_PCIESTS1 0x328 +#define B_PCH_PCIE_PCIESTS1_LTSMSTATE 0xFF000000 +#define N_PCH_PCIE_PCIESTS1_LTSMSTATE 24 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDY 0x01 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_L0 0x33 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAIT 0x5E +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_DISWAITPG 0x60 +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C +#define V_PCH_PCIE_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F + + +#define B_PCH_PCIE_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19) +#define N_PCH_PCIE_PCIESTS1_LNKSTAT 19 +#define V_PCH_PCIE_PCIESTS1_LNKSTAT_L0 0x7 + +#define R_PCH_PCIE_PCIESTS2 0x32C +#define B_PCH_PCIE_PCIESTS2_P4PNCCWSSCMES BIT31 +#define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30 +#define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29 +#define B_PCH_PCIE_PCIESTS2_P1PNCCWSSCMES BIT28 +#define B_PCH_PCIE_PCIESTS2_CLRE 0x0000F000 +#define N_PCH_PCIE_PCIESTS2_CLRE 12 + +#define R_PCH_PCIE_PCIEALC 0x338 +#define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29 +#define B_PCH_PCIE_PCIEALC_ILLRCLD BIT28 +#define B_PCH_PCIE_PCIEALC_BLKDQDA BIT26 +#define R_PCH_PCIE_PHYCTL4 0x408 +#define B_PCH_PCIE_PHYCTL4_SQDIS BIT27 + +#define R_PCH_PCIE_PCIEPMECTL2 0x424 +#define B_PCH_PCIE_PCIEPMECTL2_PHYCLPGE BIT11 +#define B_PCH_PCIE_PCIEPMECTL2_FDCPGE BIT8 +#define B_PCH_PCIE_PCIEPMECTL2_DETSCPGE BIT7 +#define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6 +#define B_PCH_PCIE_PCIEPMECTL2_DISSCPGE BIT5 +#define B_PCH_PCIE_PCIEPMECTL2_L1SCPGE BIT4 + +#define R_PCH_PCIE_PCE 0x428 +#define B_PCH_PCIE_PCE_HAE BIT5 +#define B_PCH_PCIE_PCE_PMCRE BIT0 + +#define R_PCH_PCIE_EQCFG1 0x450 +#define S_PCH_PCIE_EQCFG1 4 +#define B_PCH_PCIE_EQCFG1_REC 0xFF000000 +#define N_PCH_PCIE_EQCFG1_REC 24 +#define B_PCH_PCIE_EQCFG1_REIFECE BIT23 +#define N_PCH_PCIE_EQCFG1_LERSMIE 21 +#define B_PCH_PCIE_EQCFG1_LEP23B BIT18 +#define B_PCH_PCIE_EQCFG1_LEP3B BIT17 +#define B_PCH_PCIE_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCIE_EQCFG1_RTPCOE BIT15 +#define B_PCH_PCIE_EQCFG1_HPCMQE BIT13 +#define B_PCH_PCIE_EQCFG1_HAED BIT12 +#define B_PCH_PCIE_EQCFG1_EQTS2IRRC BIT7 +#define B_PCH_PCIE_EQCFG1_TUPP BIT1 + +#define R_PCH_PCIE_RTPCL1 0x454 +#define B_PCH_PCIE_RTPCL1_PCM BIT31 +#define B_PCH_PCIE_RTPCL1_RTPRECL2PL4 0x3F000000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL1PL3 0xFC0000 +#define B_PCH_PCIE_RTPCL1_RTPRECL1PL2 0x3F000 +#define B_PCH_PCIE_RTPCL1_RTPOSTCL0PL1 0xFC0 +#define B_PCH_PCIE_RTPCL1_RTPRECL0PL0 0x3F + +#define R_PCH_PCIE_RTPCL2 0x458 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL3PL 0x3F000 +#define B_PCH_PCIE_RTPCL2_RTPRECL3PL6 0xFC0 +#define B_PCH_PCIE_RTPCL2_RTPOSTCL2PL5 0x3F + +#define R_PCH_PCIE_RTPCL3 0x45C +#define B_PCH_PCIE_RTPCL3_RTPRECL7 0x3F000000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL6 0xFC0000 +#define B_PCH_PCIE_RTPCL3_RTPRECL6 0x3F000 +#define B_PCH_PCIE_RTPCL3_RTPOSTCL5 0xFC0 +#define B_PCH_PCIE_RTPCL3_RTPRECL5PL10 0x3F + +#define R_PCH_PCIE_RTPCL4 0x460 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL9 0x3F000000 +#define B_PCH_PCIE_RTPCL4_RTPRECL9 0xFC0000 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL8 0x3F000 +#define B_PCH_PCIE_RTPCL4_RTPRECL8 0xFC0 +#define B_PCH_PCIE_RTPCL4_RTPOSTCL7 0x3F + +#define R_PCH_PCIE_FOMS 0x464 +#define B_PCH_PCIE_FOMS_I (BIT30 | BIT29) +#define N_PCH_PCIE_FOMS_I 29 +#define B_PCH_PCIE_FOMS_LN 0x1F000000 +#define N_PCH_PCIE_FOMS_LN 24 +#define B_PCH_PCIE_FOMS_FOMSV 0x00FFFFFF +#define B_PCH_PCIE_FOMS_FOMSV0 0x000000FF +#define N_PCH_PCIE_FOMS_FOMSV0 0 +#define B_PCH_PCIE_FOMS_FOMSV1 0x0000FF00 +#define N_PCH_PCIE_FOMS_FOMSV1 8 +#define B_PCH_PCIE_FOMS_FOMSV2 0x00FF0000 +#define N_PCH_PCIE_FOMS_FOMSV2 16 + +#define R_PCH_PCIE_HAEQ 0x468 +#define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28) +#define N_PCH_PCIE_HAEQ_HAPCCPI 28 +#define B_PCH_PCIE_HAEQ_MACFOMC BIT19 + +#define R_PCH_PCIE_LTCO1 0x470 +#define B_PCH_PCIE_LTCO1_L1TCOE BIT25 +#define B_PCH_PCIE_LTCO1_L0TCOE BIT24 +#define B_PCH_PCIE_LTCO1_L1TPOSTCO 0xFC0000 +#define N_PCH_PCIE_LTCO1_L1TPOSTCO 18 +#define B_PCH_PCIE_LTCO1_L1TPRECO 0x3F000 +#define N_PCH_PCIE_LTCO1_L1TPRECO 12 +#define B_PCH_PCIE_LTCO1_L0TPOSTCO 0xFC0 +#define N_PCH_PCIE_LTCO1_L0TPOSTCO 6 +#define B_PCH_PCIE_LTCO1_L0TPRECO 0x3F +#define N_PCH_PCIE_LTCO1_L0TPRECO 0 + +#define R_PCH_PCIE_LTCO2 0x474 +#define B_PCH_PCIE_LTCO2_L3TCOE BIT25 +#define B_PCH_PCIE_LTCO2_L2TCOE BIT24 +#define B_PCH_PCIE_LTCO2_L3TPOSTCO 0xFC0000 +#define B_PCH_PCIE_LTCO2_L3TPRECO 0x3F000 +#define B_PCH_PCIE_LTCO2_L2TPOSTCO 0xFC0 +#define B_PCH_PCIE_LTCO2_L2TPRECO 0x3F + +#define R_PCH_PCIE_G3L0SCTL 0x478 +#define B_PCH_PCIE_G3L0SCTL_G3UCNFTS 0x0000FF00 +#define B_PCH_PCIE_G3L0SCTL_G3CCNFTS 0x000000FF + +#define R_PCH_PCIE_EQCFG2 0x47C +#define B_PCH_PCIE_EQCFG2_NTIC 0xFF000000 +#define B_PCH_PCIE_EQCFG2_EMD BIT23 +#define B_PCH_PCIE_EQCFG2_NTSS (BIT22 | BIT21 | BIT20) +#define B_PCH_PCIE_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16) +#define N_PCH_PCIE_EQCFG2_PCET 16 +#define B_PCH_PCIE_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT13 | BIT12) +#define N_PCH_PCIE_EQCFG2_HAPCSB 12 +#define B_PCH_PCIE_EQCFG2_NTEME BIT11 +#define B_PCH_PCIE_EQCFG2_MPEME BIT10 +#define B_PCH_PCIE_EQCFG2_REWMETM (BIT9 | BIT8) +#define B_PCH_PCIE_EQCFG2_REWMET 0xFF + +#define R_PCH_PCIE_MM 0x480 +#define B_PCH_PCIE_MM_MSST 0xFFFFFF00 +#define N_PCH_PCIE_MM_MSST 8 +#define B_PCH_PCIE_MM_MSS 0xFF + +// +//PCI Express Extended End Point Capability Registers +// + +#define R_PCH_PCIE_LTRECH_OFFSET 0 +#define R_PCH_PCIE_LTRECH_CID 0x0018 +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04 +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06 + + +// +// PCIE PCRs (PID:SPA SPB SPC SPD SPE) +// +#define R_PCH_PCR_SPX_PCD 0 ///< Port configuration and disable +#define B_PCH_PCR_SPX_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number +#define B_PCH_PCR_SPX_PCD_RP1CH BIT3 ///< Port 1 config hide +#define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number +#define B_PCH_PCR_SPX_PCD_RP2CH BIT7 ///< Port 2 config hide +#define B_PCH_PCR_SPX_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///< Port 3 Function Number +#define B_PCH_PCR_SPX_PCD_RP3CH BIT11 ///< Port 3 config hide +#define B_PCH_PCR_SPX_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Number +#define B_PCH_PCR_SPX_PCD_RP4CH BIT15 ///< Port 4 config hide +#define S_PCH_PCR_SPX_PCD_RP_FIELD 4 ///< 4 bits for each RP FN +#define B_PCH_PCR_SPX_PCD_P1D BIT16 ///< Port 1 disable +#define B_PCH_PCR_SPX_PCD_P2D BIT17 ///< Port 2 disable +#define B_PCH_PCR_SPX_PCD_P3D BIT18 ///< Port 3 disable +#define B_PCH_PCR_SPX_PCD_P4D BIT19 ///< Port 4 disable +#define B_PCH_PCR_SPX_PCD_SRL BIT31 ///< Secured Register Lock + +#define R_PCH_PCR_SPX_PCIEHBP 0x0004 ///< PCI Express high-speed bypass +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPME BIT0 ///< PCIe HBP mode enable +#define B_PCH_PCR_SPX_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///< PCIe gen mode override +#define B_PCH_PCR_SPX_PCIEHBP_PCIETIL0O BIT3 ///< PCIe transmitter-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELRO BIT5 ///< PCIe link recovery override +#define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 ///< PCIe link down override +#define B_PCH_PCR_SPX_PCIEHBP_PCIESSM BIT7 ///< PCIe SKP suppression mode +#define B_PCH_PCR_SPX_PCIEHBP_PCIESST BIT8 ///< PCIe suppress SKP transmission +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///< PCIe HBP port select +#define B_PCH_PCR_SPX_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select +#define B_PCH_PCR_SPX_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///< PCIe HBP CRC + + +// +// ICC PCR (PID: ICC) +// +#define R_PCH_PCR_ICC_TMCSRCCLK 0x1000 ///< Timing Control SRC Clock Register +#define R_PCH_PCR_ICC_TMCSRCCLK2 0x1004 ///< Timing Control SRC Clock Register 2 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPcr.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPcr.h new file mode 100644 index 0000000000..3cd0c432b4 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPcr.h @@ -0,0 +1,70 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/// +/// Definition for PCR base address (defined in PchReservedResources.h) +/// +//#define PCH_PCR_BASE_ADDRESS 0xFD000000 +//#define PCH_PCR_MMIO_SIZE 0x01000000 +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming +**/ +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(Pid) << 16) | (UINT16)(Offset)) + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well. +**/ +typedef enum { + PID_DMI = 0xEF, + PID_ESPISPI = 0xEE, + PID_MODPHY1 = 0xE9, + PID_OTG = 0xE5, + PID_SPE = 0xE4, // Reserved in SKL PCH LP + PID_SPD = 0xE3, // Reserved in SKL PCH LP + PID_SPC = 0xE2, + PID_SPB = 0xE1, + PID_SPA = 0xE0, + PID_ICC = 0xDC, + PID_DSP = 0xD7, + PID_FIA = 0xCF, + PID_FIAWM26 = 0x13, + PID_USB2 = 0xCA, + PID_LPC = 0xC7, + PID_SMB = 0xC6, + PID_ITSS = 0xC4, + PID_RTC = 0xC3, + PID_PSF4 = 0xBD, + PID_PSF3 = 0xBC, + PID_PSF2 = 0xBB, + PID_PSF1 = 0xBA, + PID_DCI = 0xB8, + PID_MMP0 = 0xB0, + PID_GPIOCOM0 = 0xAF, + PID_GPIOCOM1 = 0xAE, + PID_GPIOCOM2 = 0xAD, + PID_GPIOCOM3 = 0xAC, + PID_GPIOCOM4 = 0xAB, + PID_GPIOCOM5 = 0x11, + PID_MODPHY2 = 0xA9, + PID_MODPHY3 = 0xA8, + PID_CSME0 = 0x90, // CSE + PID_CSME_PSF = 0x8F, // ME PSF + PID_PSTH = 0x89 +} PCH_SBI_PID; + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPmc.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPmc.h new file mode 100644 index 0000000000..fd67b1338d --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPmc.h @@ -0,0 +1,633 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_PMC_H_ +#define _PCH_REGS_PMC_H_ + +// +//PMC Registers (D31:F2) +// +#define PCI_DEVICE_NUMBER_PCH_PMC 31 +#define PCI_FUNCTION_NUMBER_PCH_PMC 2 + +#define V_PCH_PMC_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_PMC_DEVICE_ID 0x9D21 +// +// LBG Production (PRQ) PMC Device ID +// +#define V_PCH_LBG_PROD_PMC_DEVICE_ID 0xA1A1 +// +// LBG Super SKU (SSX) PMC Device ID +// +#define V_PCH_LBG_PMC_DEVICE_ID 0xA221 + +#define V_PCH_LP_PMC_DEVICE_ID 0x9D21 +#define R_PCH_PMC_PM_DATA_BAR 0x10 +#define B_PCH_PMC_PM_DATA_BAR 0xFFFFC000 +#define R_PCH_PMC_ACPI_BASE 0x40 +#define B_PCH_PMC_ACPI_BASE_BAR 0xFFFC +#define R_PCH_PMC_ACPI_CNT 0x44 +#define B_PCH_PMC_ACPI_CNT_PWRM_EN BIT8 ///< PWRM enable +#define B_PCH_PMC_ACPI_CNT_ACPI_EN BIT7 ///< ACPI eanble +#define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ9 0 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ10 1 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ11 2 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ20 4 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ21 5 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ22 6 +#define V_PCH_PMC_ACPI_CNT_SCIS_IRQ23 7 +#define R_PCH_PMC_PWRM_BASE 0x48 +#define B_PCH_PMC_PWRM_BASE_BAR 0xFFFF0000 ///< PWRM must be 64KB alignment to align the source decode. +#define R_PCH_PMC_GEN_PMCON_A 0xA0 +#define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30 +#define B_PCH_PMC_GEN_PMCON_A_DSX_PP_DIS BIT29 +#define B_PCH_PMC_GEN_PMCON_A_AG3_PP_EN BIT28 +#define B_PCH_PMC_GEN_PMCON_A_SX_PP_EN BIT27 +#define B_PCH_PMC_GEN_PMCON_A_DISB BIT23 +#define B_PCH_PMC_GEN_PMCON_A_MEM_SR BIT21 +#define B_PCH_PMC_GEN_PMCON_A_MS4V BIT18 +#define B_PCH_PMC_GEN_PMCON_A_GBL_RST_STS BIT16 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_PLL_SD_INC0 BIT13 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT12 +#define B_PCH_PMC_GEN_PMCON_A_BIOS_PCI_EXP_EN BIT10 +#define B_PCH_PMC_GEN_PMCON_A_PWRBTN_LVL BIT9 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT7 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT6 +#define B_PCH_PMC_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT5 +#define B_PCH_PMC_GEN_PMCON_A_SMI_LOCK BIT4 +#define B_PCH_PMC_GEN_PMCON_A_ESPI_SMI_LOCK BIT3 ///< ESPI SMI lock +#define B_PCH_PMC_GEN_PMCON_A_PER_SMI_SEL 0x0003 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_64S 0x0000 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_32S 0x0001 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_16S 0x0002 +#define V_PCH_PMC_GEN_PMCON_A_PER_SMI_8S 0x0003 +#define R_PCH_PMC_GEN_PMCON_B 0xA4 +#define B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width +#define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at 0x40, only cleared by reset when set +#define B_PCH_PMC_GEN_PMCON_B_PM_DATA_BAR_DIS BIT16 +#define B_PCH_PMC_GEN_PMCON_B_PME_B0_S5_DIS BIT15 +#define B_PCH_PMC_GEN_PMCON_B_SUS_PWR_FLR BIT14 +#define B_PCH_PMC_GEN_PMCON_B_WOL_EN_OVRD BIT13 +#define B_PCH_PMC_GEN_PMCON_B_DISABLE_SX_STRETCH BIT12 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW 0xC00 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_60US 0x000 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_1MS 0x400 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_50MS 0x800 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S3_MAW_2S 0xC00 +#define B_PCH_PMC_GEN_PMCON_B_HOST_RST_STS BIT9 +#define B_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_64MS 0xC0 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_32MS 0x80 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_16MS 0x40 +#define V_PCH_PMC_GEN_PMCON_B_SWSMI_RTSL_1_5MS 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_1S 0x30 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_2S 0x20 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_3S 0x10 +#define V_PCH_PMC_GEN_PMCON_B_SLP_S4_MAW_4S 0x00 +#define B_PCH_PMC_GEN_PMCON_B_SLP_S4_ASE BIT3 +#define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2 +#define B_PCH_PMC_GEN_PMCON_B_PWR_FLR BIT1 +#define B_PCH_PMC_GEN_PMCON_B_AFTERG3_EN BIT0 +#define R_PCH_PMC_BM_CX_CNF 0xA8 +#define B_PCH_PMC_BM_CX_CNF_STORAGE_BREAK_EN BIT31 +#define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30 +#define B_PCH_PMC_BM_CX_CNF_AZ_BREAK_EN BIT24 +#define B_PCH_PMC_BM_CX_CNF_DPSN_BREAK_EN BIT19 +#define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17 +#define B_PCH_PMC_BM_CX_CNF_SATA3_BREAK_EN BIT16 +#define B_PCH_PMC_BM_CX_CNF_SCRATCHPAD BIT15 +#define B_PCH_PMC_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14 +#define B_PCH_PMC_BM_CX_CNF_MASK_CF BIT11 +#define B_PCH_PMC_BM_CX_CNF_BM_STS_ZERO_EN BIT10 +#define B_PCH_PMC_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9 +#define R_PCH_PMC_ETR3 0xAC +#define B_PCH_PMC_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown +#define B_PCH_PMC_ETR3_USB_CACHE_DIS BIT21 +#define B_PCH_PMC_ETR3_CF9GR BIT20 ///< CF9h Global Reset +#define B_PCH_PMC_ETR3_SKIP_HOST_RST_HS BIT19 +#define B_PCH_PMC_ETR3_CWORWRE BIT18 + +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_PCH_ACPI_PM1_STS 0x00 +#define S_PCH_ACPI_PM1_STS 2 +#define B_PCH_ACPI_PM1_STS_WAK 0x8000 +#define B_PCH_ACPI_PM1_STS_PRBTNOR 0x0800 +#define B_PCH_ACPI_PM1_STS_RTC 0x0400 +#define B_PCH_ACPI_PM1_STS_PWRBTN 0x0100 +#define B_PCH_ACPI_PM1_STS_GBL 0x0020 +#define B_PCH_ACPI_PM1_STS_BM 0x0010 +#define B_PCH_ACPI_PM1_STS_TMROF 0x0001 +#define N_PCH_ACPI_PM1_STS_WAK 15 +#define N_PCH_ACPI_PM1_STS_PRBTNOR 11 +#define N_PCH_ACPI_PM1_STS_RTC 10 +#define N_PCH_ACPI_PM1_STS_PWRBTN 8 +#define N_PCH_ACPI_PM1_STS_GBL 5 +#define N_PCH_ACPI_PM1_STS_BM 4 +#define N_PCH_ACPI_PM1_STS_TMROF 0 + +#define R_PCH_ACPI_PM1_EN 0x02 +#define S_PCH_ACPI_PM1_EN 2 +#define B_PCH_ACPI_PM1_EN_RTC 0x0400 +#define B_PCH_ACPI_PM1_EN_PWRBTN 0x0100 +#define B_PCH_ACPI_PM1_EN_GBL 0x0020 +#define B_PCH_ACPI_PM1_EN_TMROF 0x0001 +#define N_PCH_ACPI_PM1_EN_RTC 10 +#define N_PCH_ACPI_PM1_EN_PWRBTN 8 +#define N_PCH_ACPI_PM1_EN_GBL 5 +#define N_PCH_ACPI_PM1_EN_TMROF 0 + +#define R_PCH_ACPI_PM1_CNT 0x04 +#define S_PCH_ACPI_PM1_CNT 4 +#define B_PCH_ACPI_PM1_CNT_SLP_EN 0x00002000 +#define B_PCH_ACPI_PM1_CNT_SLP_TYP 0x00001C00 +#define V_PCH_ACPI_PM1_CNT_S0 0x00000000 +#define V_PCH_ACPI_PM1_CNT_S1 0x00000400 +#define V_PCH_ACPI_PM1_CNT_S3 0x00001400 +#define V_PCH_ACPI_PM1_CNT_S4 0x00001800 +#define V_PCH_ACPI_PM1_CNT_S5 0x00001C00 +#define B_PCH_ACPI_PM1_CNT_GBL_RLS 0x00000004 +#define B_PCH_ACPI_PM1_CNT_BM_RLD 0x00000002 +#define B_PCH_ACPI_PM1_CNT_SCI_EN 0x00000001 + +#define R_PCH_ACPI_PM1_TMR 0x08 +#define V_PCH_ACPI_TMR_FREQUENCY 3579545 +#define B_PCH_ACPI_PM1_TMR_VAL 0xFFFFFF +#define V_PCH_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow + +#define R_PCH_SMI_EN 0x30 +#define S_PCH_SMI_EN 4 +#define B_PCH_SMI_EN_LEGACY_USB3 BIT31 +#define B_PCH_SMI_EN_GPIO_UNLOCK_SMI BIT27 +#define B_PCH_SMI_EN_LEGACY_USB2 BIT17 +#define B_PCH_SMI_EN_PERIODIC BIT14 +#define B_PCH_SMI_EN_TCO BIT13 +#define B_PCH_SMI_EN_MCSMI BIT11 +#define B_PCH_SMI_EN_BIOS_RLS BIT7 +#define B_PCH_SMI_EN_SWSMI_TMR BIT6 +#define B_PCH_SMI_EN_APMC BIT5 +#define B_PCH_SMI_EN_ON_SLP_EN BIT4 +#define B_PCH_SMI_EN_LEGACY_USB BIT3 +#define B_PCH_SMI_EN_BIOS BIT2 +#define B_PCH_SMI_EN_EOS BIT1 +#define B_PCH_SMI_EN_GBL_SMI BIT0 +#define N_PCH_SMI_EN_LEGACY_USB3 31 +#define N_PCH_SMI_EN_ESPI 28 +#define N_PCH_SMI_EN_GPIO_UNLOCK 27 +#define N_PCH_SMI_EN_INTEL_USB2 18 +#define N_PCH_SMI_EN_LEGACY_USB2 17 +#define N_PCH_SMI_EN_PERIODIC 14 +#define N_PCH_SMI_EN_TCO 13 +#define N_PCH_SMI_EN_MCSMI 11 +#define N_PCH_SMI_EN_BIOS_RLS 7 +#define N_PCH_SMI_EN_SWSMI_TMR 6 +#define N_PCH_SMI_EN_APMC 5 +#define N_PCH_SMI_EN_ON_SLP_EN 4 +#define N_PCH_SMI_EN_LEGACY_USB 3 +#define N_PCH_SMI_EN_BIOS 2 +#define N_PCH_SMI_EN_EOS 1 +#define N_PCH_SMI_EN_GBL_SMI 0 + +#define R_PCH_SMI_STS 0x34 +#define S_PCH_SMI_STS 4 +#define B_PCH_SMI_STS_LEGACY_USB3 BIT31 +#define B_PCH_SMI_STS_GPIO_UNLOCK BIT27 +#define B_PCH_SMI_STS_SPI BIT26 +#define B_PCH_SMI_STS_MONITOR BIT21 +#define B_PCH_SMI_STS_PCI_EXP BIT20 +#define B_PCH_SMI_STS_PATCH BIT19 +#define B_PCH_SMI_STS_INTEL_USB2 BIT18 +#define B_PCH_SMI_STS_LEGACY_USB2 BIT17 +#define B_PCH_SMI_STS_SMBUS BIT16 +#define B_PCH_SMI_STS_SERIRQ BIT15 +#define B_PCH_SMI_STS_PERIODIC BIT14 +#define B_PCH_SMI_STS_TCO BIT13 +#define B_PCH_SMI_STS_DEVMON BIT12 +#define B_PCH_SMI_STS_MCSMI BIT11 +#define B_PCH_SMI_STS_GPIO_SMI BIT10 +#define B_PCH_SMI_STS_GPE0 BIT9 +#define B_PCH_SMI_STS_PM1_STS_REG BIT8 +#define B_PCH_SMI_STS_SWSMI_TMR BIT6 +#define B_PCH_SMI_STS_APM BIT5 +#define B_PCH_SMI_STS_ON_SLP_EN BIT4 +#define B_PCH_SMI_STS_LEGACY_USB BIT3 +#define B_PCH_SMI_STS_BIOS BIT2 +#define N_PCH_SMI_STS_LEGACY_USB3 31 +#define N_PCH_SMI_STS_ESPI 28 +#define N_PCH_SMI_STS_GPIO_UNLOCK 27 +#define N_PCH_SMI_STS_SPI 26 +#define N_PCH_SMI_STS_MONITOR 21 +#define N_PCH_SMI_STS_PCI_EXP 20 +#define N_PCH_SMI_STS_PATCH 19 +#define N_PCH_SMI_STS_INTEL_USB2 18 +#define N_PCH_SMI_STS_LEGACY_USB2 17 +#define N_PCH_SMI_STS_SMBUS 16 +#define N_PCH_SMI_STS_SERIRQ 15 +#define N_PCH_SMI_STS_PERIODIC 14 +#define N_PCH_SMI_STS_TCO 13 +#define N_PCH_SMI_STS_DEVMON 12 +#define N_PCH_SMI_STS_MCSMI 11 +#define N_PCH_SMI_STS_GPIO_SMI 10 +#define N_PCH_SMI_STS_GPE0 9 +#define N_PCH_SMI_STS_PM1_STS_REG 8 +#define N_PCH_SMI_STS_SWSMI_TMR 6 +#define N_PCH_SMI_STS_APM 5 +#define N_PCH_SMI_STS_ON_SLP_EN 4 +#define N_PCH_SMI_STS_LEGACY_USB 3 +#define N_PCH_SMI_STS_BIOS 2 + +#define R_PCH_ACPI_GPE_CNTL 0x40 +#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17 + +#define R_PCH_DEVACT_STS 0x44 +#define S_PCH_DEVACT_STS 2 +#define B_PCH_DEVACT_STS_MASK 0x13E1 +#define B_PCH_DEVACT_STS_KBC 0x1000 +#define B_PCH_DEVACT_STS_PIRQDH 0x0200 +#define B_PCH_DEVACT_STS_PIRQCG 0x0100 +#define B_PCH_DEVACT_STS_PIRQBF 0x0080 +#define B_PCH_DEVACT_STS_PIRQAE 0x0040 +#define B_PCH_DEVACT_STS_D0_TRP 0x0001 +#define N_PCH_DEVACT_STS_KBC 12 +#define N_PCH_DEVACT_STS_PIRQDH 9 +#define N_PCH_DEVACT_STS_PIRQCG 8 +#define N_PCH_DEVACT_STS_PIRQBF 7 +#define N_PCH_DEVACT_STS_PIRQAE 6 + +#define R_PCH_ACPI_PM2_CNT 0x50 +#define B_PCH_ACPI_PM2_CNT_ARB_DIS 0x01 + +#define R_PCH_OC_WDT_CTL 0x54 +#define B_PCH_OC_WDT_CTL_RLD BIT31 +#define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25 +#define B_PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT24 +#define B_PCH_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_PCH_OC_WDT_CTL_EN BIT14 +#define B_PCH_OC_WDT_CTL_ICCSURV BIT13 +#define B_PCH_OC_WDT_CTL_LCK BIT12 +#define B_PCH_OC_WDT_CTL_TOV_MASK 0x3FF +#define B_PCH_OC_WDT_CTL_FAILURE_STS BIT23 +#define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 +#define B_PCH_OC_WDT_CTL_AFTER_POST 0x3F0000 +#define V_PCH_OC_WDT_CTL_STATUS_FAILURE 1 +#define V_PCH_OC_WDT_CTL_STATUS_OK 0 + +#define R_PCH_ACPI_GPE0_STS_127_96 0x8C +#define S_PCH_ACPI_GPE0_STS_127_96 4 +#define B_PCH_ACPI_GPE0_STS_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_STS_127_96_LAN_WAKE BIT16 +#define B_PCH_ACPI_GPE0_STS_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_STS_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_STS_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_STS_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_STS_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_STS_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_STS_127_96_SMB_WAK BIT7 +#define B_PCH_ACPI_GPE0_STS_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_STS_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_STS_127_96_PME 11 +#define N_PCH_ACPI_GPE0_STS_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_STS_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_STS_127_96_RI 8 +#define N_PCH_ACPI_GPE0_STS_127_96_SMB_WAK 7 +#define N_PCH_ACPI_GPE0_STS_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_STS_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_STS_127_96_HOT_PLUG 1 + +#define R_PCH_ACPI_GPE0_EN_31_0 0x90 +#define R_PCH_ACPI_GPE0_EN_63_31 0x94 +#define R_PCH_ACPI_GPE0_EN_94_64 0x98 +#define R_PCH_ACPI_GPE0_EN_127_96 0x9C +#define S_PCH_ACPI_GPE0_EN_127_96 4 +#define B_PCH_ACPI_GPE0_EN_127_96_WADT BIT18 +#define B_PCH_ACPI_GPE0_EN_127_96_LAN_WAKE BIT16 +#define B_PCH_ACPI_GPE0_EN_127_96_PME_B0 BIT13 +#define B_PCH_ACPI_GPE0_EN_127_96_ME_SCI BIT12 +#define B_PCH_ACPI_GPE0_EN_127_96_PME BIT11 +#define B_PCH_ACPI_GPE0_EN_127_96_BATLOW BIT10 +#define B_PCH_ACPI_GPE0_EN_127_96_PCI_EXP BIT9 +#define B_PCH_ACPI_GPE0_EN_127_96_RI BIT8 +#define B_PCH_ACPI_GPE0_EN_127_96_TC0SCI BIT6 +#define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2 +#define B_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG BIT1 +#define N_PCH_ACPI_GPE0_EN_127_96_PME_B0 13 +#define N_PCH_ACPI_GPE0_EN_127_96_USB3 12 +#define N_PCH_ACPI_GPE0_EN_127_96_PME 11 +#define N_PCH_ACPI_GPE0_EN_127_96_BATLOW 10 +#define N_PCH_ACPI_GPE0_EN_127_96_PCI_EXP 9 +#define N_PCH_ACPI_GPE0_EN_127_96_RI 8 +#define N_PCH_ACPI_GPE0_EN_127_96_TC0SCI 6 +#define N_PCH_ACPI_GPE0_EN_127_96_SWGPE 2 +#define N_PCH_ACPI_GPE0_EN_127_96_HOT_PLUG 1 + + +// +// TCO register I/O map +// +#define R_PCH_TCO_RLD 0x0 +#define R_PCH_TCO_DAT_IN 0x2 +#define R_PCH_TCO_DAT_OUT 0x3 +#define R_PCH_TCO1_STS 0x04 +#define S_PCH_TCO1_STS 2 +#define B_PCH_TCO1_STS_DMISERR BIT12 +#define B_PCH_TCO1_STS_DMISMI BIT10 +#define B_PCH_TCO1_STS_DMISCI BIT9 +#define B_PCH_TCO1_STS_BIOSWR BIT8 +#define B_PCH_TCO1_STS_NEWCENTURY BIT7 +#define B_PCH_TCO1_STS_TIMEOUT BIT3 +#define B_PCH_TCO1_STS_TCO_INT BIT2 +#define B_PCH_TCO1_STS_SW_TCO_SMI BIT1 +#define B_PCH_TCO1_STS_NMI2SMI BIT0 +#define N_PCH_TCO1_STS_DMISMI 10 +#define N_PCH_TCO1_STS_BIOSWR 8 +#define N_PCH_TCO1_STS_NEWCENTURY 7 +#define N_PCH_TCO1_STS_TIMEOUT 3 +#define N_PCH_TCO1_STS_SW_TCO_SMI 1 +#define N_PCH_TCO1_STS_NMI2SMI 0 + +#define R_PCH_TCO2_STS 0x06 +#define S_PCH_TCO2_STS 2 +#define B_PCH_TCO2_STS_SMLINK_SLV_SMI BIT4 +#define B_PCH_TCO2_STS_BAD_BIOS BIT3 +#define B_PCH_TCO2_STS_BOOT BIT2 +#define B_PCH_TCO2_STS_SECOND_TO BIT1 +#define B_PCH_TCO2_STS_INTRD_DET BIT0 +#define N_PCH_TCO2_STS_INTRD_DET 0 + +#define R_PCH_TCO1_CNT 0x08 +#define S_PCH_TCO1_CNT 2 +#define B_PCH_TCO_CNT_LOCK BIT12 +#define B_PCH_TCO_CNT_TMR_HLT BIT11 +#define B_PCH_TCO_CNT_NMI2SMI_EN BIT9 +#define B_PCH_TCO_CNT_NMI_NOW BIT8 +#define N_PCH_TCO_CNT_NMI2SMI_EN 9 + +#define R_PCH_TCO2_CNT 0x0A +#define S_PCH_TCO2_CNT 2 +#define B_PCH_TCO2_CNT_OS_POLICY 0x0030 +#define B_PCH_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008 +#define B_PCH_TCO2_CNT_INTRD_SEL 0x0006 +#define N_PCH_TCO2_CNT_INTRD_SEL 2 + +#define R_PCH_TCO_MESSAGE1 0x0C +#define R_PCH_TCO_MESSAGE2 0x0D +#define R_PCH_TCO_WDCNT 0x0E +#define R_PCH_TCO_SW_IRQ_GEN 0x10 +#define B_PCH_TCO_IRQ12_CAUSE BIT1 +#define B_PCH_TCO_IRQ1_CAUSE BIT0 +#define R_PCH_TCO_TMR 0x12 + +// +// PWRM Registers +// +#define R_PCH_WADT_AC 0x0 ///< Wake Alarm Device Timer: AC +#define R_PCH_WADT_DC 0x4 ///< Wake Alarm Device Timer: DC +#define R_PCH_WADT_EXP_AC 0x8 ///< Wake Alarm Device Expired Timer: AC +#define R_PCH_WADT_EXP_DC 0xC ///< Wake Alarm Device Expired Timer: DC +#define R_PCH_PWRM_PRSTS 0x10 ///< Power and Reset Status +#define B_PCH_PWRM_PRSTS_VE_WD_TMR_STS BIT7 ///< VE Watchdog Timer Status +#define B_PCH_PWRM_PRSTS_WOL_OVR_WK_STS BIT5 +#define B_PCH_PWRM_PRSTS_FIELD_1 BIT4 +#define B_PCH_PWRM_PRSTS_ME_WAKE_STS BIT0 +#define R_PCH_PWRM_14 0x14 +#define R_PCH_PWRM_CFG 0x18 ///< Power Management Configuration +#define B_PCH_PWRM_CFG_ALLOW_24_OSC_SD BIT29 ///< Allow 24MHz Crystal Oscillator Shutdown +#define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow USB2 Core Power Gating +#define B_PCH_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 ///< RTC Wake from Deep S4/S5 Disable +#define B_PCH_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width +#define V_PCH_PWRM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds +#define V_PCH_PWRM_CFG_SSMAW_1S BIT19 ///< 1 second +#define V_PCH_PWRM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms) +#define V_PCH_PWRM_CFG_SSMAW_0S 0 ///< 0 second +#define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width +#define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds +#define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms +#define V_PCH_PWRM_CFG_SAMAW_4S BIT16 ///< 4 seconds +#define V_PCH_PWRM_CFG_SAMAW_0S 0 ///< 0 second +#define B_PCH_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration +#define V_PCH_PWRM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds +#define V_PCH_PWRM_CFG_RPCD_2S BIT9 ///< 2-3 seconds +#define V_PCH_PWRM_CFG_RPCD_3S BIT8 ///< 3-4 seconds +#define V_PCH_PWRM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default) +#define R_PCH_PWRM_MTPMC 0x20 ///< Message to PMC +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_0_15 0xE ///< Command to override lanes 0-15 power gating +#define V_PCH_PWRM_MTPMC_COMMAND_PG_LANE_16_31 0xF ///< Command to override lanes 16-31 power gating +#define B_PCH_PWRM_MTPMC_PG_CMD_DATA 0xFFFF0000 ///< Data part of PowerGate Message to PMC +#define N_PCH_PWRM_MTPMC_PG_CMD_DATA 16 +#define R_PCH_PWRM_S3_PWRGATE_POL 0x28 ///< S3 Power Gating Policies +#define B_PCH_PWRM_S3DC_GATE_SUS BIT1 ///< Deep S3 Enable in DC Mode +#define B_PCH_PWRM_S3AC_GATE_SUS BIT0 ///< Deep S3 Enable in AC Mode +#define R_PCH_PWRM_S4_PWRGATE_POL 0x2C ///< Deep S4 Power Policies +#define B_PCH_PWRM_S4DC_GATE_SUS BIT1 ///< Deep S4 Enable in DC Mode +#define B_PCH_PWRM_S4AC_GATE_SUS BIT0 ///< Deep S4 Enable in AC Mode +#define R_PCH_PWRM_S5_PWRGATE_POL 0x30 ///< Deep S5 Power Policies +#define B_PCH_PWRM_S5DC_GATE_SUS BIT15 ///< Deep S5 Enable in DC Mode +#define B_PCH_PWRM_S5AC_GATE_SUS BIT14 ///< Deep S5 Enable in AC Mode +#define R_PCH_PWRM_DSX_CFG 0x34 ///< Deep SX Configuration +#define B_PCH_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 ///< WAKE# Pin DeepSx Enable +#define B_PCH_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 ///< AC_PRESENT pin pulldown in DeepSx disable +#define B_PCH_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable +#define R_PCH_PWRM_CFG2 0x3C ///< Power Management Configuration Reg 2 +#define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period (PBOP) +#define N_PCH_PWRM_CFG2_PBOP 29 ///< Power Button Override Period (PBOP) +#define B_PCH_PWRM_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable (PB_DIS) +#define B_PCH_PWRM_CFG2_DRAM_RESET_CTL BIT26 ///< DRAM RESET# control +#define R_PCH_PWRM_EN_SN_SLOW_RING 0x48 ///< Enable Snoop Request to SLOW_RING +#define R_PCH_PWRM_EN_SN_SLOW_RING2 0x4C ///< Enable Snoop Request to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_SN_SA 0x50 ///< Enable Snoop Request to SA +#define R_PCH_PWRM_EN_SN_SA2 0x54 ///< Enable Snoop Request to SA 2nd Reg +#define R_PCH_PWRM_EN_SN_SLOW_RING_CF 0x58 ///< Enable Snoop Request to SLOW_RING_CF +#define R_PCH_PWRM_EN_NS_SA 0x68 ///< Enable Non-Snoop Request to SA +#define R_PCH_PWRM_EN_CW_SLOW_RING 0x80 ///< Enable Clock Wake to SLOW_RING +#define R_PCH_PWRM_EN_CW_SLOW_RING2 0x84 ///< Enable Clock Wake to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_CW_SA 0x88 ///< Enable Clock Wake to SA +#define R_PCH_PWRM_EN_CW_SA2 0x8C ///< Enable Clock Wake to SA 2nd Reg +#define R_PCH_PWRM_EN_CW_SLOW_RING_CF 0x98 ///< Enable Clock Wake to SLOW_RING_CF +#define R_PCH_PWRM_EN_PA_SLOW_RING 0xA8 ///< Enable Pegged Active to SLOW_RING +#define R_PCH_PWRM_EN_PA_SLOW_RING2 0xAC ///< Enable Pegged Active to SLOW_RING 2nd Reg +#define R_PCH_PWRM_EN_PA_SA 0xB0 ///< Enable Pegged Active to SA +#define R_PCH_PWRM_EN_PA_SA2 0xB4 ///< Enable Pegged Active to SA 2nd Reg +#define R_PCH_PWRM_EN_MISC_EVENT 0xC0 ///< Enable Misc PM_SYNC Events +#define R_PCH_PWRM_PMSYNC_TPR_CONFIG 0xC4 +#define B_PCH_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26 +#define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) +#define N_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE 24 +#define V_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1 +#define R_PCH_PWRM_PMSYNC_MISC_CFG 0xC8 +#define B_PCH_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 ///< PM_SYNC Configuration Lock +#define B_PCH_PWRM_PMSYNC_GPIO_D_SEL BIT11 +#define B_PCH_PWRM_PMSYNC_GPIO_C_SEL BIT10 +#define PM_SYNC_GPIO_B 0 +#define R_PCH_PWRM_PM_SYNC_STATE_HYS 0xD0 ///< PM_SYNC State Hysteresis +#define R_PCH_PWRM_PM_SYNC_MODE 0xD4 ///< PM_SYNC Pin Mode +#define R_PCH_PWRM_CFG3 0xE0 ///< Power Management Configuration Reg 3 +#define B_PCH_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 ///< Deep-Sx WLAN Phy Power Enable +#define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host Wireless LAN Phy Power Enable +#define B_PCH_PWRM_CFG3_PWRG_LOCK BIT2 ///< Lock power gating override messages +#define R_PCH_PWRM_PM_DOWN_PPB_CFG 0xE4 ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION +#define R_PCH_PWRM_CFG4 0xE8 ///< Power Management Configuration Reg 4 +#define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 PHY SUS Well Power Gating Enable +#define B_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0] +#define N_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007 +#define V_PCH_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018 +#define R_PCH_PWRM_CPU_EPOC 0xEC +#define R_PCH_PWRM_VR_MISC_CTL 0x100 +#define B_PCH_PWRM_VR_MISC_CTL_VIDSOVEN BIT3 +#define R_PCH_PWRM_GPIO_CFG 0x120 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW2 8 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW1 4 +#define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) +#define N_PCH_PWRM_GPIO_CFG_GPE0_DW0 0 +#define R_PCH_PWRM_PM_SYNC_MODE_C0 0xF4 ///< PM_SYNC Pin Mode in C0 +#define R_PCH_PWRM_124 0x124 +#define R_PCH_PWRM_HPR_CAUSE0 0x12C ///< Host partition reset causes +#define B_PCH_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< Global reset converted to host reset +#define R_PCH_PWRM_MODPHY_PM_CFG1 0x200 +#define R_PCH_PWRM_MODPHY_PM_CFG2 0x204 ///< ModPHY Power Management Configuration Reg 2 +#define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Domain Dynamic Gating Enable +#define B_PCH_PWRM_MODPHY_PM_CFG2_EMFC BIT29 ///< Enable ModPHY FET Control +#define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24) ///< External FET Ramp Time +#define N_PCH_PWRM_MODPHY_PM_CFG2_EFRT 24 +#define V_PCH_PWRM_MODPHY_PM_CFG2_EFRT_200US 0x0A +#define B_PCH_PWRM_MODPHY_PM_CFG2_ASLOR_UFS BIT16 ///< UFS ModPHY SPD SPD Override +#define R_PCH_PWRM_MODPHY_PM_CFG3 0x208 ///< ModPHY Power Management Configuration Reg 3 +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_UFS BIT16 ///< UFS ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request +#define B_PCH_PWRM_MODPHY_PM_CFG3_MSPDRTREQ_SATA BIT12 ///< SATA ModPHY SPD RT Request +#define R_PCH_PWRM_30C 0x30C +#define R_PCH_PWRM_OBFF_CFG 0x314 ///< OBFF Configuration +#define R_PCH_PWRM_31C 0x31C +#define R_PCH_PWRM_CPPM_MISC_CFG 0x320 ///< CPPM Miscellaneous Configuration +#define R_PCH_PWRM_CPPM_CG_POL1A 0x324 ///< CPPM Clock Gating Policy Reg 1 +#define R_PCH_PWRM_CPPM_CG_POL2A 0x340 ///< CPPM Clock Gating Policy Reg 3 +#define R_PCH_PWRM_34C 0x34C +#define R_PCH_PWRM_CPPM_CG_POL3A 0x3A8 ///< CPPM Clock Gating Policy Reg 5 +#define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for Clock Source Group X +#define B_PCH_PWRM_CPPM_CG_POLXA_LTR_GX_THRESH (0x000001FF) ///< LTR Threshold for Clock Source Group X, [8:0] +#define R_PCH_PWRM_3D0 0x3D0 +#define R_PCH_PWRM_CPPM_MPG_POL1A 0x3E0 ///< CPPM ModPHY Gating Policy Reg 1A +#define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LT_MODPHY_SEL BIT29 ///< ASLT/PLT Selection for ModPHY +#define B_PCH_PWRM_CPPM_MPG_POL1A_LTR_MODPHY_THRESH (0x000001FF) ///< LTR Threshold for ModPHY, [8:0] +#define R_PCH_PWRM_CS_SD_CTL1 0x3E8 ///< Clock Source Shutdown Control Reg 1 +#define B_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20) ///< Clock Source 5 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20 +#define B_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0) ///< Clock Source 1 Control Configuration +#define N_PCH_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0 +#define R_PCH_PWRM_CS_SD_CTL2 0x3EC ///< Clock Source Shutdown Control Reg 2 +#define R_PCH_PWRM_HSWPGCR1 0x5D0 +#define B_PCH_PWRM_SW_PG_CTRL_LOCK BIT31 +#define B_PCH_PWRM_DFX_SW_PG_CTRL BIT0 +#define R_PCH_PWRM_600 0x600 +#define R_PCH_PWRM_604 0x604 +#define R_PCH_PWRM_ST_PG_FDIS_PMC_1 0x620 ///< Static PG Related Function Disable Register 1 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Camera Function Disable (PMC Version) (CAM_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH Function Disable (PMC Version) (ISH_FDIS_PMC) +#define B_PCH_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE Function Disable (PMC Version) (GBE_FDIS_PMC) +#define R_PCH_PWRM_ST_PG_FDIS_PMC_2 0x624 ///< Static Function Disable Control Register 2 +#define V_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_FDIS_PMC 0x7FF ///< Static Function Disable Control Register 2 +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< SerialIo Controller GSPI Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< SerialIo Controller GSPI Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< SerialIo Controller UART Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< SerialIo Controller UART Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< SerialIo Controller UART Device 0 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< SerialIo Controller I2C Device 5 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< SerialIo Controller I2C Device 4 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< SerialIo Controller I2C Device 3 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< SerialIo Controller I2C Device 2 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< SerialIo Controller I2C Device 1 Function Disable +#define B_PCH_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< SerialIo Controller I2C Device 0 Function Disable +#define R_PCH_PWRM_NST_PG_FDIS_1 0x628 +#define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT24 ///< XDCI Function Disable. This is only avaiable in B0 onward. +#define B_PCH_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< ADSP Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SATA Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PCIe Controller C Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PCIe Controller C Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PCIe Controller C Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PCIe Controller C Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PCIe Controller B Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PCIe Controller B Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PCIe Controller B Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PCIe Controller B Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PCIe Controller A Port 3 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PCIe Controller A Port 2 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PCIe Controller A Port 1 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PCIe Controller A Port 0 Function Disable +#define B_PCH_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XHCI Function Disable +#define R_PCH_PWRM_FUSE_DIS_RD_1 0x640 ///< Fuse Disable Read 1 Register +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E3_FUSE_DIS BIT21 ///< PCIe Controller E Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E2_FUSE_DIS BIT20 ///< PCIe Controller E Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E1_FUSE_DIS BIT19 ///< PCIe Controller E Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_E0_FUSE_DIS BIT18 ///< PCIe Controller E Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D2_FUSE_DIS BIT16 ///< PCIe Controller D Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D1_FUSE_DIS BIT15 ///< PCIe Controller D Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D0_FUSE_DIS BIT14 ///< PCIe Controller D Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C3_FUSE_DIS BIT13 ///< PCIe Controller C Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C2_FUSE_DIS BIT12 ///< PCIe Controller C Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C1_FUSE_DIS BIT11 ///< PCIe Controller C Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_C0_FUSE_DIS BIT10 ///< PCIe Controller C Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B3_FUSE_DIS BIT9 ///< PCIe Controller B Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B2_FUSE_DIS BIT8 ///< PCIe Controller B Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B1_FUSE_DIS BIT7 ///< PCIe Controller B Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_B0_FUSE_DIS BIT6 ///< PCIe Controller B Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A3_FUSE_DIS BIT5 ///< PCIe Controller A Port 3 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A2_FUSE_DIS BIT4 ///< PCIe Controller A Port 2 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A1_FUSE_DIS BIT3 ///< PCIe Controller A Port 1 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_A0_FUSE_DIS BIT2 ///< PCIe Controller A Port 0 Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_1_XHCI_FUSE_DIS BIT0 ///< XHCI Fuse Disable +#define R_PCH_PWRM_FUSE_DIS_RD_2 0x644 ///< Fuse Disable Read 2 Register +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA Fuse Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PSTH Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHCI Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SATA Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRSB Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITSS Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< SerialIo Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_SCC_FUSE_SS_DIS BIT4 ///< SCC Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_CAM_FUSE_SS_DIS BIT2 ///< Camera Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE Fuse or Soft Strap Disable +#define R_PCH_PWRM_FUSE_DIS_RD_3 0x648 ///< Static PG Fuse and Soft Strap Disable Read Register 3 +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNCRA3 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNCRA2 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNCRA1 Fuse or Soft Strap Disable +#define B_PCH_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNCRA Fuse or Soft Strap Disable + + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPsf.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPsf.h new file mode 100644 index 0000000000..a38ef5346c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPsf.h @@ -0,0 +1,216 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_PSF_H_ +#define _PCH_REGS_PSF_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. +// + +// +// PSFx segment registers +// +#define R_PCH_PCR_PSF_GLOBAL_CONFIG 0x4000 ///< PSF Segment Global Configuration Register +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENTCG BIT4 +#define B_PCH_PCR_PSF_GLOBAL_CONFIG_ENLCG BIT3 +#define R_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0 0x4014 ///< PSF Segment Rootspace Configuration Register +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_ENADDRP2P BIT1 +#define B_PCH_PCR_PSF_ROOTSPACE_CONFIG_RS0_VTDEN BIT0 +#define R_PCH_PCR_PSF_PORT_CONFIG_PG0_PORT0 0x4020 ///< PSF Segment Port Configuration Register + +#define S_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR 4 +#define S_PCH_PSF_TARGET_GNTCNT_RELOAD 4 +#define B_PCH_PSF_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F +#define B_PCH_PSF_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F + +// +// PSFx PCRs definitions +// +#define R_PCH_PCR_PSFX_T0_SHDW_BAR0 0 ///< PCI BAR0 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR1 0x04 ///< PCI BAR1 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR2 0x08 ///< PCI BAR2 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR3 0x0C ///< PCI BAR3 +#define R_PCH_PCR_PSFX_T0_SHDW_BAR4 0x10 ///< PCI BAR4 +#define R_PCH_PCR_PSFX_T0_SHDW_PCIEN 0x1C ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR0DIS BIT16 ///< Disable BAR0 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR1DIS BIT17 ///< Disable BAR1 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR2DIS BIT18 ///< Disable BAR2 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR3DIS BIT19 ///< Disable BAR3 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR4DIS BIT20 ///< Disable BAR4 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_BAR5DIS BIT21 ///< Disable BAR5 +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T0_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable +#define R_PCH_PCR_PSFX_T0_SHDW_PMCSR 0x20 ///< PCI power management configuration +#define B_PCH_PCR_PSFX_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) ///< Power status +#define R_PCH_PCR_PSFX_T0_SHDW_CFG_DIS 0x38 ///< PCI configuration disable +#define B_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS BIT0 ///< config disable + +#define R_PCH_PCR_PSFX_T1_SHDW_PCIEN 0x3C ///< PCI configuration space enable bits +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_FUNDIS BIT8 ///< Function disable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_MEMEN BIT1 ///< Memory decoding enable +#define B_PCH_PCR_PSFX_T1_SHDW_PCIEN_IOEN BIT0 ///< IO decoding enable + +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 ///< device number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_DEVICE 4 +#define B_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BIT2 | BIT1) ///< function number +#define N_PCH_PCR_PSFX_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1 + +#define V_PCH_LP_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38A00 +#define V_PCH_H_PCR_PSFX_PSF_MC_AGENT_MCAST_TGT_P2SB 0x38B00 + +// +// PSF1 PCRs +// +// PSF1 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF1_T0_SHDW_GBE_REG_BASE 0x0200 ///< D31F6 PSF base address (GBE) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CAM_REG_BASE 0x0300 ///< D20F3 PSF base address (CAM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0500 ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0700 ///< D22F4 PSF base address (CSME: HECI3) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0800 ///< D22F1 PSF base address (CSME: HECI2) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0900 ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0A00 ///< D22F0 PSF base address (CSME: HECI1) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0B00 ///< D22F3 PSF base address (CSME: KT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0C00 ///< D22F2 PSF base address (CSME: IDER) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_CLINK_REG_BASE 0x0D00 ///< D18F1 PSF base address (CSME: CLINK) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_PMT_REG_BASE 0x0E00 ///< D18F2 PSF base address (CSME: PMT) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_KVM_REG_BASE 0x0F00 ///< D18F0 PSF base address (CSME: KVM) +#define R_PCH_LP_PCR_PSF1_T0_SHDW_SATA_REG_BASE 0x1000 ///< PCH-LP D23F0 PSF base address (SATA) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2000 ///< PCH-LP D29F3 PSF base address (PCIE PORT 12) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2100 ///< PCH-LP D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2200 ///< PCH-LP D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2300 ///< PCH-LP D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2400 ///< PCH-LP D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2500 ///< PCH-LP D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2600 ///< PCH-LP D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2700 ///< PCH-LP D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x2800 ///< PCH-LP D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x2900 ///< PCH-LP D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x2A00 ///< PCH-LP D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_LP_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x2B00 ///< PCH-LP D28F0 PSF base address (PCIE PORT 01) + +// PSF1 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_WLAN_REG_BASE 0x0200 ///< D22F7 PSF base address (CSME: WLAN) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI3_REG_BASE 0x0300 ///< SPT-H D22F4 PSF base address (CSME: HECI3) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI2_REG_BASE 0x0400 ///< SPT-H D22F1 PSF base address (CSME: HECI2) +#define R_PCH_H_PCR_PSF1_T0_SHDW_CSE_UMA_REG_BASE 0x0500 ///< D18F3 PSF base address (CSME: CSE UMA) +#define R_PCH_H_PCR_PSF1_T0_SHDW_HECI1_REG_BASE 0x0600 ///< SPT-H D22F0 PSF base address (CSME: HECI1) +#define R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE 0x0700 ///< SPT-H D22F3 PSF base address (CSME: KT) +#define R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE 0x0800 ///< SPT-H D22F2 PSF base address (CSME: IDER) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE20_REG_BASE 0x2000 ///< PCH-H D27F3 PSF base address (PCIE PORT 20) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE19_REG_BASE 0x2100 ///< PCH-H D27F2 PSF base address (PCIE PORT 19) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE18_REG_BASE 0x2200 ///< PCH-H D27F1 PSF base address (PCIE PORT 18) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE17_REG_BASE 0x2300 ///< PCH-H D27F0 PSF base address (PCIE PORT 17) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE16_REG_BASE 0x2400 ///< PCH-H D29F7 PSF base address (PCIE PORT 16) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE15_REG_BASE 0x2500 ///< PCH-H D29F6 PSF base address (PCIE PORT 15) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE14_REG_BASE 0x2600 ///< PCH-H D29F5 PSF base address (PCIE PORT 14) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE13_REG_BASE 0x2700 ///< PCH-H D29F4 PSF base address (PCIE PORT 13) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE12_REG_BASE 0x2800 ///< PCH-H D29F3 PSF base address (PCIE PORT 10) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE11_REG_BASE 0x2900 ///< PCH-H D29F2 PSF base address (PCIE PORT 11) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE10_REG_BASE 0x2A00 ///< PCH-H D29F1 PSF base address (PCIE PORT 10) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE09_REG_BASE 0x2B00 ///< PCH-H D29F0 PSF base address (PCIE PORT 09) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE08_REG_BASE 0x2C00 ///< PCH-H D28F7 PSF base address (PCIE PORT 08) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE07_REG_BASE 0x2D00 ///< PCH-H D28F6 PSF base address (PCIE PORT 07) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE06_REG_BASE 0x2E00 ///< PCH-H D28F5 PSF base address (PCIE PORT 06) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE05_REG_BASE 0x2F00 ///< PCH-H D28F4 PSF base address (PCIE PORT 05) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE04_REG_BASE 0x3000 ///< PCH-H D28F3 PSF base address (PCIE PORT 04) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE03_REG_BASE 0x3100 ///< PCH-H D28F2 PSF base address (PCIE PORT 03) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE02_REG_BASE 0x3200 ///< PCH-H D28F1 PSF base address (PCIE PORT 02) +#define R_PCH_H_PCR_PSF1_T1_SHDW_PCIE01_REG_BASE 0x3300 ///< PCH-H D28F0 PSF base address (PCIE PORT 01) + +// Other PSF1 PCRs definition +#define R_PCH_LP_PCR_PSF1_PSF_PORT_CONFIG_PG1_PORT7 0x403C ///< PSF Port Configuration Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST0_EOI 0x4050 ///< Multicast Control Register +#define R_PCH_LP_PCR_PSF1_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4060 ///< Destination ID + + +//PSF 1 Multicast Message Configuration + +#define R_PCH_PCR_PSF1_RC_OWNER_RS0 0x4008 ///< Destination ID + +#define B_PCH_PCR_PSF1_TARGET_CHANNELID 0xFF +#define B_PCH_PCR_PSF1_TARGET_PORTID 0x7F00 +#define N_PCH_PCR_PSF1_TARGET_PORTID 8 +#define B_PCH_PCR_PSF1_TARGET_PORTGROUPID BIT15 +#define N_PCH_PCR_PSF1_TARGET_PORTGROUPID 15 +#define B_PCH_PCR_PSF1_TARGET_PSFID 0xFF0000 +#define N_PCH_PCR_PSF1_TARGET_PSFID 16 +#define B_PCH_PCR_PSF1_TARGET_CHANMAP BIT31 + +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_CHANNELID 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTID 10 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PORTGROUPID_DOWNSTREAM 1 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PMT 0 +#define V_PCH_PCR_PSF1_RC_OWNER_RS0_PSFID_PSF1 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_UPSTREAM 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTGROUPID_DOWNSTREAM 1 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PSFID_PSF1 1 + +#define R_PCH_LP_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x4058 ///< Multicast Control Register + +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_MULTCEN BIT0 +#define B_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 0xFE +#define N_PCH_PCR_PSF1_PSF_MC_CONTROL_MCAST1_RS0_MCTP1_NUMMC 1 + +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_CHANNELID_DMI 0 +#define V_PCH_PCR_PSF1_PSF_MC_AGENT_MCAST1_RS0_TGTX_MCTP1_PORTID_DMI 0 + + + +// +// controls the PCI configuration header of a PCI function +// +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F0 0x4198 ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F1 0x419C ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F2 0x41A0 ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPA_D28_F3 0x41A4 ///< SPA +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F4 0x41A8 ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F5 0x41AC ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F6 0x41B0 ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPB_D28_F7 0x41B4 ///< SPB +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F0 0x41B8 ///< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F1 0x41BC ///< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F2 0x41C0 ///< SPC +#define R_PCH_LP_PCR_PSF1_T1_AGENT_FUNCTION_CONFIG_SPC_D29_F3 0x41C4 ///< SPC + + +// +// PSF1 grant count registers +// +#define R_PCH_LP_PSF1_DEV_GNTCNT_RELOAD_DGCR0 0x41CC +#define R_PCH_LP_PSF1_TARGET_GNTCNT_RELOAD_PG1_TGT0 0x45D0 + + +// +// PSF2 PCRs (PID:PSF2) +// +#define R_PCH_PCR_PSF2_T0_SHDW_TRH_REG_BASE 0x0100 ///< D20F2 PSF base address (Thermal). // LP&H +// PSF2 PCH-LP Specific Base Address +#define R_PCH_LP_PCR_PSF2_T0_SHDW_UFS_REG_BASE 0x0200 ///< D30F7 PSF base address (SCC: UFS) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDCARD_REG_BASE 0x0300 ///< D30F6 PSF base address (SCC: SDCard) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_SDIO_REG_BASE 0x0400 ///< D30F5 PSF base address (SCC: SDIO) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_EMMC_REG_BASE 0x0500 ///< D30F4 PSF base address (SCC: eMMC) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0600 ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_LP_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0700 ///< D20F0 PSF base address (XHCI) +// PSF2 PCH-H Specific Base Address +#define R_PCH_H_PCR_PSF2_T0_SHDW_OTG_REG_BASE 0x0200 ///< D20F1 PSF base address (USB device controller: OTG) +#define R_PCH_H_PCR_PSF2_T0_SHDW_XHCI_REG_BASE 0x0300 ///< D20F0 PSF base address (XHCI) + +// +// PSF3 PCRs (PID:PSF3) +// + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPsth.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPsth.h new file mode 100644 index 0000000000..0c9ce3135f --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsPsth.h @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_PSTH_H_ +#define _PCH_REGS_PSTH_H_ + +// +// Private chipset regsiter (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. +// + +// +// PSTH and IO Trap PCRs (PID:PSTH) +// +#define R_PCH_PCR_PSTH_PSTHCTL 0x1D00 ///< PSTH control register +#define B_PCH_PCR_PSTH_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF sideband trunk clock gating enable +#define B_PCH_PCR_PSTH_PSTHDCGE BIT0 ///< PSTH dynamic clock gating enable +#define R_PCH_PCR_PSTH_TRPST 0x1E00 ///< Trap status regsiter +#define B_PCH_PCR_PSTH_TRPST_CTSS 0x0000000F ///< Cycle Trap SMI# Status mask +#define R_PCH_PCR_PSTH_TRPC 0x1E10 ///< Trapped cycle +#define B_PCH_PCR_PSTH_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write +#define B_PCH_PCR_PSTH_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables +#define B_PCH_PCR_PSTH_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address +#define R_PCH_PCR_PSTH_TRPD 0x1E18 ///< Trapped write data +#define B_PCH_PCR_PSTH_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle I/O data +#define R_PCH_PCR_PSTH_TRPREG0 0x1E80 ///< IO Tarp 0 register +#define R_PCH_PCR_PSTH_TRPREG1 0x1E88 ///< IO Tarp 1 register +#define R_PCH_PCR_PSTH_TRPREG2 0x1E90 ///< IO Tarp 2 register +#define R_PCH_PCR_PSTH_TRPREG3 0x1E98 ///< IO Tarp 3 register +#define B_PCH_PCR_PSTH_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask +#define B_PCH_PCR_PSTH_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write +#define N_PCH_PCR_PSTH_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field +#define N_PCH_PCR_PSTH_TRPREG_BEM (36 - 32) +#define B_PCH_PCR_PSTH_TRPREG_BEM 0x000000F000000000 ///< Byte enable mask +#define B_PCH_PCR_PSTH_TRPREG_BE 0x0000000F00000000 ///< Byte enable +#define B_PCH_PCR_PSTH_TRPREG_AM 0x0000000000FC0000 ///< IO Address mask +#define B_PCH_PCR_PSTH_TRPREG_AD 0x000000000000FFFC ///< IO Address +#define B_PCH_PCR_PSTH_TRPREG_TSE BIT0 ///< Trap and SMI# Enable + + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSata.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSata.h new file mode 100644 index 0000000000..385f868f98 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSata.h @@ -0,0 +1,640 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +// +// SATA Controller Registers (D23:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SATA 23 +#define PCI_FUNCTION_NUMBER_PCH_SATA 0 +#define V_PCH_SATA_VENDOR_ID V_PCH_INTEL_VENDOR_ID + +#define PCH_SATA_FIRST_CONTROLLER 1 +#define PCH_SATA_SECOND_CONTROLLER 2 + +// +// SKL PCH-LP SATA Device ID's +// +#define V_PCH_LP_SATA_DEVICE_ID_M_AHCI 0x9D03 ///< SATA Controller (AHCI) - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID 0x9D05 ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_ALTDIS 0x282A ///< SATA Controller (RAID 0/1/5/10) - NOT premium - Mobile - Alternate ID +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_PREM 0x9D07 ///< SATA Controller (RAID 0/1/5/10) - premium - Mobile +#define V_PCH_LP_SATA_DEVICE_ID_M_RAID_RRT 0x9D0F ///< SATA Controller (RAID 1/RRT Only) - Mobile + +// +// SKL PCH-H SATA Device ID's +// +#define V_PCH_H_SATA_DEVICE_ID_D_AHCI 0xA102 ///< SATA Controller (AHCI) +#define V_PCH_H_SATA_DEVICE_ID_D_AHCI_A0 0xA103 ///< SATA Controller (AHCI) - SPTH A0 +#define V_PCH_H_SATA_DEVICE_ID_D_RAID 0xA105 ///< SATA Controller (RAID 0/1/5/10) - NOT premium +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Controller (RAID 0/1/5/10) - premium - Alternate ID +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Controller (RAID 0/1/5/10) - RSTe of Server SKU +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_PREM 0xA107 ///< SATA Controller (RAID 0/1/5/10) - premium +#define V_PCH_H_SATA_DEVICE_ID_D_RAID_RRT 0xA10F ///< SATA Controller (RAID 1/RRT Only) + + +// +// LBG PRODUCTION INCLUDING QUAL SAMPLES SATA Device ID's +// +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_AHCI 0xA182 ///< Server AHCI Mode (Ports 0-5) +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID 0xA184 ///< Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA186 ///< Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_PROD_SATA_DEVICE_ID_D_RAID1 0xA18E ///< Server RAID 1/RRT Only + +// +// LBG SSX (Super SKUs and Pre Production) SATA Device ID's +// +#define V_PCH_LBG_SATA_DEVICE_ID_D_AHCI 0xA202 ///< Server AHCI Mode (Ports 0-5) +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID 0xA204 ///< Server RAID 0/1/5/10 - NOT premium +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM 0xA206 ///< Server RAID 0/1/5/10 - premium +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID1 0xA20E ///< Server RAID 1/RRT Only + +// +// LBG Alternate RST Device IDs +// +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL0 0x2822 ///< Server RAID 0/1/5/10 - premium - Alternate ID for RST +#define V_PCH_LBG_SATA_DEVICE_ID_D_RAID_PREMIUM_DSEL1 0x2826 ///< Server RAID 0/1/5/10 - premium - Alternate ID for RSTe + +// +// SATA Controller common Registers +// +#define V_PCH_SATA_SUB_CLASS_CODE_AHCI 0x06 +#define V_PCH_SATA_SUB_CLASS_CODE_RAID 0x04 +#define R_PCH_SATA_AHCI_BAR 0x24 +#define B_PCH_SATA_AHCI_BAR_BA 0xFFFFF800 +#define V_PCH_SATA_AHCI_BAR_LENGTH 0x800 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT 11 +#define V_PCH_SATA_AHCI_BAR_LENGTH_512K 0x80000 +#define N_PCH_SATA_AHCI_BAR_ALIGNMENT_512K 19 +#define B_PCH_SATA_AHCI_BAR_PF BIT3 +#define B_PCH_SATA_AHCI_BAR_TP (BIT2 | BIT1) +#define B_PCH_SATA_AHCI_BAR_RTE BIT0 +#define R_PCH_SATA_PID 0x70 +#define B_PCH_SATA_PID_NEXT 0xFF00 +#define V_PCH_SATA_PID_NEXT_0 0xB000 +#define V_PCH_SATA_PID_NEXT_1 0xA800 +#define B_PCH_SATA_PID_CID 0x00FF +#define R_PCH_SATA_PC 0x72 +#define S_PCH_SATA_PC 2 +#define B_PCH_SATA_PC_PME (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) +#define V_PCH_SATA_PC_PME_0 0x0000 +#define V_PCH_SATA_PC_PME_1 0x4000 +#define B_PCH_SATA_PC_D2_SUP BIT10 +#define B_PCH_SATA_PC_D1_SUP BIT9 +#define B_PCH_SATA_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_SATA_PC_DSI BIT5 +#define B_PCH_SATA_PC_PME_CLK BIT3 +#define B_PCH_SATA_PC_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_SATA_PMCS 0x74 +#define B_PCH_SATA_PMCS_PMES BIT15 +#define B_PCH_SATA_PMCS_PMEE BIT8 +#define B_PCH_SATA_PMCS_NSFRST BIT3 +#define V_PCH_SATA_PMCS_NSFRST_1 0x01 +#define V_PCH_SATA_PMCS_NSFRST_0 0x00 +#define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) +#define V_PCH_SATA_PMCS_PS_3 0x03 +#define V_PCH_SATA_PMCS_PS_0 0x00 +#define R_PCH_SATA_MID 0x80 +#define B_PCH_SATA_MID_NEXT 0xFF00 +#define B_PCH_SATA_MID_CID 0x00FF +#define R_PCH_SATA_MC 0x82 +#define B_PCH_SATA_MC_C64 BIT7 +#define B_PCH_SATA_MC_MME (BIT6 | BIT5 | BIT4) +#define V_PCH_SATA_MC_MME_4 0x04 +#define V_PCH_SATA_MC_MME_2 0x02 +#define V_PCH_SATA_MC_MME_1 0x01 +#define V_PCH_SATA_MC_MME_0 0x00 +#define B_PCH_SATA_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_PCH_SATA_MC_MMC_4 0x04 +#define V_PCH_SATA_MC_MMC_0 0x00 +#define B_PCH_SATA_MC_MSIE BIT0 +#define V_PCH_SATA_MC_MSIE_1 0x01 +#define V_PCH_SATA_MC_MSIE_0 0x00 +#define R_PCH_SATA_MA 0x84 +#define B_PCH_SATA_MA 0xFFFFFFFC +#define R_PCH_SATA_MD 0x88 +#define B_PCH_SATA_MD_MSIMD 0xFFFF + +// +// Sata Register for PCH-LP +// +#define R_PCH_LP_SATA_MAP 0x90 +#define B_PCH_LP_SATA_MAP_SPD (BIT10 | BIT9 | BIT8) +#define N_PCH_LP_SATA_MAP_SPD 8 +#define B_PCH_LP_SATA_MAP_SPD2 BIT10 +#define B_PCH_LP_SATA_MAP_SPD1 BIT9 +#define B_PCH_LP_SATA_MAP_SPD0 BIT8 +#define B_PCH_LP_SATA_MAP_SMS_MASK BIT6 +#define N_PCH_LP_SATA_MAP_SMS_MASK 6 +#define V_PCH_LP_SATA_MAP_SMS_AHCI 0x0 +#define V_PCH_LP_SATA_MAP_SMS_RAID 0x1 +#define R_PCH_LP_SATA_PCS 0x92 +#define B_PCH_LP_SATA_PCS_OOB_RETRY BIT15 +#define B_PCH_LP_SATA_PCS_P2P BIT10 +#define B_PCH_LP_SATA_PCS_P1P BIT9 +#define B_PCH_LP_SATA_PCS_P0P BIT8 +#define B_PCH_LP_SATA_PCS_PXE_MASK (BIT2 | BIT1 | BIT0) +#define B_PCH_LP_SATA_PCS_P2E BIT2 +#define B_PCH_LP_SATA_PCS_P1E BIT1 +#define B_PCH_LP_SATA_PCS_P0E BIT0 +#define R_PCH_LP_SATA_SCLKGC 0x94 +#define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24) +#define B_PCH_LP_SATA_SCLKGC_PORT2_PCD BIT26 +#define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25 +#define B_PCH_LP_SATA_SCLKGC_PORT0_PCD BIT24 +#define R_PCH_LP_SATA_98 0x98 + +// +// Sata Register for PCH-H +// +#define R_PCH_H_SATA_MAP 0x90 +#define B_PCH_H_SATA_MAP_SPD 0xFF0000 +#define N_PCH_H_SATA_MAP_SPD 16 +#define B_PCH_H_SATA_MAP_SPD7 BIT23 +#define B_PCH_H_SATA_MAP_SPD6 BIT22 +#define B_PCH_H_SATA_MAP_SPD5 BIT21 +#define B_PCH_H_SATA_MAP_SPD4 BIT20 +#define B_PCH_H_SATA_MAP_SPD3 BIT19 +#define B_PCH_H_SATA_MAP_SPD2 BIT18 +#define B_PCH_H_SATA_MAP_SPD1 BIT17 +#define B_PCH_H_SATA_MAP_SPD0 BIT16 +#define B_PCH_H_SATA_MAP_PCD 0xFF +#define B_PCH_H_SATA_MAP_PORT7_PCD BIT7 +#define B_PCH_H_SATA_MAP_PORT6_PCD BIT6 +#define B_PCH_H_SATA_MAP_PORT5_PCD BIT5 +#define B_PCH_H_SATA_MAP_PORT4_PCD BIT4 +#define B_PCH_H_SATA_MAP_PORT3_PCD BIT3 +#define B_PCH_H_SATA_MAP_PORT2_PCD BIT2 +#define B_PCH_H_SATA_MAP_PORT1_PCD BIT1 +#define B_PCH_H_SATA_MAP_PORT0_PCD BIT0 +#define R_PCH_H_SATA_PCS 0x94 +#define B_PCH_H_SATA_PCS_P7P BIT23 +#define B_PCH_H_SATA_PCS_P6P BIT22 +#define B_PCH_H_SATA_PCS_P5P BIT21 +#define B_PCH_H_SATA_PCS_P4P BIT20 +#define B_PCH_H_SATA_PCS_P3P BIT19 +#define B_PCH_H_SATA_PCS_P2P BIT18 +#define B_PCH_H_SATA_PCS_P1P BIT17 +#define B_PCH_H_SATA_PCS_P0P BIT16 +#define B_PCH_H_SATA_PCS_PXE_MASK 0xFF +#define B_PCH_H_SATA_PCS_P7E BIT7 +#define B_PCH_H_SATA_PCS_P6E BIT6 +#define B_PCH_H_SATA_PCS_P5E BIT5 +#define B_PCH_H_SATA_PCS_P4E BIT4 +#define B_PCH_H_SATA_PCS_P3E BIT3 +#define B_PCH_H_SATA_PCS_P2E BIT2 +#define B_PCH_H_SATA_PCS_P1E BIT1 +#define B_PCH_H_SATA_PCS_P0E BIT0 + +#define R_PCH_SATA_SATAGC 0x9C +#define B_PCH_H_SATA_SATAGC_SMS_MASK BIT16 +#define N_PCH_H_SATA_SATAGC_SMS_MASK 16 +#define V_PCH_H_SATA_SATAGC_SMS_AHCI 0x0 +#define V_PCH_H_SATA_SATAGC_SMS_RAID 0x1 +#define B_PCH_SATA_SATAGC_AIE BIT7 +#define B_PCH_SATA_SATAGC_AIES BIT6 +#define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3) +#define V_PCH_SATA_SATAGC_MSS_8K 0x2 +#define N_PCH_SATA_SATAGC_MSS 3 +#define B_PCH_SATA_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) + +#define V_PCH_SATA_SATAGC_ASSEL_2K 0x0 +#define V_PCH_SATA_SATAGC_ASSEL_16K 0x1 +#define V_PCH_SATA_SATAGC_ASSEL_32K 0x2 +#define V_PCH_SATA_SATAGC_ASSEL_64K 0x3 +#define V_PCH_SATA_SATAGC_ASSEL_128K 0x4 +#define V_PCH_SATA_SATAGC_ASSEL_256K 0x5 +#define V_PCH_SATA_SATAGC_ASSEL_512K 0x6 + +#define R_PCH_SATA_SIRI 0xA0 +#define R_PCH_SATA_STRD 0xA4 +#define R_PCH_SATA_SIR_50 0x50 +#define R_PCH_SATA_SIR_54 0x54 +#define R_PCH_SATA_SIR_58 0x58 +#define R_PCH_SATA_SIR_5C 0x5C +#define R_PCH_SATA_SIR_60 0x60 +#define R_PCH_SATA_SIR_64 0x64 +#define R_PCH_SATA_SIR_68 0x68 +#define R_PCH_SATA_SIR_6C 0x6C +#define R_PCH_SATA_SIR_70 0x70 +#define R_PCH_SATA_SIR_80 0x80 +#define R_PCH_SATA_SIR_84 0x84 +#define R_PCH_SATA_SIR_8C 0x8C +#define R_PCH_SATA_SIR_90 0x90 +#define R_PCH_SATA_SIR_98 0x98 +#define R_PCH_SATA_SIR_9C 0x9C +#define R_PCH_SATA_SIR_A0 0xA0 +#define R_PCH_SATA_SIR_A4 0xA4 +#define R_PCH_SATA_SIR_A8 0xA8 +#define R_PCH_SATA_SIR_C8 0xC8 +#define R_PCH_SATA_SIR_CC 0xCC +#define R_PCH_SATA_SIR_D0 0xD0 +#define R_PCH_SATA_SIR_D4 0xD4 +#define B_PCH_SATA_STRD_DTA 0xFFFFFFFF +#define R_PCH_SATA_CR0 0xA8 +#define B_PCH_SATA_CR0_MAJREV 0x00F00000 +#define B_PCH_SATA_CR0_MINREV 0x000F0000 +#define B_PCH_SATA_CR0_NEXT 0x0000FF00 +#define B_PCH_SATA_CR0_CAP 0x000000FF +#define R_PCH_SATA_CR1 0xAC +#define B_PCH_SATA_CR1_BAROFST 0xFFF0 +#define B_PCH_SATA_CR1_BARLOC 0x000F +#define R_PCH_SATA_FLR_CID 0xB0 +#define B_PCH_SATA_FLR_CID_NEXT 0xFF00 +#define B_PCH_SATA_FLR_CID 0x00FF +#define V_PCH_SATA_FLR_CID_1 0x0009 +#define V_PCH_SATA_FLR_CID_0 0x0013 +#define R_PCH_SATA_FLR_CLV 0xB2 +#define B_PCH_SATA_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_PCH_SATA_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_PCH_SATA_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_PCH_SATA_FLRC 0xB4 +#define B_PCH_SATA_FLRC_TXP BIT8 +#define B_PCH_SATA_FLRC_INITFLR BIT0 +#define R_PCH_SATA_SP 0xC0 +#define B_PCH_SATA_SP 0xFFFFFFFF +#define R_PCH_SATA_MXID 0xD0 +#define N_PCH_SATA_MXID_NEXT 8 + +#define R_PCH_SATA_BFCS 0xE0 +#define B_PCH_SATA_BFCS_P7BFI BIT17 +#define B_PCH_SATA_BFCS_P6BFI BIT16 +#define B_PCH_SATA_BFCS_P5BFI BIT15 +#define B_PCH_SATA_BFCS_P4BFI BIT14 +#define B_PCH_SATA_BFCS_P3BFI BIT13 +#define B_PCH_SATA_BFCS_P2BFI BIT12 +#define B_PCH_SATA_BFCS_P2BFS BIT11 +#define B_PCH_SATA_BFCS_P2BFF BIT10 +#define B_PCH_SATA_BFCS_P1BFI BIT9 +#define B_PCH_SATA_BFCS_P0BFI BIT8 +#define B_PCH_SATA_BFCS_BIST_FIS_T BIT7 +#define B_PCH_SATA_BFCS_BIST_FIS_A BIT6 +#define B_PCH_SATA_BFCS_BIST_FIS_S BIT5 +#define B_PCH_SATA_BFCS_BIST_FIS_L BIT4 +#define B_PCH_SATA_BFCS_BIST_FIS_F BIT3 +#define B_PCH_SATA_BFCS_BIST_FIS_P BIT2 +#define R_PCH_SATA_BFTD1 0xE4 +#define B_PCH_SATA_BFTD1 0xFFFFFFFF +#define R_PCH_SATA_BFTD2 0xE8 +#define B_PCH_SATA_BFTD2 0xFFFFFFFF + +#define R_PCH_SATA_VS_CAP 0xA4 +#define B_PCH_SATA_VS_CAP_NRMBE BIT0 ///< NVM Remap Memory BAR Enable +#define B_PCH_SATA_VS_CAP_MSL 0x1FFE ///< Memory Space Limit +#define N_PCH_SATA_VS_CAP_MSL 1 +#define V_PCH_SATA_VS_CAP_MSL 0x1EF ///< Memory Space Limit Field Value +#define B_PCH_SATA_VS_CAP_NRMO 0xFFF0000 ///< NVM Remapped Memory Offset +#define N_PCH_SATA_VS_CAP_NRMO 16 +#define V_PCH_SATA_VS_CAP_NRMO 0x10 ///< NVM Remapped Memory Offset Field Value + +// +// RST PCIe Storage Remapping Registers +// +#define R_PCH_RST_PCIE_STORAGE_RCR 0x800 ///< Remap Capability Register +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) ///< Number of Remapping Supported +#define B_PCH_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 ///< Number of Remapping Supported (RST PCIe Storage Cycle Router #1) +#define R_PCH_RST_PCIE_STORAGE_SPR 0x80C ///< Scratch Pad Register +#define R_PCH_RST_PCIE_STORAGE_CR1_DCC 0x880 ///< CR#1 Device Class Code +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_SCC 8 +#define N_PCH_RST_PCIE_STORAGE_CR1_DCC_BCC 16 +#define B_PCH_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 ///< Device Type +#define V_PCH_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 ///< Remapped Configuration for RST PCIe Storage Cycle Router #n +#define V_PCH_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 ///< Remapped Root Port Offset Value +#define R_PCH_RST_PCIE_STORAGE_CCFG 0x1D0 ///< Port Configuration Register + +// +// AHCI BAR Area related Registers +// +#define R_PCH_SATA_AHCI_CAP 0x0 +#define B_PCH_SATA_AHCI_CAP_S64A BIT31 +#define B_PCH_SATA_AHCI_CAP_SCQA BIT30 +#define B_PCH_SATA_AHCI_CAP_SSNTF BIT29 +#define B_PCH_SATA_AHCI_CAP_SIS BIT28 ///< Supports Interlock Switch +#define B_PCH_SATA_AHCI_CAP_SSS BIT27 ///< Supports Stagger Spin-up +#define B_PCH_SATA_AHCI_CAP_SALP BIT26 +#define B_PCH_SATA_AHCI_CAP_SAL BIT25 +#define B_PCH_SATA_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override +#define B_PCH_SATA_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) +#define N_PCH_SATA_AHCI_CAP_ISS 20 ///< Interface Speed Support +#define V_PCH_SATA_AHCI_CAP_ISS_1_5_G 0x01 +#define V_PCH_SATA_AHCI_CAP_ISS_3_0_G 0x02 +#define V_PCH_SATA_AHCI_CAP_ISS_6_0_G 0x03 +#define B_PCH_SATA_AHCI_CAP_SNZO BIT19 +#define B_PCH_SATA_AHCI_CAP_SAM BIT18 +#define B_PCH_SATA_AHCI_CAP_PMS BIT17 ///< Supports Port Multiplier +#define B_PCH_SATA_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block +#define B_PCH_SATA_AHCI_CAP_SSC BIT14 +#define B_PCH_SATA_AHCI_CAP_PSC BIT13 +#define B_PCH_SATA_AHCI_CAP_NCS 0x1F00 +#define B_PCH_SATA_AHCI_CAP_CCCS BIT7 +#define B_PCH_SATA_AHCI_CAP_EMS BIT6 +#define B_PCH_SATA_AHCI_CAP_SXS BIT5 ///< External SATA is supported +#define B_PCH_SATA_AHCI_CAP_NPS 0x001F + +#define R_PCH_SATA_AHCI_GHC 0x04 +#define B_PCH_SATA_AHCI_GHC_AE BIT31 +#define B_PCH_SATA_AHCI_GHC_MRSM BIT2 +#define B_PCH_SATA_AHCI_GHC_IE BIT1 +#define B_PCH_SATA_AHCI_GHC_HR BIT0 + +#define R_PCH_SATA_AHCI_IS 0x08 +#define B_PCH_SATA_AHCI_IS_PORT7 BIT7 +#define B_PCH_SATA_AHCI_IS_PORT6 BIT6 +#define B_PCH_SATA_AHCI_IS_PORT5 BIT5 +#define B_PCH_SATA_AHCI_IS_PORT4 BIT4 +#define B_PCH_SATA_AHCI_IS_PORT3 BIT3 +#define B_PCH_SATA_AHCI_IS_PORT2 BIT2 +#define B_PCH_SATA_AHCI_IS_PORT1 BIT1 +#define B_PCH_SATA_AHCI_IS_PORT0 BIT0 +#define R_PCH_SATA_AHCI_PI 0x0C +#define B_PCH_H_SATA_PORT_MASK 0xFF +#define B_PCH_LP_SATA_PORT_MASK 0x03 +#define B_PCH_SATA_PORT7_IMPLEMENTED BIT7 +#define B_PCH_SATA_PORT6_IMPLEMENTED BIT6 +#define B_PCH_SATA_PORT5_IMPLEMENTED BIT5 +#define B_PCH_SATA_PORT4_IMPLEMENTED BIT4 +#define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 +#define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 +#define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 +#define B_PCH_SATA_PORT0_IMPLEMENTED BIT0 +#define R_PCH_SATA_AHCI_VS 0x10 +#define B_PCH_SATA_AHCI_VS_MJR 0xFFFF0000 +#define B_PCH_SATA_AHCI_VS_MNR 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_LOC 0x1C +#define B_PCH_SATA_AHCI_EM_LOC_OFST 0xFFFF0000 +#define B_PCH_SATA_AHCI_EM_LOC_SZ 0x0000FFFF +#define R_PCH_SATA_AHCI_EM_CTRL 0x20 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_ALHD BIT26 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 +#define B_PCH_SATA_AHCI_EM_CTRL_ATTR_SMB BIT24 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SGPIO BIT19 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SES2 BIT18 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_SAFTE BIT17 +#define B_PCH_SATA_AHCI_EM_CTRL_SUPP_LED BIT16 +#define B_PCH_SATA_AHCI_EM_CTRL_RST BIT9 +#define B_PCH_SATA_AHCI_EM_CTRL_CTL_TM BIT8 +#define B_PCH_SATA_AHCI_EM_CTRL_STS_MR BIT0 +#define R_PCH_SATA_AHCI_CAP2 0x24 +#define B_PCH_SATA_AHCI_CAP2_DESO BIT5 +#define B_PCH_SATA_AHCI_CAP2_SADM BIT4 +#define B_PCH_SATA_AHCI_CAP2_SDS BIT3 +#define B_PCH_SATA_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions +#define R_PCH_SATA_AHCI_VSP 0xA0 +#define B_PCH_SATA_AHCI_VSP_SLPD BIT0 +#define R_PCH_SATA_AHCI_RSTF 0xC8 ///< RST Feature Capabilities +#define B_PCH_SATA_AHCI_RSTF_OUD (BIT11 | BIT10) +#define N_PCH_SATA_AHCI_RSTF_OUD 10 +#define B_PCH_SATA_AHCI_RSTF_SEREQ BIT9 +#define B_PCH_SATA_AHCI_RSTF_IROES BIT8 +#define B_PCH_SATA_AHCI_RSTF_LEDL BIT7 +#define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6 +#define B_PCH_SATA_AHCI_RSTF_IRSTOROM BIT5 +#define B_PCH_SATA_AHCI_RSTF_RSTE BIT4 +#define B_PCH_SATA_AHCI_RSTF_R5E BIT3 +#define B_PCH_SATA_AHCI_RSTF_R10E BIT2 +#define B_PCH_SATA_AHCI_RSTF_R1E BIT1 +#define B_PCH_SATA_AHCI_RSTF_R0E BIT0 +#define B_PCH_SATA_AHCI_RSTF_LOWBYTES 0x1FF +#define R_PCH_SATA_AHCI_P0CLB 0x100 +#define R_PCH_SATA_AHCI_P1CLB 0x180 +#define R_PCH_SATA_AHCI_P2CLB 0x200 +#define R_PCH_SATA_AHCI_P3CLB 0x280 +#define R_PCH_SATA_AHCI_P4CLB 0x300 +#define R_PCH_SATA_AHCI_P5CLB 0x380 +#define R_PCH_SATA_AHCI_P6CLB 0x400 +#define R_PCH_SATA_AHCI_P7CLB 0x480 +#define B_PCH_SATA_AHCI_PXCLB 0xFFFFFC00 +#define R_PCH_SATA_AHCI_P0CLBU 0x104 +#define R_PCH_SATA_AHCI_P1CLBU 0x184 +#define R_PCH_SATA_AHCI_P2CLBU 0x204 +#define R_PCH_SATA_AHCI_P3CLBU 0x284 +#define R_PCH_SATA_AHCI_P4CLBU 0x304 +#define R_PCH_SATA_AHCI_P5CLBU 0x384 +#define R_PCH_SATA_AHCI_P6CLBU 0x404 +#define R_PCH_SATA_AHCI_P7CLBU 0x484 +#define B_PCH_SATA_AHCI_PXCLBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0FB 0x108 +#define R_PCH_SATA_AHCI_P1FB 0x188 +#define R_PCH_SATA_AHCI_P2FB 0x208 +#define R_PCH_SATA_AHCI_P3FB 0x288 +#define R_PCH_SATA_AHCI_P4FB 0x308 +#define R_PCH_SATA_AHCI_P5FB 0x388 +#define R_PCH_SATA_AHCI_P6FB 0x408 +#define R_PCH_SATA_AHCI_P7FB 0x488 +#define B_PCH_SATA_AHCI_PXFB 0xFFFFFF00 +#define R_PCH_SATA_AHCI_P0FBU 0x10C +#define R_PCH_SATA_AHCI_P1FBU 0x18C +#define R_PCH_SATA_AHCI_P2FBU 0x20C +#define R_PCH_SATA_AHCI_P3FBU 0x28C +#define R_PCH_SATA_AHCI_P4FBU 0x30C +#define R_PCH_SATA_AHCI_P5FBU 0x38C +#define R_PCH_SATA_AHCI_P6FBU 0x40C +#define R_PCH_SATA_AHCI_P7FBU 0x48C +#define B_PCH_SATA_AHCI_PXFBU 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0IS 0x110 +#define R_PCH_SATA_AHCI_P1IS 0x190 +#define R_PCH_SATA_AHCI_P2IS 0x210 +#define R_PCH_SATA_AHCI_P3IS 0x290 +#define R_PCH_SATA_AHCI_P4IS 0x310 +#define R_PCH_SATA_AHCI_P5IS 0x390 +#define R_PCH_SATA_AHCI_P6IS 0x410 +#define R_PCH_SATA_AHCI_P7IS 0x490 +#define B_PCH_SATA_AHCI_PXIS_CPDS BIT31 +#define B_PCH_SATA_AHCI_PXIS_TFES BIT30 +#define B_PCH_SATA_AHCI_PXIS_HBFS BIT29 +#define B_PCH_SATA_AHCI_PXIS_HBDS BIT28 +#define B_PCH_SATA_AHCI_PXIS_IFS BIT27 +#define B_PCH_SATA_AHCI_PXIS_INFS BIT26 +#define B_PCH_SATA_AHCI_PXIS_OFS BIT24 +#define B_PCH_SATA_AHCI_PXIS_IPMS BIT23 +#define B_PCH_SATA_AHCI_PXIS_PRCS BIT22 +#define B_PCH_SATA_AHCI_PXIS_DIS BIT7 +#define B_PCH_SATA_AHCI_PXIS_PCS BIT6 +#define B_PCH_SATA_AHCI_PXIS_DPS BIT5 +#define B_PCH_SATA_AHCI_PXIS_UFS BIT4 +#define B_PCH_SATA_AHCI_PXIS_SDBS BIT3 +#define B_PCH_SATA_AHCI_PXIS_DSS BIT2 +#define B_PCH_SATA_AHCI_PXIS_PSS BIT1 +#define B_PCH_SATA_AHCI_PXIS_DHRS BIT0 +#define R_PCH_SATA_AHCI_P0IE 0x114 +#define R_PCH_SATA_AHCI_P1IE 0x194 +#define R_PCH_SATA_AHCI_P2IE 0x214 +#define R_PCH_SATA_AHCI_P3IE 0x294 +#define R_PCH_SATA_AHCI_P4IE 0x314 +#define R_PCH_SATA_AHCI_P5IE 0x394 +#define R_PCH_SATA_AHCI_P6IE 0x414 +#define R_PCH_SATA_AHCI_P7IE 0x494 +#define B_PCH_SATA_AHCI_PXIE_CPDE BIT31 +#define B_PCH_SATA_AHCI_PXIE_TFEE BIT30 +#define B_PCH_SATA_AHCI_PXIE_HBFE BIT29 +#define B_PCH_SATA_AHCI_PXIE_HBDE BIT28 +#define B_PCH_SATA_AHCI_PXIE_IFE BIT27 +#define B_PCH_SATA_AHCI_PXIE_INFE BIT26 +#define B_PCH_SATA_AHCI_PXIE_OFE BIT24 +#define B_PCH_SATA_AHCI_PXIE_IPME BIT23 +#define B_PCH_SATA_AHCI_PXIE_PRCE BIT22 +#define B_PCH_SATA_AHCI_PXIE_DIE BIT7 +#define B_PCH_SATA_AHCI_PXIE_PCE BIT6 +#define B_PCH_SATA_AHCI_PXIE_DPE BIT5 +#define B_PCH_SATA_AHCI_PXIE_UFIE BIT4 +#define B_PCH_SATA_AHCI_PXIE_SDBE BIT3 +#define B_PCH_SATA_AHCI_PXIE_DSE BIT2 +#define B_PCH_SATA_AHCI_PXIE_PSE BIT1 +#define B_PCH_SATA_AHCI_PXIE_DHRE BIT0 +#define R_PCH_SATA_AHCI_P0CMD 0x118 +#define R_PCH_SATA_AHCI_P1CMD 0x198 +#define R_PCH_SATA_AHCI_P2CMD 0x218 +#define R_PCH_SATA_AHCI_P3CMD 0x298 +#define R_PCH_SATA_AHCI_P4CMD 0x318 +#define R_PCH_SATA_AHCI_P5CMD 0x398 +#define R_PCH_SATA_AHCI_P6CMD 0x418 +#define R_PCH_SATA_AHCI_P7CMD 0x498 +#define B_PCH_SATA_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28) +#define B_PCH_SATA_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21 | BIT19 | BIT18) +#define B_PCH_SATA_AHCI_PxCMD_ASP BIT27 +#define B_PCH_SATA_AHCI_PxCMD_ALPE BIT26 +#define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 +#define B_PCH_SATA_AHCI_PxCMD_ATAPI BIT24 +#define B_PCH_SATA_AHCI_PxCMD_APSTE BIT23 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define R_PCH_SATA_AHCI_P0DEVSLP 0x144 +#define R_PCH_SATA_AHCI_P1DEVSLP 0x1C4 +#define R_PCH_SATA_AHCI_P2DEVSLP 0x244 +#define R_PCH_SATA_AHCI_P3DEVSLP 0x2C4 +#define R_PCH_SATA_AHCI_P4DEVSLP 0x344 +#define R_PCH_SATA_AHCI_P5DEVSLP 0x3C4 +#define R_PCH_SATA_AHCI_P6DEVSLP 0x444 +#define R_PCH_SATA_AHCI_P7DEVSLP 0x4C4 +#define B_PCH_SATA_AHCI_PxDEVSLP_DSP BIT1 +#define B_PCH_SATA_AHCI_PxDEVSLP_ADSE BIT0 +#define B_PCH_SATA_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DITO_625 0x01388000 +#define B_PCH_SATA_AHCI_PxDEVSLP_DM_MASK 0x1E000000 +#define V_PCH_SATA_AHCI_PxDEVSLP_DM_16 0x1E000000 +#define B_PCH_SATA_AHCI_PxCMD_ESP BIT21 ///< Used with an external SATA device +#define B_PCH_SATA_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port +#define B_PCH_SATA_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable +#define B_PCH_SATA_AHCI_PxCMD_CR BIT15 +#define B_PCH_SATA_AHCI_PxCMD_FR BIT14 +#define B_PCH_SATA_AHCI_PxCMD_ISS BIT13 +#define B_PCH_SATA_AHCI_PxCMD_CCS 0x00001F00 +#define B_PCH_SATA_AHCI_PxCMD_FRE BIT4 +#define B_PCH_SATA_AHCI_PxCMD_CLO BIT3 +#define B_PCH_SATA_AHCI_PxCMD_POD BIT2 +#define B_PCH_SATA_AHCI_PxCMD_SUD BIT1 +#define B_PCH_SATA_AHCI_PxCMD_ST BIT0 +#define R_PCH_SATA_AHCI_P0TFD 0x120 +#define R_PCH_SATA_AHCI_P1TFD 0x1A0 +#define R_PCH_SATA_AHCI_P2TFD 0x220 +#define R_PCH_SATA_AHCI_P3TFD 0x2A0 +#define R_PCH_SATA_AHCI_P4TFD 0x320 +#define R_PCH_SATA_AHCI_P5TFD 0x3A0 +#define R_PCH_SATA_AHCI_P6TFD 0x420 +#define B_PCH_SATA_AHCI_PXTFD_ERR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXTFD_STS 0x000000FF +#define R_PCH_SATA_AHCI_P0SIG 0x124 +#define R_PCH_SATA_AHCI_P1SIG 0x1A4 +#define R_PCH_SATA_AHCI_P2SIG 0x224 +#define R_PCH_SATA_AHCI_P3SIG 0x2A4 +#define R_PCH_SATA_AHCI_P4SIG 0x324 +#define R_PCH_SATA_AHCI_P5SIG 0x3A4 +#define R_PCH_SATA_AHCI_P6SIG 0x424 +#define B_PCH_SATA_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_PCH_SATA_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_PCH_SATA_AHCI_PXSIG_SCR 0x000000FF +#define R_PCH_SATA_AHCI_P0SSTS 0x128 +#define R_PCH_SATA_AHCI_P1SSTS 0x1A8 +#define R_PCH_SATA_AHCI_P2SSTS 0x228 +#define R_PCH_SATA_AHCI_P3SSTS 0x2A8 +#define R_PCH_SATA_AHCI_P4SSTS 0x328 +#define R_PCH_SATA_AHCI_P5SSTS 0x3A8 +#define R_PCH_SATA_AHCI_P6SSTS 0x428 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_PCH_SATA_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_PCH_SATA_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSSTS_DET_0 0x00000000 +#define B_PCH_SATA_AHCI_PXSSTS_DET_1 0x00000001 +#define B_PCH_SATA_AHCI_PXSSTS_DET_3 0x00000003 +#define B_PCH_SATA_AHCI_PXSSTS_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SCTL 0x12C +#define R_PCH_SATA_AHCI_P1SCTL 0x1AC +#define R_PCH_SATA_AHCI_P2SCTL 0x22C +#define R_PCH_SATA_AHCI_P3SCTL 0x2AC +#define R_PCH_SATA_AHCI_P4SCTL 0x32C +#define R_PCH_SATA_AHCI_P5SCTL 0x3AC +#define R_PCH_SATA_AHCI_P6SCTL 0x42C +#define B_PCH_SATA_AHCI_PXSCTL_IPM 0x00000F00 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_PCH_SATA_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_PCH_SATA_AHCI_PXSCTL_SPD 0x000000F0 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_PCH_SATA_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_PCH_SATA_AHCI_PXSCTL_DET 0x0000000F +#define V_PCH_SATA_AHCI_PXSCTL_DET_0 0x00000000 +#define V_PCH_SATA_AHCI_PXSCTL_DET_1 0x00000001 +#define V_PCH_SATA_AHCI_PXSCTL_DET_4 0x00000004 +#define R_PCH_SATA_AHCI_P0SERR 0x130 +#define R_PCH_SATA_AHCI_P1SERR 0x1B0 +#define R_PCH_SATA_AHCI_P2SERR 0x230 +#define R_PCH_SATA_AHCI_P3SERR 0x2B0 +#define R_PCH_SATA_AHCI_P4SERR 0x330 +#define R_PCH_SATA_AHCI_P5SERR 0x3B0 +#define R_PCH_SATA_AHCI_P6SERR 0x430 +#define B_PCH_SATA_AHCI_PXSERR_EXCHG BIT26 +#define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_PCH_SATA_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_PCH_SATA_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_PCH_SATA_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_PCH_SATA_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_PCH_SATA_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_PCH_SATA_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_PCH_SATA_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_PCH_SATA_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_PCH_SATA_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_PCH_SATA_AHCI_PXSERR_PCDIE BIT9 +#define B_PCH_SATA_AHCI_PXSERR_TDIE BIT8 +#define B_PCH_SATA_AHCI_PXSERR_RCE BIT1 +#define B_PCH_SATA_AHCI_PXSERR_RDIE BIT0 +#define R_PCH_SATA_AHCI_P0SACT 0x134 +#define R_PCH_SATA_AHCI_P1SACT 0x1B4 +#define R_PCH_SATA_AHCI_P2SACT 0x234 +#define R_PCH_SATA_AHCI_P3SACT 0x2B4 +#define R_PCH_SATA_AHCI_P4SACT 0x334 +#define R_PCH_SATA_AHCI_P5SACT 0x3B4 +#define R_PCH_SATA_AHCI_P6SACT 0x434 +#define B_PCH_SATA_AHCI_PXSACT_DS 0xFFFFFFFF +#define R_PCH_SATA_AHCI_P0CI 0x138 +#define R_PCH_SATA_AHCI_P1CI 0x1B8 +#define R_PCH_SATA_AHCI_P2CI 0x238 +#define R_PCH_SATA_AHCI_P3CI 0x2B8 +#define R_PCH_SATA_AHCI_P4CI 0x338 +#define R_PCH_SATA_AHCI_P5CI 0x3B8 +#define R_PCH_SATA_AHCI_P6CI 0x438 +#define B_PCH_SATA_AHCI_PXCI 0xFFFFFFFF + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsScs.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsScs.h new file mode 100644 index 0000000000..b58618f49c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsScs.h @@ -0,0 +1,158 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_SCS_H_ +#define _PCH_REGS_SCS_H_ + +// +// SCS Devices PCI Config Space Registers +// +#define R_PCH_SCS_DEV_PCS 0x84 ///< PME Control Status +#define B_PCH_SCS_DEV_PCS_PMESTS BIT15 ///< PME Status +#define B_PCH_SCS_DEV_PCS_PMEEN BIT8 ///< PME Enable +#define B_PCH_SCS_DEV_PCS_NSS BIT3 ///< No Soft Reset +#define B_PCH_SCS_DEV_PCS_PS (BIT1 | BIT0) ///< Power State +#define B_PCH_SCS_DEV_PCS_PS_D3HOT (BIT1 | BIT0) ///< Power State: D3Hot State +#define R_PCH_SCS_DEV_PG_CONFIG 0xA2 ///< PG Config +#define B_PCH_SCS_DEV_PG_CONFIG_SE BIT3 ///< Sleep Enable +#define B_PCH_SCS_DEV_PG_CONFIG_PGE BIT2 ///< PG Enable +#define B_PCH_SCS_DEV_PG_CONFIG_I3E BIT1 ///< I3 Enable +#define B_PCH_SCS_DEV_PG_CONFIG_PMCRE BIT0 ///< PMC Request Enable +#define V_PCH_SCS_DEV_BAR0_SIZE 0x1000 ///< BAR0 size +// +// SCS Devices MMIO Space Register +// +#define R_PCH_SCS_DEV_MEM_DMAADR 0x00 +#define R_PCH_SCS_DEV_MEM_BLKSZ 0x04 +#define R_PCH_SCS_DEV_MEM_BLKCNT 0x06 +#define R_PCH_SCS_DEV_MEM_CMDARG 0x08 +#define R_PCH_SCS_DEV_MEM_XFRMODE 0x0C +#define B_PCH_SCS_DEV_MEM_XFRMODE_DMA_EN BIT0 +#define B_PCH_SCS_DEV_MEM_XFRMODE_BLKCNT_EN BIT1 +#define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3) +#define V_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD12_EN 1 +#define B_PCH_SCS_DEV_MEM_XFRMODE_DATA_TRANS_DIR BIT4 ///< 1: Read (Card to Host), 0: Write (Host to Card) +#define B_PCH_SCS_DEV_MEM_XFRMODE_MULTI_SINGLE_BLK BIT5 ///< 1: Multiple Block, 0: Single Block +#define R_PCH_SCS_DEV_MEM_SDCMD 0x0E +#define B_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_MASK (BIT0 | BIT1) +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_NO_RESP 0 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP136 1 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48 2 +#define V_PCH_SCS_DEV_MEM_SDCMD_RESP_TYPE_SEL_RESP48_CHK 3 +#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3 +#define B_PCH_SCS_DEV_MEM_SDCMD_CMD_INDEX_CHECK_EN BIT4 +#define B_PCH_SCS_DEV_MEM_SDCMD_DATA_PRESENT_SEL BIT5 +#define R_PCH_SCS_DEV_MEM_RESP 0x10 +#define R_PCH_SCS_DEV_MEM_BUFDATAPORT 0x20 +#define R_PCH_SCS_DEV_MEM_PSTATE 0x24 +#define B_PCH_SCS_DEV_MEM_PSTATE_DAT0 BIT20 +#define R_PCH_SCS_DEV_MEM_PWRCTL 0x29 +#define R_PCH_SCS_DEV_MEM_CLKCTL 0x2C +#define R_PCH_SCS_DEV_MEM_TIMEOUT_CTL 0x2E ///< Timeout Control +#define B_PCH_SCS_DEV_MEM_TIMEOUT_CTL_DTCV 0x0F ///< Data Timeout Counter Value +#define R_PCH_SCS_DEV_MEM_SWRST 0x2F +#define B_PCH_SCS_DEV_MEM_SWRST_CMDLINE BIT1 +#define B_PCH_SCS_DEV_MEM_SWRST_DATALINE BIT2 +#define R_PCH_SCS_DEV_MEM_NINTSTS 0x30 +#define B_PCH_SCS_DEV_MEM_NINTSTS_MASK 0xFFFF +#define B_PCH_SCS_DEV_MEM_NINTSTS_CLEAR_MASK 0x60FF +#define B_PCH_SCS_DEV_MEM_NINTSTS_CMD_COMPLETE BIT0 +#define B_PCH_SCS_DEV_MEM_NINTSTS_TRANSFER_COMPLETE BIT1 +#define B_PCH_SCS_DEV_MEM_NINTSTS_DMA_INTERRUPT BIT3 +#define B_PCH_SCS_DEV_MEM_NINTSTS_BUF_READ_READY_INTR BIT5 +#define R_PCH_SCS_DEV_MEM_ERINTSTS 0x32 +#define B_PCH_SCS_DEV_MEM_ERINTSTS_MASK 0x13FF +#define B_PCH_SCS_DEV_MEM_ERINTSTS_CLEAR_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_NINTEN 0x34 +#define B_PCH_SCS_DEV_MEM_NINTEN_MASK 0x7FFF +#define R_PCH_SCS_DEV_MEM_ERINTEN 0x36 +#define B_PCH_SCS_DEV_MEM_ERINTEN_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_NINTSIGNEN 0x38 +#define B_PCH_SCS_DEV_MEM_NINTSIGNEN_MASK 0x7FFF +#define R_PCH_SCS_DEV_MEM_ERINTSIGNEN 0x3A +#define B_PCH_SCS_DEV_MEM_ERINTSIGNEN_MASK 0x13FF +#define R_PCH_SCS_DEV_MEM_HOST_CTL2 0x3E +#define B_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_MASK (BIT0 | BIT1 | BIT2) +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_HS400 5 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_DDR50 4 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR104 3 +#define V_PCH_SCS_DEV_MEM_HOST_CTL2_MODE_SDR25 1 +#define R_PCH_SCS_DEV_MEM_CAP1 0x40 +#define R_PCH_SCS_DEV_MEM_CAP2 0x44 +#define B_PCH_SCS_DEV_MEM_CAP2_HS400_SUPPORT BIT31 +#define B_PCH_SCS_DEV_MEM_CAP2_SDR104_SUPPORT BIT1 +#define R_PCH_SCS_DEV_MEM_CESHC2 0x3C ///< Auto CMD12 Error Status Register & Host Control 2 +#define B_PCH_SCS_DEV_MEM_CESHC2_ASYNC_INT BIT30 ///< Asynchronous Interrupt Enable +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL 0x810 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_CONTROL_EN 0x5A +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1 0x814 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_EMMC_DEFAULTS 0x3C80EB1E +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDIO_DEFAULTS 0x1C80EF1E +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SDCARD_DEFAULTS 0x1C80E75C +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_HS400 BIT29 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ (BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 22 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMEOUT_CLK_FREQ 0x1 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT (BIT20 | BIT19 | BIT18 | BIT17) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 17 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_TIMER_COUNT 0x8 +#define B_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE (BIT12 | BIT11) +#define N_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE 11 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG1_SLOT_TYPE_EMBEDDED 0x1 +#define R_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2 0x818 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_EMMC_DEFAULTS 0x040040C8 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDIO_DEFAULTS 0x040000C8 +#define V_PCH_SCS_DEV_MEM_CAP_BYPASS_REG2_SDCARD_DEFAULTS 0x040000C8 +#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL1 0x820 +#define R_PCH_SCS_DEV_MEM_TX_CMD_DLL_CNTL2 0x80C +#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL1 0x824 +#define R_PCH_SCS_DEV_MEM_TX_DATA_DLL_CNTL2 0x828 +#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL1 0x82C +#define R_PCH_SCS_DEV_MEM_RX_STROBE_DLL_CNTL 0x830 +#define R_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2 0x834 +#define N_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX 16 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AUTO 0x2 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_BEFORE 0x1 +#define V_PCH_SCS_DEV_MEM_RX_CMD_DATA_DLL_CNTL2_CLKSRC_RX_CLK_AFTER 0x0 + +// +// SCS Private Configuration Space Registers +// +#define R_PCH_PCR_SCS_IOSFCTL 0x00 ///< IOSF Control +#define B_PCH_PCR_SCS_IOSFCTL_NSNPDIS BIT7 ///< Non-Snoop Disable +#define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BIT0) ///< Max upstream pending reads +#define R_PCH_PCR_SCS_OCPCTL 0x10 ///< OCP Control +#define B_PCH_PCR_SCS_OCPCTL_NPEN BIT0 ///< Downstream non-posted memory write capability +#define R_PCH_PCR_SCS_PMCTL 0x1D0 ///< Power Management Control +#define R_PCH_PCR_SCS_PCICFGCTR1 0x200 ///< PCI Configuration Control 1 - eMMC +#define R_PCH_PCR_SCS_PCICFGCTR2 0x204 ///< PCI Configuration Control 2 - SDIO +#define R_PCH_PCR_SCS_PCICFGCTR3 0x208 ///< PCI Configuration Control 3 - SD Card +#define B_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 0x0FF00000 ///< PCI IRQ number +#define N_PCH_PCR_SCS_PCICFGCTR_PCI_IRQ 20 +#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 0x000FF000 ///< ACPI IRQ number +#define N_PCH_PCR_SCS_PCICFGCTR_ACPI_IRQ 12 +#define B_PCH_PCR_SCS_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) ///< Interrupt Pin +#define N_PCH_PCR_SCS_PCICFGCTR_IPIN1 8 +#define B_PCH_PCR_SCS_PCICFGCTR_BAR1DIS BIT7 ///< BAR 1 Disable +#define B_PCH_PCR_SCS_PCICFGCTR_PS 0x7C ///< PME Support +#define B_PCH_PCR_SCS_PCICFGCTR_ACPI_INT_EN BIT1 ///< ACPI Interrupt Enable +#define B_PCH_PCR_SCS_PCICFGCTR_PCI_CFG_DIS BIT0 ///< PCI Configuration Space Disable + +#define R_PCH_PCR_SCS_GPPRVRW1 0x600 ///< Clock Gating Control +#define R_PCH_PCR_SCS_GPPRVRW2 0x604 ///< Host Controller Disable +#define B_PCH_PCR_SCS_GPPRVRW2_EMMC_DIS BIT1 ///< eMMC Host Controller Disable +#define B_PCH_PCR_SCS_GPPRVRW2_SDIO_SDCARD_DIS BIT2 ///< 1: SDIO Host Controller Disable, 0: SDCARD Host Controller Disable +#define R_PCH_PCR_SCS_GPPRVRW6 0x614 ///< 1.8V Signal Select Delay Control +#define V_PCH_PCR_SCS_GPPRVRW6_1P8_SEL_DELAY 0x7F ///< Rcomp SDCARD 10ms delay during switch + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSerialIo.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSerialIo.h new file mode 100644 index 0000000000..e0d048b94e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSerialIo.h @@ -0,0 +1,288 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_SERIAL_IO_ +#define _PCH_REGS_SERIAL_IO_ + + +// +// Serial IO I2C0 Controller Registers (D21:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0 +#define V_PCH_LP_SERIAL_IO_I2C0_SKL_DEVICE_ID 0x9D60 +#define V_PCH_H_SERIAL_IO_I2C0_SKL_DEVICE_ID 0xA160 + +// +// Serial IO I2C1 Controller Registers (D21:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1 +#define V_PCH_LP_SERIAL_IO_I2C1_SKL_DEVICE_ID 0x9D61 +#define V_PCH_H_SERIAL_IO_I2C1_SKL_DEVICE_ID 0xA161 + +// +// Serial IO I2C2 Controller Registers (D21:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2 +#define V_PCH_LP_SERIAL_IO_I2C2_SKL_DEVICE_ID 0x9D62 +#define V_PCH_H_SERIAL_IO_I2C2_SKL_DEVICE_ID 0xA162 + +// +// Serial IO I2C3 Controller Registers (D21:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3 +#define V_PCH_LP_SERIAL_IO_I2C3_SKL_DEVICE_ID 0x9D63 +#define V_PCH_H_SERIAL_IO_I2C3_SKL_DEVICE_ID 0xA163 + +// +// Serial IO I2C4 Controller Registers (D25:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 2 +#define V_PCH_LP_SERIAL_IO_I2C4_SKL_DEVICE_ID 0x9D64 + +// +// Serial IO I2C5 Controller Registers (D25:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1 +#define V_PCH_LP_SERIAL_IO_I2C5_SKL_DEVICE_ID 0x9D65 + +// +// Serial IO SPI0 Controller Registers (D30:F2) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2 +#define V_PCH_LP_SERIAL_IO_SPI0_SKL_DEVICE_ID 0x9D29 +#define V_PCH_H_SERIAL_IO_SPI0_SKL_DEVICE_ID 0xA129 + +// +// Serial IO SPI1 Controller Registers (D30:F3) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3 +#define V_PCH_LP_SERIAL_IO_SPI1_SKL_DEVICE_ID 0x9D2A +#define V_PCH_H_SERIAL_IO_SPI1_SKL_DEVICE_ID 0xA129 + +// +// Serial IO UART0 Controller Registers (D30:F0) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0 +#define V_PCH_LP_SERIAL_IO_UART0_SKL_DEVICE_ID 0x9D28 +#define V_PCH_H_SERIAL_IO_UART0_SKL_DEVICE_ID 0xA128 + +// +// Serial IO UART1 Controller Registers (D30:F1) +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1 +#define V_PCH_LP_SERIAL_IO_UART1_SKL_DEVICE_ID 0x9D66 +#define V_PCH_H_SERIAL_IO_UART1_SKL_DEVICE_ID 0xA166 + +#define V_PCH_SERIAL_IO_DEV_MIN_FUN 0 +#define V_PCH_SERIAL_IO_DEV_MAX_FUN 5 + +// +// Serial IO Controllers General PCI Configuration Registers +// registers accessed using PciD21FxRegBase + offset +// +#define R_PCH_SERIAL_IO_BAR0_LOW 0x10 +#define B_PCH_SERIAL_IO_BAR0_LOW_BAR 0xFFFFF000 +#define R_PCH_SERIAL_IO_BAR0_HIGH 0x14 +#define R_PCH_SERIAL_IO_BAR1_LOW 0x18 +#define B_PCH_SERIAL_IO_BAR1_LOW_BAR 0xFFFFF000 +#define R_PCH_SERIAL_IO_BAR1_HIGH 0x1C +#define V_PCH_SERIAL_IO_BAR_SIZE (4 * 1024) +#define N_PCH_SERIAL_IO_BAR_ALIGNMENT 12 + +#define R_PCH_SERIAL_IO_PME_CTRL_STS 0x84 +#define B_PCH_SERIAL_IO_PME_CTRL_STS_PWR_ST (BIT1| BIT0) + +#define R_PCH_SERIAL_IO_D0I3MAXDEVPG 0xA0 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PMCRE BIT16 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_I3E BIT17 +#define B_PCH_SERIAL_IO_D0I3MAXDEVPG_PGE BIT18 + +#define R_PCH_SERIAL_IO_INTERRUPTREG 0x3C +#define B_PCH_SERIAL_IO_INTERRUPTREG_INTLINE 0x000000FF + +// +// Serial IO Controllers Private Registers +// registers accessed : BAR0 + offset +// +#define R_PCH_SERIAL_IO_SSCR1 0x4 +#define B_PCH_SERIAL_IO_SSCR1_IFS BIT16 + +#define R_PCH_SERIAL_IO_PPR_CLK 0x200 +#define B_PCH_SERIAL_IO_PPR_CLK_EN BIT0 +#define B_PCH_SERIAL_IO_PPR_CLK_UPDATE BIT31 +#define V_PCH_SERIAL_IO_PPR_CLK_M_DIV 0x30 +#define V_PCH_SERIAL_IO_PPR_CLK_N_DIV 0xC35 + +#define R_PCH_SERIAL_IO_PPR_RESETS 0x204 +#define B_PCH_SERIAL_IO_PPR_RESETS_FUNC BIT0 +#define B_PCH_SERIAL_IO_PPR_RESETS_APB BIT1 +#define B_PCH_SERIAL_IO_PPR_RESETS_IDMA BIT2 + +#define R_PCH_SERIAL_IO_ACTIVE_LTR 0x210 +#define R_PCH_SERIAL_IO_IDLE_LTR 0x214 +#define B_PCH_SERIAL_IO_LTR_SNOOP_VALUE 0x000003FF +#define B_PCH_SERIAL_IO_LTR_SNOOP_SCALE 0x00001C00 +#define B_PCH_SERIAL_IO_LTR_SNOOP_REQUIREMENT BIT15 + +#define R_PCH_SERIAL_IO_SPI_CS_CONTROL 0x224 +#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_STATE BIT1 +#define B_PCH_SERIAL_IO_SPI_CS_CONTROL_MODE BIT0 + +#define R_PCH_SERIAL_IO_REMAP_ADR_LOW 0x240 +#define R_PCH_SERIAL_IO_REMAP_ADR_HIGH 0x244 + +#define R_PCH_SERIAL_IO_I2C_SDA_HOLD 0x7C +#define V_PCH_SERIAL_IO_I2C_SDA_HOLD_VALUE 0x002C002C + +// +// I2C Controller +// Registers accessed through BAR0 + offset +// +#define R_IC_CON 0x00 // I2c Control +#define B_IC_MASTER_MODE BIT0 +#define B_IC_RESTART_EN BIT5 +#define B_IC_SLAVE_DISABLE BIT6 +#define V_IC_SPEED_STANDARD 0x02 +#define V_IC_SPEED_FAST 0x04 +#define V_IC_SPEED_HIGH 0x06 + +#define R_IC_TAR 0x04 // I2c Target Address +#define B_IC_TAR_10BITADDR_MASTER BIT12 + +#define R_IC_DATA_CMD 0x10 // I2c Rx/Tx Data Buffer and Command +#define B_IC_CMD_READ BIT8 // 1 = read, 0 = write +#define B_IC_CMD_STOP BIT9 // 1 = STOP +#define B_IC_CMD_RESTART BIT10 // 1 = IC_RESTART_EN +#define V_IC_WRITE_CMD_MASK 0xFF + +#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2c Clock SCL High Count +#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2c Clock SCL Low Count +#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2c Clock SCL High Count +#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2c Clock SCL Low Count +#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2c Clock SCL High Count +#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2c Clock SCL Low Count +#define R_IC_INTR_STAT 0x2C // I2c Inetrrupt Status +#define R_IC_INTR_MASK 0x30 // I2c Interrupt Mask +#define B_IC_INTR_GEN_CALL BIT11 // General call received +#define B_IC_INTR_START_DET BIT10 +#define B_IC_INTR_STOP_DET BIT9 +#define B_IC_INTR_ACTIVITY BIT8 +#define B_IC_INTR_TX_ABRT BIT6 // Set on NACK +#define B_IC_INTR_TX_EMPTY BIT4 +#define B_IC_INTR_TX_OVER BIT3 +#define B_IC_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold +#define B_IC_INTR_RX_OVER BIT1 +#define B_IC_INTR_RX_UNDER BIT0 +#define R_IC_RAW_INTR_STAT ( 0x34) // I2c Raw Interrupt Status +#define R_IC_RX_TL ( 0x38) // I2c Receive FIFO Threshold +#define R_IC_TX_TL ( 0x3C) // I2c Transmit FIFO Threshold +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt +#define R_IC_ENABLE ( 0x6C) // I2c Enable + +#define R_IC_STATUS 0x70 // I2c Status +#define B_IC_STATUS_RFF BIT4 // RX FIFO is completely full +#define B_IC_STATUS_RFNE BIT3 // RX FIFO is not empty +#define B_IC_STATUS_TFE BIT2 // TX FIFO is completely empty +#define B_IC_STATUS_TFNF BIT1 // TX FIFO is not full +#define B_IC_STATUS_ACTIVITY BIT0 // Controller Activity Status. + +#define R_IC_TXFL R ( 0x74) // Transmit FIFO Level Register +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register +#define R_IC_SDA_HOLD ( 0x7C) +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2c Transmit Abort Status Register +#define B_IC_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit address + +#define R_IC_SDA_SETUP ( 0x94) // I2c SDA Setup Register +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2c ACK General Call Register +#define R_IC_ENABLE_STATUS ( 0x9C) // I2c Enable Status Register +#define B_IC_EN BIT0 // I2c enable status + +#define R_IC_CLK_GATE (0xC0) +#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register +#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID +#define R_IC_COMP_TYPE ( 0xFC) // Component Type + + + +// +// Bridge Private Configuration Registers +// accessed only through SB messaging. SB access = SerialIo IOSF2OCP Bridge Port ID + offset +// +#define R_PCH_PCR_SERIAL_IO_PMCTL 0x1D0 +#define V_PCH_PCR_SERIAL_IO_PMCTL_PWR_GATING 0x3F + +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRLx 0x200 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_N_OFFS 0x04 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL1 0x200 //I2C0 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL2 0x204 //I2C1 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL3 0x208 //I2C2 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL4 0x20C //I2C3 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL5 0x210 //I2C4 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL6 0x214 //I2C5 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL9 0x218 //UA00 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL10 0x21C //UA01 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL11 0x220 //UA02 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL13 0x224 //SPI0 +#define R_PCH_PCR_SERIAL_IO_PCICFGCTRL14 0x228 //SPI1 + +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_CFG_DIS BIT0 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_INTR_EN BIT1 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_BAR1_DIS BIT7 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9 | BIT8) +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_INT_PIN 8 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTA 0x01 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTB 0x02 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTC 0x03 +#define V_PCH_PCR_SERIAL_IO_PCICFGCTRL_INTD 0x04 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_SERIAL_IO_PCICFGCTRL_PCI_IRQ 20 + +#define R_PCH_PCR_SERIAL_IO_GPPRVRW2 0x604 +#define V_PCH_PCR_SERIAL_IO_GPPRVRW2_CLK_GATING (BIT11 | BIT1) + +#define R_PCH_PCR_SERIAL_IO_GPPRVRW7 0x618 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART1_BYTE_ADDR_EN BIT1 +#define B_PCH_PCR_SERIAL_IO_GPPRVRW7_UART2_BYTE_ADDR_EN BIT2 + +// +// Number of pins used by SerialIo controllers +// +#define PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER 2 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 +#define PCH_SERIAL_IO_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSmbus.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSmbus.h new file mode 100644 index 0000000000..cc04d39653 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSmbus.h @@ -0,0 +1,140 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers (D31:F4) +// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 +#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_SMBUS_DEVICE_ID 0xA123 +// +// LBG Production SMBus Controller Device ID +// +#define V_PCH_LBG_PROD_SMBUS_DEVICE_ID 0xA1A3 +// +// LBG SSX (Super SKU) SMBus Controller Device ID +// +#define V_PCH_LBG_SMBUS_DEVICE_ID 0xA223 +#define V_PCH_LP_SMBUS_DEVICE_ID 0x9D23 +#define R_PCH_SMBUS_BASE 0x20 +#define V_PCH_SMBUS_BASE_SIZE (1 << 5) +#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_SPDWD BIT4 +#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 +#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 +#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 +#define R_PCH_SMBUS_TCOBASE 0x50 +#define B_PCH_SMBUS_TCOBASE_BAR 0x0000FFE0 +#define R_PCH_SMBUS_TCOCTL 0x54 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_EN BIT8 +#define B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK BIT0 +#define R_PCH_SMBUS_64 0x64 +#define R_PCH_SMBUS_80 0x80 + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 ///< Host Status Register R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define B_PCH_SMBUS_INTR 0x02 +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_FAIL 0x10 +#define B_PCH_SMBUS_SMBALERT_STS 0x20 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_ERROR (B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR | B_PCH_SMBUS_FAIL) +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define R_PCH_SMBUS_HCTL 0x02 ///< Host Control Register R/W +#define B_PCH_SMBUS_INTREN 0x01 +#define B_PCH_SMBUS_KILL 0x02 +#define B_PCH_SMBUS_SMB_CMD 0x1C +#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 +#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 +#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 +#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C +#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 +#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 +#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 +#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C +#define B_PCH_SMBUS_LAST_BYTE 0x20 +#define B_PCH_SMBUS_START 0x40 +#define B_PCH_SMBUS_PEC_EN 0x80 +#define R_PCH_SMBUS_HCMD 0x03 ///< Host Command Register R/W +#define R_PCH_SMBUS_TSA 0x04 ///< Transmit Slave Address Register R/W +#define B_PCH_SMBUS_RW_SEL 0x01 +#define B_PCH_SMBUS_READ 0x01 // RW +#define B_PCH_SMBUS_WRITE 0x00 // RW +#define B_PCH_SMBUS_ADDRESS 0xFE +#define R_PCH_SMBUS_HD0 0x05 ///< Data 0 Register R/W +#define R_PCH_SMBUS_HD1 0x06 ///< Data 1 Register R/W +#define R_PCH_SMBUS_HBD 0x07 ///< Host Block Data Register R/W +#define R_PCH_SMBUS_PEC 0x08 ///< Packet Error Check Data Register R/W +#define R_PCH_SMBUS_RSA 0x09 ///< Receive Slave Address Register R/W +#define B_PCH_SMBUS_SLAVE_ADDR 0x7F +#define R_PCH_SMBUS_SD 0x0A ///< Receive Slave Data Register R/W +#define R_PCH_SMBUS_AUXS 0x0C ///< Auxiliary Status Register R/WC +#define B_PCH_SMBUS_CRCE 0x01 +#define B_PCH_SMBUS_STCO 0x02 ///< SMBus TCO Mode +#define R_PCH_SMBUS_AUXC 0x0D ///< Auxiliary Control Register R/W +#define B_PCH_SMBUS_AAC 0x01 +#define B_PCH_SMBUS_E32B 0x02 +#define R_PCH_SMBUS_SMLC 0x0E ///< SMLINK Pin Control Register R/W +#define B_PCH_SMBUS_SMLINK0_CUR_STS 0x01 +#define B_PCH_SMBUS_SMLINK1_CUR_STS 0x02 +#define B_PCH_SMBUS_SMLINK_CLK_CTL 0x04 +#define R_PCH_SMBUS_SMBC 0x0F ///< SMBus Pin Control Register R/W +#define B_PCH_SMBUS_SMBCLK_CUR_STS 0x01 +#define B_PCH_SMBUS_SMBDATA_CUR_STS 0x02 +#define B_PCH_SMBUS_SMBCLK_CTL 0x04 +#define R_PCH_SMBUS_SSTS 0x10 ///< Slave Status Register R/WC +#define B_PCH_SMBUS_HOST_NOTIFY_STS 0x01 +#define R_PCH_SMBUS_SCMD 0x11 ///< Slave Command Register R/W +#define B_PCH_SMBUS_HOST_NOTIFY_INTREN 0x01 +#define B_PCH_SMBUS_HOST_NOTIFY_WKEN 0x02 +#define B_PCH_SMBUS_SMBALERT_DIS 0x04 +#define R_PCH_SMBUS_NDA 0x14 ///< Notify Device Address Register RO +#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE +#define R_PCH_SMBUS_NDLB 0x16 ///< Notify Data Low Byte Register RO +#define R_PCH_SMBUS_NDHB 0x17 ///< Notify Data High Byte Register RO + +// +// SMBus Private Config Registers +// (PID:SMB) +// +#define R_PCH_PCR_SMBUS_TCOCFG 0x00 ///< TCO Configuration register +#define B_PCH_PCR_SMBUS_TCOCFG_IE BIT7 ///< TCO IRQ Enable +#define B_PCH_PCR_SMBUS_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_9 0x00 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_10 0x01 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_11 0x02 +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled +#define V_PCH_PCR_SMBUS_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled +#define R_PCH_PCR_SMBUS_SMBTM 0x04 ///< SMBus Test Mode +#define B_PCH_PCR_SMBUS_SMBTM_SMBCT BIT1 ///< SMBus Counter +#define B_PCH_PCR_SMBUS_SMBTM_SMBDG BIT0 ///< SMBus Deglitch +#define R_PCH_PCR_SMBUS_SCTM 0x08 ///< Short Counter Test Mode +#define B_PCH_PCR_SMBUS_SCTM_SSU BIT31 ///< Simulation Speed-Up +#define R_PCH_PCR_SMBUS_GC 0x0C ///< General Control +#define B_PCH_PCR_SMBUS_GC_FD BIT0 ///< Function Disable +#define B_PCH_PCR_SMBUS_GC_NR BIT1 ///< No Reboot +#define B_PCH_PCR_SMBUS_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSpi.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSpi.h new file mode 100644 index 0000000000..cab12792d1 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsSpi.h @@ -0,0 +1,297 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +// +// SPI Registers (D31:F5) +// + +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 +#define V_PCH_SPI_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_SPI_DEVICE_ID 0xA124 +// +// LBG PRODUCTION SPI Device ID +// +#define V_PCH_LBG_PROD_SPI_DEVICE_ID 0xA1A4 +// +// LBG SSX (Super SKU) SPI Device ID +// +#define V_PCH_LBG_SPI_DEVICE_ID 0xA224 +#define V_PCH_LP_SPI_DEVICE_ID 0x9D24 +#define R_PCH_SPI_BAR0 0x10 +#define B_PCH_SPI_BAR0_MASK 0x0FFF + +#define R_PCH_SPI_BDE 0xD8 +#define B_PCH_SPI_BDE_F8 0x8000 +#define B_PCH_SPI_BDE_F0 0x4000 +#define B_PCH_SPI_BDE_E8 0x2000 +#define B_PCH_SPI_BDE_E0 0x1000 +#define B_PCH_SPI_BDE_D8 0x0800 +#define B_PCH_SPI_BDE_D0 0x0400 +#define B_PCH_SPI_BDE_C8 0x0200 +#define B_PCH_SPI_BDE_C0 0x0100 +#define B_PCH_SPI_BDE_LEG_F 0x0080 +#define B_PCH_SPI_BDE_LEG_E 0x0040 +#define B_PCH_SPI_BDE_70 0x0008 +#define B_PCH_SPI_BDE_60 0x0004 +#define B_PCH_SPI_BDE_50 0x0002 +#define B_PCH_SPI_BDE_40 0x0001 + +#define R_PCH_SPI_BC 0xDC +#define S_PCH_SPI_BC 4 +#define N_PCH_SPI_BC_ASE_BWP 11 +#define B_PCH_SPI_BC_ASE_BWP BIT11 +#define N_PCH_SPI_BC_ASYNC_SS 10 +#define B_PCH_SPI_BC_ASYNC_SS BIT10 +#define B_PCH_SPI_BC_OSFH BIT9 ///< OS Function Hide +#define N_PCH_SPI_BC_SYNC_SS 8 +#define B_PCH_SPI_BC_SYNC_SS BIT8 +#define B_PCH_SPI_BC_BILD BIT7 +#define B_PCH_SPI_BC_BBS BIT6 ///< Boot BIOS strap +#define N_PCH_SPI_BC_BBS 6 +#define V_PCH_SPI_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI +#define V_PCH_SPI_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC +#define B_PCH_SPI_BC_EISS BIT5 ///< Enable InSMM.STS +#define B_PCH_SPI_BC_TSS BIT4 +#define B_PCH_SPI_BC_SRC (BIT3 | BIT2) +#define N_PCH_SPI_BC_SRC 2 +#define V_PCH_SPI_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetching and Caching enabled +#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching +#define V_PCH_SPI_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefetching, but caching enabled +#define B_PCH_SPI_BC_LE BIT1 ///< Lock Enable +#define N_PCH_SPI_BC_BLE 1 +#define B_PCH_SPI_BC_WPD BIT0 ///< Write Protect Disable + +// +// BIOS Flash Program Registers (based on SPI_BAR0) +// +#define R_PCH_SPI_BFPR 0x00 ///< BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1 +#define B_PCH_SPI_BFPR_PRL 0x7FFF0000 ///< BIOS Flash Primary Region Limit mask +#define N_PCH_SPI_BFPR_PRL 16 ///< BIOS Flash Primary Region Limit bit position +#define B_PCH_SPI_BFPR_PRB 0x00007FFF ///< BIOS Flash Primary Region Base mask +#define N_PCH_SPI_BFPR_PRB 0 ///< BIOS Flash Primary Region Base bit position +#define R_PCH_SPI_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits) +#define B_PCH_SPI_HSFSC_FSMIE BIT31 ///< Flash SPI SMI# Enable +#define B_PCH_SPI_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1. +#define N_PCH_SPI_HSFSC_FDBC 24 +#define B_PCH_SPI_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle. +#define N_PCH_SPI_HSFSC_CYCLE 17 +#define V_PCH_SPI_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read +#define V_PCH_SPI_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write +#define V_PCH_SPI_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase +#define V_PCH_SPI_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase +#define V_PCH_SPI_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP +#define V_PCH_SPI_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID +#define V_PCH_SPI_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status +#define V_PCH_SPI_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status +#define B_PCH_SPI_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go. +#define B_PCH_SPI_HSFSC_FLOCKDN BIT15 ///< Flash Configuration Lock-Down +#define B_PCH_SPI_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs +#define B_PCH_SPI_HSFSC_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status +#define B_PCH_SPI_HSFSC_PRR34_LOCKDN BIT12 ///< PRR3 PRR4 Lock-Down +#define B_PCH_SPI_HSFSC_SAF_CE BIT8 ///< SAF ctype error +#define B_PCH_SPI_HSFSC_SAF_MODE_ACTIVE BIT7 ///< Indicates flash is attached either directly to the PCH via the SPI bus or EC/BMC +#define B_PCH_SPI_HSFSC_SAF_LE BIT6 ///< SAF link error +#define B_PCH_SPI_HSFSC_SCIP BIT5 ///< SPI cycle in progress +#define B_PCH_SPI_HSFSC_SAF_DLE BIT4 ///< SAF Data length error +#define B_PCH_SPI_HSFSC_SAF_ERROR BIT3 ///< SAF Error +#define B_PCH_SPI_HSFSC_AEL BIT2 ///< Access Error Log +#define B_PCH_SPI_HSFSC_FCERR BIT1 ///< Flash Cycle Error +#define B_PCH_SPI_HSFSC_FDONE BIT0 ///< Flash Cycle Done +#define R_PCH_SPI_FADDR 0x08 ///< SPI Flash Address +#define B_PCH_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit) +#define R_PCH_SPI_DLOCK 0x0C ///< Discrete Lock Bits +#define B_PCH_SPI_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN +#define R_PCH_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits) +#define R_PCH_SPI_FDATA01 0x14 ///< SPI Data 01 +#define R_PCH_SPI_FDATA02 0x18 ///< SPI Data 02 +#define R_PCH_SPI_FDATA03 0x1C ///< SPI Data 03 +#define R_PCH_SPI_FDATA04 0x20 ///< SPI Data 04 +#define R_PCH_SPI_FDATA05 0x24 ///< SPI Data 05 +#define R_PCH_SPI_FDATA06 0x28 ///< SPI Data 06 +#define R_PCH_SPI_FDATA07 0x2C ///< SPI Data 07 +#define R_PCH_SPI_FDATA08 0x30 ///< SPI Data 08 +#define R_PCH_SPI_FDATA09 0x34 ///< SPI Data 09 +#define R_PCH_SPI_FDATA10 0x38 ///< SPI Data 10 +#define R_PCH_SPI_FDATA11 0x3C ///< SPI Data 11 +#define R_PCH_SPI_FDATA12 0x40 ///< SPI Data 12 +#define R_PCH_SPI_FDATA13 0x44 ///< SPI Data 13 +#define R_PCH_SPI_FDATA14 0x48 ///< SPI Data 14 +#define R_PCH_SPI_FDATA15 0x4C ///< SPI Data 15 +#define R_PCH_SPI_FRAP 0x50 ///< Flash Region Access Permisions Register +#define B_PCH_SPI_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData +#define N_PCH_SPI_FRAP_BRWA 8 ///< BIOS Region Write Access bit position +#define B_PCH_SPI_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData +#define B_PCH_SPI_FRAP_BMRAG_MASK 0x00FF0000 ///< BIOS Master Read Access Grant +#define B_PCH_SPI_FRAP_BMWAG_MASK 0xFF000000 ///< BIOS Master Write Access Grant +#define R_PCH_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits) +#define R_PCH_SPI_FREG1_BIOS 0x58 ///< Flash Region 1(BIOS)(32bits) +#define R_PCH_SPI_FREG2_ME 0x5C ///< Flash Region 2(ME)(32bits) +#define R_PCH_SPI_FREG3_GBE 0x60 ///< Flash Region 3(GbE)(32bits) +#define R_PCH_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4(Platform Data)(32bits) +#define R_PCH_SPI_FREG5_DER 0x68 ///< Flash Region 5(Device Expansion Region)(32bits) +#define S_PCH_SPI_FREGX 4 ///< Size of Flash Region register +#define B_PCH_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh +#define N_PCH_SPI_FREGX_LIMIT 16 ///< Region limit bit position +#define N_PCH_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position +#define B_PCH_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12] +#define N_PCH_SPI_FREGX_BASE 0 ///< Region base bit position +#define N_PCH_SPI_FREGX_BASE_REPR 12 ///< Region base bit represents position +#define R_PCH_SPI_PR0 0x84 ///< Protected Region 0 Register +#define R_PCH_SPI_PR1 0x88 ///< Protected Region 1 Register +#define R_PCH_SPI_PR2 0x8C ///< Protected Region 2 Register +#define R_PCH_SPI_PR3 0x90 ///< Protected Region 3 Register +#define R_PCH_SPI_PR4 0x94 ///< Protected Region 4 Register +#define S_PCH_SPI_PRX 4 ///< Protected Region X Register size +#define B_PCH_SPI_PRX_WPE BIT31 ///< Write Protection Enable +#define B_PCH_SPI_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12] +#define N_PCH_SPI_PRX_PRL 16 ///< Protected Range Limit bit position +#define B_PCH_SPI_PRX_RPE BIT15 ///< Read Protection Enable +#define B_PCH_SPI_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12] +#define N_PCH_SPI_PRX_PRB 0 ///< Protected Range Base bit position +#define R_PCH_SPI_SFRAP 0xB0 ///< Secondary Flash Regions Access Permisions Register +#define R_PCH_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits) +#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select +#define V_PCH_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map +#define V_PCH_SPI_FDOC_FDSS_COMP 0x1000 ///< Component +#define V_PCH_SPI_FDOC_FDSS_REGN 0x2000 ///< Region +#define V_PCH_SPI_FDOC_FDSS_MSTR 0x3000 ///< Master +#define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 ///< PCH soft straps +#define V_PCH_SPI_FDOC_FDSS_SFDP 0x5000 ///< SFDP Parameter Table +#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index +#define R_PCH_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits) +#define R_PCH_SPI_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_PCH_SPI_SFDPX_VSCCX_CPPTV BIT31 ///< Component Property Parameter Table Valid +#define B_PCH_SPI_SFDP0_VSCC0_VCL BIT30 ///< Vendor Component Lock +#define B_PCH_SPI_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid) +#define B_PCH_SPI_SFDPX_VSCCX_EO_4K BIT28 ///< 4k Erase valid (EO_4k_valid) +#define B_PCH_SPI_SFDPX_VSCCX_RPMC BIT27 ///< RPMC Supported +#define B_PCH_SPI_SFDPX_VSCCX_DPD BIT26 ///< Deep Powerdown Supported +#define B_PCH_SPI_SFDPX_VSCCX_SUSRES BIT25 ///< Suspend/Resume Supported +#define B_PCH_SPI_SFDPX_VSCCX_SOFTRES BIT24 ///< Soft Reset Supported +#define B_PCH_SPI_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 ///< 64k Erase Opcode (EO_64k) +#define B_PCH_SPI_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 ///< 4k Erase Opcode (EO_4k) +#define B_PCH_SPI_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) ///< Quad Enable Requirements +#define B_PCH_SPI_SFDPX_VSCCX_WEWS BIT4 ///< Write Enable on Write Status +#define B_PCH_SPI_SFDPX_VSCCX_WSR BIT3 ///< Write Status Required +#define B_PCH_SPI_SFDPX_VSCCX_WG_64B BIT2 ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define R_PCH_SPI_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits) +#define R_PCH_SPI_PINTX 0xCC ///< Parameter Table Index +#define N_PCH_SPI_PINTX_SPT 14 +#define V_PCH_SPI_PINTX_SPT_CPT0 0x0 ///< Component 0 Property Parameter Table +#define V_PCH_SPI_PINTX_SPT_CPT1 0x1 ///< Component 1 Property Parameter Table +#define N_PCH_SPI_PINTX_HORD 12 +#define V_PCH_SPI_PINTX_HORD_SFDP 0x0 ///< SFDP Header +#define V_PCH_SPI_PINTX_HORD_PT 0x1 ///< Parameter Table Header +#define V_PCH_SPI_PINTX_HORD_DATA 0x2 ///< Data +#define R_PCH_SPI_PTDATA 0xD0 ///< Parameter Table Data +#define R_PCH_SPI_SBRS 0xD4 ///< SPI Bus Requester Status +#define R_PCH_SPI_SSML 0xF0 ///< Set Strap Msg Lock +#define B_PCH_SPI_SSML_SSL BIT0 ///< Set_Strap Lock +#define R_PCH_SPI_SSMC 0xF4 ///< Set Strap Msg Control +#define B_PCH_SPI_SSMC_SSMS BIT0 ///< Set_Strap Mux Select +#define R_PCH_SPI_SSMD 0xF8 ///< Set Strap Msg Data +// +// @todo Follow up with EDS owner if it should be 3FFF or FFFF. +// +#define B_PCH_SPI_SRD_SSD 0x0000FFFF ///< Set_Strap Data +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_PCH_SPI_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature +#define V_PCH_SPI_FDBAR_FLVALSIG 0x0FF0A55A +#define R_PCH_SPI_FDBAR_FLASH_MAP0 0x04 +#define B_PCH_SPI_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address +#define B_PCH_SPI_FDBAR_NC 0x00000300 ///< Number Of Components +#define N_PCH_SPI_FDBAR_NC 8 ///< Number Of Components +#define V_PCH_SPI_FDBAR_NC_1 0x00000000 +#define V_PCH_SPI_FDBAR_NC_2 0x00000100 +#define B_PCH_SPI_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address +#define B_PCH_SPI_FDBAR_NR 0x07000000 ///< Number Of Regions +#define R_PCH_SPI_FDBAR_FLASH_MAP1 0x08 +#define B_PCH_SPI_FDBAR_FMBA 0x000000FF ///< Flash Master Base Address +#define B_PCH_SPI_FDBAR_NM 0x00000700 ///< Number Of Masters +#define B_PCH_SPI_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4] +#define N_PCH_SPI_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position +#define N_PCH_SPI_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position +#define B_PCH_SPI_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords +#define N_PCH_SPI_FDBAR_PCHSL 24 ///< PCH Strap Length bit position +#define R_PCH_SPI_FDBAR_FLASH_MAP2 0x0C +#define B_PCH_SPI_FDBAR_FCPUSBA 0x000000FF ///< CPU Strap Base Address, [7:0] represents [11:4] +#define N_PCH_SPI_FDBAR_FCPUSBA 0 ///< CPU Strap Base Address bit position +#define N_PCH_SPI_FDBAR_FCPUSBA_REPR 4 ///< CPU Strap Base Address bit represents position +#define B_PCH_SPI_FDBAR_CPUSL 0x0000FF00 ///< CPU Strap Length, [15:8] represents number of Dwords +#define N_PCH_SPI_FDBAR_CPUSL 8 ///< CPU Strap Length bit position +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_PCH_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register +#define B_PCH_SPI_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency +#define B_PCH_SPI_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency +#define B_PCH_SPI_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency +#define B_PCH_SPI_FLCOMP_FR_SUP BIT20 ///< Fast Read Support. +#define B_PCH_SPI_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) ///< Read Clock Frequency. +#define V_PCH_SPI_FLCOMP_FREQ_48MHZ 0x02 +#define V_PCH_SPI_FLCOMP_FREQ_30MHZ 0x04 +#define V_PCH_SPI_FLCOMP_FREQ_17MHZ 0x06 +#define B_PCH_SPI_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK +#define N_PCH_SPI_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position +#define B_PCH_SPI_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK +#define V_PCH_SPI_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_PCH_SPI_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1 +#define B_PCH_SPI_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address +#define B_PCH_SPI_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length + +#define R_PCH_SPI_VTBA_JID0 0x00 ///< JEDEC-ID 0 Register +#define S_PCH_SPI_VTBA_JID0 0x04 +#define B_PCH_SPI_VTBA_JID0_VID 0x000000FF +#define B_PCH_SPI_VTBA_JID0_DID0 0x0000FF00 +#define B_PCH_SPI_VTBA_JID0_DID1 0x00FF0000 +#define N_PCH_SPI_VTBA_JID0_DID0 0x08 +#define N_PCH_SPI_VTBA_JID0_DID1 0x10 +#define R_PCH_SPI_VTBA_VSCC0 0x04 +#define S_PCH_SPI_VTBA_VSCC0 0x04 + + +// +// SPI Private Configuration Space Registers +// +#define R_PCH_PCR_SPI_CLK_CTL 0xC004 +#define R_PCH_PCR_SPI_PWR_CTL 0xC008 + +// +// MMP0 +// +#define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap offset +#define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap bit + + +#define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SFDP +#define B_PCH_SPI_STRP_SFDP_QIORE BIT3 ///< Quad IO Read Enable +#define B_PCH_SPI_STRP_SFDP_QORE BIT2 ///< Quad Output Read Enable +#define B_PCH_SPI_STRP_SFDP_DIORE BIT1 ///< Dual IO Read Enable +#define B_PCH_SPI_STRP_SFDP_DORE BIT0 ///< Dual Output Read Enable + +// +// Descriptor Record 0 +// +#define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0 +#define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsThermal.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsThermal.h new file mode 100644 index 0000000000..e9eddfe6f1 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsThermal.h @@ -0,0 +1,99 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_THERMAL_H_ +#define _PCH_REGS_THERMAL_H_ + +// +// Thermal Device Registers (D20:2) +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL 20 +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 2 +#define V_PCH_THERMAL_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_THERMAL_DEVICE_ID 0x8C24 + +// +// LBG Production Thermal Device Device ID +// +#define V_PCH_LBG_PROD_THERMAL_DEVICE_ID 0xA1B1 +// +// LBG SSX (Super SKU) Thermal Device Device ID +// +#define V_PCH_LBG_THERMAL_DEVICE_ID 0xA231 + +#define V_PCH_LP_THERMAL_DEVICE_ID 0x9C24 +#define R_PCH_THERMAL_TBAR 0x10 +#define V_PCH_THERMAL_TBAR_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBAR_ALIGNMENT 12 +#define B_PCH_THERMAL_TBAR_MASK 0xFFFFF000 +#define R_PCH_THERMAL_TBARH 0x14 +#define R_PCH_THERMAL_TBARB 0x40 +#define V_PCH_THERMAL_TBARB_SIZE (4 * 1024) +#define N_PCH_THREMAL_TBARB_ALIGNMENT 12 +#define B_PCH_THERMAL_SPTYPEN BIT0 +#define R_PCH_THERMAL_TBARBH 0x44 +#define B_PCH_THERMAL_TBARB_MASK 0xFFFFF000 + +// +// Thermal TBAR MMIO registers +// +#define R_PCH_TBAR_TSC 0x04 +#define B_PCH_TBAR_TSC_PLD BIT7 +#define B_PCH_TBAR_TSC_CPDE BIT0 +#define R_PCH_TBAR_TSS 0x06 +#define R_PCH_TBAR_TSEL 0x08 +#define B_PCH_TBAR_TSEL_PLD BIT7 +#define B_PCH_TBAR_TSEL_ETS BIT0 +#define R_PCH_TBAR_TSREL 0x0A +#define R_PCH_TBAR_TSMIC 0x0C +#define B_PCH_TBAR_TSMIC_PLD BIT7 +#define B_PCH_TBAR_TSMIC_SMIE BIT0 +#define R_PCH_TBAR_CTT 0x10 +#define R_PCH_TBAR_TAHV 0x14 +#define R_PCH_TBAR_TALV 0x18 +#define R_PCH_TBAR_TSPM 0x1C +#define B_PCH_TBAR_TSPM_LTT (BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) +#define V_PCH_TBAR_TSPM_LTT 0x0C8 +#define B_PCH_TBAR_TSPM_MAXTSST (BIT11 | BIT10 | BIT9) +#define V_PCH_TBAR_TSPM_MAXTSST (0x4 << 9) +#define B_PCH_TBAR_TSPM_MINTSST BIT12 +#define B_PCH_TBAR_TSPM_DTSSIC0 BIT13 +#define B_PCH_TBAR_TSPM_DTSSS0EN BIT14 +#define B_PCH_TBAR_TSPM_TSPMLOCK BIT15 +#define R_PCH_TBAR_TL 0x40 +#define B_PCH_TBAR_TL_LOCK BIT31 +#define B_PCH_TBAR_TL_TTEN BIT29 +#define R_PCH_TBAR_TL2 0x50 +#define R_PCH_TBAR_TL2_LOCK BIT15 +#define R_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_PHL 0x60 +#define B_PCH_TBAR_PHLE BIT15 +#define R_PCH_TBAR_PHLC 0x62 +#define B_PCH_TBAR_PHLC_LOCK BIT0 +#define R_PCH_TBAR_TAS 0x80 +#define R_PCH_TBAR_TSPIEN 0x82 +#define R_PCH_TBAR_TSGPEN 0x84 +#define B_PCH_TBAR_TL2_PMCTEN BIT14 +#define R_PCH_TBAR_A4 0xA4 +#define R_PCH_TBAR_C0 0xC0 +#define R_PCH_TBAR_C4 0xC4 +#define R_PCH_TBAR_C8 0xC8 +#define R_PCH_TBAR_CC 0xCC +#define R_PCH_TBAR_D0 0xD0 +#define R_PCH_TBAR_E0 0xE0 +#define R_PCH_TBAR_E4 0xE4 +#define R_PCH_TBAR_E8 0xE8 +#define R_PCH_TBAR_TCFD 0xF0 ///< Thermal controller function disable +#define B_PCH_TBAR_TCFD_TCD BIT0 ///< Thermal controller disable + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsTraceHub.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsTraceHub.h new file mode 100644 index 0000000000..60201d1195 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsTraceHub.h @@ -0,0 +1,131 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_TRACE_HUB_H_ +#define _PCH_REGS_TRACE_HUB_H_ + +// +// TraceHub Registers (D31:F7) +// +#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31 +#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7 + +#define V_PCH_TRACE_HUB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_TRACE_HUB_DEVICE_ID 0x0963 + +// +// LBG Production (PRQ) TraceHub Device ID +// +#define V_PCH_LBG_PROD_TRACE_HUB_DEVICE_ID 0xA1A6 +// +// LBG SuperSKU (SSX) TraceHub Device ID +// +#define V_PCH_LBG_TRACE_HUB_DEVICE_ID 0xA226 + +#define R_PCH_TRACE_HUB_CSR_MTB_LBAR 0x10 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAL 0xFFF00000 +#define R_PCH_TRACE_HUB_CSR_MTB_UBAR 0x14 +#define B_PCH_TRACE_HUB_CSR_MTB_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_SW_LBAR 0x18 +#define B_PCH_TRACE_HUB_SW_RBAL 0xFFE00000 +#define R_PCH_TRACE_HUB_SW_UBAR 0x1C +#define B_PCH_TRACE_HUB_SW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_RTIT_LBAR 0x20 +#define B_PCH_TRACE_HUB_RTIT_RBAL 0xFFFFFF00 +#define R_PCH_TRACE_HUB_RTIT_UBAR 0x24 +#define B_PCH_TRACE_HUB_RTIT_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_MSICID 0x40 +#define R_PCH_TRACE_HUB_MSINCP 0x41 +#define R_PCH_TRACE_HUB_MSIMC 0x42 +#define R_PCH_TRACE_HUB_MSILMA 0x44 +#define R_PCH_TRACE_HUB_MSIUMA 0x48 +#define R_PCH_TRACE_HUB_MSIMD 0x4C +#define B_PCH_TRACE_HUB_FW_RBAL 0xFFFC0000 +#define B_PCH_TRACE_HUB_FW_RBAU 0xFFFFFFFF +#define R_PCH_TRACE_HUB_DSC 0x80 +#define B_PCH_TRACE_HUB_BYP BIT0 //< TraceHub Bypass +#define R_PCH_TRACE_HUB_DSS 0x81 +#define R_PCH_TRACE_HUB_ISTOT 0x84 +#define R_PCH_TRACE_HUB_ICTOT 0x88 +#define R_PCH_TRACE_HUB_IPAD 0x8C +#define R_PCH_TRACE_HUB_DSD 0x90 + +// +// Offsets from CSR_MTB_BAR +// +#define R_PCH_TRACE_HUB_MTB_GTHOPT0 0x00 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P0FLUSH BIT7 +#define B_PCH_TRACE_HUB_MTB_GTHOPT0_P1FLUSH BIT15 +#define V_PCH_TRACE_HUB_MTB_SWDEST_PTI 0x0A +#define V_PCH_TRACE_HUB_MTB_SWDEST_MEMEXI 0x08 +#define V_PCH_TRACE_HUB_MTB_SWDEST_DISABLE 0x00 +#define R_PCH_TRACE_HUB_MTB_SWDEST_1 0x0C +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_1 0x0000000F +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_2 0x000000F0 +#define B_PCH_TRACE_HUB_MTB_SWDEST_CSE_3 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_1 0x0000F000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_2 0x000F0000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_ISH_3 0x00F00000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AUDIO 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_PMC 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_2 0x10 +#define B_PCH_TRACE_HUB_MTB_SWDEST_FTH 0x0000000F +#define R_PCH_TRACE_HUB_MTB_SWDEST_3 0x14 +#define B_PCH_TRACE_HUB_MTB_SWDEST_MAESTRO 0x00000F00 +#define B_PCH_TRACE_HUB_MTB_SWDEST_SKYCAM 0x0F000000 +#define B_PCH_TRACE_HUB_MTB_SWDEST_AET 0xF0000000 +#define R_PCH_TRACE_HUB_MTB_SWDEST_4 0x18 +#define R_PCH_TRACE_HUB_MTB_MSC0CTL 0xA0100 +#define R_PCH_TRACE_HUB_MTB_MSC1CTL 0xA0200 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DCI 0x2 +#define V_PCH_TRACE_HUB_MTB_MSCNMODE_DEBUG 0x3 +#define B_PCH_TRACE_HUB_MTB_MSCNLEN (BIT10 | BIT9 | BIT8) +#define B_PCH_TRACE_HUB_MTB_MSCNMODE (BIT5 | BIT4) +#define N_PCH_TRACE_HUB_MTB_MSCNMODE 0x4 +#define B_PCH_TRACE_HUB_MTB_MSCN_RD_HDR_OVRD BIT2 +#define B_PCH_TRACE_HUB_MTB_WRAPENN BIT1 +#define B_PCH_TRACE_HUB_MTB_MSCNEN BIT0 +#define R_PCH_TRACE_HUB_MTB_GTHSTAT 0xD4 +#define R_PCH_TRACE_HUB_MTB_SCR2 0xD8 +#define B_PCH_TRACE_HUB_MTB_SCR2_FCD BIT0 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF2 BIT2 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF3 BIT3 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF4 BIT4 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF5 BIT5 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF6 BIT6 +#define B_PCH_TRACE_HUB_MTB_SCR2_FSEOFF7 BIT7 +#define R_PCH_TRACE_HUB_MTB_MSC0BAR 0xA0108 +#define R_PCH_TRACE_HUB_MTB_MSC0SIZE 0xA010C +#define R_PCH_TRACE_HUB_MTB_MSC1BAR 0xA0208 +#define R_PCH_TRACE_HUB_MTB_MSC1SIZE 0xA020C +#define R_PCH_TRACE_HUB_MTB_STREAMCFG1 0xA1000 +#define B_PCH_TRACE_HUB_MTB_STREAMCFG1_ENABLE BIT28 +#define R_PCH_TRACE_HUB_MTB_PTI_CTL 0x1C00 +#define B_PCH_TRACE_HUB_MTB_PTIMODESEL 0xF0 +#define B_PCH_TRACE_HUB_MTB_PTICLKDIV (BIT17 | BIT16) +#define B_PCH_TRACE_HUB_MTB_PATGENMOD (BIT22 | BIT21 | BIT20) +#define B_PCH_TRACE_HUB_MTB_PTI_EN BIT0 +#define R_PCH_TRACE_HUB_MTB_SCR 0xC8 +#define R_PCH_TRACE_HUB_MTB_GTH_FREQ 0xCC +#define V_PCH_TRACE_HUB_MTB_SCR 0x00130000 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD0 0xE0 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD1 0xE4 +#define R_PCH_TRACE_HUB_CSR_MTB_SCRATCHPAD10 0xE40 +#define R_PCH_TRACE_HUB_MTB_CTPGCS 0x1C14 +#define B_PCH_TRACE_HUB_MTB_CTPEN BIT0 +#define V_PCH_TRACE_HUB_MTB_CHLCNT 0x80 +#define V_PCH_TRACE_HUB_MTB_STHMSTR 0x20 +#define R_PCH_TRACE_HUB_CSR_MTB_TSUCTRL 0x2000 +#define B_PCH_TRACE_HUB_CSR_MTB_TSUCTRL_CTCRESYNC BIT0 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsUsb.h b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsUsb.h new file mode 100644 index 0000000000..6d92b4dfff --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/Register/PchRegsUsb.h @@ -0,0 +1,469 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_REGS_USB_H_ +#define _PCH_REGS_USB_H_ + +// +// USB3 (XHCI) related definitions +// +#define PCI_BUS_NUMBER_PCH_XHCI 0 +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// XHCI PCI Config Space registers +// +#define V_PCH_USB_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define V_PCH_H_USB_DEVICE_ID_XHCI_1 0x8C31 ///< SKL PCH H XHCI#1 +// +// LBG Production (PRQ) XHCI Controller Device ID +// +#define V_PCH_LBG_PROD_USB_DEVICE_ID_XHCI_1 0xA1AF ///< LBG Production DID XHCI#1 +// +// LBG Super SKU (SSX) XHCI Controller Device ID +// +#define V_PCH_LBG_USB_DEVICE_ID_XHCI_1 0xA22F ///< LBG Super SKU DID XHCI#1 +#define V_PCH_LP_USB_DEVICE_ID_XHCI_1 0x9C31 ///< SKL PCH LP XHCI#1 + +#define R_PCH_XHCI_MEM_BASE 0x10 +#define V_PCH_XHCI_MEM_LENGTH 0x10000 +#define N_PCH_XHCI_MEM_ALIGN 16 +#define B_PCH_XHCI_MEM_ALIGN_MASK 0xFFFF + +#define R_PCH_XHCI_XHCC1 0x40 +#define B_PCH_XHCI_XHCC1_ACCTRL BIT31 +#define B_PCH_XHCI_XHCC1_RMTASERR BIT24 +#define B_PCH_XHCI_XHCC1_URD BIT23 +#define B_PCH_XHCI_XHCC1_URRE BIT22 +#define B_PCH_XHCI_XHCC1_IIL1E (BIT21 | BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_DIS 0 +#define V_PCH_XHCI_XHCC1_IIL1E_32 (BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_64 (BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_128 (BIT20 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_256 (BIT21) +#define V_PCH_XHCI_XHCC1_IIL1E_512 (BIT21 | BIT19) +#define V_PCH_XHCI_XHCC1_IIL1E_1024 (BIT21 | BIT20) +#define V_PCH_XHCI_XHCC1_IIL1E_131072 (BIT21 | BIT20 | BIT19) +#define B_PCH_XHCI_XHCC1_XHCIL1E BIT18 +#define B_PCH_XHCI_XHCC1_D3IL1E BIT17 +#define B_PCH_XHCI_XHCC1_UNPPA (BIT16 | BIT15 | BIT14 | BIT13 | BIT12) +#define B_PCH_XHCI_XHCC1_SWAXHCI BIT11 +#define B_PCH_XHCI_XHCC1_L23HRAWC (BIT10 | BIT9 | BIT8) +#define B_PCH_XHCI_XHCC1_UTAGCP (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4) +#define B_PCH_XHCI_XHCC1_UDAGCCP (BIT3 | BIT2) +#define B_PCH_XHCI_XHCC1_UDAGC (BIT1 | BIT0) + +#define R_PCH_XHCI_XHCC2 0x44 +#define B_PCH_XHCI_XHCC2_OCCFDONE BIT31 +#define B_PCH_XHCI_XHCC2_XHCUPRDROE BIT11 +#define B_PCH_XHCI_XHCC2_IOSFSRAD BIT10 +#define B_PCH_XHCI_XHCC2_SWACXIHB (BIT9 | BIT8) +#define B_PCH_XHCI_XHCC2_SWADMIL1IHB (BIT7 | BIT6) +#define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3) +#define B_PCH_XHCI_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) + +#define R_PCH_XHCI_XHCLKGTEN 0x50 +#define B_PCH_XHCI_XHCLKGTEN_SSLSE BIT26 +#define B_PCH_XHCI_XHCLKGTEN_USB2PLLSE BIT25 +#define B_PCH_XHCI_XHCLKGTEN_IOSFSTCGE BIT24 +#define B_PCH_XHCI_XHCLKGTEN_HSTCGE (BIT23 | BIT22 | BIT21 | BIT20) +#define B_PCH_XHCI_XHCLKGTEN_SSTCGE (BIT19 | BIT18 | BIT17 | BIT16) +#define B_PCH_XHCI_XHCLKGTEN_XHCIGEU3S BIT15 +#define B_PCH_XHCI_XHCLKGTEN_XHCFTCLKSE BIT14 +#define B_PCH_XHCI_XHCLKGTEN_XHCBBTCGIPISO BIT13 +#define B_PCH_XHCI_XHCLKGTEN_XHCHSTCGU2NRWE BIT12 +#define B_PCH_XHCI_XHCLKGTEN_XHCUSB2PLLSDLE (BIT11 | BIT10) +#define B_PCH_XHCI_XHCLKGTEN_HSPLLSUE (BIT9 | BIT8) +#define B_PCH_XHCI_XHCLKGTEN_SSPLLSUE (BIT7 | BIT6 | BIT5) +#define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4 +#define B_PCH_XHCI_XHCLKGTEN_HSLTCGE BIT3 +#define B_PCH_XHCI_XHCLKGTEN_SSLTCGE BIT2 +#define B_PCH_XHCI_XHCLKGTEN_IOSFBTCGE BIT1 +#define B_PCH_XHCI_XHCLKGTEN_IOSFGBLCGE BIT0 + +#define R_PCH_XHCI_USB_RELNUM 0x60 +#define B_PCH_XHCI_USB_RELNUM 0xFF +#define R_PCH_XHCI_FL_ADJ 0x61 +#define B_PCH_XHCI_FL_ADJ 0x3F +#define R_PCH_XHCI_PWR_CAPID 0x70 +#define B_PCH_XHCI_PWR_CAPID 0xFF +#define R_PCH_XHCI_NXT_PTR1 0x71 +#define B_PCH_XHCI_NXT_PTR1 0xFF +#define R_PCH_XHCI_PWR_CAP 0x72 +#define B_PCH_XHCI_PWR_CAP_PME_SUP 0xF800 +#define B_PCH_XHCI_PWR_CAP_D2_SUP BIT10 +#define B_PCH_XHCI_PWR_CAP_D1_SUP BIT9 +#define B_PCH_XHCI_PWR_CAP_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_PCH_XHCI_PWR_CAP_DSI BIT5 +#define B_PCH_XHCI_PWR_CAP_PME_CLK BIT3 +#define B_PCH_XHCI_PWR_CAP_VER (BIT2 | BIT1 | BIT0) +#define R_PCH_XHCI_PWR_CNTL_STS 0x74 +#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15 +#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) +#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 | BIT9) +#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN BIT8 +#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) +#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) +#define R_PCH_XHCI_MSI_MCTL 0x82 +#define R_PCH_XHCI_U2OCM 0xB0 +#define R_PCH_XHCI_U3OCM 0xD0 +#define V_PCH_XHCI_NUMBER_OF_OC_PINS 8 + +#define R_PCH_XHCI_FUS 0xE0 +#define B_PCH_XHCI_FUS_USBR (BIT5) +#define V_PCH_XHCI_FUS_USBR_EN 0 +#define V_PCH_XHCI_FUS_USBR_DIS (BIT5) + +#define R_PCH_XHCI_FC 0xFC + +#define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_SSPRTCNT_01B (BIT3) +#define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4) +#define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3) + +#define B_PCH_XHCI_FUS_HSPRTCNT (BIT2 | BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_00B 0 +#define V_PCH_XHCI_FUS_HSPRTCNT_01B (BIT1) +#define V_PCH_XHCI_FUS_HSPRTCNT_10B (BIT2) +#define V_PCH_XHCI_FUS_HSPRTCNT_11B (BIT2 | BIT1) + +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_CNT 6 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_CNT 4 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_CNT 2 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_CNT 0 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_00B_MASK 0x3F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_01B_MASK 0x0F +#define V_PCH_H_XHCI_FUS_SSPRTCNT_10B_MASK 0x03 +#define V_PCH_H_XHCI_FUS_SSPRTCNT_11B_MASK 0x00 + +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_CNT 14 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_CNT 12 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_CNT 10 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_CNT 8 +#define V_PCH_H_XHCI_FUS_HSPRTCNT_00B_MASK 0x3FFF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_01B_MASK 0x3F3F +#define V_PCH_H_XHCI_FUS_HSPRTCNT_10B_MASK 0x03FF +#define V_PCH_H_XHCI_FUS_HSPRTCNT_11B_MASK 0x00FF + +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT 4 +#define V_PCH_LP_XHCI_FIXED_SSPRTCNT_MASK 0x0F + +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT 8 +#define V_PCH_LP_XHCI_FIXED_HSPRTCNT_MASK 0x00FF + +// +// xHCI MMIO registers +// + +// +// 0x00 - 0x1F - Capability Registers +// +#define R_PCH_XHCI_CAPLENGTH 0x00 +#define R_PCH_XHCI_HCIVERSION 0x02 +#define R_PCH_XHCI_HCSPARAMS1 0x04 +#define R_PCH_XHCI_HCSPARAMS2 0x08 +#define R_PCH_XHCI_HCSPARAMS3 0x0C +#define B_PCH_XHCI_HCSPARAMS3_U2DEL 0xFFFF0000 +#define B_PCH_XHCI_HCSPARAMS3_U1DEL 0x0000FFFF +#define R_PCH_XHCI_HCCPARAMS 0x10 +#define B_PCH_XHCI_HCCPARAMS_LHRC BIT5 +#define B_PCH_XHCI_HCCPARAMS_MAXPSASIZE 0xF000 +#define R_PCH_XHCI_DBOFF 0x14 +#define R_PCH_XHCI_RTSOFF 0x18 + +// +// 0x80 - 0xBF - Operational Registers +// +#define R_PCH_XHCI_USBCMD 0x80 +#define B_PCH_XHCI_USBCMD_RS BIT0 ///< Run/Stop +#define B_PCH_XHCI_USBCMD_RST BIT1 ///< HCRST +#define R_PCH_XHCI_USBSTS 0x84 +#define B_PCH_XHCI_USBSTS_HCH BIT0 +#define B_PCH_XHCI_USBSTS_CNR BIT11 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_LP_XHCI_PORTSC01USB2 0x480 +#define R_PCH_LP_XHCI_PORTSC02USB2 0x490 +#define R_PCH_LP_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_LP_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_LP_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_LP_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_LP_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_LP_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_LP_XHCI_PORTSC09USB2 0x500 +#define R_PCH_LP_XHCI_PORTSC10USB2 0x510 + + +#define R_PCH_LP_XHCI_PORTSC01USB3 0x540 +#define R_PCH_LP_XHCI_PORTSC02USB3 0x550 +#define R_PCH_LP_XHCI_PORTSC03USB3 0x560 +#define R_PCH_LP_XHCI_PORTSC04USB3 0x570 +#define R_PCH_LP_XHCI_PORTSC05USB3 0x580 +#define R_PCH_LP_XHCI_PORTSC06USB3 0x590 + +// +// 0x480 - 0x5CF - Port Status and Control Registers +// +#define R_PCH_H_XHCI_PORTSC01USB2 0x480 +#define R_PCH_H_XHCI_PORTSC02USB2 0x490 +#define R_PCH_H_XHCI_PORTSC03USB2 0x4A0 +#define R_PCH_H_XHCI_PORTSC04USB2 0x4B0 +#define R_PCH_H_XHCI_PORTSC05USB2 0x4C0 +#define R_PCH_H_XHCI_PORTSC06USB2 0x4D0 +#define R_PCH_H_XHCI_PORTSC07USB2 0x4E0 +#define R_PCH_H_XHCI_PORTSC08USB2 0x4F0 +#define R_PCH_H_XHCI_PORTSC09USB2 0x500 +#define R_PCH_H_XHCI_PORTSC10USB2 0x510 +#define R_PCH_H_XHCI_PORTSC11USB2 0x520 +#define R_PCH_H_XHCI_PORTSC12USB2 0x530 +#define R_PCH_H_XHCI_PORTSC13USB2 0x540 +#define R_PCH_H_XHCI_PORTSC14USB2 0x550 + +#define R_PCH_H_XHCI_PORTSC15USBR 0x560 +#define R_PCH_H_XHCI_PORTSC16USBR 0x570 + +#define R_PCH_H_XHCI_PORTSC01USB3 0x580 +#define R_PCH_H_XHCI_PORTSC02USB3 0x590 +#define R_PCH_H_XHCI_PORTSC03USB3 0x5A0 +#define R_PCH_H_XHCI_PORTSC04USB3 0x5B0 +#define R_PCH_H_XHCI_PORTSC05USB3 0x5C0 +#define R_PCH_H_XHCI_PORTSC06USB3 0x5D0 +#define R_PCH_H_XHCI_PORTSC07USB3 0x5E0 +#define R_PCH_H_XHCI_PORTSC08USB3 0x5F0 +#define R_PCH_H_XHCI_PORTSC09USB3 0x600 +#define R_PCH_H_XHCI_PORTSC10USB3 0x610 + +#define B_PCH_XHCI_PORTSCXUSB2_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_CEC BIT23 ///< Port Config Error Change +#define B_PCH_XHCI_PORTSCXUSB2_PLC BIT22 ///< Port Link State Change +#define B_PCH_XHCI_PORTSCXUSB2_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB2_WRC BIT19 ///< Warm Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB2_PEC BIT18 ///< Port Enabled Disabled Change +#define B_PCH_XHCI_PORTSCXUSB2_CSC BIT17 ///< Connect Status Change +#define B_PCH_XHCI_PORTSCXUSB2_LWS BIT16 ///< Port Link State Write Strobe +#define B_PCH_XHCI_USB2_U3_EXIT (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_USB2_U0_MASK (BIT5 | BIT6 | BIT7 | BIT8) +#define B_PCH_XHCI_PORTSCXUSB2_PP BIT9 +#define B_PCH_XHCI_PORTSCXUSB2_PLS (BIT5 | BIT6 | BIT7 | BIT8) ///< Port Link State +#define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled +#define B_PCH_XHCI_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status +#define B_PCH_XHCI_PORT_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB2_CEC | B_PCH_XHCI_PORTSCXUSB2_PLC | B_PCH_XHCI_PORTSCXUSB2_PRC | B_PCH_XHCI_PORTSCXUSB2_OCC | B_PCH_XHCI_PORTSCXUSB2_WRC | B_PCH_XHCI_PORTSCXUSB2_PEC | B_PCH_XHCI_PORTSCXUSB2_CSC | B_PCH_XHCI_PORTSCXUSB2_PED) +#define B_PCH_XHCI_PORTPMSCXUSB2_PTC (BIT28 | BIT29 | BIT30 | BIT31) ///< Port Test Control + +#define B_PCH_XHCI_PORTSCXUSB3_WPR BIT31 ///< Warm Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_CEC BIT23 ///< Port Config Error Change +#define B_PCH_XHCI_PORTSCXUSB3_PLC BIT22 ///< Port Link State Change +#define B_PCH_XHCI_PORTSCXUSB3_PRC BIT21 ///< Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_OCC BIT20 ///< Over-current Change +#define B_PCH_XHCI_PORTSCXUSB3_WRC BIT19 ///< Warm Port Reset Change +#define B_PCH_XHCI_PORTSCXUSB3_PEC BIT18 ///< Port Enabled Disabled Change +#define B_PCH_XHCI_PORTSCXUSB3_CSC BIT17 ///< Connect Status Change +#define B_PCH_XHCI_PORTSCXUSB3_PP BIT9 ///< Port Power +#define B_PCH_XHCI_PORTSCXUSB3_PLS (BIT8 | BIT7 | BIT6 | BIT5) ///< Port Link State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_POLLING 0x000000E0 ///< Link is in the Polling State +#define V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT 0x000000A0 ///< Link is in the RxDetect State +#define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset +#define B_PCH_XHCI_PORTSCXUSB3_PED BIT1 ///< Port Enable/Disabled +#define B_PCH_XHCI_PORTSCXUSB3_CHANGE_ENABLE_MASK (B_PCH_XHCI_PORTSCXUSB3_CEC | B_PCH_XHCI_PORTSCXUSB3_PLC | B_PCH_XHCI_PORTSCXUSB3_PRC | B_PCH_XHCI_PORTSCXUSB3_OCC | B_PCH_XHCI_PORTSCXUSB3_WRC | B_PCH_XHCI_PORTSCXUSB3_PEC | B_PCH_XHCI_PORTSCXUSB3_CSC | B_PCH_XHCI_PORTSCXUSB3_PED) +// +// 0x2000 - 0x21FF - Runtime Registers +// 0x3000 - 0x307F - Doorbell Registers +// +#define R_PCH_XHCI_XECP_SUPP_USB2_2 0x8008 +#define R_PCH_XHCI_XECP_SUPP_USB3_2 0x8028 +#define R_PCH_XHCI_HOST_CTRL_SCH_REG 0x8094 +#define R_PCH_XHCI_HOST_CTRL_IDMA_REG 0x809C +#define R_PCH_XHCI_PMCTRL 0x80A4 +#define R_PCH_XHCI_PGCBCTRL 0x80A8 ///< PGCB Control +#define R_PCH_XHCI_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg +#define R_PCH_XHCI_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2 +#define R_PCH_XHCI_SSPE 0x80B8 ///< Super Speed Port Enables +#define B_PCH_XHCI_LP_SSPE_MASK 0x3F ///< LP: Mask for 6 USB3 ports +#define B_PCH_XHCI_H_SSPE_MASK 0x3FF ///< H: Mask for 10 USB3 ports +#define R_PCH_XHCI_DUAL_ROLE_CFG0 0x80D8 +#define R_PCH_XHCI_DUAL_ROLE_CFG1 0x80DC +#define R_PCH_XHCI_AUX_CTRL_REG1 0x80E0 +#define R_PCH_XHCI_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG1 0x818C ///< Command Manager Control 1 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG2 0x8190 ///< Command Manager Control 2 +#define R_PCH_XHCI_XECP_CMDM_CTRL_REG3 0x8194 ///< Command Manager Control 3 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW1 0x80F0 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW2 0x80F4 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW3 0x80F8 ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_USB2_LINK_MGR_CTRL_REG1_DW4 0x80FC ///< USB2_LINK_MGR_CTRL_REG1 - USB2 Port Link Control 1, 2, 3, 4 +#define R_PCH_XHCI_HOST_CTRL_TRM_REG2 0x8110 ///< HOST_CTRL_TRM_REG2 - Host Controller Transfer Manager Control 2 +#define R_PCH_XHCI_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2 +#define R_PCH_XHCI_AUXCLKCTL 0x816C ///< xHCI Aux Clock Control Register +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0 +#define R_PCH_XHCI_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1 +#define R_PCH_XHCI_XHCLTVCTL2 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control +#define R_PCH_XHCI_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control +#define R_PCH_XHCI_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control +#define R_PCH_XHCI_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control +#define R_PCH_XHCI_USB2PHYPM 0x8164 ///< USB2 PHY Power Management Control +#define R_PCH_XHCI_PDDIS 0x8198 ///< xHC Pulldown Disable Control +#define R_PCH_XHCI_THROTT 0x819C ///< XHCI Throttle Control +#define R_PCH_XHCI_LFPSPM 0x81A0 ///< LFPS PM Control +#define R_PCH_XHCI_THROTT2 0x81B4 ///< XHCI Throttle +#define R_PCH_XHCI_LFPSONCOUNT 0x81B8 ///< LFPS On Count +#define R_PCH_XHCI_D0I2CTRL 0x81BC ///< D0I2 Control Register +#define R_PCH_XHCI_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control + +// +// SKL PCH LP FUSE +// +#define R_PCH_XHCI_LP_FUSE1 0x8410 +#define B_PCH_XHCI_LP_FUS_HSPRTCNT (BIT1) +#define B_PCH_XHCI_LP_FUS_USBR (BIT5) +#define R_PCH_XHCI_STRAP2 0x8420 ///< USB3 Mode Strap +#define R_PCH_XHCI_USBLEGCTLSTS 0x8470 ///< USB Legacy Support Control Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBAR BIT31 ///< SMI on BAR Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCIC BIT30 ///< SMI on PCI Command Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSC BIT29 ///< SMI on OS Ownership Change Status +#define B_PCH_XHCI_USBLEGCTLSTS_SMIBARE BIT15 ///< SMI on BAR Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIPCICE BIT14 ///< SMI on PCI Command Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIOSOE BIT13 ///< SMI on OS Ownership Enable +#define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable +#define B_PCH_XHCI_USBLEGCTLSTS_USBSMIE BIT0 ///< USB SMI Enable + +// +// Extended Capability Registers +// +#define R_PCH_XHCI_USB2PDO 0x84F8 +#define B_PCH_XHCI_LP_USB2PDO_MASK 0x3FF ///< LP: Mask for 10 USB2 ports +#define B_PCH_XHCI_H_USB2PDO_MASK 0x7FFF ///< H: Mask for 14 USB2 ports +#define B_PCH_XHCI_USB2PDO_DIS_PORT0 BIT0 + +#define R_PCH_XHCI_USB3PDO 0x84FC +#define B_PCH_XHCI_LP_USB3PDO_MASK 0x3F ///< LP: Mask for 6 USB3 ports +#define B_PCH_XHCI_H_USB3PDO_MASK 0x3FF ///< H: Mask for 10 USB3 ports +#define B_PCH_XHCI_USB3PDO_DIS_PORT0 BIT0 + +// +// Debug Capability Descriptor Parameters +// +#define R_PCH_XHCI_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 + +// +// xDCI (OTG) PCI Config Space Registers +// +#define R_PCH_XDCI_MEM_BASE 0x10 +#define V_PCH_XDCI_MEM_LENGTH 0x200000 +#define R_PCH_XDCI_PMCSR 0x84 ///< Power Management Control and Status Register +#define R_PCH_XDCI_GENERAL_PURPOSER_REG1 0xA0 ///< General Purpose PCI RW Register1 +#define R_PCH_XDCI_CPGE 0xA2 ///< Chassis Power Gate Enable +#define R_PCH_XDCI_GENERAL_PURPOSER_REG4 0xAC ///< General Purpose PCI RW Register4 +#define R_PCH_OTG_GENERAL_INPUT_REG 0xC0 ///< General Input Register + +// +// xDCI (OTG) MMIO registers +// +#define R_PCH_XDCI_GCTL 0xC110 ///< Xdci Global Ctrl +#define B_PCH_XDCI_GCTL_GHIBEREN BIT1 ///< Hibernation enable +#define R_PCH_XDCI_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register +#define B_PCH_XDCI_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY +#define R_PCH_XDCI_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0 +#define B_PCH_XDCI_GUSB3PIPECTL0_UX_IN_PX BIT27 ///< Ux Exit in Px +#define R_PCH_XDCI_APBFC_U3PMU_CFG2 0x10F810 +#define R_PCH_XDCI_APBFC_U3PMU_CFG4 0x10F818 + +// +// xDCI (OTG) Private Configuration Registers +// (PID:OTG) +// +#define R_PCH_PCR_OTG_IOSF_A2 0xA2 +#define R_PCH_PCR_OTG_IOSF_PMCTL 0x1D0 +#define R_PCH_PCR_OTG_PCICFGCTRL1 0x200 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_PCH_PCR_OTG_PCICFGCTRL_PCI_IRQ 20 +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_PCH_PCR_OTG_PCICFGCTRL_ACPI_IRQ 12 +#define B_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 0x00000F00 +#define N_PCH_PCR_OTG_PCICFGCTRL_INT_PIN 8 +#define B_PCH_PCR_OTG_PCICFGCTRL_BAR1_DIS 0x00000080 +#define B_PCH_PCR_OTG_PCICFGCTRL_PME_SUP 0x0000007C +#define B_PCH_PCR_OTG_PCICFGCTRL_ACPI_INT_EN 0x00000002 +#define B_PCH_PCR_OTG_PCICFGCTRL_PCI_CFG_DIS 0x00000001 + +// +// USB2 Private Configuration Registers +// USB2 HIP design featured +// (PID:USB2) +// +#define R_PCH_PCR_USB2_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT +#define R_PCH_PCR_USB2_400C 0x400C +#define R_PCH_PCR_USB2_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address +#define V_PCH_PCR_USB2_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00 +#define V_PCH_PCR_USB2_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08 +#define V_PCH_PCR_USB2_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26 +#define R_PCH_PCR_USB2_402A 0x402A +#define R_PCH_PCR_USB2_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG +#define R_PCH_PCR_USB2_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2 +#define R_PCH_PCR_USB2_7034 0x7034 +#define R_PCH_PCR_USB2_7038 0x7038 +#define R_PCH_PCR_USB2_703C 0x703C +#define R_PCH_PCR_USB2_7040 0x7040 +#define R_PCH_PCR_USB2_7044 0x7044 +#define R_PCH_PCR_USB2_7048 0x7048 +#define R_PCH_PCR_USB2_704C 0x704C +#define R_PCH_PCR_USB2_CFG_COMPBG 0x7F04 ///< USB2 COMPBG + +// +// xHCI SSIC registers +// +#define R_PCH_XHCI_SSIC_GLOBAL_CONF_CTRL 0x8804 ///< SSIC Global Configuration Control +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_1 0x8808 ///< SSIC Configuration Register 1 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_1 0x8810 ///< SSIC Configuration Register 3 Port 1 +#define R_PCH_XHCI_SSIC_CONF_REG1_PORT_2 0x8838 ///< SSIC Configuration Register 1 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2 +#define R_PCH_XHCI_SSIC_CONF_REG3_PORT_2 0x8840 ///< SSIC Configuration Register 3 Port 2 +#define B_PCH_XHCI_SSIC_CONF_REG2_PORT_UNUSED BIT31 +#define B_PCH_XHCI_SSIC_CONF_REG2_PROG_DONE BIT30 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_1 0x8900 ///< Profile Attributes: Port 1 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_1 0x8904 ///< SSIC Port N Register Access Control: Port 1 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_0C 0x890C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_10 0x8910 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_14 0x8914 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_18 0x8918 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_1C 0x891C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_20 0x8920 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_24 0x8924 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P1_28 0x8928 + +#define R_PCH_XHCI_SSIC_PROF_ATTR_PORT_2 0x8A10 ///< Profile Attributes: Port 2 ... N +#define R_PCH_XHCI_SSIC_ACCESS_CONT_PORT_2 0x8A14 ///< SSIC Port N Register Access Control: Port 2 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_0C 0x8A1C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_10 0x8A20 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_14 0x8A24 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_18 0x8A28 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_1C 0x8A2C +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_20 0x8A30 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_24 0x8A34 +#define R_PCH_XHCI_SSIC_PROF_ATTR_P2_28 0x8A38 + +#endif diff --git a/Silicon/Intel/LewisburgPkg/Include/SaRegs.h b/Silicon/Intel/LewisburgPkg/Include/SaRegs.h new file mode 100644 index 0000000000..322fc882d6 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Include/SaRegs.h @@ -0,0 +1,706 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SA_REGS_H_ +#define _SA_REGS_H_ + +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID 0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +// +// Macros that judge which type a device ID belongs to +// + +// +// CPU Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_MB_ULT_1 0x1904 ///< Skylake Ult (OPI) (2+1F/1.5F/2F/3/3E) Mobile SA DID +#define V_SA_DEVICE_ID_SKL_MB_ULX_2 0x190C ///< Skylake Ulx (OPI) (2+1F/1.5F/2) SA DID +#define V_SA_DEVICE_ID_SKL_MB_ULX_3 0x1924 ///< Skylake Ulx (OPI) +// +// CPU Halo SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_HALO_1 0x1900 ///< Skylake Halo (2+2/1) SA DID +#define V_SA_DEVICE_ID_SKL_HALO_2 0x1910 ///< Skylake Halo (4+2/4E/3FE) SA DID +// +// CPU Desktop SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_DT_1 0x190F ///< Skylake Desktop (2+1F/1.5F/2) SA DID +#define V_SA_DEVICE_ID_SKL_DT_2 0x191F ///< Skylake Desktop (4+2/4) SA DID +// +// CPU Server SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_SKL_SVR_1 0x1908 ///< Skylake Server (2+2/3E) SA DID +#define V_SA_DEVICE_ID_SKL_SVR_2 0x1918 ///< Skylake Server (4+1/2/4E) SA DID + +/// +/// Device IDs that are Mobile specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId == V_SA_DEVICE_ID_SKL_MB_ULT_1) || \ + (DeviceId == V_SA_DEVICE_ID_SKL_MB_ULX_2) || \ + (DeviceId == V_SA_DEVICE_ID_SKL_MB_ULX_3) \ + ) + +/// +/// Device IDs that are Desktop specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId == V_SA_DEVICE_ID_SKL_DT_1) || \ + (DeviceId == V_SA_DEVICE_ID_SKL_DT_2) \ + ) + +/// +/// Device IDS that are Server specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId == V_SA_DEVICE_ID_SKL_SVR_1) || \ + (DeviceId == V_SA_DEVICE_ID_SKL_SVR_2) \ + ) + +/// +/// Device IDs that are Halo specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_HALO(DeviceId) \ + ( \ + (DeviceId == V_SA_DEVICE_ID_SKL_HALO_1) || \ + (DeviceId == V_SA_DEVICE_ID_SKL_HALO_2) \ + ) + +/** + <b>Description</b>: + This is the base address for the PCI Express Egress Port MMIO Configuration space. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0]. + All the bits in this register are locked in LT mode. +**/ +#define R_SA_PXPEPBAR (0x40) +// +// Description of PXPEPBAREN (0:0) +// - 0: PXPEPBAR is disabled and does not claim any memory +// - 1: PXPEPBAR memory mapped accesses are claimed and decoded appropriately +// - This register is locked by LT. +// +#define N_SA_PXPEPBAR_PXPEPBAREN_OFFSET (0x0) +#define S_SA_PXPEPBAR_PXPEPBAREN_WIDTH (0x1) +#define B_SA_PXPEPBAR_PXPEPBAREN_MASK (0x1) +#define V_SA_PXPEPBAR_PXPEPBAREN_DEFAULT (0x0) +// +// Description of PXPEPBAR (12:38) +// - This field corresponds to bits 38 to 12 of the base address PCI Express Egress Port MMIO configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the PCI Express Egress Port MMIO register set. All the bits in this register are locked in LT mode. +// +#define N_SA_PXPEPBAR_PXPEPBAR_OFFSET (0xc) +#define S_SA_PXPEPBAR_PXPEPBAR_WIDTH (0x1b) +#define B_SA_PXPEPBAR_PXPEPBAR_MASK (0x7ffffff000) +#define V_SA_PXPEPBAR_PXPEPBAR_DEFAULT (0x0) + +/** + <b>Description</b>: + - This is the base address for the Host Memory Mapped Configuration space. There is no physical memory within this 32KB window that can be addressed. The 32KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Host MMIO Memory Mapped Configuation space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0]. + - All the bits in this register are locked in LT mode. + - The register space contains memory control, initialization, timing, and buffer strength registers; clocking registers; and power and thermal management registers. +**/ +#define R_SA_MCHBAR (0x48) +/** + Description of MCHBAREN (0:0) + - 0: MCHBAR is disabled and does not claim any memory + - 1: MCHBAR memory mapped accesses are claimed and decoded appropriately + - This register is locked by LT. +**/ +#define N_SA_MCHBAR_MCHBAREN_OFFSET (0x0) +#define S_SA_MCHBAR_MCHBAREN_WIDTH (0x1) +#define B_SA_MCHBAR_MCHBAREN_MASK (0x1) +#define V_SA_MCHBAR_MCHBAREN_DEFAULT (0x0) +/** + Description of MCHBAR (15:38) + - This field corresponds to bits 38 to 15 of the base address Host Memory Mapped configuration space. BIOS will program this register resulting in a base address for a 32KB block of contiguous memory address space. This register ensures that a naturally aligned 32KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the Host Memory Mapped register set. All the bits in this register are locked in LT mode. +**/ +#define N_SA_MCHBAR_MCHBAR_OFFSET (0xf) +#define S_SA_MCHBAR_MCHBAR_WIDTH (0x18) +#define B_SA_MCHBAR_MCHBAR_MASK (0x7fffff8000ULL) +#define V_SA_MCHBAR_MCHBAR_DEFAULT (0x0) + +/** + <b>Description</b>: + - All the bits in this register are LT lockable. +**/ +#define R_SA_GGC (0x50) +/** + Description of GGCLCK (0:0) + - When set to 1b, this bit will lock all bits in this register. +**/ +#define N_SA_GGC_GGCLCK_OFFSET (0x0) +#define S_SA_GGC_GGCLCK_WIDTH (0x1) +#define B_SA_GGC_GGCLCK_MASK (0x1) +#define V_SA_GGC_GGCLCK_DEFAULT (0x0) +/** + Description of IVD (1:1) + - 0: Enable. Device 2 (IGD) claims VGA memory and IO cycles, the Sub-Class Code within Device 2 Class Code register is 00. + - 1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO), and the Sub- Class Code field within Device 2 function 0 Class Code register is 80. + - BIOS Requirement: BIOS must not set this bit to 0 if the GMS field (bits 7:3 of this register) pre-allocates no memory. + - This bit MUST be set to 1 if Device 2 is disabled either via a fuse or fuse override (CAPID0[46] = 1) or via a register (DEVEN[3] = 0). + - This register is locked by LT lock. +**/ +#define N_SA_GGC_IVD_OFFSET (0x1) +#define S_SA_GGC_IVD_WIDTH (0x1) +#define B_SA_GGC_IVD_MASK (0x2) +#define V_SA_GGC_IVD_DEFAULT (0x0) +/** + For SKL + Description of GMS (8:15) + - This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. + - This register is also LT lockable. + - Valid options are 0 (0x0) to 2048MB (0x40) in multiples of 32 MB + - Default is 64MB + - All other values are reserved + - Hardware does not clear or set any of these bits automatically based on IGD being disabled/enabled. + - BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of this register) is 0. +**/ +#define N_SKL_SA_GGC_GMS_OFFSET (0x8) +#define S_SKL_SA_GGC_GMS_WIDTH (0x8) +#define B_SKL_SA_GGC_GMS_MASK (0xff00) +#define V_SKL_SA_GGC_GMS_DEFAULT (0x01) + +/** + For SKL + Description of GGMS (6:7) + - This field is used to select the amount of Main Memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled. + - GSM is assumed to be a contiguous physical DRAM space with DSM, and BIOS needs to allocate a contiguous memory chunk. Hardware will derive the base of GSM from DSM only using the GSM size programmed in the register. + - Valid options: + - 0h: 0 MB of memory pre-allocated for GTT. + - 1h: 2 MB of memory pre-allocated for GTT. + - 2h: 4 MB of memory pre-allocated for GTT. (default) + - 3h: 8 MB of memory pre-allocated for GTT. + - Others: Reserved + - Hardware functionality in case of programming this value to Reserved is not guaranteed. +**/ +#define N_SKL_SA_GGC_GGMS_OFFSET (0x6) +#define S_SKL_SA_GGC_GGMS_WIDTH (0x2) +#define B_SKL_SA_GGC_GGMS_MASK (0xc0) +#define V_SKL_SA_GGC_GGMS_DEFAULT (2) +#define V_SKL_SA_GGC_GGMS_DIS 0 +#define V_SKL_SA_GGC_GGMS_2MB 1 +#define V_SKL_SA_GGC_GGMS_4MB 2 +#define V_SKL_SA_GGC_GGMS_8MB 3 + +/** + Description: + - Allows for enabling/disabling of PCI devices and functions that are within the CPU package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. + All the bits in this register are LT Lockable. +**/ +#define R_SA_DEVEN (0x54) + +/** + Description + - Protected Audio Video Path Control + - All the bits in this register are locked by LT. When locked the R/W bits are RO. +**/ +#define R_SA_PAVPC (0x58) +/** + Description of PCME (0:0) + - This field enables Protected Content Memory within Graphics Stolen Memory. + - This register is locked (becomes read-only) when PAVPLCK = 1b. + - This register is read-only (stays at 0b) when PAVP fuse is set to "disabled" + - 0: Protected Content Memory is disabled + - 1: Protected Content Memory is enabled +**/ +#define N_SA_PAVPC_PCME_OFFSET (0x0) +#define S_SA_PAVPC_PCME_WIDTH (0x1) +#define B_SA_PAVPC_PCME_MASK (0x1) +#define V_SA_PAVPC_PCME_MASK (0x0) +/** + Description of PAVPE (1:1) + - 0: PAVP path is disabled + - 1: PAVP path is enabled + - This register is locked (becomes read-only) when PAVPLCK = 1b + - This register is read-only (stays at 0b) when PAVP capability is set to "disabled" as defined by CAPID0_B[PAVPE]. +**/ +#define N_SA_PAVPC_PAVPE_OFFSET (0x1) +#define S_SA_PAVPC_PAVPE_WIDTH (0x1) +#define B_SA_PAVPC_PAVPE_MASK (0x2) +#define V_SA_PAVPC_PAVPE_DEFAULT (0x0) +/** + Description of PAVPLCK (2:2) + - This bit will lock all writeable contents in this register when set (including itself). + - This bit will be locked if PAVP is fused off. +**/ +#define N_SA_PAVPC_PAVPLCK_OFFSET (0x2) +#define S_SA_PAVPC_PAVPLCK_WIDTH (0x1) +#define B_SA_PAVPC_PAVPLCK_MASK (0x4) +#define V_SA_PAVPC_PAVPLCK_DEFAULT (0x0) +/** + Description of PCMBASE (20:31) + - This field is used to set the base of Protected Content Memory. + - This corresponds to bits 31:20 of the system memory address range, giving a 1MB granularity. This value MUST be at least 1MB above the base and below the top of stolen memory. + - This register is locked (becomes read-only) when PAVPE = 1b. +**/ +#define N_SA_PAVPC_PCMBASE_OFFSET (0x14) +#define S_SA_PAVPC_PCMBASE_WIDTH (0xc) +#define B_SA_PAVPC_PCMBASE_MASK (0xfff00000) +#define V_SA_PAVPC_PCMBASE_DEFAULT (0x0) + +#define R_SA_DPR (0x5c) ///< DMA protected range register +/** + Description of LOCK (0:0) + - This bit will lock all writeable settings in this register, including itself. +**/ +#define N_SA_DPR_LOCK_OFFSET (0x0) +#define S_SA_DPR_LOCK_WIDTH (0x1) +#define B_SA_DPR_LOCK_MASK (0x1) +#define V_SA_DPR_LOCK_DEFAULT (0x0) +/** + Description of PRS (1:1) + - This field indicates the status of DPR. + - 0: DPR protection disabled + - 1: DPR protection enabled +**/ +#define N_SA_DPR_PRS_OFFSET (0x1) +#define S_SA_DPR_PRS_WIDTH (0x1) +#define B_SA_DPR_PRS_MASK (0x2) +#define V_SA_DPR_PRS_DEFAULT (0x0) +/** + Description of EPM (2:2) + - This field controls DMA accesses to the DMA Protected Range (DPR) region. + - 0: DPR is disabled + - 1: DPR is enabled. All DMA requests accessing DPR region are blocked. + - HW reports the status of DPR enable/disable through the PRS field in this register. +**/ +#define N_SA_DPR_EPM_OFFSET (0x2) +#define S_SA_DPR_EPM_WIDTH (0x1) +#define B_SA_DPR_EPM_MASK (0x4) +#define V_SA_DPR_EPM_DEFAULT (0x0) +/** + Description of DPRSIZE (11:4) + - This field is used to specify the size of memory protected from DMA access in MB + - The maximum amount of memory that will be protected is 255MB + - The Top of protected range is the base of TSEG-1 +**/ +#define N_DPR_DPRSIZE_OFFSET (0x4) +#define V_DPR_DPRSIZE_WIDTH (0x8) +#define V_DPR_DPRSIZE_MASK (0xFF0) +#define V_DPR_DPRSIZE_DEFAULT (0x0) +/** + Description of TOPOFDPR (31:20) + - This is the Top address 1 of DPR - Base of TSEG +**/ +#define N_SA_DPR_TOPOFDPR_OFFSET (20) +#define S_SA_DPR_TOPOFDPR_WIDTH (0xC) +#define B_SA_DPR_TOPOFDPR_MASK (0xFFF00000) +#define V_SA_DPR_TOPOFDPR_DEFAULT (0x0) + +/** + This is the base address for the Root Complex configuration space. This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge. There is no physical memory within this 4KB window that can be addressed. The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. On reset, the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0] All the bits in this register are locked in LT mode. +**/ +#define R_SA_DMIBAR (0x68) +/** + Description of DMIBAREN (0:0) + - 0: DMIBAR is disabled and does not claim any memory + - 1: DMIBAR memory mapped accesses are claimed and decoded appropriately + - This register is locked by LT. +**/ +#define N_SA_DMIBAR_DMIBAREN_OFFSET (0x0) +#define S_SA_DMIBAR_DMIBAREN_WIDTH (0x1) +#define B_SA_DMIBAR_DMIBAREN_MASK (0x1) +#define V_SA_DMIBAR_DMIBAREN_DEFAULT (0x0) +/** + Description of DMIBAR (12:38) + - This field corresponds to bits 38 to 12 of the base address DMI configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the DMI register set. All the Bits in this register are locked in LT mode. +**/ +#define N_SA_DMIBAR_DMIBAR_OFFSET (0xc) +#define S_SA_DMIBAR_DMIBAR_WIDTH (0x1b) +#define B_SA_DMIBAR_DMIBAR_MASK (0x7ffffff000) +#define V_SA_DMIBAR_DMIBAR_DEFAULT (0x0) + +/** + Description: + - This register determines the Mask Address register of the memory range that is pre-allocated to the Manageability Engine. Together with the MESEG_BASE register it controls the amount of memory allocated to the ME. + - This register is locked by LT. +**/ +#define R_SA_MESEG_MASK (0x78) +/** + Description of MELCK (10:10) + - This field indicates whether all bits in the MESEG_BASE and MESEG_MASK registers are locked. When locked, updates to any field for these registers must be dropped. +**/ +#define N_SA_MESEG_MASK_MELCK_OFFSET (0xa) +#define S_SA_MESEG_MASK_MELCK_WIDTH (0x1) +#define B_SA_MESEG_MASK_MELCK_MASK (0x400) +#define V_SA_MESEG_MASK_MELCK_DEFAULT (0x0) +/** + Description of ME_STLEN_EN (11:11) + - Indicates whether the ME stolen Memory range is enabled or not. +**/ +#define N_SA_MESEG_MASK_ME_STLEN_EN_OFFSET (0xb) +#define S_SA_MESEG_MASK_ME_STLEN_EN_WIDTH (0x1) +#define B_SA_MESEG_MASK_ME_STLEN_EN_MASK (0x800) +#define V_SA_MESEG_MASK_ME_STLEN_EN_DEFAULT (0x0) +/** + Description of MEMASK (20:38) + - This field indicates the bits that must match MEBASE in order to qualify as an ME Memory Range access. + - For example, if the field is set to 7FFFFh, then ME Memory is 1MB in size. + - Another example is that if the field is set to 7FFFEh, then ME Memory is 2MB in size. + - In other words, the size of ME Memory Range is limited to power of 2 times 1MB. +**/ +#define N_SA_MESEG_MASK_MEMASK_OFFSET (0x14) +#define S_SA_MESEG_MASK_MEMASK_WIDTH (0x13) +#define B_SA_MESEG_MASK_MEMASK_MASK (0x7ffff00000) +#define V_SA_MESEG_MASK_MEMASK_DEFAULT (0x0) + +/** + Description: + - This register controls the read, write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core. + - Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are: + - RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI. + - WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI. + - The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only. +**/ +#define R_SA_PAM0 (0x80) +/// +/// Description: +/// This register controls the read, write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core. +/// Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are: +/// RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI. +/// WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI. +/// The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only. +/// +#define R_SA_PAM5 (0x85) +/// +/// Description: +/// This register controls the read, write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh. The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768KB to 1MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR register in the core. +/// Two bits are used to specify memory attributes for each memory segment. These bits apply to host accesses to the PAM areas. These attributes are: +/// RE - Read Enable. When RE=1, the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when RE=0, the host read accesses are directed to DMI. +/// WE - Write Enable. When WE=1, the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory. Conversely, when WE=0, the host read accesses are directed to DMI. +/// The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the segment is Read Only. +/// +#define R_SA_PAM6 (0x86) +/// +/// Description: +/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set. +/// +#define R_SA_SMRAMC (0x88) + +/// +/// Description: +/// +#define R_SA_REMAPBASE (0x90) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_REMAPBASE_LOCK_OFFSET (0x0) +#define S_SA_REMAPBASE_LOCK_WIDTH (0x1) +#define B_SA_REMAPBASE_LOCK_MASK (0x1) +#define V_SA_REMAPBASE_LOCK_DEFAULT (0x0) +/// +/// Description of REMAPBASE (20:35) +/// The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[19:0] of the Remap Base Address are assumed to be 0's. Thus the bottom of the defined memory range will be aligned to a 1MB boundary. +/// When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled. +/// These bits are LT lockable. +/// +#define N_SA_REMAPBASE_REMAPBASE_OFFSET (0x14) +#define S_SA_REMAPBASE_REMAPBASE_WIDTH (0x10) +#define B_SA_REMAPBASE_REMAPBASE_MASK (0xffff00000) +#define V_SA_REMAPBASE_REMAPBASE_DEFAULT (0xffff00000) + +/// +/// Description: +/// +#define R_SA_REMAPLIMIT (0x98) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_REMAPLIMIT_LOCK_OFFSET (0x0) +#define S_SA_REMAPLIMIT_LOCK_WIDTH (0x1) +#define B_SA_REMAPLIMIT_LOCK_MASK (0x1) +#define V_SA_REMAPLIMIT_LOCK_DEFAULT (0x0) +/// +/// Description of REMAPLMT (20:35) +/// The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[19:0] of the remap limit address are assumed to be F's. Thus the top of the defined range will be one byte less than a 1MB boundary. +/// When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled. +/// These Bits are LT lockable. +/// +#define N_SA_REMAPLIMIT_REMAPLMT_OFFSET (0x14) +#define S_SA_REMAPLIMIT_REMAPLMT_WIDTH (0x10) +#define B_SA_REMAPLIMIT_REMAPLMT_MASK (0xffff00000) +#define V_SA_REMAPLIMIT_REMAPLMT_DEFAULT (0x0) + +/// +/// Description: +/// This Register contains the size of physical memory. BIOS determines the memory size reported to the OS using this Register. +/// +#define R_SA_TOM (0xa0) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_TOM_LOCK_OFFSET (0x0) +#define S_SA_TOM_LOCK_WIDTH (0x1) +#define B_SA_TOM_LOCK_MASK (0x1) +#define V_SA_TOM_LOCK_DEFAULT (0x0) + +/// +/// Description of TOM (20:38) +/// This register reflects the total amount of populated physical memory. This is NOT necessarily the highest main memory address (holes may exist in main memory address map due to addresses allocated for memory mapped IO). These bits correspond to address bits 38:20 (1MB granularity). Bits 19:0 are assumed to be 0. All the bits in this register are locked in LT mode. +/// +#define N_SA_TOM_TOM_OFFSET (0x14) +#define S_SA_TOM_TOM_WIDTH (0x13) +#define B_SA_TOM_TOM_MASK (0x7ffff00000) +#define V_SA_TOM_TOM_DEFAULT (0x7ffff00000) + +/// +/// Description: +/// This 64 bit register defines the Top of Upper Usable DRAM. +/// Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1byte, 1MB aligned, since reclaim limit is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4GB. +/// BIOS Restriction: Minimum value for TOUUD is 4GB. +/// These bits are LT lockable. +/// +#define R_SA_TOUUD (0xa8) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_TOUUD_LOCK_OFFSET (0x0) +#define S_SA_TOUUD_LOCK_WIDTH (0x1) +#define B_SA_TOUUD_LOCK_MASK (0x1) +#define V_SA_TOUUD_LOCK_DEFAULT (0x0) +/// +/// Description of TOUUD (20:38) +/// This register contains bits 38 to 20 of an address one byte above the maximum DRAM memory above 4G that is usable by the operating system. Configuration software must set this value to TOM minus all EP stolen memory if reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit 1MB aligned since reclaim limit + 1byte is 1MB aligned. Address bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4GB. +/// All the bits in this register are locked in LT mode. +/// +#define N_SA_TOUUD_TOUUD_OFFSET (0x14) +#define S_SA_TOUUD_TOUUD_WIDTH (0x13) +#define B_SA_TOUUD_TOUUD_MASK (0x7ffff00000ULL) +#define V_SA_TOUUD_TOUUD_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BC bits 31:20). +/// +#define R_SA_BDSM (0xb0) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_BDSM_LOCK_OFFSET (0x0) +#define S_SA_BDSM_LOCK_WIDTH (0x1) +#define B_SA_BDSM_LOCK_MASK (0x1) +#define V_SA_BDSM_LOCK_DEFAULT (0x0) +/// +/// Description of BDSM (20:31) +/// This register contains bits 31 to 20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0 offset 52 bits 6:4) from TOLUD (PCI Device 0 offset BC bits 31:20). +/// +#define N_SA_BDSM_BDSM_OFFSET (0x14) +#define S_SA_BDSM_BDSM_WIDTH (0xc) +#define B_SA_BDSM_BDSM_MASK (0xfff00000) +#define V_SA_BDSM_BDSM_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). +/// +#define R_SA_BGSM (0xb4) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_BGSM_LOCK_OFFSET (0x0) +#define S_SA_BGSM_LOCK_WIDTH (0x1) +#define B_SA_BGSM_LOCK_MASK (0x1) +#define V_SA_BGSM_LOCK_DEFAULT (0x0) +/// +/// Description of BGSM (20:31) +/// This register contains the base address of stolen DRAM memory for the GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size (PCI Device 0 offset 52 bits 11:8) from the Graphics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20). +/// +#define N_SA_BGSM_BGSM_OFFSET (0x14) +#define S_SA_BGSM_BGSM_WIDTH (0xc) +#define B_SA_BGSM_BGSM_MASK (0xfff00000) +#define V_SA_BGSM_BGSM_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20). +/// +#define R_SA_TSEGMB (0xb8) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_TSEGMB_LOCK_OFFSET (0x0) +#define S_SA_TSEGMB_LOCK_WIDTH (0x1) +#define B_SA_TSEGMB_LOCK_MASK (0x1) +#define V_SA_TSEGMB_LOCK_DEFAULT (0x0) +/// +/// Description of TSEGMB (20:31) +/// This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset B4 bits 31:20). +/// +#define N_SA_TSEGMB_TSEGMB_OFFSET (0x14) +#define S_SA_TSEGMB_TSEGMB_WIDTH (0xc) +#define B_SA_TSEGMB_TSEGMB_MASK (0xfff00000) +#define V_SA_TSEGMB_TSEGMB_DEFAULT (0x0) + +/// +/// Description: +/// This register contains the Top of low memory address. +/// +#define R_SA_TOLUD (0xbc) +/// +/// Description of LOCK (0:0) +/// This bit will lock all writeable settings in this register, including itself. +/// +#define N_SA_TOLUD_LOCK_OFFSET (0x0) +#define S_SA_TOLUD_LOCK_WIDTH (0x1) +#define B_SA_TOLUD_LOCK_MASK (0x1) +#define V_SA_TOLUD_LOCK_DEFAULT (0x0) +/// +/// Description of TOLUD (20:31) +/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register. +/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode. +/// This register must be 1MB aligned when reclaim is enabled. +/// +#define N_SA_TOLUD_TOLUD_OFFSET (0x14) +#define S_SA_TOLUD_TOLUD_WIDTH (0xc) +#define B_SA_TOLUD_TOLUD_MASK (0xfff00000) +#define V_SA_TOLUD_TOLUD_DEFAULT (0x100000) + +#define R_SA_MC_CAPID0_A_OFFSET 0xE4 + +// +// Thermal Management Controls +// +/// +/// Device 2 Register Equates +// +// The following equates must be reviewed and revised when the specification is ready. +// +#define SA_IGD_BUS 0x00 +#define SA_IGD_DEV 0x02 +#define SA_IGD_FUN_0 0x00 +#define SA_IGD_FUN_1 0x01 +#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3) +#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN +#define V_SA_IGD_VID 0x8086 +#define V_SA_IGD_DID 0x2A42 +#define V_SA_IGD_DID_MB 0x0106 +#define V_SA_IGD_DID_MB_1 0x0116 +#define V_SA_IGD_DID_MB_2 0x0126 +#define V_SA_IGD_DID_DT 0x0102 +#define V_SA_IGD_DID_DT_1 0x0112 +#define V_SA_IGD_DID_DT_2 0x0122 +#define V_SA_IGD_DID_DT_3 0x010A + +/// +/// For SKL IGD +/// +#define V_SA_PCI_DEV_2_GT1_SULTM_ID 0x01906 ///< Dev2-SKL ULT GT1 (2+1F) Mobile +#define V_SA_PCI_DEV_2_GT15F_SULTM_ID 0x01913 ///< Dev2-SKL ULT GT1.5 (2+1.5F) Mobile +#define V_SA_PCI_DEV_2_GT2_SULTM_ID 0x01916 ///< Dev2-SKL ULT GT2 (2+2) Mobile +#define V_SA_PCI_DEV_2_GT2F_SULTM_ID 0x01921 ///< Dev2-SKL ULT GT2 (2+2F) Mobile +#define V_SA_PCI_DEV_2_GT3_SULTM_ID 0x01926 ///< Dev2-SKL ULT GT3 (3+3/3E) Mobile +#define V_SA_PCI_DEV_2_GT1_SHALM_ID 0x0190B ///< Dev2-SKL Halo GT1 (2+1) +#define V_SA_PCI_DEV_2_GT2_SHALM_ID 0x0191B ///< Dev2-SKL Halo GT2 (4/2+2) +#define V_SA_PCI_DEV_2_GT3_SHALM_ID 0x0192B ///< Dev2-SKL Halo GT3 (4+3FE) +#define V_SA_PCI_DEV_2_GT4_SHALM_ID 0x0193B ///< Dev2-SKL Halo GT4 (4+4E) +#define V_SA_PCI_DEV_2_GT1_SULXM_ID 0x0190E ///< Dev2-SKL ULX GT1(2+1F) Mobile +#define V_SA_PCI_DEV_2_GT15_SULXM_ID 0x01915 ///< Dev2-SKL ULX GT1.5(2+1.5F) Mobile +#define V_SA_PCI_DEV_2_GT2_SULXM_ID 0x0191E ///< Dev2-SKL ULX GT2 (2+2)Mobile +#define V_SA_PCI_DEV_2_GT1_SSR_ID 0x0190A ///< Dev2-SKL GT1 (4+1F) Server +#define V_SA_PCI_DEV_2_GT2_SSR_ID 0x0191A ///< Dev2-SKL GT2 (4/2+2) Server +#define V_SA_PCI_DEV_2_GT3_SSR_ID 0x0192A ///< Dev2-SKL GT3 (2+3E) Server +#define V_SA_PCI_DEV_2_GT4_SSR_ID 0x0193A ///< Dev2-SKL GT4 (4+4E) Server +#define V_SA_PCI_DEV_2_GT1_SDT_ID 0x01902 ///< Dev2-SKL GT1 (2+1F) Desktop +#define V_SA_PCI_DEV_2_GT2_SDT_ID 0x01912 ///< Dev2-SKL GT2 (4/2+2) Desktop +#define V_SA_PCI_DEV_2_GT15_SDT_ID 0x01917 ///< Dev2-SKL GT1.5 (2+1.5F) Desktop +#define V_SA_PCI_DEV_2_GT4_SDT_ID 0x01932 ///< Dev2-SKL GT4 (4+4) Desktop + +#define R_SA_IGD_VID 0x00 +#define R_SA_IGD_DID 0x02 +#define R_SA_IGD_CMD 0x04 +/// +/// GTTMMADR for SKL is 16MB alignment (Base address = [38:24]) +/// +#define R_SA_IGD_GTTMMADR 0x10 +#define R_SA_IGD_GMADR 0x18 +#define R_SA_IGD_IOBAR 0x20 +#define R_SA_IGD_BSM_OFFSET 0x005C ///< Base of Stolen Memory +#define R_SA_IGD_MSAC_OFFSET 0x0062 ///< Multisize Aperture Control +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage +/// +/// Maximum number of SDRAM channels supported by the memory controller +/// +/// +/// Maximum number of SDRAM channels supported by the memory controller +/// +#define SA_MC_MAX_CHANNELS 2 +/// +/// Maximum number of DIMM sockets supported by each channel +/// +#define SA_MC_MAX_SLOTS 2 + +/// +/// Maximum number of sides supported per DIMM +/// +#define SA_MC_MAX_SIDES 2 + +/// +/// Maximum number of DIMM sockets supported by the memory controller +/// +#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS) + +/// +/// Maximum memory supported by the memory controller +/// 4 GB in terms of KB +/// +#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024) + +/// +/// Define the SPD Address for DIMM 0 +/// +#define SA_MC_DIMM0_SPD_ADDRESS 0xA0 + +/// +/// Define the maximum number of data bytes on a system with no ECC memory support. +/// +#define SA_MC_MAX_BYTES_NO_ECC (8) + +/// +/// Define the maximum number of SPD data bytes on a DIMM. +/// +#define SA_MC_MAX_SPD_SIZE (512) + +/// +/// Vt-d Engine base address. +/// +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT2 for IGD +#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT3 for all other - PEG, USB, SATA etc + +#endif diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/Library/PchResetCommonLib.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/Library/PchResetCommonLib.h new file mode 100644 index 0000000000..c64d3dbb47 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/Library/PchResetCommonLib.h @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_RESET_COMMON_LIB_H_ +#define _PCH_RESET_COMMON_LIB_H_ +#include <Uefi/UefiSpec.h> +#include <Protocol/PchReset.h> +/// +/// Private data structure definitions for the driver +/// +#define PCH_RESET_SIGNATURE SIGNATURE_32 ('I', 'E', 'R', 'S') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + union { + PCH_RESET_PPI PchResetPpi; + PCH_RESET_PROTOCOL PchResetProtocol; + }PchResetInterface; + UINT32 PchPwrmBase; + UINT16 PchAcpiBase; + UINTN PchPmcBase; +} PCH_RESET_INSTANCE; + +// +// Function prototypes used by the Pch Reset ppi/protocol. +// +/** + Initialize an Pch Reset ppi/protocol instance. + + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initialized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +PchResetConstructor ( + PCH_RESET_INSTANCE *PchResetInstance + ); + +/** + Execute Pch Reset from the host controller. + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +EFI_STATUS +PchReset ( + IN PCH_RESET_INSTANCE *PchResetInstance, + IN PCH_RESET_TYPE PchResetType + ); +#endif diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioAx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioAx.h new file mode 100644 index 0000000000..9b3eb39a3e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioAx.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_H_HSIO_AX_H_ +#define _PCH_H_HSIO_AX_H_ + +#define PCH_H_HSIO_VER_AX 0x11 + +extern UINT8 PchHChipsetInitTable_Ax[1300]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Ax[136]; + +#endif //_PCH_H_HSIO_AX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioBx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioBx.h new file mode 100644 index 0000000000..2d191d9863 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioBx.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_H_HSIO_BX_H_ +#define _PCH_H_HSIO_BX_H_ + +#define PCH_H_HSIO_VER_BX 0x3e + +extern UINT8 PchHChipsetInitTable_Bx[2060]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Bx[136]; + +#endif //_PCH_H_HSIO_BX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioDx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioDx.h new file mode 100644 index 0000000000..ed97364512 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHHsioDx.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_H_HSIO_DX_H_ +#define _PCH_H_HSIO_DX_H_ + +#define PCH_H_HSIO_VER_DX 0x34 + +extern UINT8 PchHChipsetInitTable_Dx[2180]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchHHsio_Dx[157]; + +#endif //_PCH_H_HSIO_DX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHsio.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHsio.h new file mode 100644 index 0000000000..4f14f5bf63 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchHsio.h @@ -0,0 +1,153 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_HSIO_H_ +#define _PCH_HSIO_H_ + +#define PCH_HSIO_SKU_SKL 0x01 + +#define PCH_LANE_OWN_COMMON 0x10 +#define PCH_LANE_BDCAST 0x11 + +#define PCH_HSIO_LANE_GROUP_NO 0x09 +#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00 +#define PCH_HSIO_LANE_GROUP_PCIE 0x01 +#define PCH_HSIO_LANE_GROUP_DMI 0x02 +#define PCH_HSIO_LANE_GROUP_GBE 0x03 +#define PCH_HSIO_LANE_GROUP_USB3 0x04 +#define PCH_HSIO_LANE_GROUP_SATA 0x05 +#define PCH_HSIO_LANE_GROUP_SSIC 0x06 + +#define PCH_MODPHY0_LP_LOS1_LANE_START 0x00 +#define PCH_MODPHY0_LP_LOS1_LANE_END 0x05 +#define PCH_MODPHY1_LP_LOS1_LANE_START 0x06 +#define PCH_MODPHY1_LP_LOS1_LANE_END 0x07 +#define PCH_MODPHY1_LP_LOS2_LANE_START 0x00 +#define PCH_MODPHY1_LP_LOS2_LANE_END 0x01 +#define PCH_MODPHY2_LP_LOS2_LANE_START 0x02 +#define PCH_MODPHY2_LP_LOS2_LANE_END 0x07 + +#define PCH_MODPHY1_LOS1_LANE_START 0x00 +#define PCH_MODPHY1_LOS1_LANE_END 0x07 +#define PCH_MODPHY1_LOS2_LANE_START 0x00 +#define PCH_MODPHY1_LOS2_LANE_END 0x01 +#define PCH_MODPHY2_LOS2_LANE_START 0x02 +#define PCH_MODPHY2_LOS2_LANE_END 0x07 +#define PCH_MODPHY2_LOS3_LANE_START 0x00 +#define PCH_MODPHY2_LOS3_LANE_END 0x07 +#define PCH_MODPHY2_LOS4_LANE_START 0x00 +#define PCH_MODPHY2_LOS4_LANE_END 0x01 + +/** + PCH SBI HSIO table data structure +**/ +typedef struct { + UINT32 PortId; + UINT32 Value; + UINT16 Offset; + UINT8 LanePhyMode; +} PCH_SBI_HSIO_TABLE_STRUCT; + + +#define PMC_DATA_SBI_CMD_SIZE ((12/sizeof(UINT16))-1) +#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1) + +// Commands specified command table and processed by the PMC & it's HW accelerator +typedef enum { + SendSBIPosted = 0x0, // Perform a SBI Write & wait for result + SendSBINonPosted, // Perform a SBI Write & ignore return result (Not Supported in HW) + DoDelay, // PMC Inserts Delay when command detected + EndStruct = 0x7 // No-op Command indicating end of list +} PHY_COMMANDS; + +/** +PCH HSIO PMC XRAM Header +**/ +typedef struct { + UINT16 Word0; + UINT16 Word1; + UINT16 Word2; + UINT16 Word3; + UINT16 Word4; + UINT16 Word5; + UINT16 Word6; + UINT16 Word7; + UINT16 Word8; + UINT16 Word9; + UINT16 Word10; + UINT16 Word11; + UINT16 Word12; + UINT16 Word13; + UINT16 Word14; + UINT16 Word15; +} PCH_SBI_HSIO_HDR_TBL; + +/** +PCH HSIO PMC XRAM Data +**/ +typedef struct { + UINT8 Command : 3; + UINT8 Size : 5; + UINT8 Pid; + UINT8 OpCode; //PrivateControlWrite + UINT8 Bar; //0 + UINT8 Fbe; //First Byte Enable : 0x0F + UINT8 Fid; //0 + UINT16 Offset; + UINT32 Value; +} PCH_SBI_HSIO_CMD_TBL; + +/** +PCH HSIO Delay XRAM Data +**/ +typedef struct { + UINT8 Command : 3; + UINT8 Size : 5; + UINT8 DelayPeriod; //(00h = 1us, 01h = 10us, 02h = 100us, ..., 07h = 10s; others reserved) + UINT8 DelayCount; //(0 - 255); total delay = Delay period * Delay count + UINT8 Padding; +} PCH_DELAY_HSIO_CMD_TBL; + +typedef enum { + Delay1us = 0x0, + Delay10us, + Delay100us, + Delay1ms, + Delay10ms, + Delay100ms, + Delay1s, + Delay10s +} DELAY; + +/** +PCH PCIE PLL SSC Data +**/ +#define MAX_PCIE_PLL_SSC_PERCENT 20 + +#include <IncludePrivate/PchHHsioBx.h> +#include <IncludePrivate/PchHHsioDx.h> +#include <IncludePrivate/PchLpHsioBx.h> +#include <IncludePrivate/PchLpHsioCx.h> + +#include <IncludePrivate/PchLbgHsioAx.h> +#include <IncludePrivate/PchLbgHsioBx.h> +#include <IncludePrivate/PchLbgHsioBx_Ext.h> +#include <IncludePrivate/PchLbgHsioSx.h> +#include <IncludePrivate/PchLbgHsioSx_Ext.h> +#ifdef SKXD_EN +#include <IncludePrivate/PchLbgHsioBxD.h> +#include <IncludePrivate/PchLbgHsioBxD_Ext.h> +#endif // SKXD_EN + +#endif //_PCH_HSIO_H_ + diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioAx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioAx.h new file mode 100644 index 0000000000..6c15d5fbd5 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioAx.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LBG_HSIO_AX_H_ +#define _PCH_LBG_HSIO_AX_H_ + +#define PCH_LBG_HSIO_VER_AX 0x19 + +extern UINT8 PchLbgChipsetInitTable_Ax[2988]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchLbgHsio_Ax[81]; + +#endif //_PCH_LBG_HSIO_AX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBx.h new file mode 100644 index 0000000000..08c0685807 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBx.h @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LBG_HSIO_BX_H_ +#define _PCH_LBG_HSIO_BX_H_ + +#define PCH_LBG_HSIO_VER_BX 0x2f + +extern UINT8 PchLbgChipsetInitTable_Bx[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Bx_Ptr; +extern UINT16 PchLbgHsio_Bx_Size; + +#endif //_PCH_LBG_HSIO_BX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBxD.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBxD.h new file mode 100644 index 0000000000..aa1b9d850c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBxD.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifdef SKXD_EN +#ifndef _PCH_LBG_HSIO_BX_D_H_ +#define _PCH_LBG_HSIO_BX_D_H_ + +#define PCH_LBG_HSIO_VER_BX_D 0x1 + +extern UINT8 PchLbgChipsetInitTable_BxD[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_BxD_Ptr; +extern UINT16 PchLbgHsio_BxD_Size; + +#endif //_PCH_LBG_HSIO_BX_D_H_ +#endif // SKXD_EN diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBxD_Ext.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBxD_Ext.h new file mode 100644 index 0000000000..45bd8b754c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBxD_Ext.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifdef SKXD_EN +#ifndef _PCH_LBG_HSIO_BX_D_EXT_H_ +#define _PCH_LBG_HSIO_BX_D_EXT_H_ + +#define PCH_LBG_HSIO_VER_BX_D_EXT 0x1 + +extern UINT8 PchLbgChipsetInitTable_BxD_Ext[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_BxD_Ext_Ptr; +extern UINT16 PchLbgHsio_BxD_Ext_Size; + +#endif //_PCH_LBG_HSIO_BX_D_EXT_H_ +#endif // SKXD_EN diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBx_Ext.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBx_Ext.h new file mode 100644 index 0000000000..2a8e17eaca --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioBx_Ext.h @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LBG_HSIO_BX_EXT_H_ +#define _PCH_LBG_HSIO_BX_EXT_H_ + +#define PCH_LBG_HSIO_VER_BX_EXT 0x2f + +extern UINT8 PchLbgChipsetInitTable_Bx_Ext[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Bx_Ext_Ptr; +extern UINT16 PchLbgHsio_Bx_Ext_Size; + +#endif //_PCH_LBG_HSIO_BX_EXT_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioSx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioSx.h new file mode 100644 index 0000000000..992a385501 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioSx.h @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LBG_HSIO_SX_H_ +#define _PCH_LBG_HSIO_SX_H_ + +#define PCH_LBG_HSIO_VER_SX 0x8 + +extern UINT8 PchLbgChipsetInitTable_Sx[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Sx_Ptr; +extern UINT16 PchLbgHsio_Sx_Size; + +#endif //_PCH_LBG_HSIO_SX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioSx_Ext.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioSx_Ext.h new file mode 100644 index 0000000000..8f28fce83e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLbgHsioSx_Ext.h @@ -0,0 +1,23 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LBG_HSIO_SX_EXT_H_ +#define _PCH_LBG_HSIO_SX_EXT_H_ + +#define PCH_LBG_HSIO_VER_SX_EXT 0x8 + +extern UINT8 PchLbgChipsetInitTable_Sx_Ext[2844]; +extern PCH_SBI_HSIO_TABLE_STRUCT *PchLbgHsio_Sx_Ext_Ptr; +extern UINT16 PchLbgHsio_Sx_Ext_Size; + +#endif //_PCH_LBG_HSIO_SX_EXT_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLpHsioBx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLpHsioBx.h new file mode 100644 index 0000000000..98125eaf1a --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLpHsioBx.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LP_HSIO_BX_H_ +#define _PCH_LP_HSIO_BX_H_ + +#define PCH_LP_HSIO_VER_BX 0x3e + +extern UINT8 PchLpChipsetInitTable_Bx[1492]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchLpHsio_Bx[109]; + +#endif //_PCH_LP_HSIO_BX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLpHsioCx.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLpHsioCx.h new file mode 100644 index 0000000000..0548f446de --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchLpHsioCx.h @@ -0,0 +1,22 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_LP_HSIO_CX_H_ +#define _PCH_LP_HSIO_CX_H_ + +#define PCH_LP_HSIO_VER_CX 0x34 + +extern UINT8 PchLpChipsetInitTable_Cx[1548]; +extern PCH_SBI_HSIO_TABLE_STRUCT PchLpHsio_Cx[120]; + +#endif //_PCH_LP_HSIO_CX_H_
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/IncludePrivate/PchPolicyHob.h b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchPolicyHob.h new file mode 100644 index 0000000000..eb2bff904e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/IncludePrivate/PchPolicyHob.h @@ -0,0 +1,24 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCH_POLICY_HOB_H_ +#define _PCH_POLICY_HOB_H_ + +#include <PchPolicyCommon.h> + +typedef struct _PCH_POLICY PCH_POLICY_HOB; + +extern EFI_GUID gPchPolicyHobGuid; + +#endif // _PCH_POLICY_HOB_H_ + diff --git a/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf b/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf new file mode 100644 index 0000000000..353aafa572 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf @@ -0,0 +1,70 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxeRuntimeResetSystemLib
+ FILE_GUID = 5602DBE0-2576-44CB-95FF-53D5A18C775F
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ LIBRARY_CLASS = ResetSystemLib
+ CONSTRUCTOR = InstallPchReset
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 EBC
+#
+
+[LibraryClasses]
+ IoLib
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiRuntimeLib
+ PchCycleDecodingLib
+ DxeServicesTableLib
+ PchResetCommonLib
+ HobLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ LewisburgPkg/PchRcPkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+[Sources]
+ PchReset.c
+ PchReset.h
+
+
+[Protocols]
+ gPchResetCallbackProtocolGuid ## CONSUMES
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+ gEfiCapsuleVendorGuid
+ gPchPowerCycleResetGuid
+ gPchGlobalResetGuid
+ gPchGlobalResetWithEcGuid
+ gPchPolicyHobGuid
+
+
+[Depex]
+ gEfiPciRootBridgeIoProtocolGuid AND # SERVER_BIOS_FLAG
+ TRUE
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/PchReset.c b/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/PchReset.c new file mode 100644 index 0000000000..cdc0f19c17 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/PchReset.c @@ -0,0 +1,598 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PchReset.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_INSTANCE *mPchResetInstance;
+STATIC UINT8 mDaysOfMonthInfo[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_DATA mPchPowerCycleReset = {
+ PCH_PLATFORM_SPECIFIC_RESET_STRING,
+ PCH_POWER_CYCLE_RESET_GUID
+};
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_DATA mPchGlobalReset = {
+ PCH_PLATFORM_SPECIFIC_RESET_STRING,
+ PCH_GLOBAL_RESET_GUID
+};
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_RESET_DATA mPchGlobalResetWithEc = {
+ PCH_PLATFORM_SPECIFIC_RESET_STRING,
+ PCH_GLOBAL_RESET_WITH_EC_GUID
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mCapsuleResetType = 0;
+
+/**
+ Check if it is leap year
+
+ @param[in] Year year to be check
+
+ @retval True year is leap year
+ @retval FALSE year is not a leap year
+**/
+BOOLEAN
+IsLeapYear (
+ IN UINT16 Year
+ )
+{
+ return (Year % 4 == 0) && ((Year % 100 != 0) || (Year % 400 == 0));
+}
+
+/**
+ Set System Wakeup Alarm.
+
+ @param[in] WakeAfter Time offset in seconds to wake from S3
+
+ @retval EFI_SUCCESS Timer started successfully
+**/
+STATIC
+EFI_STATUS
+SetSystemWakeupAlarm (
+ IN UINT32 WakeAfter
+ )
+{
+ EFI_STATUS Status;
+ EFI_TIME Time;
+ EFI_TIME_CAPABILITIES Capabilities;
+ UINT32 Reminder;
+ UINT16 ABase;
+ UINT8 DayOfMonth;
+
+ ///
+ /// For an instant wake 2 seconds is a safe value
+ ///
+ if (WakeAfter < 2) {
+ WakeAfter = 2;
+ }
+
+ Status = EfiGetTime (&Time, &Capabilities);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ Reminder = WakeAfter + (UINT32) Time.Second;
+ Time.Second = Reminder % 60;
+ Reminder = Reminder / 60;
+ Reminder = Reminder + (UINT32) Time.Minute;
+ Time.Minute = Reminder % 60;
+ Reminder = Reminder / 60;
+ Reminder = Reminder + (UINT32) Time.Hour;
+ Time.Hour = Reminder % 24;
+ Reminder = Reminder / 24;
+
+ if (Reminder > 0) {
+ Reminder = Reminder + (UINT32) Time.Day;
+ if ((Time.Month == 2) && IsLeapYear (Time.Year)) {
+ DayOfMonth = 29;
+ } else {
+ DayOfMonth = mDaysOfMonthInfo[Time.Month - 1];
+ }
+ if (Reminder > DayOfMonth) {
+ Time.Day = (UINT8)Reminder - DayOfMonth;
+ Reminder = 1;
+ } else {
+ Time.Day = (UINT8)Reminder;
+ Reminder = 0;
+ }
+ }
+ if (Reminder > 0) {
+ if (Time.Month == 12) {
+ Time.Month = 1;
+ Time.Year = Time.Year + 1;
+ } else {
+ Time.Month = Time.Month + 1;
+ }
+ }
+
+ Status = EfiSetWakeupTime (TRUE, &Time);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ ABase = mPchResetInstance->PchAcpiBase;
+
+
+ ///
+ /// Clear RTC PM1 status
+ ///
+ IoWrite16 (ABase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_RTC);
+
+ ///
+ /// set RTC_EN bit in PM1_EN to wake up from the alarm
+ ///
+ IoWrite16 (
+ ABase + R_PCH_ACPI_PM1_EN,
+ (IoRead16 (ABase + R_PCH_ACPI_PM1_EN) | B_PCH_ACPI_PM1_EN_RTC)
+ );
+ return Status;
+}
+
+/**
+ Retrieve PCH platform specific ResetData
+
+ @param[in] Guid PCH platform specific reset GUID.
+ @param[out] DataSize The size of ResetData in bytes.
+
+ @retval ResetData A platform specific reset that the exact type of
+ the reset is defined by the EFI_GUID that follows
+ the Null-terminated Unicode string.
+ @retval NULL If Guid is not defined in PCH platform specific reset.
+**/
+VOID *
+EFIAPI
+GetResetData (
+ IN EFI_GUID *Guid,
+ OUT UINTN *DataSize
+ )
+{
+ *DataSize = 0;
+ if (CompareGuid (Guid, &gPchPowerCycleResetGuid)) {
+ *DataSize = sizeof (mPchPowerCycleReset);
+ return (VOID *)&mPchPowerCycleReset;
+ } else if (CompareGuid (Guid, &gPchGlobalResetGuid)) {
+ *DataSize = sizeof (mPchGlobalReset);
+ return (VOID *)&mPchGlobalReset;
+ } else if (CompareGuid (Guid, &gPchGlobalResetWithEcGuid)) {
+ *DataSize = sizeof (mPchGlobalResetWithEc);
+ return (VOID *)&mPchGlobalResetWithEc;
+ }
+
+ return NULL;
+}
+
+/**
+ Execute Pch Reset from the host controller.
+
+ @param[in] This Pointer to the PCH_RESET_PROTOCOL instance.
+ @param[in] ResetType UEFI defined reset type.
+ @param[in] DataSize The size of ResetData in bytes.
+ @param[in] ResetData Optional element used to introduce a platform specific reset.
+ The exact type of the reset is defined by the EFI_GUID that follows
+ the Null-terminated Unicode string.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER If ResetType is invalid.
+**/
+EFI_STATUS
+EFIAPI
+Reset (
+ IN PCH_RESET_PROTOCOL *This,
+ IN EFI_RESET_TYPE ResetType,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ )
+{
+ PCH_RESET_INSTANCE *PchResetInstance;
+ EFI_STATUS Status;
+ PCH_RESET_TYPE PchResetType;
+
+ PchResetInstance = PCH_RESET_INSTANCE_FROM_THIS (This);
+ PchResetType = (PCH_RESET_TYPE)ResetType;
+
+ Status = PchReset (PchResetInstance, PchResetType);
+
+ return Status;
+}
+
+/**
+ Calling this function causes a system-wide reset. This sets
+ all circuitry within the system to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ System reset should not return, if it returns, it means the system does
+ not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ )
+{
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetCold);
+}
+
+/**
+ Calling this function causes a system-wide initialization. The processors
+ are set to their initial state, and pending cycles are not corrupted.
+
+ System reset should not return, if it returns, it means the system does
+ not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ )
+{
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetWarm);
+}
+
+/**
+ Calling this function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ System shutdown should not return, if it returns, it means the system does
+ not support shut down reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ )
+{
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetShutdown);
+}
+
+/**
+ Calling this function causes the system to enter a power state for platform specific.
+
+ @param[in] ResetStatus The status code for the reset.
+ @param[in] DataSize The size of ResetData in bytes.
+ @param[in] ResetData Optional element used to introduce a platform specific reset.
+ The exact type of the reset is defined by the EFI_GUID that follows
+ the Null-terminated Unicode string.
+
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
+ )
+{
+ EFI_GUID *GuidPtr;
+
+ if (ResetData == NULL) {
+ if (!EfiAtRuntime ()) {
+ DEBUG ((DEBUG_ERROR, "[DxeRuntimeResetSystemLib] ResetData is not available.\n"));
+ }
+ return;
+ }
+ GuidPtr = (EFI_GUID *) ((UINT8 *) ResetData + DataSize - sizeof (EFI_GUID));
+ if (CompareGuid (GuidPtr, &gPchPowerCycleResetGuid)) {
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) PowerCycleReset);
+ } else if (CompareGuid (GuidPtr, &gPchGlobalResetGuid)) {
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) GlobalReset);
+ } else if (CompareGuid (GuidPtr, &gPchGlobalResetWithEcGuid)) {
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) GlobalResetWithEc);
+ } else {
+ return;
+ }
+}
+
+/**
+ Calling this function causes the system to enter a power state for capsule update.
+
+ Reset update should not return, if it returns, it means the system does
+ not support capsule update.
+
+**/
+VOID
+EFIAPI
+EnterS3WithImmediateWake (
+ VOID
+ )
+{
+ PchReset (mPchResetInstance, (PCH_RESET_TYPE) EfiResetWarm);
+}
+
+/**
+ <b>PchReset Runtime DXE Driver Entry Point</b>\n
+ - <b>Introduction</b>\n
+ The PchReset Runtime DXE driver provide a standard way for other modules to
+ use the PCH Reset Interface in DXE/SMM/Runtime environments. It has no longer
+ hooked ResetSystem() function of the runtime service table.
+
+ - @pre
+ - If there is any driver which needs to run the callback function right before
+ issuing the reset, PCH Reset Callback Protocol will need to be installed
+ before PCH Reset Runtime DXE driver. If PchReset Runtime DXE driver is run
+ before Status Code Runtime Protocol is installed and there is the need
+ to use Status code in the driver, it will be necessary to add EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID
+ to the dependency file.
+ - @link _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL @endlink
+
+ - @result
+ The Reset driver produces @link _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL @endlink
+
+ @param[in] ImageHandle Image handle of the loaded driver
+ @param[in] SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the timer service
+**/
+EFI_STATUS
+EFIAPI
+InstallPchReset (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT64 BaseAddress;
+ UINT64 Length;
+ UINT32 PwrmBaseAddress;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemorySpaceDescriptor;
+ UINT64 Attributes;
+ EFI_EVENT AddressChangeEvent;
+ EFI_PEI_HOB_POINTERS HobPtr;
+ PCH_POLICY_HOB *PchPolicyHob;
+
+ DEBUG ((DEBUG_INFO, "InstallPchReset() Start\n"));
+
+ //
+ // Set PMC PCI address space to RUNTIME MEMORY.
+ //
+ BaseAddress = MmPciBase(
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_PMC,
+ PCI_FUNCTION_NUMBER_PCH_PMC
+ );
+ Length = 0x1000; // 4KB
+
+ Status = gDS->GetMemorySpaceDescriptor (BaseAddress, &MemorySpaceDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ Attributes = MemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME;
+
+ Status = gDS->SetMemorySpaceAttributes (
+ BaseAddress,
+ Length,
+ Attributes
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Set PWRM MMIO address space to RUNTIME MEMORY.
+ //
+ PchPwrmBaseGet (&PwrmBaseAddress);
+ Length = 0x10000; // 64KB
+
+ Status = gDS->GetMemorySpaceDescriptor (PwrmBaseAddress, &MemorySpaceDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ Attributes = MemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME;
+
+ Status = gDS->SetMemorySpaceAttributes (
+ PwrmBaseAddress,
+ Length,
+ Attributes
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// Allocate Runtime memory for the PchReset protocol instance.
+ ///
+ mPchResetInstance = AllocateRuntimeZeroPool (sizeof (PCH_RESET_INSTANCE));
+ if (mPchResetInstance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = PchResetConstructor (mPchResetInstance);
+
+ ///
+ /// Create Address Change event
+ ///
+ ///
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ PchResetVirtualAddressChangeEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &AddressChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ HobPtr.Guid = GetFirstGuidHob (&gPchPolicyHobGuid);
+ if (HobPtr.Guid != NULL) {
+ PchPolicyHob = GET_GUID_HOB_DATA (HobPtr.Guid);
+ mCapsuleResetType = PchPolicyHob->PmConfig.CapsuleResetType;
+ }
+ ///
+ /// The Lib Deconstruct will automatically be called when entrypoint return error.
+ ///
+ DEBUG ((DEBUG_INFO, "InstallPchReset() End\n"));
+
+ return Status;
+}
+
+/**
+ If need be, do any special reset required for capsules. For this
+ implementation where we're called from the ResetSystem() api,
+ just set our capsule variable and return to let the caller
+ do a soft reset.
+**/
+VOID
+CapsuleS3Reset (
+ VOID
+ )
+{
+ UINT32 Data32;
+ UINT32 Eflags;
+ UINT16 ABase;
+
+ DEBUG ((DEBUG_INFO, "Capsule Present: Will be issuing S3 reset.\n"));
+
+ ///
+ /// Wake up system 2 seconds after putting system into S3 to complete the reset operation.
+ ///
+ SetSystemWakeupAlarm (2);
+ ///
+ /// Process capsules across a system reset.
+ ///
+ ABase = mPchResetInstance->PchAcpiBase;
+ ASSERT (ABase != 0);
+
+ Data32 = IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT));
+
+ Data32 = (UINT32) ((Data32 & ~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S3);
+
+ Eflags = (UINT32) AsmReadEflags ();
+
+ if ((Eflags & 0x200)) {
+ DisableInterrupts ();
+ }
+
+ AsmWbinvd ();
+ AsmWriteCr0 (AsmReadCr0 () | 0x060000000);
+
+ IoWrite32 (
+ (UINTN) (ABase + R_PCH_ACPI_PM1_CNT),
+ (UINT32) Data32
+ );
+
+ Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;
+
+ IoWrite32 (
+ (UINTN) (ABase + R_PCH_ACPI_PM1_CNT),
+ (UINT32) Data32
+ );
+
+ if ((Eflags & 0x200)) {
+ EnableInterrupts ();
+ }
+ ///
+ /// Should not return
+ ///
+ CpuDeadLoop ();
+}
+
+/**
+ Execute call back function for Pch Reset.
+
+ @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset.
+
+ @retval EFI_SUCCESS The callback function has been done successfully
+ @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of
+ callback protocol is installed.
+ @retval Others Do not do any reset from PCH
+**/
+EFI_STATUS
+EFIAPI
+PchResetCallback (
+ IN PCH_RESET_TYPE PchResetType
+ )
+{
+ EFI_STATUS Status;
+ UINTN NumHandles;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ PCH_RESET_CALLBACK_PROTOCOL *PchResetCallback;
+ UINTN Size;
+ UINTN CapsuleDataPtr;
+
+ if (EfiAtRuntime () == FALSE) {
+ DEBUG((DEBUG_ERROR, "Not in Runtime"));
+ ///
+ /// Retrieve all instances of Pch Reset Callback protocol
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gPchResetCallbackProtocolGuid,
+ NULL,
+ &NumHandles,
+ &HandleBuffer
+ );
+
+ if (EFI_ERROR (Status)) {
+ ///
+ /// Those drivers that need to install Pch Reset Callback protocol have the responsibility
+ /// to make sure themselves execute before Pch Reset Runtime driver.
+ ///
+ if (Status == EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_ERROR | DEBUG_INFO, "Or, none of Pch Reset callback protocol is installed.\n"));
+ }
+
+ return Status;
+ }
+
+ for (Index = 0; Index < NumHandles; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gPchResetCallbackProtocolGuid,
+ (VOID **) &PchResetCallback
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!EFI_ERROR (Status)) {
+ DEBUG((EFI_D_ERROR, "Calling PchResetCallback %d\n", Index));
+ PchResetCallback->ResetCallback (PchResetType);
+ } else {
+ DEBUG ((DEBUG_ERROR | DEBUG_INFO, "Failed to locate Pch Reset Callback protocol.\n"));
+ return Status;
+ }
+ }
+ }
+ DEBUG((EFI_D_ERROR, "PchResetCallback After Runtime Check\n"));
+ if(PchResetType == WarmReset) {
+ ///
+ /// Check if there are pending capsules to process
+ ///
+ DEBUG((EFI_D_ERROR, "PchResetCallback Warmreset\n"));
+ Size = sizeof (CapsuleDataPtr);
+ Status = EfiGetVariable (
+ EFI_CAPSULE_VARIABLE_NAME,
+ &gEfiCapsuleVendorGuid,
+ NULL,
+ &Size,
+ (VOID *) &CapsuleDataPtr
+ );
+ if (Status == EFI_SUCCESS) {
+ if (mCapsuleResetType == CAPSULE_RESET_S3) { //default value S3 resume
+ CapsuleS3Reset ();
+ }
+ AsmWbinvd ();
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Fixup internal data pointers so that the services can be called in virtual mode.
+
+ @param[in] Event The event registered.
+ @param[in] Context Event context. Not used in this event handler.
+
+**/
+VOID
+EFIAPI
+PchResetVirtualAddressChangeEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mPchResetInstance->PchPmcBase));
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mPchResetInstance->PchPwrmBase));
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mPchResetInstance));
+}
diff --git a/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/PchReset.h b/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/PchReset.h new file mode 100644 index 0000000000..bfcd15888c --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/DxeRuntimeResetSystemLib/PchReset.h @@ -0,0 +1,111 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_RESET_H
+#define _PCH_RESET_H
+
+#include <Library/IoLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Guid/EventGroup.h>
+#include <Library/MmPciBaseLib.h>
+#include <Protocol/PchReset.h>
+#include <PchAccess.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <IncludePrivate/Library/PchResetCommonLib.h>
+#include <IncludePrivate/PchPolicyHob.h>
+#include <Library/HobLib.h>
+
+#define EFI_INTERNAL_POINTER 0x04
+
+#define PCH_RESET_INSTANCE_FROM_THIS(a) \
+ CR ( \
+ a, \
+ PCH_RESET_INSTANCE, \
+ PchResetInterface.PchResetProtocol, \
+ PCH_RESET_SIGNATURE \
+ )
+
+#define CAPSULE_RESET_S3 0
+#define CAPSULE_RESET_WARM 1
+
+/**
+ <b>PchReset Runtime DXE Driver Entry Point</b>\n
+ - <b>Introduction</b>\n
+ The PchReset Runtime DXE driver provide a standard way for other modules to
+ use the PCH Reset Interface in DXE/SMM/Runtime environments. It has no longer
+ hooked ResetSystem() function of the runtime service table.
+
+ - @pre
+ - If there is any driver which needs to run the callback function right before
+ issuing the reset, PCH Reset Callback Protocol will need to be installed
+ before PCH Reset Runtime DXE driver. If PchReset Runtime DXE driver is run
+ before Status Code Runtime Protocol is installed and there is the need
+ to use Status code in the driver, it will be necessary to add EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID
+ to the dependency file.
+ - @link _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL @endlink
+
+ - @result
+ The Reset driver produces @link _PCH_RESET_PROTOCOL PCH_RESET_PROTOCOL @endlink
+
+ @param[in] ImageHandle Image handle of the loaded driver
+ @param[in] SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the timer service
+**/
+EFI_STATUS
+EFIAPI
+InstallPchReset (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+/**
+ Execute call back function for Pch Reset.
+
+ @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset.
+
+ @retval EFI_SUCCESS The callback function has been done successfully
+ @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protocol. Or, none of
+ callback protocol is installed.
+ @retval Others Do not do any reset from PCH
+**/
+EFI_STATUS
+EFIAPI
+PchResetCallback (
+ IN PCH_RESET_TYPE PchResetType
+ );
+
+/**
+ Fixup internal data pointers so that the services can be called in virtual mode.
+
+ @param[in] Event The event registered.
+ @param[in] Context Event context. Not used in this event handler.
+
+**/
+VOID
+EFIAPI
+PchResetVirtualAddressChangeEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ );
+#endif
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioInit.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioInit.c new file mode 100644 index 0000000000..422ecfcee1 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioInit.c @@ -0,0 +1,409 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "GpioLibrary.h" + + +/** + This procedure will handle requirement on SATA DEVSLPx pins. + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO PadMode value + @param[in out] Dw0Reg Value for PADCFG_DW0 register + @param[in out] Dw0RegMask Mask of bits which will change in PADCFG_DWO register + + @retval None + +**/ +static +VOID +GpioHandleSataDevSlpPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadMode, + IN OUT UINT32 *Dw0Reg, + IN OUT UINT32 *Dw0RegMask + ) +{ + // + // For SATA DEVSLPx pins if used in native 1 mode then ensure that PadRstCfg + // is set to "00" - Powergood + // + if (GpioIsPadASataDevSlpPin (GpioPad, PadMode)) { + // + // Set PadRstCfg to Powergood + // + *Dw0RegMask |= B_PCH_GPIO_RST_CONF; + *Dw0Reg |= ((GpioResetPwrGood >> 1) << N_PCH_GPIO_RST_CONF); + } +} + +/** + This SKL PCH specific procedure will initialize multiple SKL PCH GPIO pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +static +EFI_STATUS +GpioConfigureSklPch ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + UINT32 Index; + UINT32 Dw0Reg; + UINT32 Dw0RegMask; + UINT32 Dw1Reg; + UINT32 Dw1RegMask; + UINT32 PadCfgReg; + UINT32 HostSoftOwnReg[V_PCH_GPIO_GROUP_MAX]; + UINT32 HostSoftOwnRegMask[V_PCH_GPIO_GROUP_MAX]; + UINT32 GpiGpeEnReg[V_PCH_GPIO_GROUP_MAX]; + UINT32 GpiGpeEnRegMask[V_PCH_GPIO_GROUP_MAX]; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + GPIO_PAD_OWN PadOwnVal; + GPIO_INIT_CONFIG *GpioData; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries (); + PadOwnVal = GpioPadOwnHost; + + ZeroMem (HostSoftOwnReg, sizeof (HostSoftOwnReg)); + ZeroMem (HostSoftOwnRegMask, sizeof (HostSoftOwnRegMask)); + ZeroMem (GpiGpeEnReg, sizeof (GpiGpeEnReg)); + ZeroMem (GpiGpeEnRegMask, sizeof (GpiGpeEnRegMask)); + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupOffset = GpioGetLowestGroup (); + NumberOfGroups = GpioGetNumberOfGroups (); + + for (Index = 0; Index < NumberOfItems; Index ++) { + + Dw0RegMask = 0; + Dw0Reg = 0; + Dw1RegMask = 0; + Dw1Reg = 0; + + GpioData = &GpioInitTableAddress[Index]; + + Group = GpioGetGroupFromGpioPad (GpioData->GpioPad); + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad); + + if (GroupIndex >= V_PCH_GPIO_GROUP_MAX) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Invalid Group Index (GroupIndex=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + continue; + } + +DEBUG_CODE_BEGIN(); + if (!(((PchSeries == PchH) && (GPIO_GET_CHIPSET_ID(GpioData->GpioPad) == GPIO_SKL_H_CHIPSET_ID)) || + ((PchSeries == PchLp) && (GPIO_GET_CHIPSET_ID(GpioData->GpioPad) == GPIO_SKL_LP_CHIPSET_ID)))) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >= NumberOfGroups + GpioGroupOffset)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){ + return EFI_INVALID_PARAMETER; + } + + if (GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + continue; + } + + if (DebugCodeEnabled ()) { + + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // + GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal); + + if (PadOwnVal != GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n")); + DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n")); + continue; + } + + } + + // + // Configure Reset Type (PadRstCfg) + // + Dw0RegMask |= ((((GpioData->GpioConfig.PowerConfig & GPIO_CONF_RESET_MASK) >> GPIO_CONF_RESET_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RST_CONF); + Dw0Reg |= (((GpioData->GpioConfig.PowerConfig & GPIO_CONF_RESET_MASK) >> (GPIO_CONF_RESET_BIT_POS + 1)) << N_PCH_GPIO_RST_CONF); + + // + // Configure how interrupt is triggered (RxEvCfg) + // + Dw0RegMask |= ((((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> GPIO_CONF_INT_TRIG_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_LVL_EDG); + Dw0Reg |= (((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> (GPIO_CONF_INT_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG); + + + // + // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + Dw0RegMask |= ((((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> GPIO_CONF_INT_ROUTE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE)); + Dw0Reg |= (((GpioData->GpioConfig.InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> (GPIO_CONF_INT_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE); + + // + // Configure GPIO direction (GPIORxDis and GPIOTxDis) + // + Dw0RegMask |= ((((GpioData->GpioConfig.Direction & GPIO_CONF_DIR_MASK) >> GPIO_CONF_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RXDIS | B_PCH_GPIO_TXDIS)); + Dw0Reg |= (((GpioData->GpioConfig.Direction & GPIO_CONF_DIR_MASK) >> (GPIO_CONF_DIR_BIT_POS + 1)) << N_PCH_GPIO_TXDIS); + + // + // Configure GPIO input inversion (RXINV) + // + Dw0RegMask |= ((((GpioData->GpioConfig.Direction & GPIO_CONF_INV_MASK) >> GPIO_CONF_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RXINV); + Dw0Reg |= (((GpioData->GpioConfig.Direction & GPIO_CONF_INV_MASK) >> (GPIO_CONF_INV_BIT_POS + 1)) << N_PCH_GPIO_RXINV); + + // + // Configure GPIO output state (GPIOTxState) + // + Dw0RegMask |= ((((GpioData->GpioConfig.OutputState & GPIO_CONF_OUTPUT_MASK) >> GPIO_CONF_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TX_STATE); + Dw0Reg |= (((GpioData->GpioConfig.OutputState & GPIO_CONF_OUTPUT_MASK) >> (GPIO_CONF_OUTPUT_BIT_POS + 1)) << N_PCH_GPIO_TX_STATE); + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + Dw0RegMask |= ((((GpioData->GpioConfig.OtherSettings & GPIO_CONF_RXRAW_MASK) >> GPIO_CONF_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_RAW1); + Dw0Reg |= (((GpioData->GpioConfig.OtherSettings & GPIO_CONF_RXRAW_MASK) >> (GPIO_CONF_RXRAW_BIT_POS + 1)) << N_PCH_GPIO_RX_RAW1); + + // + // Configure GPIO Pad Mode (PMode) + // + if (((GpioData->GpioPad == GPIO_SKL_H_GPP_B2) || + (GpioData->GpioPad == GPIO_SKL_H_GPD7) || + (GpioData->GpioPad == GPIO_SKL_H_GPD9)) && + (GpioData->GpioConfig.PadMode != GpioPadModeGpio)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group/Index: %d/%d, Pad: %d cannot be set as NATIVE. Force it to GPIO mode!\n", Group, GroupIndex, PadNumber)); + Dw0RegMask |= B_PCH_GPIO_PAD_MODE; + Dw0Reg |= ((GpioPadModeGpio >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + } else { + Dw0RegMask |= ((((GpioData->GpioConfig.PadMode & GPIO_CONF_PAD_MODE_MASK) >> GPIO_CONF_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PAD_MODE); + Dw0Reg |= (((GpioData->GpioConfig.PadMode & GPIO_CONF_PAD_MODE_MASK) >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + } + + // + // Configure GPIO termination (Term) + // + Dw1RegMask |= ((((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_TERM_MASK) >> GPIO_CONF_TERM_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TERM); + Dw1Reg |= (((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_TERM_MASK) >> (GPIO_CONF_TERM_BIT_POS + 1)) << N_PCH_GPIO_TERM); + + // + // Configure GPIO pad tolerance (padtol) + // + Dw1RegMask |= ((((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> GPIO_CONF_PADTOL_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PADTOL); + Dw1Reg |= (((GpioData->GpioConfig.ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> (GPIO_CONF_PADTOL_BIT_POS + 1)) << N_PCH_GPIO_PADTOL); + + // + // Check for additional requirements on setting PADCFG register + // + GpioHandleSataDevSlpPad (GpioData->GpioPad, GpioData->GpioConfig.PadMode, &Dw0Reg, &Dw0RegMask); + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + // + // Write PADCFG DW0 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg), + ~(UINT32)Dw0RegMask, + (UINT32)Dw0Reg + ); + + // + // Write PADCFG DW1 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4), + ~(UINT32)Dw1RegMask, + (UINT32)Dw1Reg + ); + // + // Update value to be programmed in HOSTSW_OWN register + // + HostSoftOwnRegMask[GroupIndex] |= (GpioData->GpioConfig.HostSoftPadOwn & 0x1) << PadNumber; + HostSoftOwnReg[GroupIndex] |= (GpioData->GpioConfig.HostSoftPadOwn >> 0x1) << PadNumber; + + // + // Update value to be programmed in GPI_GPE_EN register + // + GpiGpeEnRegMask[GroupIndex] |= (GpioData->GpioConfig.InterruptConfig & 0x1) << PadNumber; + GpiGpeEnReg[GroupIndex] |= ((GpioData->GpioConfig.InterruptConfig & GpioIntSci) >> 3) << PadNumber; + } + + for (Index = 0; Index < NumberOfGroups; Index++) { + // + // Write HOSTSW_OWN registers + // + if (GpioGroupInfo[Index].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[Index].Community, GpioGroupInfo[Index].HostOwnOffset), + ~(UINT32)HostSoftOwnRegMask[Index], + (UINT32)HostSoftOwnReg[Index] + ); + } + + // + // Write GPI_GPE_EN registers + // + if (GpioGroupInfo[Index].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[Index].Community, GpioGroupInfo[Index].GpiGpeEnOffset), + ~(UINT32)GpiGpeEnRegMask[Index], + (UINT32)GpiGpeEnReg[Index] + ); + } + } + + return EFI_SUCCESS; +} + +/** + This procedure will clear all status bits of any GPIO interrupts. + + @param[in] none + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +static +EFI_STATUS +GpioClearAllGpioInterrupts ( + VOID + ) +{ + GPIO_GROUP Group; + GPIO_GROUP_INFO *GpioGroupInfo; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + UINT32 GroupIndex; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupLowest = GpioGetLowestGroup (); + GpioGroupHighest = GpioGetHighestGroup (); + + for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) { + GroupIndex = GpioGetGroupIndexFromGroup (Group); + // + // Check if group has GPI IS register + // + if (GpioGroupInfo[Group].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) { + // + // Clear all GPI_IS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiIsOffset), + (UINT32)0xFFFFFFFF + ); + } + + // + // Check if group has GPI_GPE_STS register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) { + // + // Clear all GPI_GPE_STS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeStsOffset), + (UINT32)0xFFFFFFFF + ); + } + + // + // Check if group has SMI_STS register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) { + // + // Clear all SMI_STS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiStsOffset), + (UINT32)0xFFFFFFFF + ); + } + + // + // Check if group has NMI_STS register + // + if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) { + // + // Clear all NMI_STS Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].NmiStsOffset), + (UINT32)0xFFFFFFFF + ); + } + + } + return EFI_SUCCESS; +} + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values. + Separate fields could be set to hardware default if it does not matter, except + GpioPad and PadMode. + Some GpioPads are configured and switched to native mode by RC, those include: + SerialIo pins, ISH pins, ClkReq Pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + EFI_STATUS Status; + Status = GpioConfigureSklPch (NumberOfItems, GpioInitTableAddress); + GpioClearAllGpioInterrupts (); + return Status; +} diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioLib.c new file mode 100644 index 0000000000..0b82c2b8df --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioLib.c @@ -0,0 +1,2744 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "GpioLibrary.h" +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiMultiPhase.h> +#include <Library/HobLib.h> + +// +// Possible registers to be accessed using GpioReadWriteReg() function +// +typedef enum { + GpioHostOwnershipRegister = 0, + GpioGpeEnableRegister, + GpioSmiEnableRegister, + GpioNmiEnableRegister, + GpioPadConfigLockRegister, + GpioPadLockOutputRegister +} GPIO_REG; + +/** + This procedure will write or read GPIO Pad Configuration register + + @param[in] GpioPad GPIO pad + @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1 + @param[in] Mask Mask + @param[in] Write Perform read(0) or write(1) + @param[in,out] ReadWriteValue Read/Write data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number + @retval EFI_UNSUPPORTED Host cannot access this pad +**/ +static +EFI_STATUS +GpioReadWritePadCfgReg ( + IN GPIO_PAD GpioPad, + IN UINT8 DwReg, + IN UINT32 Mask, + IN BOOLEAN Write, + IN OUT UINT32 *ReadWriteVal + ) +{ + UINT32 PadCfgReg; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 GroupIndex; + UINT32 PadNumber; + + + GPIO_PAD_OWN PadOwnVal; + + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + if (Write && (DwReg == 1 || (Mask & ~B_PCH_GPIO_TX_STATE) != 0) && GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_WRITE_PROTECTED; + } + +DEBUG_CODE_BEGIN(); + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // If GPIO is not owned by Host all access to PadCfg will be dropped + // + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal != GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } + + // +DEBUG_CODE_END(); + + // + // Create Pad Configuration register offset + // + PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + if(DwReg == 1) { + PadCfgReg += 0x4; + } + + if (Write) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg), + (UINT32)(~Mask), + (UINT32)(*ReadWriteVal & Mask) + ); + } else { + *ReadWriteVal = MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg)); + *ReadWriteVal &= Mask; + } + + return EFI_SUCCESS; +} + +/** + This procedure will write or read GPIO register + + @param[in] RegType GPIO register type + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (parameter applicable in accessing whole register). + For group which has less then 32 pads per group DwNum must be 0. + @param[in] GpioPad GPIO pad + @param[in] Write Perform read(0) or write(1) + @param[in] OnePad Access whole register(0) or one pad(1) + @param[in,out] ReadWriteValue Read/Write data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group, pad or DwNum parameter number +**/ +static +EFI_STATUS +GpioReadWriteReg ( + IN GPIO_REG RegType, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN GPIO_PAD GpioPad, + IN BOOLEAN Write, + IN BOOLEAN OnePad, + IN OUT UINT32 *ReadWriteVal + ) +{ + UINT32 Mask; + UINT32 RegOffset; + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + RegOffset = 0; + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + if (OnePad) { + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + } else { + GroupIndex = GpioGetGroupIndexFromGroup (Group); + PadNumber = 0; + } + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + switch (RegType) { + case GpioHostOwnershipRegister: + RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset; + break; + case GpioGpeEnableRegister: + RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset; + break; + case GpioSmiEnableRegister: + RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset; + break; + case GpioNmiEnableRegister: + RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset; + break; + case GpioPadConfigLockRegister: + RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset; + break; + case GpioPadLockOutputRegister: + RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset; + break; + default: + ASSERT (FALSE); + break; + } + + // + // Check if selected register exists + // + if (RegOffset == NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + + // + // Access one GPIO Pad + // + if (OnePad) { + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + // + // For future use. If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // + RegOffset += (PadNumber >> 5) * 0x4; + // + // Calculate pad bit position within DWord register + // + PadNumber %= 32; + Mask = BIT0 << PadNumber; + + if (Write) { + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOffset), + (UINT32)(~Mask), + (UINT32)((*ReadWriteVal << PadNumber) & Mask) + ); + } else { + *ReadWriteVal = MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOffset)); + *ReadWriteVal = (*ReadWriteVal & Mask) >> PadNumber; + } + // + // Access whole register + // + } else { + // + // Check if DwNum argument does not exceed number of DWord registers + // resulting from available pads for certain group + // + if (DwNum > ((GpioGroupInfo[GroupIndex].PadPerGroup - 1) >> 5)){ + return EFI_INVALID_PARAMETER; + } + // + // For future use. If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // For SKL PCH DwNum must be 0. + // + RegOffset += DwNum *0x4; + + if (Write) { + MmioWrite32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOffset), + (UINT32)(*ReadWriteVal) + ); + } else { + *ReadWriteVal = MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOffset)); + } + } + + return EFI_SUCCESS; +} + +/** + This procedure will write GPIO Lock/LockTx register using SBI. + + @param[in] RegType GPIO register (Lock or LockTx) + @param[in] Unlock Lock pads(0) or unlock(1) + @param[in] Group GPIO group number + @param[in] DwNum Register number for current group (parameter applicable in accessing whole register). + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToModify Bit mask for pads that are going to be modified + @param[in] GpioPad GPIO pad + @param[in] OnePad Access whole register(0) or one pad(1) + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group, pad or DwNum parameter number +**/ +static +EFI_STATUS +GpioLockPadsUsingSbi ( + IN GPIO_REG RegType, + IN BOOLEAN Unlock, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToModify, + IN GPIO_PAD GpioPad, + IN BOOLEAN OnePad + ) +{ + UINT8 Response; + EFI_STATUS Status; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 RegOffset; + UINT32 OldPadCfgLockRegVal; + UINT32 NewPadCfgLockRegVal; + UINT32 GroupIndex; + UINT32 PadNumber; + + RegOffset = 0; + OldPadCfgLockRegVal = 0; + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + if (OnePad) { + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + Group = GpioGetGroupFromGpioPad (GpioPad); +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + } else { + GroupIndex = GpioGetGroupIndexFromGroup (Group); + PadNumber = 0; + } + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + switch (RegType) { + case GpioPadConfigLockRegister: + RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset; + break; + case GpioPadLockOutputRegister: + RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset; + break; + default: + ASSERT (FALSE); + break; + } + + // + // Check if selected register exists + // + if (RegOffset == NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + + // + // Access one GPIO Pad + // + if (OnePad) { + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + // + // For future use. If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // + DwNum = (PadNumber >> 5); + RegOffset += DwNum * 0x4; + // + // Calculate pad bit position within DWord register + // + PadNumber %= 32; + + switch (RegType) { + case GpioPadConfigLockRegister: + GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + case GpioPadLockOutputRegister: + GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + } + if (Unlock) { + NewPadCfgLockRegVal = OldPadCfgLockRegVal & (~(0x1 << PadNumber)); + } else { + NewPadCfgLockRegVal = OldPadCfgLockRegVal | (0x1 << PadNumber); + } + + } else { + // + // Access whole register + // + + // + // Check if DwNum argument does not exceed number of DWord registers + // resulting from available pads for certain group + // + if (DwNum > ((GpioGroupInfo[GroupIndex].PadPerGroup - 1) >> 5)){ + return EFI_INVALID_PARAMETER; + } + // + // For future use. If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // For SKL PCH DwNum must be 0. + // + RegOffset += DwNum *0x4; + + switch (RegType) { + case GpioPadConfigLockRegister: + GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + case GpioPadLockOutputRegister: + GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldPadCfgLockRegVal); + break; + } + if (Unlock) { + NewPadCfgLockRegVal = OldPadCfgLockRegVal & (~PadsToModify); + } else { + NewPadCfgLockRegVal = OldPadCfgLockRegVal | PadsToModify; + } + } + + Status = PchSbiExecution ( + GpioGroupInfo[GroupIndex].Community, + RegOffset, + GpioLockUnlock, + FALSE, + &NewPadCfgLockRegVal, + &Response + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ) +{ + UINT32 Dw0Reg; + UINT32 Dw1Reg; + UINT32 PadCfgReg; + UINT32 RegVal; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + + GPIO_PAD_OWN PadOwnVal; + + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Group = GpioGetGroupFromGpioPad (GpioPad); + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal != GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ())) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + // + // Read PADCFG DW0 register + // + Dw0Reg = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg)); + + // + // Read PADCFG DW1 register + // + Dw1Reg = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4)); + + + // + // Get Reset Type (PadRstCfg) + // + GpioData->PowerConfig = ((Dw0Reg & B_PCH_GPIO_RST_CONF) >> (N_PCH_GPIO_RST_CONF - (GPIO_CONF_RESET_BIT_POS + 1))) | (0x1 << GPIO_CONF_RESET_BIT_POS); + + // + // Get how interrupt is triggered (RxEvCfg) + // + GpioData->InterruptConfig = ((Dw0Reg & B_PCH_GPIO_RX_LVL_EDG) >> (N_PCH_GPIO_RX_LVL_EDG - (GPIO_CONF_INT_TRIG_BIT_POS + 1))) | (0x1 << GPIO_CONF_INT_TRIG_BIT_POS); + + // + // Get interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + GpioData->InterruptConfig |= ((Dw0Reg & (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE)) >> (N_PCH_GPIO_RX_NMI_ROUTE - (GPIO_CONF_INT_ROUTE_BIT_POS + 1))) | (0x1 << GPIO_CONF_INT_ROUTE_BIT_POS); + + // + // Get GPIO direction (GPIORxDis and GPIOTxDis) + // + GpioData->Direction = ((Dw0Reg & (B_PCH_GPIO_RXDIS | B_PCH_GPIO_TXDIS)) >> (N_PCH_GPIO_TXDIS - (GPIO_CONF_DIR_BIT_POS + 1))) | (0x1 << GPIO_CONF_DIR_BIT_POS); + + // + // Get GPIO input inversion (RXINV) + // + GpioData->Direction |= ((Dw0Reg & B_PCH_GPIO_RXINV) >> (N_PCH_GPIO_RXINV - (GPIO_CONF_INV_BIT_POS + 1))) | (0x1 << GPIO_CONF_INV_BIT_POS); + + // + // Get GPIO output state (GPIOTxState) + // + GpioData->OutputState = ((Dw0Reg & B_PCH_GPIO_TX_STATE) << (N_PCH_GPIO_TX_STATE + (GPIO_CONF_OUTPUT_BIT_POS + 1))) | (0x1 << GPIO_CONF_OUTPUT_BIT_POS) ; + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + GpioData->OtherSettings = ((Dw0Reg & B_PCH_GPIO_RX_RAW1) >> (N_PCH_GPIO_RX_RAW1 - (GPIO_CONF_RXRAW_BIT_POS + 1))) | (0x1 << GPIO_CONF_RXRAW_BIT_POS) ; + + // + // Get GPIO Pad Mode (PMode) + // + GpioData->PadMode = ((Dw0Reg & B_PCH_GPIO_PAD_MODE) >> (N_PCH_GPIO_PAD_MODE - (GPIO_CONF_PAD_MODE_BIT_POS + 1))) | (0x1 << GPIO_CONF_PAD_MODE_BIT_POS); + + // + // Get GPIO termination (Term) + // + GpioData->ElectricalConfig = ((Dw1Reg & B_PCH_GPIO_TERM) >> (N_PCH_GPIO_TERM - (GPIO_CONF_TERM_BIT_POS + 1))) | (0x1 << GPIO_CONF_TERM_BIT_POS) ; + + // + // Get GPIO pad tolerance (padtol) + // + GpioData->ElectricalConfig |= ((Dw1Reg & B_PCH_GPIO_PADTOL) >> (N_PCH_GPIO_PADTOL - (GPIO_CONF_PADTOL_BIT_POS + 1))) | (0x1 << GPIO_CONF_PADTOL_BIT_POS) ; + + // + // Read HOSTSW_OWN registers + // + RegVal = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].HostOwnOffset)); + + // + // Get Host Software Ownership + // + GpioData->HostSoftPadOwn = (((RegVal >> PadNumber) & 0x1) << (GPIO_CONF_HOST_OWN_BIT_POS + 1)) | (0x1 << GPIO_CONF_HOST_OWN_BIT_POS); + + // + // Read PADCFGLOCK register + // + RegVal = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].PadCfgLockOffset)); + + // + // Get Pad Configuration Lock state + // + GpioData->LockConfig = (((RegVal >> PadNumber) & 0x1) << 1) | 0x1; + + // + // Read PADCFGLOCKTX register + // + RegVal = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].PadCfgLockTxOffset)); + + // + // Get Pad Configuration Lock Tx state + // + GpioData->LockConfig |= (((RegVal >> PadNumber) & 0x1) << 2) | 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ) +{ + UINT32 Dw0Reg; + UINT32 Dw0RegMask; + UINT32 Dw1Reg; + UINT32 Dw1RegMask; + UINT32 PadCfgReg; + UINT32 HostSoftOwnReg; + UINT32 HostSoftOwnRegMask; + UINT32 GpiGpeEnReg; + UINT32 GpiGpeEnRegMask; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + + GPIO_PAD_OWN PadOwnVal; + + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Dw0RegMask = 0; + Dw0Reg = 0; + Dw1RegMask = 0; + Dw1Reg = 0; + + Group = GpioGetGroupFromGpioPad (GpioPad); + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal != GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ())) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + if (GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_WRITE_PROTECTED; + } + + // + // Configure Reset Type (PadRstCfg) + // + Dw0RegMask |= ((((GpioData->PowerConfig & GPIO_CONF_RESET_MASK) >> GPIO_CONF_RESET_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RST_CONF); + Dw0Reg |= (((GpioData->PowerConfig & GPIO_CONF_RESET_MASK) >> (GPIO_CONF_RESET_BIT_POS + 1)) << N_PCH_GPIO_RST_CONF); + + // + // Configure how interrupt is triggered (RxEvCfg) + // + Dw0RegMask |= ((((GpioData->InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> GPIO_CONF_INT_TRIG_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_LVL_EDG); + Dw0Reg |= (((GpioData->InterruptConfig & GPIO_CONF_INT_TRIG_MASK) >> (GPIO_CONF_INT_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG); + + // + // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + Dw0RegMask |= ((((GpioData->InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> GPIO_CONF_INT_ROUTE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE)); + Dw0Reg |= (((GpioData->InterruptConfig & GPIO_CONF_INT_ROUTE_MASK) >> (GPIO_CONF_INT_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE); + + // + // Configure GPIO direction (GPIORxDis and GPIOTxDis) + // + Dw0RegMask |= ((((GpioData->Direction & GPIO_CONF_DIR_MASK) >> GPIO_CONF_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_PCH_GPIO_RXDIS | B_PCH_GPIO_TXDIS)); + Dw0Reg |= (((GpioData->Direction & GPIO_CONF_DIR_MASK) >> (GPIO_CONF_DIR_BIT_POS + 1)) << N_PCH_GPIO_TXDIS); + + // + // Configure GPIO input inversion (RXINV) + // + Dw0RegMask |= ((((GpioData->Direction & GPIO_CONF_INV_MASK) >> GPIO_CONF_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RXINV); + Dw0Reg |= (((GpioData->Direction & GPIO_CONF_INV_MASK) >> (GPIO_CONF_INV_BIT_POS + 1)) << N_PCH_GPIO_RXINV); + + // + // Configure GPIO output state (GPIOTxState) + // + Dw0RegMask |= ((((GpioData->OutputState & GPIO_CONF_OUTPUT_MASK) >> GPIO_CONF_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TX_STATE); + Dw0Reg |= (((GpioData->OutputState & GPIO_CONF_OUTPUT_MASK) >> (GPIO_CONF_OUTPUT_BIT_POS + 1)) << N_PCH_GPIO_TX_STATE); + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + Dw0RegMask |= ((((GpioData->OtherSettings & GPIO_CONF_RXRAW_MASK) >> GPIO_CONF_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_RX_RAW1); + Dw0Reg |= (((GpioData->OtherSettings & GPIO_CONF_RXRAW_MASK) >> (GPIO_CONF_RXRAW_BIT_POS + 1)) << N_PCH_GPIO_RX_RAW1); + + // + // Configure GPIO Pad Mode (PMode) + // + Dw0RegMask |= ((((GpioData->PadMode & GPIO_CONF_PAD_MODE_MASK) >> GPIO_CONF_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PAD_MODE); + Dw0Reg |= (((GpioData->PadMode & GPIO_CONF_PAD_MODE_MASK) >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + + // + // Configure GPIO termination (Term) + // + Dw1RegMask |= ((((GpioData->ElectricalConfig & GPIO_CONF_TERM_MASK) >> GPIO_CONF_TERM_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_TERM); + Dw1Reg |= (((GpioData->ElectricalConfig & GPIO_CONF_TERM_MASK) >> (GPIO_CONF_TERM_BIT_POS + 1)) << N_PCH_GPIO_TERM); + + // + // Configure GPIO pad tolerance (padtol) + // + Dw1RegMask |= ((((GpioData->ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> GPIO_CONF_PADTOL_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PADTOL); + Dw1Reg |= (((GpioData->ElectricalConfig & GPIO_CONF_PADTOL_MASK) >> (GPIO_CONF_PADTOL_BIT_POS + 1)) << N_PCH_GPIO_PADTOL); + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + // + // Write PADCFG DW0 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg), + ~(UINT32)Dw0RegMask, + (UINT32)Dw0Reg + ); + + // + // Write PADCFG DW1 register + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4), + ~(UINT32)Dw1RegMask, + (UINT32)Dw1Reg + ); + + // + // Update value to be programmed in HOSTSW_OWN register + // + HostSoftOwnRegMask = (GpioData->HostSoftPadOwn & 0x1) << PadNumber; + HostSoftOwnReg = (GpioData->HostSoftPadOwn >> 0x1) << PadNumber; + + // + // Write HOSTSW_OWN registers + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].HostOwnOffset), + ~(UINT32)HostSoftOwnRegMask, + (UINT32)HostSoftOwnReg + ); + + // + // Update value to be programmed in GPI_GPE_EN register + // + GpiGpeEnRegMask = (GpioData->InterruptConfig & 0x1) << PadNumber; + GpiGpeEnReg = ((GpioData->InterruptConfig & GpioIntSci) >> 3) << PadNumber; + + // + // Write GPI_GPE_EN registers + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeEnOffset), + ~(UINT32)GpiGpeEnRegMask, + (UINT32)GpiGpeEnReg + ); + + // + // Program Pad Configuration Lock + // + if ((GpioData->LockConfig & GpioPadConfigLock) == GpioPadConfigLock) { + GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + } + + // + // Program Pad Configuration Lock Tx + // + if ((GpioData->LockConfig & GpioOutputStateLock) == GpioOutputStateLock) { + GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + } + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_TX_STATE, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ) +{ + EFI_STATUS Status; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_TX_STATE, + FALSE, + OutputVal + ); + ASSERT_EFI_ERROR (Status); + *OutputVal >>= N_PCH_GPIO_TX_STATE; + + return Status; +} + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InpuHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ) +{ + EFI_STATUS Status; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_STATE, + FALSE, + InputVal + ); + ASSERT_EFI_ERROR (Status); + *InputVal >>= N_PCH_GPIO_RX_STATE; + + return Status; +} + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ) +{ + EFI_STATUS Status; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 1, + B_PCH_GPIO_INTSEL, + FALSE, + IrqNum + ); + ASSERT_EFI_ERROR (Status); + *IrqNum >>= N_PCH_GPIO_INTSEL; + + return Status; +} + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Value <<= N_PCH_GPIO_RXINV; + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RXINV, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ) +{ + EFI_STATUS Status; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RXINV, + FALSE, + InvertState + ); + ASSERT_EFI_ERROR (Status); + *InvertState >>= N_PCH_GPIO_RXINV; + + return Status; +} + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ) +{ + EFI_STATUS Status; + UINT32 RxLvlEdgeValue; + UINT32 IntRouteValue; + UINT32 GpeEnable; + + Status = EFI_SUCCESS; + + if (((Value & GPIO_CONF_INT_TRIG_MASK) >> GPIO_CONF_INT_TRIG_BIT_POS) != GpioHardwareDefault) { + RxLvlEdgeValue = ((Value & GPIO_CONF_INT_TRIG_MASK) >> (GPIO_CONF_INT_TRIG_BIT_POS + 1)) << N_PCH_GPIO_RX_LVL_EDG; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_LVL_EDG, + TRUE, + &RxLvlEdgeValue + ); + ASSERT_EFI_ERROR (Status); + } + + if (((Value & GPIO_CONF_INT_ROUTE_MASK) >> GPIO_CONF_INT_ROUTE_BIT_POS) != GpioHardwareDefault) { + + IntRouteValue = ((Value & GPIO_CONF_INT_ROUTE_MASK) >> (GPIO_CONF_INT_ROUTE_BIT_POS + 1)) << N_PCH_GPIO_RX_NMI_ROUTE; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + (B_PCH_GPIO_RX_NMI_ROUTE | B_PCH_GPIO_RX_SCI_ROUTE | B_PCH_GPIO_RX_SMI_ROUTE | B_PCH_GPIO_RX_APIC_ROUTE), + TRUE, + &IntRouteValue + ); + ASSERT_EFI_ERROR (Status); + + if ((Value & GpioIntSci) == GpioIntSci) { + GpeEnable = 0x1; + } else { + GpeEnable = 0x0; + } + + Status = GpioReadWriteReg ( + GpioGpeEnableRegister, + 0, + 0, + GpioPad, + TRUE, + TRUE, + &GpeEnable + ); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ) +{ + EFI_STATUS Status; + UINT32 TermValue; + UINT32 PadTolValue; + + Status = EFI_SUCCESS; + + if (((Value & GPIO_CONF_TERM_MASK) >> GPIO_CONF_TERM_BIT_POS) != GpioHardwareDefault) { + TermValue = ((Value & GPIO_CONF_TERM_MASK) >> (GPIO_CONF_TERM_BIT_POS + 1)) << N_PCH_GPIO_TERM; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 1, + B_PCH_GPIO_TERM, + TRUE, + &TermValue + ); + ASSERT_EFI_ERROR (Status); + } + + if (((Value & GPIO_CONF_PADTOL_MASK) >> GPIO_CONF_PADTOL_BIT_POS) != GpioHardwareDefault) { + PadTolValue = ((Value & GPIO_CONF_PADTOL_MASK) >> (GPIO_CONF_PADTOL_BIT_POS + 1)) << N_PCH_GPIO_PADTOL; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 1, + B_PCH_GPIO_PADTOL, + TRUE, + &PadTolValue + ); + ASSERT_EFI_ERROR (Status); + } + return Status; +} + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ) +{ + EFI_STATUS Status; + UINT32 ResetValue; + + Status = EFI_SUCCESS; + + if (((Value & GPIO_CONF_RESET_MASK) >> GPIO_CONF_RESET_BIT_POS) != GpioHardwareDefault) { + ResetValue = ((Value & GPIO_CONF_RESET_MASK) >> (GPIO_CONF_RESET_BIT_POS + 1)) << N_PCH_GPIO_RST_CONF; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RST_CONF, + TRUE, + &ResetValue + ); + ASSERT_EFI_ERROR (Status); + } + return Status; +} + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ) +{ + EFI_STATUS Status; + UINT32 ResetValue; + + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RST_CONF, + FALSE, + &ResetValue + ); + ASSERT_EFI_ERROR (Status); + + // + // Get Reset Type (PadRstCfg) + // + *Value = (ResetValue >> (N_PCH_GPIO_RST_CONF - (GPIO_CONF_RESET_BIT_POS + 1))) | (0x1 << GPIO_CONF_RESET_BIT_POS); + + return Status; +} + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + 0, + FALSE, + FALSE, + HostSwRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get GPIO Host Software Pad Ownership for certain group + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for current group + For group which has less then 32 pads per group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership register + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + 0, + TRUE, + FALSE, + &HostSwRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioHostOwnershipRegister, + 0, + 0, + GpioPad, + FALSE, + TRUE, + PadHostSwOwn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioHostOwnershipRegister, + 0, + 0, + GpioPad, + TRUE, + TRUE, + &PadHostSwOwn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ) +{ + UINT32 Mask; + UINT32 RegOffset; + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 PadOwnRegValue; + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Calculate RegOffset using Pad Ownership offset and GPIO Pad number. + // One DWord register contains information for 8 pads. + // + RegOffset = GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4; + + // + // Calculate pad bit position within DWord register + // + PadNumber %= 8; + Mask = (BIT1 | BIT0) << (PadNumber * 4); + + PadOwnRegValue = MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOffset)); + + *PadOwnVal = (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4)); + + return EFI_SUCCESS; +} + +/** + This procedure will check state of Pad Config Lock for pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioPadConfigLockRegister, + Group, + DwNum, + 0, + FALSE, + FALSE, + PadCfgLockRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioPadConfigLockRegister, + 0, + 0, + GpioPad, + FALSE, + TRUE, + PadCfgLock + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will check state of Pad Config Tx Lock for pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioPadLockOutputRegister, + Group, + DwNum, + 0, + FALSE, + FALSE, + PadCfgLockTxRegVal + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ) +{ + EFI_STATUS Status; + + Status = GpioReadWriteReg ( + GpioPadLockOutputRegister, + 0, + 0, + GpioPad, + FALSE, + TRUE, + PadCfgLockTx + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + TRUE, + Group, + DwNum, + PadsToUnlock, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + TRUE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be locked + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + FALSE, + Group, + DwNum, + PadsToLock, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadConfigLockRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLockTx for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + TRUE, + Group, + DwNum, + PadsToUnlockTx, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + TRUE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current group. + For group which has less then 32 pads per group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be locked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + FALSE, + Group, + DwNum, + PadsToLockTx, + 0, + FALSE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ) +{ + EFI_STATUS Status; + + Status = GpioLockPadsUsingSbi ( + GpioPadLockOutputRegister, + FALSE, + 0, + 0, + 0, + GpioPad, + TRUE + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + + +/** + This procedure will get Group to GPE mapping. + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ) +{ + UINT32 Data32; + UINT32 PchPwrmBase; + GPIO_GROUP GpioGroupOffset; + + GpioGroupOffset = GpioGetLowestGroup (); + + + PchPwrmBaseGet (&PchPwrmBase); + + Data32 = MmioRead32 ((UINTN) (PchPwrmBase + R_PCH_PWRM_GPIO_CFG)); + + *GroupToGpeDw0 = ((Data32 & B_PCH_PWRM_GPIO_CFG_GPE0_DW0) >> N_PCH_PWRM_GPIO_CFG_GPE0_DW0) + GpioGroupOffset; + *GroupToGpeDw1 = ((Data32 & B_PCH_PWRM_GPIO_CFG_GPE0_DW1) >> N_PCH_PWRM_GPIO_CFG_GPE0_DW1) + GpioGroupOffset; + *GroupToGpeDw2 = ((Data32 & B_PCH_PWRM_GPIO_CFG_GPE0_DW2) >> N_PCH_PWRM_GPIO_CFG_GPE0_DW2) + GpioGroupOffset; + + return EFI_SUCCESS; +} + +/** + This procedure will set Group to GPE mapping. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + UINT32 PchPwrmBase; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + + GpioGroupLowest = GpioGetLowestGroup (); + GpioGroupHighest = GpioGetHighestGroup (); + + // + // Check if group argument exceeds GPIO group range + // + if (((UINT32)GroupToGpeDw0 < GpioGroupLowest) || ((UINT32)GroupToGpeDw0 > GpioGroupHighest) || + ((UINT32)GroupToGpeDw1 < GpioGroupLowest) || ((UINT32)GroupToGpeDw1 > GpioGroupHighest) || + ((UINT32)GroupToGpeDw2 < GpioGroupLowest) || ((UINT32)GroupToGpeDw2 > GpioGroupHighest)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument exceeds GPIO group range\n")); + return EFI_INVALID_PARAMETER; + } + + // + // Check if each group number is unique + // + if ((GroupToGpeDw0 == GroupToGpeDw1) || + (GroupToGpeDw0 == GroupToGpeDw2) || + (GroupToGpeDw1 == GroupToGpeDw2)) { + return EFI_INVALID_PARAMETER; + } + + // + // Values in GPE0_DWx registers are 0 based (GPP_A = 0h) + // + GroupToGpeDw0 = GpioGetGroupIndexFromGroup(GroupToGpeDw0); + GroupToGpeDw1 = GpioGetGroupIndexFromGroup(GroupToGpeDw1); + GroupToGpeDw2 = GpioGetGroupIndexFromGroup(GroupToGpeDw2); + + PchPwrmBaseGet (&PchPwrmBase); + + // + // Program GPIO_CFG (PMRMBASE + 120h) register + // + Data32And = (UINT32) ~(B_PCH_PWRM_GPIO_CFG_GPE0_DW2 | B_PCH_PWRM_GPIO_CFG_GPE0_DW1 | B_PCH_PWRM_GPIO_CFG_GPE0_DW0); + Data32Or = (UINT32)((GroupToGpeDw2 << N_PCH_PWRM_GPIO_CFG_GPE0_DW2) | + (GroupToGpeDw1 << N_PCH_PWRM_GPIO_CFG_GPE0_DW1) | + (GroupToGpeDw0 << N_PCH_PWRM_GPIO_CFG_GPE0_DW0)); + + MmioAndThenOr32 ( + (UINTN) (PchPwrmBase + R_PCH_PWRM_GPIO_CFG), + Data32And, + Data32Or + ); + + Data32And = (UINT32) ~(B_PCH_PCR_GPIO_MISCCFG_GPE0_DW2 | B_PCH_PCR_GPIO_MISCCFG_GPE0_DW1 | B_PCH_PCR_GPIO_MISCCFG_GPE0_DW0); + Data32Or = (UINT32)((GroupToGpeDw2 << N_PCH_PCR_GPIO_MISCCFG_GPE0_DW2) | + (GroupToGpeDw1 << N_PCH_PCR_GPIO_MISCCFG_GPE0_DW1) | + (GroupToGpeDw0 << N_PCH_PCR_GPIO_MISCCFG_GPE0_DW0)); + // + // Program MISCCFG register for Community 0 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM0, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + // + // Program MISCCFG register for Community 1 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM1, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + // + // Program MISCCFG register for Community 2 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM2, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + // + // Program MISCCFG register for Community 3 + // + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (PID_GPIOCOM3, R_PCH_PCR_GPIO_MISCCFG), + Data32And, + Data32Or + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Purpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ) +{ + GPIO_GROUP GroupToGpeDw0; + GPIO_GROUP GroupToGpeDw1; + GPIO_GROUP GroupToGpeDw2; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + UINT32 GroupIndex; + GPIO_GROUP Group; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Group = GpioGetGroupFromGpioPad (GpioPad); + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGroupLowest = GpioGetLowestGroup (); + GpioGroupHighest = GpioGetHighestGroup (); + + // + // Check if group argument exceeds GPIO group range + // + if ((GroupIndex < GpioGetGroupIndexFromGroup (GpioGroupLowest)) || (GroupIndex > GpioGetGroupIndexFromGroup (GpioGroupHighest))) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Get GPIO groups mapping to 1-tier GPE + // + GpioGetGroupToGpeDwX (&GroupToGpeDw0,&GroupToGpeDw1,&GroupToGpeDw2); + + if (Group == GroupToGpeDw0) { + *GpeNumber = PadNumber; + } else if (Group== GroupToGpeDw1) { + *GpeNumber = PadNumber + 32; + } else if (Group == GroupToGpeDw2) { + *GpeNumber = PadNumber + 64; + } else { + // + // If Group number doesn't match any of above then + // it means than certain pad is routed to 2-tier GPE + // which all are under GPE_111 (0x6F) + // + *GpeNumber = PCH_GPIO_2_TIER_MASTER_GPE_NUMBER; + } + + return EFI_SUCCESS; +} + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if group has GPI SMI register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset == NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + // + // Clear all GPI SMI Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiStsOffset), + (UINT32)(BIT0 << PadNumber) + ); + + return EFI_SUCCESS; +} + +/** + This procedure is used by PchSmiDispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ) +{ + UINT32 GroupIndex; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) { + // + // Check if group has GPI SMI register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset == NO_REGISTER_FOR_PROPERTY) { + continue; + } + // + // Clear all GPI SMI Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiStsOffset), + (UINT32)0xFFFFFFFF + ); + } + return EFI_SUCCESS; +} + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ) +{ + GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GroupIndex; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) { + // + // Check if group has GPI SMI register + // + if (GpioGroupInfo[GroupIndex].SmiEnOffset == NO_REGISTER_FOR_PROPERTY) { + continue; + } + + // + // Disable all GPI SMI + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiEnOffset), + (UINT32)0x0 + ); + } + return EFI_SUCCESS; +} + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ) +{ + UINT32 GroupIndex; + UINT32 Index; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + return EFI_INVALID_PARAMETER; + } + + *GpiNum = 0; + + for (Index = 0; Index < (UINT32)GroupIndex; Index++) { + *GpiNum += (UINTN)(GpioGroupInfo[Index].PadPerGroup); + } + *GpiNum += (UINTN)PadNumber; + + return EFI_SUCCESS; +} + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 Data32; + + GpioGetGpeNumber (GpioPad, &Data32); + if(Data32 == PCH_GPIO_2_TIER_MASTER_GPE_NUMBER) { + return TRUE; + } + + return FALSE; +} + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if group has GPI GPE register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset == NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + + // Check for 2-tier + if(!(GpioCheckFor2Tier (GpioPad))) { + return EFI_INVALID_PARAMETER; + } + + // + // Clear all GPI SMI Status bits by writing '1' + // + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeStsOffset), + (UINT32)(BIT0 << PadNumber) + ); + + return EFI_SUCCESS; +} + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ) +{ + UINT32 Data32; + UINT32 Mask; + UINT32 GroupIndex; + UINT32 PadNumber; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + *Data = 0xFFFFFFFF; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) exceeds GPIO group range\n", GroupIndex)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pad number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for this group\n", PadNumber)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check if group has GPI GPE register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset == NO_REGISTER_FOR_PROPERTY) { + return EFI_INVALID_PARAMETER; + } + + // Check for 2-tier + if(!(GpioCheckFor2Tier (GpioPad))) { + return EFI_INVALID_PARAMETER; + } + + // + // Read GPI GPE Status bits + // + Data32 = MmioRead32( + PCH_PCR_ADDRESS(GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeStsOffset) + ); + + Mask = (UINT32)(BIT0 << PadNumber); + Data32 = (Data32 & Mask) >> PadNumber; + *Data = Data32; + + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO Input Rout SCI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSCI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSci ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Value <<= N_PCH_GPIO_RX_SCI_ROUTE; + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_SCI_ROUTE, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set GPIO Input Rout SMI + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIRoutSMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiRoutSmi ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Value <<= N_PCH_GPIO_RX_SMI_ROUTE; + Status = GpioReadWritePadCfgReg ( + GpioPad, + 0, + B_PCH_GPIO_RX_SMI_ROUTE, + TRUE, + &Value + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set GPI SMI Enable setting for selected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiSmiEn GPI SMI Enable setting for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiSmiPadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiSmiEn + ) +{ + GPIO_GROUP Group; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + EFI_STATUS Status; + + GpioGroupOffset = GpioGetLowestGroup (); + NumberOfGroups = GpioGetNumberOfGroups (); + + Group = GpioGetGroupFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >= NumberOfGroups + GpioGroupOffset)) { + return EFI_INVALID_PARAMETER; + } + + Status = GpioReadWriteReg ( + GpioSmiEnableRegister, + Group, + 0, + GpioPad, + TRUE, + TRUE, + &PadGpiSmiEn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This procedure will set GPI General Purpose Event Enable setting for selected pad + + @param[in] GpioPad GPIO pad + @param[in] PadGpiGpeEn GPI General Purpose Event Enable setting for selected pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGpiGpePadEn ( + IN GPIO_PAD GpioPad, + IN UINT32 PadGpiGpeEn + ) +{ + GPIO_GROUP Group; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + EFI_STATUS Status; + + GpioGroupOffset = GpioGetLowestGroup (); + NumberOfGroups = GpioGetNumberOfGroups (); + + Group = GpioGetGroupFromGpioPad (GpioPad); + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >= NumberOfGroups + GpioGroupOffset)) { + return EFI_INVALID_PARAMETER; + } + + + Status = GpioReadWriteReg ( + GpioGpeEnableRegister, + Group, + 0, + GpioPad, + TRUE, + TRUE, + &PadGpiGpeEn + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + Check if given GPIO Pad is locked + + @param[in] GroupIndex GPIO group index + @param[in] PadNumber GPIO pad number + + @retval TRUE Pad is locked + @retval FALSE Pad is not locked +**/ +BOOLEAN +GpioIsPadLocked ( + IN UINT32 GroupIndex, + IN GPIO_PAD PadNumber + ) +{ + UINT32 RegVal; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // Read PADCFGLOCK register + // + RegVal = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].PadCfgLockOffset)); + + return (((RegVal >> PadNumber) & 0x1) == 1); +} + +/** + Locks multiple GPIO pads using GPIO_INIT_CONFIG array. + Only locking is applied and no other GPIO pad configuration is changed. + + @param[in] NumberOfItems Number of GPIO pads to be locked + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number + @retval EFI_UNSUPPORTED Incorrect GPIO pad definition +**/ +static +EFI_STATUS +GpioLockPads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + UINT32 Index; + UINT32 PadsToLock[V_PCH_GPIO_GROUP_MAX]; + UINT32 PadsToLockTx[V_PCH_GPIO_GROUP_MAX]; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + GPIO_PAD_OWN PadOwnVal; + GPIO_INIT_CONFIG *GpioData; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries (); + PadOwnVal = GpioPadOwnHost; + + ZeroMem (PadsToLock, sizeof (PadsToLock)); + ZeroMem (PadsToLockTx, sizeof (PadsToLockTx)); + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupOffset = GpioGetLowestGroup (); + NumberOfGroups = GpioGetNumberOfGroups (); + + for (Index = 0; Index < NumberOfItems; Index ++) { + + GpioData = &GpioInitTableAddress[Index]; + + Group = GpioGetGroupFromGpioPad (GpioData->GpioPad); + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad); + + // + // Checking GroupIndex to avoid Buffer Overflows or Array Out of Index + // + if (GroupIndex >= V_PCH_GPIO_GROUP_MAX) { + ASSERT (FALSE); + continue; + } + + // + // Check if group argument exceeds GPIO group range + // + if ((Group < GpioGroupOffset) || (Group >= NumberOfGroups + GpioGroupOffset)) { + return EFI_INVALID_PARAMETER; + } + + // + // Check if legal pin number + // + if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){ + return EFI_INVALID_PARAMETER; + } + + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // + GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal); + + if (PadOwnVal != GpioPadOwnHost) { + continue; + } + + // + // Update information on Pad Configuration Lock + // + PadsToLock[GroupIndex] |= ((GpioData->GpioConfig.LockConfig >> 0x1) & 0x1) << PadNumber; + + // + // Update information on Pad Configuration Lock Tx + // + PadsToLockTx[GroupIndex] |= ((GpioData->GpioConfig.LockConfig >> 0x2) & 0x1) << PadNumber; + } + + for (Index = 0; Index < NumberOfGroups; Index++) { + // + // Write Pad Configuration Lock + // + if (PadsToLock[Index] != 0) { + GpioLockPadCfgForGroupDw (Index + GpioGroupOffset, 0, PadsToLock[Index]); + } + + // + // Write Pad Configuration Lock Tx + // + if (PadsToLockTx[Index] != 0) { + GpioLockPadCfgTxForGroupDw (Index + GpioGroupOffset, 0, PadsToLockTx[Index]); + } + } + + return EFI_SUCCESS; +} + +/** + Locks GPIO pads according to GPIO_INIT_CONFIG array from + gPlatformGpioConfigGuid HOB. Only locking is applied and no other GPIO pad + configuration is changed. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_NOT_FOUND gPlatformGpioConfigGuid not found +**/ +EFI_STATUS +GpioLockGpios ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GpioConfigHob; + GPIO_INIT_CONFIG *GpioConfig; + UINT16 GpioConfigSize; + + GpioConfigHob = GetFirstGuidHob (&gPlatformGpioConfigGuid); + if (GpioConfigHob == NULL) { + return EFI_NOT_FOUND; + } + ASSERT (GET_GUID_HOB_DATA_SIZE (GpioConfigHob) % sizeof (GpioConfig[0]) == 0); + GpioConfigSize = GET_GUID_HOB_DATA_SIZE (GpioConfigHob) / sizeof (GpioConfig[0]); + GpioConfig = GET_GUID_HOB_DATA (GpioConfigHob); + GpioLockPads (GpioConfigSize, GpioConfig); + + return EFI_SUCCESS; +} + +/** + Unlocks all PCH GPIO pads + + @retval None +**/ +VOID +GpioUnlockAllGpios ( + VOID + ) +{ + GPIO_GROUP GpioGroupOffset; + UINT32 NumberOfGroups; + UINT32 Index; + + GpioGroupOffset = GpioGetLowestGroup (); + NumberOfGroups = GpioGetNumberOfGroups (); + + for (Index = 0; Index < NumberOfGroups; Index++) { + // + // Reset Pad Configuration Lock + // + GpioUnlockPadCfgForGroupDw (Index + GpioGroupOffset, 0, 0xFFFFFFFF); + + // + // Reset Pad Configuration Lock Tx + // + GpioUnlockPadCfgTxForGroupDw (Index + GpioGroupOffset, 0, 0xFFFFFFFF); + } +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioLibrary.h new file mode 100644 index 0000000000..8618099e24 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioLibrary.h @@ -0,0 +1,222 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _GPIO_LIBRARY_H_ +#define _GPIO_LIBRARY_H_ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <PchAccess.h> +#include <Library/PchPcrLib.h> +#include <GpioPinsSklH.h> +#include <Library/GpioLib.h> +#include <Library/GpioNativeLib.h> +#include <Library/MmPciBaseLib.h> +#include <Library/PchInfoLib.h> +#include <Library/PchCycleDecodingLib.h> +#include <Library/PchSbiAccessLib.h> + +typedef struct { + GPIO_PAD Pad; + GPIO_PAD_MODE Mode; +} GPIO_PAD_NATIVE_FUNCTION; + + +// BIT15-0 - pad number +// BIT31-16 - group info +// BIT23- 16 - group index +// BIT31- 24 - chipset ID +#define PAD_INFO_MASK 0x0000FFFF +#define GROUP_INFO_POSITION 16 +#define GROUP_INFO_MASK 0xFFFF0000 +#define GROUP_INDEX_MASK 0x00FF0000 +#define UNIQUE_ID_MASK 0xFF000000 +#define UNIQUE_ID_POSITION 24 + +#define GPIO_PAD_DEF(Group,Pad) (UINT32)((Group << 16) + Pad) +#define GPIO_GROUP_DEF(Index,ChipsetId) (Index | (ChipsetId << 8)) +#define GPIO_GET_GROUP_INDEX(Group) (Group & 0xFF) +#define GPIO_GET_GROUP_FROM_PAD(Pad) (Pad >> 16) +#define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX ((Pad >> 16)) +#define GPIO_GET_PAD_NUMBER(Pad) (Pad & 0xFFFF) +#define GPIO_GET_CHIPSET_ID(Pad) (Pad >> 24) + +// +// Unique ID used in GpioPad defines +// +#define GPIO_SKL_H_CHIPSET_ID 0x1 +#define GPIO_SKL_LP_CHIPSET_ID 0x2 + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +// +// Structure for storing information about registers offset, community, +// maximal pad number for available groups +// +typedef struct { + UINT32 Community; + UINT32 PadOwnOffset; + UINT32 HostOwnOffset; + UINT32 GpiIsOffset; + UINT32 GpiIeOffset; + UINT32 GpiGpeStsOffset; + UINT32 GpiGpeEnOffset; + UINT32 SmiStsOffset; + UINT32 SmiEnOffset; + UINT32 NmiStsOffset; + UINT32 NmiEnOffset; + UINT32 PadCfgLockOffset; + UINT32 PadCfgLockTxOffset; + UINT32 PadCfgOffset; + UINT32 PadPerGroup; +} GPIO_GROUP_INFO; + +// +// If in GPIO_GROUP_INFO structure certain register doesn't exist +// it will have value equal to NO_REGISTER_FOR_PROPERTY +// +#define NO_REGISTER_FOR_PROPERTY (~0u) + + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ); + + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table + +**/ +GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINTN *GpioGroupInfoTableLength + ); + +/** + This procedure will set GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +SetGpioPadMode ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ); + +/** + This procedure will get GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GetGpioPadMode ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ); + +/** + This function checks if GPIO pin is a GSPI chip select pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsGpioPadAGSpiCsbPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ); + +/** + This function checks if GPIO pin is a SataDevSlp pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsPadASataDevSlpPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ); + +/** + Check if given GPIO Pad is locked + + @param[in] GroupIndex GPIO group index + @param[in] PadNumber GPIO pad number + + @retval TRUE Pad is locked + @retval FALSE Pad is not locked +**/ +BOOLEAN +GpioIsPadLocked ( + IN UINT32 GroupIndex, + IN GPIO_PAD PadNumber + ); + +#endif // _GPIO_LIBRARY_H_ diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioNativeLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioNativeLib.c new file mode 100644 index 0000000000..a86c144679 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/GpioNativeLib.c @@ -0,0 +1,454 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "GpioLibrary.h" + +// +// Chipset specific data +// +//SATA +extern GPIO_PAD_NATIVE_FUNCTION mPchHSataPortResetToGpioMap[PCH_H_AHCI_MAX_PORTS]; +extern GPIO_PAD_NATIVE_FUNCTION mPchHSataDevSlpPinToGpioMap[PCH_H_AHCI_MAX_PORTS]; + +// +// SKX specific +// +extern GPIO_GROUP_INFO mPchGpioGroupInfo[V_PCH_GPIO_GROUP_MAX]; + +/** + This procedure will set GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +SetGpioPadMode ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ) +{ + GPIO_PAD_OWN PadOwnVal; + UINT32 PadCfgReg; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 PadNumber; + UINT32 GroupIndex; + UINT32 Dw0Reg; + UINT32 Dw0RegMask; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + + if (PadOwnVal != GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } + + if (GpioIsPadLocked (GroupIndex, PadNumber)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pad is locked (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_WRITE_PROTECTED; + } + + // + // Create Pad Configuration register offset + // + PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + Dw0RegMask = ((((PadModeValue & GPIO_CONF_PAD_MODE_MASK) >> GPIO_CONF_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_PCH_GPIO_PAD_MODE); + Dw0Reg = (((PadModeValue & GPIO_CONF_PAD_MODE_MASK) >> (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + + MmioAndThenOr32 ( + (UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg), + ~(UINT32)Dw0RegMask, + (UINT32)Dw0Reg + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GetGpioPadMode ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ) +{ + GPIO_PAD_OWN PadOwnVal; + UINT32 PadCfgReg; + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 PadNumber; + UINT32 GroupIndex; + UINT32 Dw0Reg; + + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber = GpioGetPadNumberFromGpioPad (GpioPad); + +DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } +DEBUG_CODE_END(); + + GpioGetPadOwnership (GpioPad, &PadOwnVal); + + if (PadOwnVal != GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber)); + return EFI_UNSUPPORTED; + } + + // + // Create Pad Configuration register offset + // + PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; + + Dw0Reg = MmioRead32 ((UINTN)PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg)); + + *PadModeValue = ((Dw0Reg & B_PCH_GPIO_PAD_MODE) >> (N_PCH_GPIO_PAD_MODE - (GPIO_CONF_PAD_MODE_BIT_POS + 1))) | (0x1 << GPIO_CONF_PAD_MODE_BIT_POS); + + return EFI_SUCCESS; +} + + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table + +**/ +GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINTN *GpioGroupInfoTableLength + ) +{ + if (GetPchGeneration () == SklPch) { + *GpioGroupInfoTableLength = sizeof (mPchGpioGroupInfo) / sizeof (GPIO_GROUP_INFO); + return mPchGpioGroupInfo; + } else { + *GpioGroupInfoTableLength = 0; + return NULL; + } +} + + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ) +{ +DEBUG_CODE_BEGIN(); + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries (); + + if ((PchSeries == PchH) && (GPIO_GET_CHIPSET_ID(GpioPad) == GPIO_SKL_H_CHIPSET_ID)) { + return TRUE; + } else if ((PchSeries == PchLp) && (GPIO_GET_CHIPSET_ID(GpioPad) == GPIO_SKL_LP_CHIPSET_ID)) { + return TRUE; + } + +DEBUG_CODE_END(); + return FALSE; +} + + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ) +{ + GPIO_GROUP_INFO *GpioGroupInfo; + UINTN GpioGroupInfoLength; + UINT32 GroupIndex; + // + // Check if group argument exceeds GPIO GROUP INFO array + // + GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength); + GroupIndex = GpioGetGroupIndexFromGroup (Group); + + if ((UINTN)GroupIndex >= GpioGroupInfoLength) { + ASSERT(FALSE); + return 0; + } else { + return GpioGroupInfo[GroupIndex].PadPerGroup; + } +} + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT8 +GpioGetNumberOfGroups ( + VOID + ) +{ + return V_PCH_H_GPIO_GROUP_MAX; +} +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ) +{ + return (UINT32)GPIO_SKL_H_GROUP_GPP_A; +} +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ) +{ + return (UINT32)GPIO_SKL_H_GROUP_GPD; +} + +/** + This procedure will get group number + + @param[in] GpioPad Gpio Pad + + @retval Value Group number +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return GPIO_GET_GROUP_FROM_PAD (GpioPad); +} + +/** + This procedure will get group index (0 based) + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return (UINT32)GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad); +} + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ) +{ + return (UINT32)GPIO_GET_GROUP_INDEX (GpioGroup); +} + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return (UINT32)GPIO_GET_PAD_NUMBER (GpioPad); +} +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ) +{ + return GPIO_PAD_DEF(Group,PadNumber); +} + + + +/** + This function checks if GPIO pin for SATA reset port is in GPIO MODE + + @param[in] SataPort SATA port number + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsSataResetPortInGpioMode ( + IN UINTN SataPort + ) +{ + EFI_STATUS Status; + UINT32 GpioPin; + GPIO_PAD_MODE GpioMode; + + + ASSERT (SataPort < PCH_H_AHCI_MAX_PORTS); + GpioPin = mPchHSataPortResetToGpioMap[SataPort].Pad; + + Status = GetGpioPadMode (GpioPin, &GpioMode); + if ((EFI_ERROR (Status)) || (GpioMode != GpioPadModeGpio)) { + return FALSE; + } else { + return TRUE; + } +} + + +/** + This function checks if GPIO pin is a SataDevSlp pin + + @param[in] GpioPad GPIO pad + @param[in] PadMode GPIO pad mode + + @retval TRUE Pin is in GPIO mode + FALSE Pin is in native mode +**/ +BOOLEAN +GpioIsPadASataDevSlpPin ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadMode + ) +{ + UINT32 SataDevSlpPinMax; + UINT32 SataDevSlpPinIndex; + GPIO_PAD_OWN PadOwnership; + GPIO_PAD_NATIVE_FUNCTION *SataDevSlpPinToGpioMap; + + SataDevSlpPinToGpioMap = mPchHSataDevSlpPinToGpioMap; + SataDevSlpPinMax = sizeof(mPchHSataDevSlpPinToGpioMap)/sizeof(GPIO_PAD_NATIVE_FUNCTION); + + for (SataDevSlpPinIndex = 0; SataDevSlpPinIndex < SataDevSlpPinMax; SataDevSlpPinIndex++) { + if ((GpioPad == SataDevSlpPinToGpioMap[SataDevSlpPinIndex].Pad) && + (PadMode == SataDevSlpPinToGpioMap[SataDevSlpPinIndex].Mode)) { + GpioGetPadOwnership (SataDevSlpPinToGpioMap[SataDevSlpPinIndex].Pad , &PadOwnership); + if (PadOwnership == GpioPadOwnHost) { + return TRUE; + } else { + return FALSE; + } + } + } + return FALSE; +} + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad + ) +{ + GPIO_PAD_MODE DevSlpPadMode; + GPIO_PAD DevSlpGpioPad; + GPIO_PAD_MODE GpioMode; + EFI_STATUS Status; + + ASSERT (SataPort < PCH_H_AHCI_MAX_PORTS); + DevSlpGpioPad = mPchHSataDevSlpPinToGpioMap[SataPort].Pad; + DevSlpPadMode = mPchHSataDevSlpPinToGpioMap[SataPort].Mode; + + Status = GetGpioPadMode (DevSlpGpioPad, &GpioMode); + + if (EFI_ERROR (Status) || (GpioMode != DevSlpPadMode)) { + *DevSlpPad = 0x0; + return FALSE; + } else { + *DevSlpPad = DevSlpGpioPad; + return TRUE; + } +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c new file mode 100644 index 0000000000..62d93d6c86 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "GpioLibrary.h" + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchGpioGroupInfo[] = { + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN, R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_A_GPI_IS, R_PCH_PCR_GPIO_GPP_A_GPI_IE, R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, V_PCH_GPIO_GPP_A_PAD_MAX}, //SKX PCH-Server GPP_A + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN, R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_B_GPI_IS, R_PCH_PCR_GPIO_GPP_B_GPI_IE, R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_B_SMI_STS, R_PCH_PCR_GPIO_GPP_B_SMI_EN, R_PCH_PCR_GPIO_GPP_B_NMI_STS, R_PCH_PCR_GPIO_GPP_B_NMI_EN, R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, V_PCH_GPIO_GPP_B_PAD_MAX}, //SKX PCH-Server GPP_B + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN, R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_C_GPI_IS, R_PCH_PCR_GPIO_GPP_C_GPI_IE, R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_C_SMI_STS, R_PCH_PCR_GPIO_GPP_C_SMI_EN, R_PCH_PCR_GPIO_GPP_C_NMI_STS, R_PCH_PCR_GPIO_GPP_C_NMI_EN, R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, V_PCH_GPIO_GPP_C_PAD_MAX}, //SKX PCH-Server GPP_C + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN, R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_D_GPI_IS, R_PCH_PCR_GPIO_GPP_D_GPI_IE, R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_D_SMI_STS, R_PCH_PCR_GPIO_GPP_D_SMI_EN, R_PCH_PCR_GPIO_GPP_D_NMI_STS, R_PCH_PCR_GPIO_GPP_D_NMI_EN, R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, V_PCH_GPIO_GPP_D_PAD_MAX}, //SKX PCH-Server GPP_D + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN, R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_E_GPI_IS, R_PCH_PCR_GPIO_GPP_E_GPI_IE, R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_E_SMI_STS, R_PCH_PCR_GPIO_GPP_E_SMI_EN, R_PCH_PCR_GPIO_GPP_E_NMI_STS, R_PCH_PCR_GPIO_GPP_E_NMI_EN, R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_E_PAD_MAX}, //SKX PCH-Server GPP_E + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_F_GPI_IS, R_PCH_H_PCR_GPIO_GPP_F_GPI_IE, R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET, V_PCH_GPIO_GPP_F_PAD_MAX}, //SKX PCH-Server GPP_F + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_G_GPI_IS, R_PCH_H_PCR_GPIO_GPP_G_GPI_IE, R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_G_PAD_MAX}, //SKX PCH-Server GPP_G + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_H_GPI_IS, R_PCH_H_PCR_GPIO_GPP_H_GPI_IE, R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_H_PAD_MAX}, //SKX PCH-Server GPP_H + {PID_GPIOCOM3, R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_I_GPI_IS, R_PCH_H_PCR_GPIO_GPP_I_GPI_IE, R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN, R_PCH_H_PCR_GPIO_GPP_I_SMI_STS,R_PCH_H_PCR_GPIO_GPP_I_SMI_EN, R_PCH_H_PCR_GPIO_GPP_I_NMI_STS,R_PCH_H_PCR_GPIO_GPP_I_NMI_EN, R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_I_PAD_MAX}, //SKX PCH-Server GPP_I + {PID_GPIOCOM4, R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_J_GPI_IS, R_PCH_H_PCR_GPIO_GPP_J_GPI_IE, R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_J_PAD_MAX}, //SKX PCH-Server GPP_J + {PID_GPIOCOM4, R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_K_GPI_IS, R_PCH_H_PCR_GPIO_GPP_K_GPI_IE, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_K_PAD_MAX}, //SKX PCH-Server GPP_K + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_L_GPI_IS, R_PCH_H_PCR_GPIO_GPP_L_GPI_IE, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_L_PAD_MAX}, //SKX PCH-Server GPP_L + {PID_GPIOCOM2, R_PCH_H_PCR_GPIO_GPD_PAD_OWN, R_PCH_PCR_GPIO_GPD_HOSTSW_OWN, R_PCH_PCR_GPIO_GPD_GPI_IS, R_PCH_PCR_GPIO_GPD_GPI_IE, R_PCH_PCR_GPIO_GPD_GPI_GPE_STS, R_PCH_PCR_GPIO_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET, V_PCH_GPIO_GPD_PAD_MAX} //SKX PCH-Server GPD +}; + + +// +// SATA reset port to GPIO pin mapping +// SATAGP_x -> GPIO pin y +// + +GPIO_PAD_NATIVE_FUNCTION mPchHSataPortResetToGpioMap[PCH_H_AHCI_MAX_PORTS] = +{ + {GPIO_SKL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F2, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F3, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F4, GpioPadModeNative2} +}; + +// +// SATADevSlpPin to GPIO pin mapping +// SATA_DEVSLP_x -> GPIO pin y +// + +GPIO_PAD_NATIVE_FUNCTION mPchHSataDevSlpPinToGpioMap[PCH_H_AHCI_MAX_PORTS] = +{ + {GPIO_SKL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F7, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F8, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F9, GpioPadModeNative1} +}; diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf new file mode 100644 index 0000000000..0d7c56c0d0 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf @@ -0,0 +1,55 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmGpioLib
+ FILE_GUID = 16EC5CA8-8195-4847-B6CB-662BD7B763F2
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = GpioLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ MmPciLib
+ PchCycleDecodingLib
+ PchSbiAccessLib
+ PchPcrLib #SERVER_BIOS
+ HobLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleyRcPkg/RcPkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+
+
+[Sources]
+ GpioLib.c
+ GpioLibrary.h
+ GpioNativeLib.c
+ GpioInit.c
+ PchSklGpioData.c
+
+[Guids]
+ gPlatformGpioConfigGuid
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c new file mode 100644 index 0000000000..3629bc5157 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c @@ -0,0 +1,1176 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <PchAccess.h> +#include <Library/PchInfoLib.h> +#include <Library/PchPcrLib.h> +#include <Library/PchP2sbLib.h> +#include <Library/PchCycleDecodingLib.h> + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes alignment, and it is IO space, so must not exceed 0xFFFF. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [7] to diable ACPI base address first before changing base address. + 2. program PMC PCI offset 40h [15:2] to ACPI base address. + 3. set PMC PCI offset 44h [7] to enable ACPI base address. + 4. program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F, PMC PCI Offset 40h bit[15:2], 1]. + 5. Program "ACPI Base Destination ID" + For SPT-LP: Program PCR[DMI] + 27B8h[31:0] to 0x23A0 + For SPT-H: Program PCR[DMI] + 27B8h[31:0] to 0x23A8 + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseSet ( + IN UINT16 Address + ) +{ + UINTN PmcBase; + UINT32 Dmic; + UINT32 Data32; + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries (); + + if (((Address & 0x00FF) != 0) || + (Address == 0)) + { + DEBUG((DEBUG_ERROR, "PchAcpiBaseSet Error. Invalid Address: %x.\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + DEBUG((DEBUG_ERROR, "PchAcpiBaseSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + PmcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Disable ABASE in PMC Device first before changing base address. + // + MmioAnd8 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + (UINT8) ~B_PCH_PMC_ACPI_CNT_ACPI_EN + ); + // + // Program ABASE in PMC Device + // + MmioAndThenOr16 ( + PmcBase + R_PCH_PMC_ACPI_BASE, + (UINT16) (~B_PCH_PMC_ACPI_BASE_BAR), + Address + ); + // + // Enable ABASE in PMC Device + // + MmioOr8 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + B_PCH_PMC_ACPI_CNT_ACPI_EN + ); + // + // Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + // + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_ACPIBA, + (0x00FC0001 + Address) + ); + // + // Program "ACPI Base Destination ID" + // For SPT-LP: + // Program PCR[DMI] + 27B8h[31:0] to 0x23A0 + // For SPT-H: + // Program PCR[DMI] + 27B8h[31:0] to 0x23A8 + // + if(PchSeries == PchLp){ + Data32 = 0x23A0; + } else { + Data32 = 0x23A8; + } + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_ACPIBDID, + Data32 + ); + return EFI_SUCCESS; +} + +/** + Get PCH ACPI base address. + + @param[out] Address Address of ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchAcpiBaseGet ( + OUT UINT16 *Address + ) +{ + UINTN PmcBase; + + if (Address == NULL) { + DEBUG((DEBUG_ERROR, "PchAcpiBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PmcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + *Address = MmioRead16 (PmcBase + R_PCH_PMC_ACPI_BASE) & B_PCH_PMC_ACPI_BASE_BAR; + return EFI_SUCCESS; +} + +/** + Set PCH PWRM base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. clear PMC PCI offset 44h [8] to diable PWRM base address first before changing PWRM base address. + 2. program PMC PCI offset 48h [31:16] to PM base address. + 3. set PMC PCI offset 44h [8] to enable PWRM base address. + 4. program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the PWRMBASE to be 64KB aligned. + program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the memory allocated to PWRMBASE to be 64KB in size. + 5. Program "PM Base Control" + For SPT-LP: Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0] + For SPT-H: Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A8] + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseSet ( + IN UINT32 Address + ) +{ + UINTN PmcBase; + UINT32 Dmic; + UINT32 Data32; + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries (); + + if (((Address & (~B_PCH_PMC_PWRM_BASE_BAR)) != 0) || + (Address == 0)) + { + DEBUG((DEBUG_ERROR, "PchPwrmBaseSet Error. Invalid Address: %x.\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + DEBUG((DEBUG_ERROR, "PchPwrmBaseSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + PmcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Disable PWRMBASE in PMC Device first before changing PWRM base address. + // + MmioAnd16 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + (UINT16) ~B_PCH_PMC_ACPI_CNT_PWRM_EN + ); + // + // Program PWRMBASE in PMC Device + // + MmioAndThenOr32 ( + PmcBase + R_PCH_PMC_PWRM_BASE, + (UINT32) (~B_PCH_PMC_PWRM_BASE_BAR), + Address + ); + // + // Enable PWRMBASE in PMC Device + // + MmioOr16 ( + PmcBase + R_PCH_PMC_ACPI_CNT, + B_PCH_PMC_ACPI_CNT_PWRM_EN + ); + // + // Program "PM Base Address Memory Range Base" PCR[DMI] + 27ACh[15:0] to the same value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the PWRMBASE to be 64KB aligned. + // Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16] to the value programmed in PMC PCI Offset 48h bit[31:16], this has an implication of making sure the memory allocated to PWRMBASE to be 64KB in size. + // + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_PMBASEA, + ((Address & 0xFFFF0000) | (Address >> 16)) + ); + // + // Program "PM Base Control" + // For SPT-LP: + // Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A0] + // For SPT-H: + // Program PCR[DMI] + 27B0h[31, 30:0] to [1, 0x23A8] + // + if(PchSeries == PchLp){ + Data32 = 0x800023A0; + } else { + Data32 = 0x800023A8; + } + PchPcrWrite32 ( + PID_DMI, R_PCH_PCR_DMI_PMBASEC, + Data32 + ); + return EFI_SUCCESS; +} + +/** + Get PCH PWRM base address. + + @param[out] Address Address of PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchPwrmBaseGet ( + OUT UINT32 *Address + ) +{ + UINTN PmcBase; + + if (Address == NULL) { + DEBUG((DEBUG_ERROR, "PchPwrmBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PmcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + if (MmioRead16 (PmcBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + *Address = MmioRead32 (PmcBase + R_PCH_PMC_PWRM_BASE) & B_PCH_PMC_PWRM_BASE_BAR; + return EFI_SUCCESS; +} + +/** + Set PCH TCO base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1]. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseSet ( + IN UINT16 Address + ) +{ + UINTN SmbusBase; + UINT32 Dmic; + + if ((Address & ~B_PCH_SMBUS_TCOBASE_BAR) != 0) { + DEBUG((DEBUG_ERROR, "PchTcoBaseSet Error. Invalid Address: %x.\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + DEBUG((DEBUG_ERROR, "PchTcoBaseSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + SmbusBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS + ); + if (MmioRead16 (SmbusBase) == 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Verify TCO base is not locked. + // + if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) != 0) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + // + // Disable TCO in SMBUS Device first before changing base address. + // + MmioAnd8 ( + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, + (UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) + ); + // + // Program TCO in SMBUS Device + // + MmioAndThenOr16 ( + SmbusBase + R_PCH_SMBUS_TCOBASE, + (UINT16) (~B_PCH_SMBUS_TCOBASE_BAR), + Address + ); + // + // Enable TCO in SMBUS Device + // + MmioOr8 ( + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, + (B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) + ); + // + // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI offset 50h[15:5], 1]. + // + PchPcrWrite16 ( + PID_DMI, R_PCH_PCR_DMI_TCOBASE, + (Address | BIT1) + ); + + return EFI_SUCCESS; +} + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +EFIAPI +PchTcoBaseGet ( + OUT UINT16 *Address + ) +{ + if (Address == NULL) { + DEBUG((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Read "TCO Base Address" PCR[DMI] + 2778h[15:5] + // Don't read TCO base address from SMBUS PCI register since SMBUS might be disabled. + // + PchPcrRead16 ( + PID_DMI, R_PCH_PCR_DMI_TCOBASE, + Address + ); + *Address &= B_PCH_PCR_DMI_TCOBASE_TCOBA; + + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI generic IO range. + For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length aligned. + This function basically checks the address and length, which should not overlap with all other generic ranges. + If no more generic range register available, it returns out of resource error. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges: + 0x00-0x1F, + 0x44-0x4B, + 0x54-0x5F, + 0x68-0x6F, + 0x80-0x8F, + 0xC0-0xFF + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h. + + @param[in] Address Address for generic IO range base address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + , IN UINT8 SlaveDevice + ) +{ + EFI_STATUS Status; + PCH_LPC_GEN_IO_RANGE_LIST LpcGenIoRangeList; + UINTN LpcBase; + UINTN Index; + UINTN BaseAddr; + UINTN MaskLength; + UINTN TempMaxAddr; + UINT32 Data32; + UINTN ArraySize; + static struct EXCEPT_RANGE { + UINT8 Start; + UINT8 Length; + } ExceptRanges[] = { {0x00, 0x20}, {0x44, 0x08}, {0x54, 0x0C}, {0x68, 0x08}, {0x80, 0x10}, {0xC0, 0x40} }; + + Index = 0; + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + + // + // For generic IO range, the base address must align to 4 and less than 0xFFFF, + // the length must be power of 2 and less than or equal to 256, and the address must be length aligned. + // IO range below 0x100 will be rejected in this function except below ranges: + // 0x00-0x1F, + // 0x44-0x4B, + // 0x54-0x5F, + // 0x68-0x6F, + // 0x80-0x8F, + // 0xC0-0xFF + // + if (((Length & (Length - 1)) != 0) || + ((Address & (UINT16)~B_PCH_LPC_GENX_DEC_IOBAR) != 0) || + (Length > 256)) + { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (Address < 0x100) { + ArraySize = sizeof (ExceptRanges) / sizeof (struct EXCEPT_RANGE); + for (Index = 0; Index < ArraySize; Index++) { + if ((Address >= ExceptRanges[Index].Start) && + ((Address + Length) <= ((UINTN)ExceptRanges[Index].Start + (UINTN)ExceptRanges[Index].Length))) + { + break; + } + } + if (Index >= ArraySize) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + } + + // + // check if range overlap + // + Status = PchLpcGenIoRangeGet (&LpcGenIoRangeList, SlaveDevice); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + if (SlaveDevice == LPC_ESPI_FIRST_SLAVE) { + for (Index = 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + BaseAddr = LpcGenIoRangeList.Range[Index].BaseAddr; + MaskLength = LpcGenIoRangeList.Range[Index].Length; + if (BaseAddr == 0) { + continue; + } + if (((Address >= BaseAddr) && (Address < (BaseAddr + MaskLength))) || + (((Address + Length) > BaseAddr) && ((Address + Length) <= (BaseAddr + MaskLength)))) + { + if ((Address >= BaseAddr) && (Length <= MaskLength)) { + // + // return SUCCESS while range is covered. + // + return EFI_SUCCESS; + } + + if ((Address + Length) > (BaseAddr + MaskLength)) { + TempMaxAddr = Address + Length; + } else { + TempMaxAddr = BaseAddr + MaskLength; + } + if (Address > BaseAddr) { + Address = (UINT16) BaseAddr; + } + Length = TempMaxAddr - Address; + break; + } + } + // + // If no range overlap + // + if (Index >= PCH_LPC_GEN_IO_RANGE_MAX) { + // + // Find a empty register + // + for (Index = 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + BaseAddr = LpcGenIoRangeList.Range[Index].BaseAddr; + if (BaseAddr == 0) { + break; + } + } + if (Index >= PCH_LPC_GEN_IO_RANGE_MAX) { + return EFI_OUT_OF_RESOURCES; + } + } + } else { + BaseAddr = LpcGenIoRangeList.Range[0].BaseAddr; + MaskLength = LpcGenIoRangeList.Range[0].Length; + if (BaseAddr != 0) { + if (((Address >= BaseAddr) && (Address < (BaseAddr + MaskLength))) || + (((Address + Length) > BaseAddr) && ((Address + Length) <= (BaseAddr + MaskLength)))) + { + if ((Address >= BaseAddr) && (Length <= MaskLength)) { + // + // return SUCCESS while range is covered. + // + return EFI_SUCCESS; + } else { + return EFI_OUT_OF_RESOURCES; + } + } + } + } + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Data32); + if ((Data32 & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Program LPC/eSPI generic IO range register accordingly. + // + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + Data32 = (UINT32) (((Length - 1) << 16) & B_PCH_LPC_GENX_DEC_IODRA); + Data32 |= (UINT32) Address; + Data32 |= B_PCH_LPC_GENX_DEC_EN; + + if (SlaveDevice == LPC_ESPI_FIRST_SLAVE) { + // + // Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + // + MmioWrite32 ( + LpcBase + R_PCH_LPC_GEN1_DEC + Index * 4, + Data32 + ); + // + // Program LPC Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same value programmed in LPC/eSPI PCI Offset 84h~93h. + // + PchPcrWrite32 ( + PID_DMI, (UINT16) (R_PCH_PCR_DMI_LPCLGIR1 + Index * 4), + Data32 + ); + } else { + ASSERT(FALSE); + } + return EFI_SUCCESS; +} + +/** + Get PCH LPC/eSPI generic IO range list. + This function returns a list of base address, length, and enable for all LPC/eSPI generic IO range regsiters. + + @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO range register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + , IN UINT8 SlaveDevice + ) +{ + UINTN Index; + UINTN LpcBase; + UINT32 Data32; + + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + + if (LpcGenIoRangeList == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + + if (SlaveDevice == LPC_ESPI_FIRST_SLAVE) { + for (Index = 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + Data32 = MmioRead32 (LpcBase + R_PCH_LPC_GEN1_DEC + Index * 4); + LpcGenIoRangeList->Range[Index].BaseAddr = Data32 & B_PCH_LPC_GENX_DEC_IOBAR; + LpcGenIoRangeList->Range[Index].Length = ((Data32 & B_PCH_LPC_GENX_DEC_IODRA) >> 16) + 4; + LpcGenIoRangeList->Range[Index].Enable = Data32 & B_PCH_LPC_GENX_DEC_EN; + } + } else { + ASSERT(FALSE); + } + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI memory range decoding. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program LPC/eSPI PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address. + 2. Program LPC/eSPI PCI Offset 98h [31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h. + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length passed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeSet ( + IN UINT32 Address + , IN UINT8 SlaveDevice + ) +{ + UINTN LpcBase; + UINT32 Dmic; + UINTN LpcReg; + UINT16 DmiReg; + + if ((Address & (~B_PCH_LPC_LGMR_MA)) != 0) { + DEBUG((DEBUG_ERROR, "PchLpcMemRangeSet Error. Invalid Address: %x.\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + DEBUG((DEBUG_ERROR, "PchLpcMemRangeSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + if (SlaveDevice == ESPI_SECONDARY_SLAVE) { + ASSERT(FALSE); + } else { + LpcReg = LpcBase + R_PCH_LPC_LGMR; + DmiReg = R_PCH_PCR_DMI_LPCGMR; + } + // + // Program LPC/eSPI PCI Offset 98h [0] (LPC/ePSI first slave) or A8h [0] (eSPI secondary slave) to [0] to disable memory decoding first before changing base address. + // + MmioAnd32 ( + LpcReg, + (UINT32) ~B_PCH_LPC_LGMR_LMRD_EN + ); + // + // Program LPC/eSPI PCI Offset 98h [31:16, 0] (LPC/ eSPI first slave) or A8h [31:16, 0] (eSPI secondary slave) to [Address, 1]. + // + MmioWrite32 ( + LpcReg, + (Address | B_PCH_LPC_LGMR_LMRD_EN) + ); + // + // Program LPC Memory Range, PCR[DMI] + 2740h (LPC/eSPI first slave) or 27C0h (eSPI secondary slave) to the same value programmed in LPC/eSPI PCI Offset 98h. + // + PchPcrWrite32 ( + PID_DMI, DmiReg, + (Address | B_PCH_LPC_LGMR_LMRD_EN) + ); + return EFI_SUCCESS; +} + +/** + Get PCH LPC/eSPI memory range decoding address. + + @param[out] Address Address of LPC/eSPI memory decoding base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +EFIAPI +PchLpcMemRangeGet ( + OUT UINT32 *Address + , IN UINT8 SlaveDevice + ) +{ + UINTN LpcBase; + + if (Address == NULL) { + DEBUG((DEBUG_ERROR, "PchLpcMemRangeGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + if (SlaveDevice == LPC_ESPI_FIRST_SLAVE) { + *Address = MmioRead32 (LpcBase + R_PCH_LPC_LGMR) & B_PCH_LPC_LGMR_MA; + } else { + ASSERT(FALSE); + } + return EFI_SUCCESS; +} + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnable. + 2. program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC or SPI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ) +{ + UINTN BaseAddr; + UINT32 DmiGcsBbs; + UINT32 Dmic; + + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + DEBUG((DEBUG_ERROR, "PchBiosDecodeEnableSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_GCS, &DmiGcsBbs); + DmiGcsBbs &= B_PCH_PCR_DMI_BBS; + // + // Check General Control and Status (GCS) [10] + // '0': SPI + // '1': LPC/eSPI + // + if (DmiGcsBbs == 0) { + BaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI + ); + // + // if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + // + MmioWrite16 (BaseAddr + R_PCH_SPI_BDE, BiosDecodeEnable); + } else { + BaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + // + // if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnable. + // + MmioWrite16 (BaseAddr + R_PCH_LPC_BDE, BiosDecodeEnable); + } + + // + // program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC or SPI Offset D8h. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_LPCBDE, BiosDecodeEnable); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO decode ranges. + Program LPC/eSPI I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ) +{ + UINTN LpcBaseAddr; + UINT32 Dmic; + + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + + LpcBaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + // + // check if setting is identical + // + if (LpcIoDecodeRanges == MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOD)) { + return EFI_SUCCESS; + } + + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC/eSPI PCI offset 80h. + // + MmioWrite16 (LpcBaseAddr + R_PCH_LPC_IOD, LpcIoDecodeRanges); + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_LPCIOD, LpcIoDecodeRanges); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO enable decoding. + Setup LPC/eSPI I/O Enables, PCR[DMI] + 2774h[15:0] to the same value program in LPC/eSPI PCI offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +EFIAPI +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + , IN UINT8 SlaveDevice + ) +{ + UINTN LpcBaseAddr; + UINT32 Dmic; + UINTN LpcReg; + + if (SlaveDevice == LPC_ESPI_FIRST_SLAVE) { + LpcReg = R_PCH_LPC_IOE; + } else { + ASSERT(FALSE); + } + + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + + LpcBaseAddr = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC + ); + if (LpcIoEnableDecoding == MmioRead16 (LpcBaseAddr + LpcReg)) { + return EFI_SUCCESS; + } + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program PCI offset 82h for LPC/eSPI CS#0 or offset A0h for eSPI CS#1. + // + MmioWrite16 (LpcBaseAddr + LpcReg, LpcIoEnableDecoding); + + if (SlaveDevice == ESPI_SECONDARY_SLAVE) { + // + // For eSPI CS#1 device program PCI offset 82h respectively + // + MmioWrite16 (LpcBaseAddr + R_PCH_LPC_IOE, (LpcIoEnableDecoding | MmioRead16(LpcBaseAddr + R_PCH_LPC_IOE))); + } + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_LPCIOE, LpcIoEnableDecoding); + return EFI_SUCCESS; +} + + +// +// PCH-LP RPR destination ID table +// +UINT16 PchLpRprDidTable[] = { + 0x2188, // Dest ID of RP1 + 0x2189, // Dest ID of RP2 + 0x218A, // Dest ID of RP3 + 0x218B, // Dest ID of RP4 + 0x2198, // Dest ID of RP5 + 0x2199, // Dest ID of RP6 + 0x219A, // Dest ID of RP7 + 0x219B, // Dest ID of RP8 + 0x21A8, // Dest ID of RP9 + 0x21A9, // Dest ID of RP10 + 0x21AA, // Dest ID of RP11 + 0x21AB // Dest ID of RP12 +}; + +// +// PCH-H RPR destination ID table +// +UINT16 PchHRprDidTable[] = { + 0x2180, // Dest ID of RP1 + 0x2181, // Dest ID of RP2 + 0x2182, // Dest ID of RP3 + 0x2183, // Dest ID of RP4 + 0x2188, // Dest ID of RP5 + 0x2189, // Dest ID of RP6 + 0x218A, // Dest ID of RP7 + 0x218B, // Dest ID of RP8 + 0x2198, // Dest ID of RP9 + 0x2199, // Dest ID of RP10 + 0x219A, // Dest ID of RP11 + 0x219B, // Dest ID of RP12 + 0x21A8, // Dest ID of RP13 + 0x21A9, // Dest ID of RP14 + 0x21AA, // Dest ID of RP15 + 0x21AB, // Dest ID of RP16 + 0x21B8, // Dest ID of RP17 + 0x21B9, // Dest ID of RP18 + 0x21BA, // Dest ID of RP19 + 0x21BB, // Dest ID of RP20 +}; + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus enumeration. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +EFIAPI +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ) +{ + UINT32 Dmic; + UINT16 *PchRprDidTable; + + PchPcrRead32 (PID_DMI, R_PCH_PCR_DMI_DMIC, &Dmic); + if ((Dmic & B_PCH_PCR_DMI_DMIC_SRL) != 0) { + DEBUG((DEBUG_ERROR, "PchIoPort80DecodeSet Error. DMIC.SRL is set.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + /// + /// IO port 80h is typically used by decoder/LED hardware for debug purposes. + /// By default PCH will forward IO port 80h cycles to LPC bus. The Reserved Page Route (RPR) bit + /// of General Control and Status register, located at PCR[DMI] + 274Ch[11] , allows software to + /// re-direct IO port 80h cycles to PCIe bus so that a target (for example, a debug card) on + /// PCIe bus can receive and claim these cycles. + /// The "RPR Destination ID", PCR[DMI] + 274Ch[31:16] need to be set accordingly to point + /// to the root port that decode this range. Reading from Port 80h may not return valid values + /// if the POST-card itself do not shadow the writes. Unlike LPC, PCIe does not shadow the Port 80 writes. + /// + + if (GetPchSeries () == PchLp) { + PchRprDidTable = PchLpRprDidTable; + } else { + PchRprDidTable = PchHRprDidTable; + } + + // + // Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP. + // + PchPcrWrite16 (PID_DMI, R_PCH_PCR_DMI_GCS + 2, PchRprDidTable[RpPhyNumber]); + // + // Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. + // Use byte write on GCS+1 and leave the BILD bit which is RWO. + // + PchPcrAndThenOr8 (PID_DMI, R_PCH_PCR_DMI_GCS + 1, 0xFF, (B_PCH_PCR_DMI_RPR >> 8)); + + return EFI_SUCCESS; +} + +/** + Get IO APIC regsiters base address. + It returns IO APIC INDEX, DATA, and EOI regsiter address once the parameter is not NULL. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] IoApicIndex Buffer of IO APIC INDEX regsiter address + @param[out] IoApicData Buffer of IO APIC DATA regsiter address + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OPTIONAL OUT UINT32 *IoApicIndex, + OPTIONAL OUT UINT32 *IoApicData + ) +{ + EFI_STATUS Status; + UINT16 RegIoac; + UINT32 RangeSelect; + + Status = PchP2sbCfgGet16 (R_PCH_P2SB_IOAC, &RegIoac); + if (EFI_ERROR (Status)) { + return Status; + } + + RangeSelect = (RegIoac & B_PCH_P2SB_IOAC_ASEL) << N_PCH_IO_APIC_ASEL; + + if (IoApicIndex != NULL) { + *IoApicIndex = R_PCH_IO_APIC_INDEX + RangeSelect; + } + if (IoApicData != NULL) { + *IoApicData = R_PCH_IO_APIC_DATA + RangeSelect; + } + + return EFI_SUCCESS; +} + +/** + Get HPET base address. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ) +{ + EFI_STATUS Status; + UINT8 RegHptc; + + if (HpetBase == NULL) { + DEBUG((DEBUG_ERROR, "PchHpetBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Status = PchP2sbCfgGet8 (R_PCH_P2SB_HPTC, &RegHptc); + + switch (RegHptc & B_PCH_P2SB_HPTC_AS) { + case 0: + *HpetBase = V_PCH_HPET_BASE0; + break; + case 1: + *HpetBase = V_PCH_HPET_BASE1; + break; + case 2: + *HpetBase = V_PCH_HPET_BASE2; + break; + case 3: + *HpetBase = V_PCH_HPET_BASE3; + break; + default: + break; + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf new file mode 100644 index 0000000000..c0cf90854f --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf @@ -0,0 +1,40 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPchCycleDecodingLib
+ FILE_GUID = 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PchCycleDecodingLib
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ MmPciLib
+ PchInfoLib
+ PchPcrLib
+ PchP2sbLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+ PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+
+[Sources]
+ PchCycleDecodingLib.c
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c new file mode 100644 index 0000000000..9d3304a1aa --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchGbeLib/PchGbeLib.c @@ -0,0 +1,166 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <Library/PchPmcLib.h> +#include <PchAccess.h> +#include <Library/PchInfoLib.h> +#include <Library/PchPcrLib.h> +#include <Library/PchCycleDecodingLib.h> + +#include <PiPei.h> +#include <Ppi/Spi.h> +#include <Library/PeiServicesLib.h> +extern EFI_GUID gPeiSpiPpiGuid; +/** + Check whether GbE region is valid + Check SPI region directly since GbE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ) +{ + UINT32 SpiBar; + SpiBar = MmioRead32 (MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI) + + R_PCH_SPI_BAR0) & ~B_PCH_SPI_BAR0_MASK; + ASSERT (SpiBar != 0); + if (MmioRead32 (SpiBar + R_PCH_SPI_FREG3_GBE) != B_PCH_SPI_FREGX_BASE_MASK) { + return TRUE; + } + return FALSE; +} + +/** + Returns GbE over PCIe port number based on a soft strap. + + @return Root port number (1-based) + @retval 0 GbE over PCIe disabled +**/ +UINT32 +PchGetGbePortNumber ( + VOID + ) +{ + UINT32 GbePortSel; + UINT32 PcieStrapFuse; + + PchPcrRead32 (PID_FIAWM26, R_PCH_PCR_FIA_STRPFUSECFG1_REG_BASE, &PcieStrapFuse); + if ((PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIE_PEN) == 0) { + return 0; // GbE disabled + } + GbePortSel = (PcieStrapFuse & B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL) >> N_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL; + + switch (GbePortSel) { + case 0: return 3 + 1; + case 1: return 4 + 1; + case 2: return 5 + 1; + case 3: return 8 + 1; + case 4: return 11 + 1; + } + + DEBUG((DEBUG_ERROR, "Invalid GbE port\n")); + ASSERT (FALSE); + return 0; +} + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ) +{ + + UINT32 SoftstrapVal; + EFI_SPI_PROTOCOL *SpiProtocol = NULL; + EFI_STATUS Status; + UINTN GbePciBase; + + if (PchIsDwrFlow() == TRUE) { + return FALSE; + } + + GbePciBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LAN, + PCI_FUNCTION_NUMBER_PCH_LAN + ); + + // + // Check GBE disable strap + // + Status = PeiServicesLocatePpi ( + &gPeiSpiPpiGuid, + 0, + NULL, + (VOID **) &SpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + Status = SpiProtocol->ReadPchSoftStrap(SpiProtocol, 0x1DC, 4, &SoftstrapVal); + if (!EFI_ERROR(Status)) { + if ((SoftstrapVal & BIT14) == BIT14) { + return FALSE; + } + } + // + // Check FIA strap/fuse + // + if (PchGetGbePortNumber () == 0) { + return FALSE; + } + // + // Check GbE NVM + // + if (PchIsGbeRegionValid () == FALSE) { + return FALSE; + } + if (MmioRead32 (GbePciBase) == 0xFFFFFFFF) { + return FALSE; + } + return TRUE; +} + +/** + Check whether LAN controller is enabled in the platform. + + @deprecated Use PchIsGbePresent instead. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbeAvailable ( + VOID + ) +{ + return PchIsGbePresent (); +} + + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf new file mode 100644 index 0000000000..59388180f1 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf @@ -0,0 +1,44 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPchGbeLib
+ FILE_GUID = FC022ED0-6EB3-43E1-A740-0BA27CBBD010
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PchGbeLib
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ MmPciLib
+ PchInfoLib
+ PchPcrLib
+ PchCycleDecodingLib
+ PchPmcLib #SERVER_BIOS
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+ PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+[Sources]
+ PchGbeLib.c
+
+[Ppis]
+ gPeiSpiPpiGuid
+
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c new file mode 100644 index 0000000000..31966dd609 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c @@ -0,0 +1,511 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MmPciBaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <PchAccess.h>
+
+#define PCH_DO_STRINGIFY(x) #x
+#define PCH_STRINGIFY(x) PCH_DO_STRINGIFY(x)
+
+//
+// This module variables are used for cache the static result.
+// @note: please pay attention to the PEI phase, the module variables on ROM
+// and can't be modified.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mLpcBaseAddr = 0;
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_STEPPING mPchStepping = PchSteppingMax;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mIsPchSupported = 0xFF;
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_SERIES mPchSeries = PchUnknownSeries;
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_GENERATION mPchGeneration = PchUnknownGeneration;
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+EFIAPI
+PchStepping (
+ VOID
+ )
+{
+ UINT8 RevId;
+ UINT16 LpcDeviceId;
+ UINTN LpcBaseAddress;
+
+ if (mPchStepping != PchSteppingMax) {
+ return mPchStepping;
+ }
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+ RevId = MmioRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET);
+
+ LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+
+ if (IS_PCH_H_LPC_DEVICE_ID (LpcDeviceId)) {
+ switch (RevId) {
+ case V_PCH_LPC_RID_0:
+ mPchStepping = PchHA0;
+ return PchHA0;
+
+ case V_PCH_LPC_RID_10:
+ mPchStepping = PchHB0;
+ return PchHB0;
+
+ case V_PCH_LPC_RID_20:
+ mPchStepping = PchHC0;
+ return PchHC0;
+
+ case V_PCH_LPC_RID_30:
+ mPchStepping = PchHD0;
+ return PchHD0;
+
+ case V_PCH_LPC_RID_31:
+ mPchStepping = PchHD1;
+ return PchHD1;
+
+ default:
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %a and above\n", PCH_STRINGIFY(PCH_H_MIN_SUPPORTED_STEPPING))) ;
+ return PchSteppingMax;
+ }
+ }
+
+ if (IS_PCH_LP_LPC_DEVICE_ID (LpcDeviceId)) {
+ switch (RevId) {
+#ifdef SIMICS_FLAG
+ case V_PCH_LPC_RID_0:
+ mPchStepping = PchLpA0;
+ return PchLpA0;
+#endif
+
+ case V_PCH_LPC_RID_10:
+ mPchStepping = PchLpB0;
+ return PchLpB0;
+
+ case V_PCH_LPC_RID_11:
+ mPchStepping = PchLpB1;
+ return PchLpB1;
+
+ case V_PCH_LPC_RID_20:
+ mPchStepping = PchLpC0;
+ return PchLpC0;
+
+ case V_PCH_LPC_RID_21:
+ mPchStepping = PchLpC1;
+ return PchLpC1;
+
+ default:
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %a and above\n", PCH_STRINGIFY(PCH_LP_MIN_SUPPORTED_STEPPING))) ;
+ return PchSteppingMax;
+ }
+ }
+
+#ifdef SKXD_EN
+ if (IS_PCH_LBG_D_SSKU_LPC_DEVICE_ID (LpcDeviceId)) {
+ switch (RevId) {
+ case V_PCH_LBG_LPC_RID_3:
+ return LbgB1_D;
+ default:
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %s and above\n", PCH_STRINGIFY(V_PCH_LBG_LPC_RID_3)));
+ return PchSteppingMax;
+ }
+ }
+#endif // SKXD_EN
+
+ if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) {
+ if (RevId == 0) {
+ return LbgA0;
+ } else {
+ switch (RevId) {
+ case V_PCH_LBG_LPC_RID_0:
+ return LbgA0;
+ case V_PCH_LBG_LPC_RID_2:
+ return LbgB0;
+ case V_PCH_LBG_LPC_RID_3:
+ return LbgB1;
+ case V_PCH_LBG_LPC_RID_4:
+ return LbgB2;
+ case V_PCH_LBG_LPC_RID_8:
+ return LbgS0;
+ case V_PCH_LBG_LPC_RID_9:
+ return LbgS1;
+ default:
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %s and above\n", PCH_STRINGIFY(PCH_LBG_MIN_SUPPORTED_STEPPING)));
+ ASSERT (FALSE);
+ return PchSteppingMax;
+ }
+ }
+ }
+ return PchSteppingMax;
+}
+
+/**
+ Determine if PCH is supported
+
+ @retval TRUE PCH is supported
+ @retval FALSE PCH is not supported
+**/
+BOOLEAN
+IsPchSupported (
+ VOID
+ )
+{
+ UINT16 LpcDeviceId;
+ UINT16 LpcVendorId;
+ UINTN LpcBaseAddress;
+
+ if (mIsPchSupported != 0xFF) {
+ return (BOOLEAN) mIsPchSupported;
+ }
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+
+ LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+ LpcVendorId = MmioRead16 (LpcBaseAddress + PCI_VENDOR_ID_OFFSET);
+
+ ///
+ /// Verify that this is a supported chipset
+ ///
+ if ((LpcVendorId == V_PCH_LPC_VENDOR_ID) &&
+ (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)))
+ {
+ mIsPchSupported = TRUE;
+ return TRUE;
+ } else {
+ DEBUG ((DEBUG_ERROR, "PCH code doesn't support the LpcDeviceId: 0x%04x!\n", LpcDeviceId));
+ mIsPchSupported = FALSE;
+ return FALSE;
+ }
+}
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+EFIAPI
+GetPchSeries (
+ VOID
+ )
+{
+ UINT16 LpcDeviceId;
+ UINT32 PchSeries;
+ UINTN LpcBaseAddress;
+
+ if (mPchSeries != PchUnknownSeries) {
+ return mPchSeries;
+ }
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+
+ LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+
+ if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) {
+ PchSeries = PchH;
+ } else if (IS_PCH_LP_LPC_DEVICE_ID (LpcDeviceId)) {
+ PchSeries = PchLp;
+ } else {
+ PchSeries = PchUnknownSeries;
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH SKU, LpcDeviceId: 0x%04x!\n", LpcDeviceId));
+ ASSERT (FALSE);
+ }
+ mPchSeries = PchSeries;
+
+ return PchSeries;
+}
+
+/**
+ Return Pch Generation
+
+ @retval PCH_GENERATION Pch Generation
+**/
+PCH_GENERATION
+EFIAPI
+GetPchGeneration (
+ VOID
+ )
+{
+ UINT16 LpcDeviceId;
+ UINT32 PchGen;
+ UINTN LpcBaseAddress;
+
+ if (mPchGeneration != PchUnknownGeneration) {
+ return mPchGeneration;
+ }
+
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+ LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+
+ if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) {
+ PchGen = SklPch;
+ } else {
+ PchGen = PchUnknownGeneration;
+ DEBUG ((DEBUG_ERROR, "Unsupported PCH SKU, LpcDeviceId: 0x%04x!\n", LpcDeviceId));
+ ASSERT (FALSE);
+ }
+ mPchGeneration = PchGen;
+
+ return PchGen;
+}
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval Pch Maximum Pcie Root Port Number
+**/
+UINT8
+EFIAPI
+GetPchMaxPciePortNum (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries ();
+ switch (PchSeries) {
+ case PchLp:
+ return PCH_LP_PCIE_MAX_ROOT_PORTS;
+
+ case PchH:
+ return PCH_H_PCIE_MAX_ROOT_PORTS;
+
+ default:
+ return 0;
+ }
+}
+
+
+/**
+ Get Pch Maximum Sata Port Number
+
+ @retval Pch Maximum Sata Port Number
+**/
+UINT8
+EFIAPI
+GetPchMaxSataPortNum (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries ();
+ switch (PchSeries) {
+ case PchLp:
+ return PCH_LP_AHCI_MAX_PORTS;
+
+ case PchH:
+ return PCH_H_AHCI_MAX_PORTS;
+
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Usb Maximum Physical Port Number
+
+ @retval Pch Usb Maximum Physical Port Number
+**/
+UINT8
+EFIAPI
+GetPchUsbMaxPhysicalPortNum (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries ();
+ switch (PchSeries) {
+ case PchLp:
+ return PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS;
+
+ case PchH:
+ return PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS;
+
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Maximum Usb2 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb2 Port Number of XHCI Controller
+**/
+UINT8
+EFIAPI
+GetPchXhciMaxUsb2PortNum (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries ();
+ switch (PchSeries) {
+ case PchLp:
+ return PCH_LP_XHCI_MAX_USB2_PORTS;
+
+ case PchH:
+ return PCH_H_XHCI_MAX_USB2_PORTS;
+
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Maximum Usb3 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb3 Port Number of XHCI Controller
+**/
+UINT8
+EFIAPI
+GetPchXhciMaxUsb3PortNum (
+ VOID
+ )
+{
+ PCH_SERIES PchSeries;
+
+ PchSeries = GetPchSeries ();
+ switch (PchSeries) {
+ case PchLp:
+ return PCH_LP_XHCI_MAX_USB3_PORTS;
+
+ case PchH:
+ return PCH_H_XHCI_MAX_USB3_PORTS;
+
+ default:
+ return 0;
+ }
+}
+
+/**
+ Determine if sSata controller is present or not
+
+ @param[in] None
+
+ @retval TRUE or FALSE
+**/
+BOOLEAN
+EFIAPI
+GetIsPchsSataPresent (
+ VOID
+ )
+{
+ UINT16 sSataDeviceId;
+ UINTN sSataBaseAddress;
+
+ sSataBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_EVA,
+ PCI_FUNCTION_NUMBER_PCH_SSATA
+ );
+
+ sSataDeviceId = MmioRead16 ( sSataBaseAddress + PCI_DEVICE_ID_OFFSET);
+
+ if (sSataDeviceId != 0xffff){
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+/**
+ Get Pch Maximum sSata Controller Number
+
+ @param[in] None
+
+ @retval Pch Maximum sSata Controller Number
+**/
+
+UINT8
+EFIAPI
+GetPchMaxsSataPortNum (
+ VOID
+ )
+{
+ return PCH_SSATA_MAX_PORTS;
+}
+
+/**
+
+ Get Pch Maximum Sata Controller Number
+
+ @param[in] None
+
+ @retval Pch Maximum Sata Controller Number
+
+**/
+UINT8
+EFIAPI
+GetPchMaxsSataControllerNum (
+ VOID
+ )
+{
+ return PCH_SSATA_MAX_CONTROLLERS;
+}
+
+/**
+ Return Pch Lpc Device Id
+
+ @retval UINT16 Pch DeviceId
+**/
+UINT16
+EFIAPI
+GetPchLpcDeviceId (
+ VOID
+ )
+{
+ UINTN LpcBaseAddress;
+
+ if (mPchSeries != PchUnknownSeries) {
+ return mPchSeries;
+ }
+
+ LpcBaseAddress = mLpcBaseAddr;
+ if (LpcBaseAddress == 0) {
+ LpcBaseAddress = MmPciBase (
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC
+ );
+ mLpcBaseAddr = LpcBaseAddress;
+ }
+
+ return MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+}
+
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PchInfoStrLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PchInfoStrLib.c new file mode 100644 index 0000000000..641277c083 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PchInfoStrLib.c @@ -0,0 +1,297 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <Library/PchInfoLib.h> +#include <PchAccess.h> + +/** + Structure for PCH stepping string mapping +**/ +struct PCH_STEPPING_STRING { + PCH_STEPPING Stepping; + CHAR8 *String; +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_STEPPING_STRING mSteppingStrs[] = { + {PchHA0, "A0"}, + {PchHB0, "B0"}, + {PchHC0, "C0"}, + {PchHD0, "D0"}, + {PchHD1, "D1"}, +#ifdef SIMICS_FLAG + {PchLpA0, "A0"}, +#endif + {PchLpB0, "B0"}, + {PchLpB1, "B1"}, + {PchLpC0, "C0"}, + {PchLpC1, "C1"}, + {LbgA0, "A0"}, + {LbgB0, "B0"}, + {LbgB1, "B1"}, + {LbgB2, "B2"}, + {LbgS0, "S0"}, + {LbgS1, "S1"}, + {PchSteppingMax, NULL} +}; + +/** + Structure for PCH series string mapping +**/ +struct PCH_SERIES_STRING { + PCH_SERIES Series; + CHAR8 *String; +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SERIES_STRING mSeriesStrs[] = { + {PchH, "SKL PCH-H"}, + {PchLp, "SKL PCH-LP"}, + {PchUnknownSeries, NULL} +}; + +/** + Structure for PCH sku string mapping +**/ +struct PCH_SKU_STRING { + UINT16 Id; + CHAR8 *String; +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SKU_STRING mSkuStrs[] = { + // + // SKL PCH H Desktop LPC Device IDs + // + {V_PCH_H_LPC_DEVICE_ID_DT_SUPER_SKU, "Super SKU"}, + {V_PCH_H_LPC_DEVICE_ID_DT_0, "Super SKU (locked)"}, + {V_PCH_H_LPC_DEVICE_ID_DT_1, "H110"}, + {V_PCH_H_LPC_DEVICE_ID_DT_2, "H170"}, + {V_PCH_H_LPC_DEVICE_ID_DT_3, "Z170"}, + {V_PCH_H_LPC_DEVICE_ID_DT_4, "Q170"}, + {V_PCH_H_LPC_DEVICE_ID_DT_5, "Q150"}, + {V_PCH_H_LPC_DEVICE_ID_DT_6, "B150"}, + {V_PCH_H_LPC_DEVICE_ID_UNFUSE, "Unfused SKU"}, + // + // SKL PCH H Server/WS LPC Device IDs + // + {V_PCH_H_LPC_DEVICE_ID_SVR_0, "C236"}, + {V_PCH_H_LPC_DEVICE_ID_SVR_1, "C232"}, + {V_PCH_H_LPC_DEVICE_ID_SVR_2, "CM236"}, + {V_PCH_H_LPC_DEVICE_ID_A14B, "Super SKU (Unlocked)"}, + {V_PCH_LBG_LPC_DEVICE_ID_UNFUSED, "LBG Unfused SKU"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_0, "LBG SuperSKU - 0"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_4_SD, "LBG SuperSKU - 4/SD"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_T80_NS, "LBG SuperSKU - T80/SD"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_1G, "LBG SuperSKU - 1G"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_T, "LBG SuperSKU - T"}, + {V_PCH_LBG_LPC_DEVICE_ID_SS_L, "LBG SuperSKU - L"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_0, "LBG QS/PRQ - 0"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_1G, "LBG QS/PRQ - 1G"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_2, "LBG QS/PRQ - 2"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_4, "LBG QS/PRQ - 4"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_E, "LBG QS/PRQ - E"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_M, "LBG QS/PRQ - M"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_T, "LBG QS/PRQ - T"}, + {V_PCH_LBG_PROD_LPC_DEVICE_ID_LP, "LBG QS/PRQ - LP"}, + // + // SKL PCH H Mobile LPC Device IDs + // + {V_PCH_H_LPC_DEVICE_ID_MB_0, "QM170"}, + {V_PCH_H_LPC_DEVICE_ID_MB_1, "HM170"}, + {V_PCH_H_LPC_DEVICE_ID_MB_2, "QMS170"}, + {V_PCH_H_LPC_DEVICE_ID_MB_SUPER_SKU, "Super SKU"}, + // + // SKL PCH LP Mobile LPC Device IDs + // + {V_PCH_LP_LPC_DEVICE_ID_UNFUSE, "Unfused SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_SUPER_SKU, "Super SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_0, "Super SKU (locked)"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_1, "(U) Base SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_2, "(Y) Premium SKU"}, + {V_PCH_LP_LPC_DEVICE_ID_MB_3, "(U) Premium SKU"}, + {0xFFFF, NULL} +}; + +/** + Get PCH stepping ASCII string + The return string is zero terminated. + + @param [in] PchStep Pch stepping + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + IN PCH_STEPPING PchStep, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ) +{ + UINTN Index; + UINT32 StrLength; + CHAR8 *Str; + EFI_STATUS Status; + + if ((Buffer == NULL) || (BufferSize == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*BufferSize > 0) { + Buffer[0] = 0; + } + + Str = NULL; + StrLength = 0; + for (Index = 0; mSteppingStrs[Index].Stepping != PchSteppingMax; Index++) { + if (PchStep == mSteppingStrs[Index].Stepping) { + StrLength = (UINT32) AsciiStrLen (mSteppingStrs[Index].String); + Str = mSteppingStrs[Index].String; + break; + } + } + if (StrLength == 0) { + // Unsupported Stepping + // ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (*BufferSize <= StrLength) { + *BufferSize = StrLength + 1; + return EFI_BUFFER_TOO_SMALL; + } + Status = AsciiStrCpyS (Buffer, *BufferSize, Str); + ASSERT_EFI_ERROR(Status); + return Status; +} + +/** + Get PCH series ASCII string + The return string is zero terminated. + + @param [in] PchSeries Pch series + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSeriesStr ( + IN PCH_SERIES PchSeries, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ) +{ + UINTN Index; + UINT32 StrLength; + CHAR8 *Str; + EFI_STATUS Status; + + if ((Buffer == NULL) || (BufferSize == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*BufferSize > 0) { + Buffer[0] = 0; + } + + Str = NULL; + StrLength = 0; + for (Index = 0; mSeriesStrs[Index].Series != PchUnknownSeries; Index++) { + if (PchSeries == mSeriesStrs[Index].Series) { + StrLength = (UINT32) AsciiStrLen (mSeriesStrs[Index].String); + Str = mSeriesStrs[Index].String; + break; + } + } + if (StrLength == 0) { + // Unsupported Series + // ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (*BufferSize <= StrLength) { + *BufferSize = StrLength + 1; + return EFI_BUFFER_TOO_SMALL; + } + Status = AsciiStrCpyS (Buffer, *BufferSize, Str); + ASSERT_EFI_ERROR(Status); + return Status; +} + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @param [in] LpcDid LPC device id + @param [out] Buffer Output buffer of string + @param [in,out] BufferSize Size of input buffer, + and return required string size when buffer is too small. + + @retval EFI_SUCCESS String copy successfully + @retval EFI_INVALID_PARAMETER The series is not supported, or parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSkuStr ( + IN UINT16 LpcDid, + OUT CHAR8 *Buffer, + IN OUT UINT32 *BufferSize + ) +{ + UINTN Index; + UINT32 StrLength; + CHAR8 *Str; + EFI_STATUS Status; + + if ((Buffer == NULL) || (BufferSize == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (*BufferSize > 0) { + Buffer[0] = 0; + } + + Str = NULL; + StrLength = 0; + for (Index = 0; mSkuStrs[Index].Id != 0xFFFF; Index++) { + if (LpcDid == mSkuStrs[Index].Id) { + StrLength = (UINT32) AsciiStrLen (mSkuStrs[Index].String); + Str = mSkuStrs[Index].String; + } + } + if (StrLength == 0) { + // Unsupported Sku + // ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + if (*BufferSize <= StrLength) { + *BufferSize = StrLength + 1; + return EFI_BUFFER_TOO_SMALL; + } + Status = AsciiStrCpyS (Buffer, *BufferSize, Str); + ASSERT_EFI_ERROR(Status); + return Status; +} diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf new file mode 100644 index 0000000000..2b3fdeb495 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf @@ -0,0 +1,39 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPchInfoLib
+ FILE_GUID = D43F3086-1D7E-4FF5-AE6A-3B0E15B11329
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PchInfoLib
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ MmPciLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+ PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+
+[Sources]
+ PchInfoLib.c
+ PchInfoStrLib.c
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchP2sbLib/PchP2sbLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchP2sbLib/PchP2sbLib.c new file mode 100644 index 0000000000..6e91828d64 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchP2sbLib/PchP2sbLib.c @@ -0,0 +1,337 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <PchAccess.h> + +/** + Get P2SB pci configuration register. (This is internal function) + It returns register at Offset of P2SB controller and size in 1byte/2bytes/4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchP2sbCfgGet ( + IN UINTN Offset, + IN UINTN Size, + OUT UINT32 *OutData + ) +{ + UINTN P2sbBase; + BOOLEAN DevicePresent; + + if ((Offset > 255) || + ((Offset & (Size - 1)) != 0)) + { + DEBUG ((DEBUG_ERROR, "PchP2sbCfgGet error. Invalid Offset: %x Size: %x", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + DevicePresent = (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF); + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + ASSERT (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF); + + switch (Size) { + case 4: + *(UINT32*)OutData = MmioRead32 (P2sbBase + Offset); + break; + case 2: + *(UINT16*)OutData = MmioRead16 (P2sbBase + Offset); + break; + case 1: + *(UINT8*) OutData = MmioRead8 (P2sbBase + Offset); + break; + default: + break; + } + + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + } + return EFI_SUCCESS; +} + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet32 ( + IN UINTN Offset, + OUT UINT32 *OutData + ) +{ + return PchP2sbCfgGet (Offset, 4, (UINT32*) OutData); +} + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet16 ( + IN UINTN Offset, + OUT UINT16 *OutData + ) +{ + return PchP2sbCfgGet (Offset, 2, (UINT32*) OutData); +} + +/** + Get P2SB pci configuration register. + It returns register at Offset of P2SB controller and size in 1byte. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgGet8 ( + IN UINTN Offset, + OUT UINT8 *OutData + ) +{ + return PchP2sbCfgGet (Offset, 1, (UINT32*) OutData); +} + +/** + Set P2SB pci configuration register. (This is internal function) + It programs register at Offset of P2SB controller and size in 1byte/2bytes/4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchP2sbCfgSet ( + IN UINTN Offset, + IN UINTN Size, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + UINTN P2sbBase; + BOOLEAN DevicePresent; + UINT32 Data32; + + if ((Offset > 255) || + ((Offset & (Size - 1)) != 0)) + { + DEBUG ((DEBUG_ERROR, "PchP2sbCfgSet error. Invalid Offset: %x Size: %x", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Data32 = 0; + + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + DevicePresent = (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF); + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + ASSERT (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF); + + switch (Size) { + case 4: + Data32 = MmioRead32 (P2sbBase + Offset); + Data32 &= AndData; + Data32 |= OrData; + MmioWrite32 (P2sbBase + Offset, (UINT32) Data32); + break; + case 2: + Data32 = MmioRead16 (P2sbBase + Offset); + Data32 &= AndData; + Data32 |= OrData; + MmioWrite16 (P2sbBase + Offset, (UINT16) Data32); + break; + case 1: + Data32 = MmioRead8 (P2sbBase + Offset); + Data32 &= AndData; + Data32 |= OrData; + MmioWrite8 (P2sbBase + Offset, (UINT8) Data32); + break; + default: + break; + } + + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + } + return EFI_SUCCESS; +} + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 4bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet32 ( + IN UINTN Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PchP2sbCfgSet (Offset, 4, AndData, OrData); +} + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 2bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet16 ( + IN UINTN Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PchP2sbCfgSet (Offset, 2, AndData, OrData); +} + +/** + Set P2SB pci configuration register. + It programs register at Offset of P2SB controller and size in 1bytes. + The Offset should not exceed 255 and must be aligned with size. + This function will be unavailable after P2SB is hidden by PSF. + + @param[in] Offset Register offset of P2SB controller. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchP2sbCfgSet8 ( + IN UINTN Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PchP2sbCfgSet (Offset, 1, AndData, OrData); +} + +/** + Hide P2SB device. + + @param[in] P2sbBase Pci base address of P2SB controller. + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchHideP2sb ( + IN UINTN P2sbBase + ) +{ + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, BIT0); + return EFI_SUCCESS; +} + +/** + Reveal P2SB device. + Also return the original P2SB status which is for Hidding P2SB or not after. + If OrgStatus is not NULL, then TRUE means P2SB is unhidden, + and FALSE means P2SB is hidden originally. + + @param[in] P2sbBase Pci base address of P2SB controller. + @param[out] OrgStatus Original P2SB hidding/unhidden status + + @retval EFI_SUCCESS Always return success. +**/ +EFI_STATUS +PchRevealP2sb ( + IN UINTN P2sbBase, + OUT BOOLEAN *OrgStatus + ) +{ + BOOLEAN DevicePresent; + + DevicePresent = (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF); + if (OrgStatus != NULL) { + *OrgStatus = DevicePresent; + } + if (!DevicePresent) { + MmioWrite8 (P2sbBase + R_PCH_P2SB_E0 + 1, 0); + } + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf new file mode 100644 index 0000000000..4f57152b2e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf @@ -0,0 +1,37 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPchP2sbLib
+ FILE_GUID = FB044F6F-5F9F-48AB-AE12-1C0B829C8AD7
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PchP2sbLib
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ MmPciLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+ PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+[Sources]
+ PchP2sbLib.c
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c new file mode 100644 index 0000000000..032349bd4e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c @@ -0,0 +1,459 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <PchAccess.h> +#include <Library/PchInfoLib.h> + +/** + Read PCR register. (This is internal function) + It returns PCR register and size in 1byte/2bytes/4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchPcrRead ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINTN Size, + OUT UINT32 *OutData + ) +{ + if ((Offset & (Size - 1)) != 0) { + DEBUG ((DEBUG_ERROR, "PchPcrRead error. Invalid Offset: %x Size: %x", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // @todo SKL PCH: check PID that not expected to use this routine, such as CAM_FLIS, CSME0 + // + + switch (Size) { + case 4: + *(UINT32*)OutData = MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); + break; + case 2: + *(UINT16*)OutData = MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); + break; + case 1: + *(UINT8*) OutData = MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); + break; + default: + break; + } + return EFI_SUCCESS; +} + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT32 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 4, (UINT32*) OutData); +} + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT16 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 2, (UINT32*) OutData); +} + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + @param[out] OutData Buffer of Output Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + OUT UINT8 *OutData + ) +{ + return PchPcrRead (Pid, Offset, 1, (UINT32*) OutData); +} + +BOOLEAN +PchPcrWriteMmioCheck ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset + ) +{ +DEBUG_CODE_BEGIN(); + PCH_SERIES PchSeries; + + PchSeries = GetPchSeries (); + // + // 1. USB2 AFE register must use SBI method + // + + // + // 2. GPIO unlock register field must use SBI method + // + if (Pid == PID_GPIOCOM0) { + if (((PchSeries == PchLp) && + ((Offset == R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_A_PADCFGLOCKTX) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_B_PADCFGLOCKTX))) || + ((PchSeries == PchH) && + ((Offset == R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX) || + (Offset == R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX)))) + { + return FALSE; + } + } + if (Pid == PID_GPIOCOM1) { + if (((PchSeries == PchLp) && + ((Offset == R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_C_PADCFGLOCKTX) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_D_PADCFGLOCKTX) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_E_PADCFGLOCKTX))) || + ((PchSeries == PchH) && + ((Offset == R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX) || + (Offset == R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX) || + (Offset == R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX) || + (Offset == R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX) || + (Offset == R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX) || + (Offset == R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX)))) + { + return FALSE; + } + } + if (Pid == PID_GPIOCOM2) { + if (((PchSeries == PchLp) && + ((Offset == R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPD_PADCFGLOCKTX))) || + ((PchSeries == PchH) && + ((Offset == R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX)))) + { + return FALSE; + } + } + if (Pid == PID_GPIOCOM3) { + if (((PchSeries == PchLp) && + ((Offset == R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_F_PADCFGLOCKTX) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCK) || + (Offset == R_PCH_LP_PCR_GPIO_GPP_G_PADCFGLOCKTX))) || + ((PchSeries == PchH) && + ((Offset == R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK) || + (Offset == R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX)))) + { + return FALSE; + } + } + // + // 3. CIO2 FLIS regsiter must use SBI method + // + + // + // 4. CSME0 based PCR should use the SBI method due to the FID requirement + // + if (Pid == PID_CSME0) { + return FALSE; + } +DEBUG_CODE_END(); + return TRUE; + +} + +/** + Write PCR register. (This is internal function) + It programs PCR register and size in 1byte/2bytes/4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Size Size for read. Must be 1 or 2 or 4. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +STATIC +EFI_STATUS +PchPcrWrite ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINTN Size, + IN UINT32 InData + ) +{ + if ((Offset & (Size - 1)) != 0) { + DEBUG ((DEBUG_ERROR, "PchPcrWrite error. Invalid Offset: %x Size: %x", Offset, Size)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } +DEBUG_CODE_BEGIN(); + if (!PchPcrWriteMmioCheck (Pid, Offset)) { + DEBUG ((DEBUG_ERROR, "PchPcrWrite error. Pid: %x Offset: %x should access through SBI interface", Pid, Offset)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } +DEBUG_CODE_END(); + + // + // Write the PCR register with provided data + // Then read back PCR register to prevent from back to back write. + // + switch (Size) { + case 4: + MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), (UINT32)InData); + break; + case 2: + MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), (UINT16)InData); + break; + case 1: + MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), (UINT8) InData); + break; + default: + break; + } + MmioRead32 (PCH_PCR_ADDRESS (PID_LPC, R_PCH_PCR_LPC_GCFD)); + + return EFI_SUCCESS; +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 InData + ) +{ + return PchPcrWrite (Pid, Offset, 4, InData); +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 InData + ) +{ + return PchPcrWrite (Pid, Offset, 2, InData); +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] InData Input Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 InData + ) +{ + return PchPcrWrite (Pid, Offset, 1, InData); +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + EFI_STATUS Status; + UINT32 Data32; + + Data32 = 0x00; + Status = PchPcrRead (Pid, Offset, 4, &Data32); + if (EFI_ERROR (Status)) { + return Status; + } + Data32 &= AndData; + Data32 |= OrData; + Status = PchPcrWrite (Pid, Offset, 4, Data32); + return Status; +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + EFI_STATUS Status; + UINT16 Data16; + + Data16 = 0x00; + Status = PchPcrRead (Pid, Offset, 2, (UINT32*) &Data16); + if (EFI_ERROR (Status)) { + return Status; + } + Data16 &= AndData; + Data16 |= OrData; + Status = PchPcrWrite (Pid, Offset, 2, Data16); + return Status; +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT16 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + EFI_STATUS Status; + UINT8 Data8; + + Status = PchPcrRead (Pid, Offset, 1, (UINT32*) &Data8); + if (EFI_ERROR (Status)) { + return Status; + } + Data8 &= AndData; + Data8 |= OrData; + Status = PchPcrWrite (Pid, Offset, 1, Data8); + return Status; +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf new file mode 100644 index 0000000000..c54dc2c4e2 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf @@ -0,0 +1,38 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcrLib
+FILE_GUID = 117C8D19-445B-46BF-B624-109F63709375
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcrLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+MmPciLib
+PchInfoLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+[Sources]
+PchPcrLib.c
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c new file mode 100644 index 0000000000..9796cb0561 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPmcLib/PchPmcLib.c @@ -0,0 +1,159 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <PchAccess.h> +#include <Library/PchCycleDecodingLib.h> +#include <Library/PchPmcLib.h> + +/** + Query PCH to determine the Pm Status + NOTE: + It's matter when did platform code use this library, since some status could be cleared by write one clear. + Therefore this funciton is not always return the same result in one boot. + It's suggested that platform code read this status in the beginning of post. + For the ColdBoot case, this function only returns one case of the cold boot. Some cold boot case might + depends on the power cycle scenario and should check with different condtion. + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Return TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ) +{ + UINTN PmcRegBase; + UINT32 PchPwrmBase; + UINT32 PmConA; + UINT32 PmConB; + UINT32 GblRst0; + + PmcRegBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + PchPwrmBaseGet (&PchPwrmBase); + + PmConA = MmioRead32 (PmcRegBase + R_PCH_PMC_GEN_PMCON_A); + PmConB = MmioRead32 (PmcRegBase + R_PCH_PMC_GEN_PMCON_B); + GblRst0 = MmioRead32 (PchPwrmBase + R_PCH_PWRM_124); + + switch(PmStatus){ + case PchWarmBoot: + + if (PmConA & B_PCH_PMC_GEN_PMCON_A_MEM_SR) { + return TRUE; + } + break; + + case PwrFlr: + if (PmConB & B_PCH_PMC_GEN_PMCON_B_PWR_FLR) { + return TRUE; + } + break; + + case PwrFlrSys: + if (GblRst0 & BIT12) { + return TRUE; + } + break; + + case PwrFlrPch: + if (GblRst0 & BIT11) { + return TRUE; + } + break; + + case PchColdBoot: + /// + /// Check following conditions for cold boot. + /// + if ((GblRst0 & BIT11) && // PCHPWR_FLR + (GblRst0 & BIT12) && // SYSPWR_FLR + (!(PmConA & B_PCH_PMC_GEN_PMCON_A_MEM_SR))) { + return TRUE; + } + break; + + default: + break; + } + + return FALSE; +} + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ) +{ + UINTN Data; + UINTN PmcBaseAddress; + + // + // Check if the CMOS battery is present + // Checks RTC_PWR_STS bit in the GEN_PMCON_3 register + // + PmcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + + Data = MmioRead32 (PmcBaseAddress + R_PCH_PMC_GEN_PMCON_B); + if ((Data & B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS) == 0) { + return TRUE; + } + return FALSE; +} + +/** + Funtion to check if DWR occurs + + @reval TRUE DWR occurs + @reval FALSE Normal boot flow +**/ +BOOLEAN +EFIAPI +PchIsDwrFlow ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 PchPwrmBase; + + Status = PchPwrmBaseGet (&PchPwrmBase); + ASSERT (PchPwrmBase != 0); + + if ((PchPwrmBase != 0) && + (MmioRead32 (PchPwrmBase + R_PCH_PWRM_HPR_CAUSE0) & B_PCH_PWRM_HPR_CAUSE0_GBL_TO_HOST)) { + return TRUE; + } else { + return FALSE; + } +} diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf new file mode 100644 index 0000000000..ffb37a199a --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf @@ -0,0 +1,38 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPmcLib
+FILE_GUID = 9D60C364-5086-41E3-BC9D-C62AB7233DBF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPmcLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+MmPciLib
+PchCycleDecodingLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+[Sources]
+PchPmcLib.c
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c new file mode 100644 index 0000000000..444b2822c7 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c @@ -0,0 +1,376 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Uefi/UefiBaseType.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/MmPciBaseLib.h> +#include <PchAccess.h> +#include <Library/PchP2sbLib.h> +#include <Library/PchSbiAccessLib.h> + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + + + return PchSbiExecutionEx ( Pid, + Offset, + Opcode, + Posted, + 0x000F, + 0x0000, + 0x0000, + Data32, + Response + ); +} + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back after done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + EFI_STATUS Status; + UINTN P2sbBase; + BOOLEAN P2sbOrgStatus; + UINTN Timeout; + UINT16 SbiStat; + + // + // Check opcode valid + // + switch (Opcode) { + case PciConfigRead: + case PciConfigWrite: + case PrivateControlRead: + case PrivateControlWrite: + case GpioLockUnlock: + break; + default: + return EFI_INVALID_PARAMETER; + break; + } + + P2sbOrgStatus = FALSE; + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + PchRevealP2sb (P2sbBase, &P2sbOrgStatus); + /// + /// BWG Section 2.2.1 + /// 1. Poll P2SB PCI offset D8h[0] = 0b + /// Make sure the previous opeartion is completed. + /// + Timeout = 0xFFFFFFF; + while (Timeout > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + Timeout--; + } + if (Timeout == 0) { + Status = EFI_DEVICE_ERROR; + goto ExitPchSbiExecutionEx; + } + // + // Initial Response status + // + *Response = SBI_INVALID_RESPONSE; + Status = EFI_SUCCESS; + SbiStat = 0; + /// + /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Port ID + /// + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIADDR, (UINT32) ((Pid << 24) | (UINT16)Offset)); + /// + /// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is expected to be 0 in SKL PCH. + /// + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR, (UINT32) RShiftU64 (Offset, 16)); + /// + /// 5. Set P2SB PCI offset D8h[15:8] = 00000110b for read + /// Set P2SB PCI offset D8h[15:8] = 00000111b for write + // + // Set SBISTAT[15:8] to the opcode passed in + // Set SBISTAT[7] to the posted passed in + // + MmioAndThenOr16 ( + (P2sbBase + R_PCH_P2SB_SBISTAT), + (UINT16) ~(B_PCH_P2SB_SBISTAT_OPCODE | B_PCH_P2SB_SBISTAT_POSTED), + (UINT16) ((Opcode << 8) | (Posted << 7)) + ); + /// + /// 6. Write P2SB PCI offset DAh[15:0] = F000h + /// + // + // Set RID[15:0] = Fbe << 12 | Bar << 8 | Fid + // + MmioWrite16 ( + (P2sbBase + R_PCH_P2SB_SBIRID), + (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF)) + ); + + switch (Opcode) { + case PciConfigWrite: + case PrivateControlWrite: + case GpioLockUnlock: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly + /// + MmioWrite32 ((P2sbBase + R_PCH_P2SB_SBIDATA), *Data32); + break; + default: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0, + /// because all D0-DFh register range must be touched in SKL PCH + /// for a successful SBI transaction. + /// + MmioWrite32 ((P2sbBase + R_PCH_P2SB_SBIDATA), 0); + break; + } + /// + /// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] = 0b + /// + // + // Set SBISTAT[0] = 1b, trigger the SBI operation + // + MmioOr16 (P2sbBase + R_PCH_P2SB_SBISTAT, (UINT16) B_PCH_P2SB_SBISTAT_INITRDY); + // + // Poll SBISTAT[0] = 0b, Polling for Busy bit + // + Timeout = 0xFFFFFFF; + while (Timeout > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + Timeout--; + } + if (Timeout == 0) { + // + // If timeout, it's fatal error. + // + Status = EFI_DEVICE_ERROR; + } else { + /// + /// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction + /// + *Response = (UINT8)((SbiStat & B_PCH_P2SB_SBISTAT_RESPONSE) >> N_PCH_P2SB_SBISTAT_RESPONSE); + if (*Response == SBI_SUCCESSFUL) { + switch (Opcode) { + case PciConfigRead: + case PrivateControlRead: + /// + /// 9. Read P2SB PCI offset D4h[31:0] for SBI data + /// + *Data32 = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIDATA); + break; + default: + break; + } + Status = EFI_SUCCESS; + } else { + Status = EFI_DEVICE_ERROR; + } + } + +ExitPchSbiExecutionEx: + if (!P2sbOrgStatus) { + PchHideP2sb (P2sbBase); + } + return Status; +} + +/** + This function saves all PCH SBI registers. + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in, out] PchSbiRegister Structure for saving the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterSave ( + IN OUT PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ) +{ + UINTN P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + if (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) { + return EFI_DEVICE_ERROR; + } + // + // Make sure it's not busy. + // Poll SBISTAT[0] = 0b + // + Timeout = 0xFFFFFFF; + while ((Timeout--) > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + } + if (Timeout == 0) { + return EFI_DEVICE_ERROR; + } + // + // Save original SBI registers + // + PchSbiRegister->SbiAddr = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIADDR); + PchSbiRegister->SbiExtAddr = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR); + PchSbiRegister->SbiData = MmioRead32 (P2sbBase + R_PCH_P2SB_SBIDATA); + PchSbiRegister->SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + PchSbiRegister->SbiRid = MmioRead16 (P2sbBase + R_PCH_P2SB_SBIRID); + + return EFI_SUCCESS; +} + +/** + This function restores all PCH SBI registers + The save and restore operations must be done while using the PchSbiExecution inside SMM. + It prevents the racing condition of PchSbiExecution re-entry between POST and SMI. + Before using this function, make sure the P2SB is not hidden. + + @param[in] PchSbiRegister Structure for restoring the registers + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Device is hidden. +**/ +EFI_STATUS +EFIAPI +PchSbiRegisterRestore ( + IN PCH_SBI_REGISTER_STRUCT *PchSbiRegister + ) +{ + UINTN P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + P2sbBase = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB + ); + if (MmioRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) { + return EFI_DEVICE_ERROR; + } + // + // Make sure it's not busy. + // Poll SBISTAT[0] = 0b + // + Timeout = 0xFFFFFFF; + while ((Timeout--) > 0){ + SbiStat = MmioRead16 (P2sbBase + R_PCH_P2SB_SBISTAT); + if ((SbiStat & B_PCH_P2SB_SBISTAT_INITRDY) == 0) { + break; + } + } + if (Timeout == 0) { + return EFI_DEVICE_ERROR; + } + // + // Restore original SBI registers + // + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIADDR , PchSbiRegister->SbiAddr); + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIEXTADDR, PchSbiRegister->SbiExtAddr); + MmioWrite32 (P2sbBase + R_PCH_P2SB_SBIDATA , PchSbiRegister->SbiData); + MmioWrite16 (P2sbBase + R_PCH_P2SB_SBISTAT , PchSbiRegister->SbiStat); + MmioWrite16 (P2sbBase + R_PCH_P2SB_SBIRID , PchSbiRegister->SbiRid); + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf new file mode 100644 index 0000000000..4f6d2a8a21 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf @@ -0,0 +1,38 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSbiAccessLib
+FILE_GUID = 96ECB0FB-A975-4DC8-B88A-D90C3378CE87
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchSbiAccessLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+MmPciLib
+PchP2sbLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+[Sources]
+PchSbiAccessLib.c
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PchPrintPolicy.c b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PchPrintPolicy.c new file mode 100644 index 0000000000..a555ff9c6e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PchPrintPolicy.c @@ -0,0 +1,736 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyLibrary.h" + +/** + Print PCH_USB_CONFIG and serial out. + + @param[in] UsbConfig Pointer to a PCH_USB_CONFIG that provides the platform setting + +**/ +VOID +PchPrintUsbConfig ( + IN CONST PCH_USB_CONFIG *UsbConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH USB Config ------------------\n")); + DEBUG ((DEBUG_INFO, " UsbPrecondition= %x\n", UsbConfig->UsbPrecondition)); + DEBUG ((DEBUG_INFO, " DisableComplianceMode= %x\n", UsbConfig->DisableComplianceMode)); + + for (i = 0; i < GetPchUsbMaxPhysicalPortNum (); i++) { + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Enabled= %x\n", i, UsbConfig->PortUsb20[i].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].OverCurrentPin= OC%x\n", i, UsbConfig->PortUsb20[i].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Petxiset= %x\n", i, UsbConfig->PortUsb20[i].Afe.Petxiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Txiset= %x\n", i, UsbConfig->PortUsb20[i].Afe.Txiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Predeemp= %x\n", i, UsbConfig->PortUsb20[i].Afe.Predeemp)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Pehalfbit= %x\n", i, UsbConfig->PortUsb20[i].Afe.Pehalfbit)); + } + + for (i = 0; i < GetPchXhciMaxUsb3PortNum (); i++) { + DEBUG ((DEBUG_INFO, " PortUsb30[%d] Enabled= %x\n", i, UsbConfig->PortUsb30[i].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].OverCurrentPin= OC%x\n", i, UsbConfig->PortUsb30[i].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmph = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDeEmph)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmphEnable = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmp = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmpEnable = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDownscaleAmpEnable)); + } + + DEBUG ((DEBUG_INFO, " XdciConfig.Enable= %x\n", UsbConfig->XdciConfig.Enable)); + + for (i = 0; i < PCH_XHCI_MAX_SSIC_PORT_COUNT; i++) { + DEBUG ((DEBUG_INFO, " SsicPort[%d].Enable = %x\n", i, UsbConfig->SsicConfig.SsicPort[i].Enable)); + } + +} + +/** + Print PCH_PCIE_CONFIG and serial out. + + @param[in] PcieConfig Pointer to a PCH_PCIE_CONFIG that provides the platform setting + @param[in] HsioPcieConfig Pointer to a PCH_HSIO_PCIE_CONFIG that provides the platform setting + +**/ +VOID +PchPrintPcieConfig ( + IN CONST PCH_PCIE_CONFIG *PcieConfig, + IN CONST PCH_HSIO_PCIE_CONFIG *HsioPcieConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config ------------------\n")); + for (i = 0; i < GetPchMaxPciePortNum (); i++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] Enabled= %x\n", i, PcieConfig->RootPort[i].Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug= %x\n", i, PcieConfig->RootPort[i].HotPlug)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci= %x\n", i, PcieConfig->RootPort[i].PmSci)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ExtSync= %x\n", i, PcieConfig->RootPort[i].ExtSync)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqSupported= %x\n", i, PcieConfig->RootPort[i].ClkReqSupported)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqNumber= %x\n", i, PcieConfig->RootPort[i].ClkReqNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqDetect= %x\n", i, PcieConfig->RootPort[i].ClkReqDetect)); + DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport= %x\n", i, PcieConfig->RootPort[i].UnsupportedRequestReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport= %x\n", i, PcieConfig->RootPort[i].FatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport= %x\n", i, PcieConfig->RootPort[i].NoFatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport= %x\n", i, PcieConfig->RootPort[i].CorrectableErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError= %x\n", i, PcieConfig->RootPort[i].SystemErrorOnFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError= %x\n", i, PcieConfig->RootPort[i].SystemErrorOnNonFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError= %x\n", i, PcieConfig->RootPort[i].SystemErrorOnCorrectableError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] MaxPayload= %x\n", i, PcieConfig->RootPort[i].MaxPayload)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled= %x\n", i, PcieConfig->RootPort[i].AcsEnabled)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting= %x\n", i, PcieConfig->RootPort[i].AdvancedErrorReporting)); + DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing= %x\n", i, PcieConfig->RootPort[i].TransmitterHalfSwing)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed= %x\n", i, PcieConfig->RootPort[i].PcieSpeed)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3EqPh3Method= %x\n", i, PcieConfig->RootPort[i].Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber= %x\n", i, PcieConfig->RootPort[i].PhysicalSlotNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout= %x\n", i, PcieConfig->RootPort[i].CompletionTimeout)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm= %x\n", i, PcieConfig->RootPort[i].Aspm)); + DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates= %x\n", i, PcieConfig->RootPort[i].L1Substates)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable= %x\n", i, PcieConfig->RootPort[i].LtrEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock= %x\n", i, PcieConfig->RootPort[i].LtrConfigLock)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency= %x\n", i, PcieConfig->RootPort[i].LtrMaxSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency= %x\n", i, PcieConfig->RootPort[i].LtrMaxNoSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode= %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier= %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue= %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode= %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier= %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue= %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale= %x\n", i, PcieConfig->RootPort[i].SlotPowerLimitScale)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue= %x\n", i, PcieConfig->RootPort[i].SlotPowerLimitValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Uptp= %x\n", i, PcieConfig->RootPort[i].Uptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Dptp= %x\n", i, PcieConfig->RootPort[i].Dptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtleEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioRxSetCtleEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtle= %x\n", i, HsioPcieConfig->Lane[i].HsioRxSetCtle)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmpEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmp= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmpEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmp= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmpEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmp= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmphEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmph= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5Enable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph3p5Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph3p5)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0Enable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph6p0Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph6p0)); + + } + DEBUG ((DEBUG_INFO, " EnablePort8xhDecode= %x\n", PcieConfig->EnablePort8xhDecode)); + DEBUG ((DEBUG_INFO, " PchPciePort8xhDecodePortIndex= %x\n", PcieConfig->PchPciePort8xhDecodePortIndex)); + DEBUG ((DEBUG_INFO, " DisableRootPortClockGating= %x\n", PcieConfig->DisableRootPortClockGating)); + DEBUG ((DEBUG_INFO, " EnablePeerMemoryWrite= %x\n", PcieConfig->EnablePeerMemoryWrite)); + DEBUG ((DEBUG_INFO, " AllowNoLtrIccPllShutdown= %x\n", PcieConfig->AllowNoLtrIccPllShutdown)); + DEBUG ((DEBUG_INFO, " ComplianceTestMode= %x\n", PcieConfig->ComplianceTestMode)); + DEBUG ((DEBUG_INFO, " RpFunctionSwap= %x\n", PcieConfig->RpFunctionSwap)); +} + +/** + Print PCH_PCIE_CONFIG2 and serial out. + + @param[in] PcieConfig2 Pointer to a PCH_PCIE_CONFIG2 that provides the platform setting + +**/ +VOID +PchPrintPcieConfig2 ( + IN CONST PCH_PCIE_CONFIG2 *PcieConfig2 + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config2 -----------------\n")); + for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + DEBUG ((DEBUG_INFO, " SwEqCoeffCm[%d] = %x\n", Index, PcieConfig2->SwEqCoeffList[Index].Cm)); + DEBUG ((DEBUG_INFO, " SwEqCoeffCp[%d] = %x\n", Index, PcieConfig2->SwEqCoeffList[Index].Cp)); + } +} + +/** + Print PCH_SATA_CONFIG and serial out. + + @param[in] SataConfig Pointer to a PCH_SATA_CONFIG that provides the platform setting + @param[in] HsioSataConfig Pointer to a PCH_HSIO_SATA_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSataConfig ( + IN CONST PCH_SATA_CONFIG *SataConfig, + IN VOID *HsioSataConfigPtr, + IN UINT8 SataControllerNo + ) +{ + UINT32 i; + + UINT32 MaxSataPortNum; + PCH_HSIO_SATA_CONFIG *HsioSataConfig; + + HsioSataConfig = HsioSataConfigPtr; + + if (SataControllerNo == PCH_SATA_FIRST_CONTROLLER) { + DEBUG ((DEBUG_INFO, "------------------- PCH Primary SATA Config ------------------\n")); + MaxSataPortNum = GetPchMaxSataPortNum (); + } else { + DEBUG ((DEBUG_INFO, "------------------ PCH Secondary SATA Config ------------------\n")); + MaxSataPortNum = GetPchMaxsSataPortNum (); + } + DEBUG ((DEBUG_INFO, " Enable= %x\n", SataConfig->Enable)); + DEBUG ((DEBUG_INFO, " SataMode= %x\n", SataConfig->SataMode)); + + + for (i = 0; i < MaxSataPortNum; i++) { + DEBUG ((DEBUG_INFO, " PortSettings[%d] Enabled= %x\n", i, SataConfig->PortSettings[i].Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HotPlug= %x\n", i, SataConfig->PortSettings[i].HotPlug)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] InterlockSw= %x\n", i, SataConfig->PortSettings[i].InterlockSw)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] External= %x\n", i, SataConfig->PortSettings[i].External)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SpinUp= %x\n", i, SataConfig->PortSettings[i].SpinUp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SolidStateDrive= %x\n", i, SataConfig->PortSettings[i].SolidStateDrive)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DevSlp= %x\n", i, SataConfig->PortSettings[i].DevSlp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] EnableDitoConfig= %x\n", i, SataConfig->PortSettings[i].EnableDitoConfig)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DmVal= %x\n", i, SataConfig->PortSettings[i].DmVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DitoVal= %x\n", i, SataConfig->PortSettings[i].DitoVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] ZpOdd= %x\n", i, SataConfig->PortSettings[i].ZpOdd)); + + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen1EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen1EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen2EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen2EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen3EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen3EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DeEmph)); + } + + DEBUG ((DEBUG_INFO, " RaidAlternateId= %x\n", SataConfig->Rst.RaidAlternateId)); + DEBUG ((DEBUG_INFO, " Raid0= %x\n", SataConfig->Rst.Raid0)); + DEBUG ((DEBUG_INFO, " Raid1= %x\n", SataConfig->Rst.Raid1)); + DEBUG ((DEBUG_INFO, " Raid10= %x\n", SataConfig->Rst.Raid10)); + DEBUG ((DEBUG_INFO, " Raid5= %x\n", SataConfig->Rst.Raid5)); + DEBUG ((DEBUG_INFO, " Irrt= %x\n", SataConfig->Rst.Irrt)); + DEBUG ((DEBUG_INFO, " OromUiBanner= %x\n", SataConfig->Rst.OromUiBanner)); + DEBUG ((DEBUG_INFO, " OromUiDelay= %x\n", SataConfig->Rst.OromUiDelay)); + DEBUG ((DEBUG_INFO, " HddUnlock= %x\n", SataConfig->Rst.HddUnlock)); + DEBUG ((DEBUG_INFO, " LedLocate= %x\n", SataConfig->Rst.LedLocate)); + DEBUG ((DEBUG_INFO, " IrrtOnly= %x\n", SataConfig->Rst.IrrtOnly)); + DEBUG ((DEBUG_INFO, " SmartStorage= %x\n", SataConfig->Rst.SmartStorage)); + + DEBUG ((DEBUG_INFO, " SpeedSupport= %x\n", SataConfig->SpeedLimit)); + DEBUG ((DEBUG_INFO, " eSATASpeedLimit= %x\n", SataConfig->eSATASpeedLimit)); + DEBUG ((DEBUG_INFO, " TestMode= %x\n", SataConfig->TestMode)); + DEBUG ((DEBUG_INFO, " SalpSupport= %x\n", SataConfig->SalpSupport)); + DEBUG ((DEBUG_INFO, " PwrOptEnable= %x\n", SataConfig->PwrOptEnable)); + + for (i = 0; i < PCH_MAX_RST_PCIE_STORAGE_CR; i++) { + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].Enable = %x\n", i, SataConfig->RstPcieStorageRemap[i].Enable)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].RstPcieStoragePort = %x\n", i, SataConfig->RstPcieStorageRemap[i].RstPcieStoragePort)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].DeviceResetDelay = %x\n", i, SataConfig->RstPcieStorageRemap[i].DeviceResetDelay)); + } +} + +/** + Print PCH_IOAPIC_CONFIG and serial out. + + @param[in] IoApicConfig Pointer to a PCH_IOAPIC_CONFIG that provides the platform setting + +**/ +VOID +PchPrintIoApicConfig ( + IN CONST PCH_IOAPIC_CONFIG *IoApicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH IOAPIC Config ------------------\n")); + DEBUG ((DEBUG_INFO, " BdfValid= %x\n", IoApicConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber= %x\n", IoApicConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber= %x\n", IoApicConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber= %x\n", IoApicConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " IoApicId= %x\n", IoApicConfig->IoApicId)); + DEBUG ((DEBUG_INFO, " ApicRangeSelect= %x\n", IoApicConfig->ApicRangeSelect)); + DEBUG ((DEBUG_INFO, " IoApicEntry24_119= %x\n", IoApicConfig->IoApicEntry24_119)); +} + +/** + Print PCH_HPET_CONFIG and serial out. + + @param[in] HpetConfig Pointer to a PCH_HPET_CONFIG that provides the platform setting + +**/ +VOID +PchPrintHpetConfig ( + IN CONST PCH_HPET_CONFIG *HpetConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HPET Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable %x\n", HpetConfig->Enable)); + DEBUG ((DEBUG_INFO, " BdfValid %x\n", HpetConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber %x\n", HpetConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber %x\n", HpetConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber %x\n", HpetConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " Base %x\n", HpetConfig->Base)); +} + +/** + Print PCH_LOCK_DOWN_CONFIG and serial out. + + @param[in] LockDownConfig Pointer to a PCH_LOCK_DOWN_CONFIG that provides the platform setting + +**/ +VOID +PchPrintLockDownConfig ( + IN CONST PCH_LOCK_DOWN_CONFIG *LockDownConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH Lock Down Config ------------------\n")); + DEBUG ((DEBUG_INFO, " GlobalSmi= %x\n", LockDownConfig->GlobalSmi)); + DEBUG ((DEBUG_INFO, " BiosInterface= %x\n", LockDownConfig->BiosInterface)); + DEBUG ((DEBUG_INFO, " RtcLock= %x\n", LockDownConfig->RtcLock)); + DEBUG ((DEBUG_INFO, " BiosLock= %x\n", LockDownConfig->BiosLock)); + DEBUG ((DEBUG_INFO, " SpiEiss= %x\n", LockDownConfig->SpiEiss)); +} + +/** + Print PCH_SMBUS_CONFIG and serial out. + + @param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSmbusConfig ( + IN CONST PCH_SMBUS_CONFIG *SmbusConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable= %x\n", SmbusConfig->Enable)); + DEBUG ((DEBUG_INFO, " ArpEnable= %x\n", SmbusConfig->ArpEnable)); + DEBUG ((DEBUG_INFO, " DynamicPowerGating= %x\n", SmbusConfig->DynamicPowerGating)); + DEBUG ((DEBUG_INFO, " SmbusIoBase= %x\n", SmbusConfig->SmbusIoBase)); + DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses= %x\n", SmbusConfig->NumRsvdSmbusAddresses)); + DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable= {")); + for (i = 0; i < SmbusConfig->NumRsvdSmbusAddresses; ++i) { + DEBUG ((DEBUG_INFO, " %02xh", SmbusConfig->RsvdSmbusAddressTable[i])); + } + DEBUG ((DEBUG_INFO, " }\n")); +} + +/** + Print PCH_HDAUDIO_CONFIG and serial out. + + @param[in] HdaConfig Pointer to a PCH_HDAUDIO_CONFIG that provides the platform setting + +**/ +VOID +PchPrintHdAudioConfig ( + IN CONST PCH_HDAUDIO_CONFIG *HdaConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HD-Audio Config ------------------\n")); + DEBUG ((DEBUG_INFO, " HDA Enable = %x\n", HdaConfig->Enable)); + DEBUG ((DEBUG_INFO, " DSP Enable = %x\n", HdaConfig->DspEnable)); + DEBUG ((DEBUG_INFO, " DSP UAA Compliance = %x\n", HdaConfig->DspUaaCompliance)); + DEBUG ((DEBUG_INFO, " iDisp Codec Disconnect = %x\n", HdaConfig->IDispCodecDisconnect)); + DEBUG ((DEBUG_INFO, " Pme = %x\n", HdaConfig->Pme)); + DEBUG ((DEBUG_INFO, " I/O Buffer Ownership = %x\n", HdaConfig->IoBufferOwnership)); + DEBUG ((DEBUG_INFO, " I/O Buffer Voltage = %x\n", HdaConfig->IoBufferVoltage)); + DEBUG ((DEBUG_INFO, " VC Type = %x\n", HdaConfig->VcType)); + DEBUG ((DEBUG_INFO, " HD-A Link Frequency = %x\n", HdaConfig->HdAudioLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link Frequency = %x\n", HdaConfig->IDispLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link T-Mode = %x\n", HdaConfig->IDispLinkTmode)); + DEBUG ((DEBUG_INFO, " DSP Endpoint DMIC = %x\n", HdaConfig->DspEndpointDmic)); + DEBUG ((DEBUG_INFO, " DSP Endpoint I2S = %x\n", HdaConfig->DspEndpointI2s)); + DEBUG ((DEBUG_INFO, " DSP Endpoint BT = %x\n", HdaConfig->DspEndpointBluetooth)); + DEBUG ((DEBUG_INFO, " DSP Feature Mask = %x\n", HdaConfig->DspFeatureMask)); + DEBUG ((DEBUG_INFO, " DSP PP Module Mask = %x\n", HdaConfig->DspPpModuleMask)); + DEBUG ((DEBUG_INFO, " ResetWaitTimer = %x\n", HdaConfig->ResetWaitTimer)); +} + +/** + Print PCH_PM_CONFIG and serial out. + + @param[in] PmConfig Pointer to a PCH_PM_CONFIG that provides the platform setting + +**/ +VOID +PchPrintPmConfig ( + IN CONST PCH_PM_CONFIG *PmConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH PM Config ------------------\n")); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeWakeSts = %x\n", PmConfig->PowerResetStatusClear.MeWakeSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHrstColdSts = %x\n", PmConfig->PowerResetStatusClear.MeHrstColdSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHrstWarmSts = %x\n", PmConfig->PowerResetStatusClear.MeHrstWarmSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHostPowerDn = %x\n", PmConfig->PowerResetStatusClear.MeHostPowerDn)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear WolOvrWkSts = %x\n", PmConfig->PowerResetStatusClear.WolOvrWkSts)); + + DEBUG ((DEBUG_INFO, " WakeConfig PmeB0S5Dis = %x\n", PmConfig->WakeConfig.PmeB0S5Dis)); + DEBUG ((DEBUG_INFO, " WakeConfig WolEnableOverride = %x\n", PmConfig->WakeConfig.WolEnableOverride)); + DEBUG ((DEBUG_INFO, " WakeConfig LanWakeFromDeepSx = %x\n", PmConfig->WakeConfig.LanWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig PcieWakeFromDeepSx = %x\n", PmConfig->WakeConfig.PcieWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanEnable = %x\n", PmConfig->WakeConfig.WoWlanEnable)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanDeepSxEnable = %x\n", PmConfig->WakeConfig.WoWlanDeepSxEnable)); + + DEBUG ((DEBUG_INFO, " PchDeepSxPol = %x\n", PmConfig->PchDeepSxPol)); + DEBUG ((DEBUG_INFO, " PchSlpS3MinAssert = %x\n", PmConfig->PchSlpS3MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpS4MinAssert = %x\n", PmConfig->PchSlpS4MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpSusMinAssert = %x\n", PmConfig->PchSlpSusMinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpAMinAssert = %x\n", PmConfig->PchSlpAMinAssert)); + DEBUG ((DEBUG_INFO, " PciClockRun = %x\n", PmConfig->PciClockRun)); + DEBUG ((DEBUG_INFO, " SlpStrchSusUp = %x\n", PmConfig->SlpStrchSusUp)); + DEBUG ((DEBUG_INFO, " SlpLanLowDc = %x\n", PmConfig->SlpLanLowDc)); + DEBUG ((DEBUG_INFO, " PwrBtnOverridePeriod = %x\n", PmConfig->PwrBtnOverridePeriod)); + DEBUG ((DEBUG_INFO, " DisableEnergyReport = %x\n", PmConfig->DisableEnergyReport)); + DEBUG ((DEBUG_INFO, " DisableDsxAcPresentPulldown = %x\n", PmConfig->DisableDsxAcPresentPulldown)); + DEBUG ((DEBUG_INFO, " PmcReadDisable = %x\n", PmConfig->PmcReadDisable)); + DEBUG ((DEBUG_INFO, " PchPwrCycDur = %x\n", PmConfig->PchPwrCycDur)); + DEBUG ((DEBUG_INFO, " PciePllSsc = %x\n", PmConfig->PciePllSsc)); + DEBUG ((DEBUG_INFO, " CapsuleResetType = %x\n", PmConfig->CapsuleResetType)); + DEBUG ((DEBUG_INFO, " DisableNativePowerButton = %x\n", PmConfig->DisableNativePowerButton)); + DEBUG ((DEBUG_INFO, " SlpS0Enabled = %x\n", PmConfig->SlpS0Enable)); +} + +/** + Print PCH_DMI_CONFIG and serial out. + + @param[in] DmiConfig Pointer to a PCH_DMI_CONFIG that provides the platform setting + +**/ +VOID +PchPrintDmiConfig ( + IN CONST PCH_DMI_CONFIG *DmiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DMI Config ------------------\n")); + DEBUG ((DEBUG_INFO, " DmiAspm= %x\n", DmiConfig->DmiAspm)); + DEBUG ((DEBUG_INFO, " PwrOptEnable= %x\n", DmiConfig->PwrOptEnable)); + +} + +/** + Print PCH_LPC_SIRQ_CONFIG and serial out. + + @param[in] SerialIrqConfig Pointer to a PCH_LPC_SIRQ_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSerialIrqConfig ( + IN CONST PCH_LPC_SIRQ_CONFIG *SerialIrqConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC SIRQ Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SirqEnable= %x\n", SerialIrqConfig->SirqEnable)); + DEBUG ((DEBUG_INFO, " SirqMode= %x\n", SerialIrqConfig->SirqMode)); + DEBUG ((DEBUG_INFO, " StartFramePulse= %x\n", SerialIrqConfig->StartFramePulse)); +} + +/** + Print PCH_THERMAL_CONFIG and serial out. + + @param[in] ThermalConfig Pointer to a PCH_THERMAL_CONFIG that provides the platform setting + +**/ +VOID +PchPrintThermalConfig ( + IN CONST PCH_THERMAL_CONFIG *ThermalConfig + ) +{ + UINTN i; + + DEBUG ((DEBUG_INFO, "------------------ PCH Thermal Config ------------------\n")); + DEBUG ((DEBUG_INFO, " TsmicLock= %x\n", ThermalConfig->TsmicLock)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T0Level %x centigrade degree\n", ThermalConfig->ThermalThrottling.TTLevels.T0Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T1Level %x centigrade degree\n", ThermalConfig->ThermalThrottling.TTLevels.T1Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T2Level %x centigrade degree\n", ThermalConfig->ThermalThrottling.TTLevels.T2Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTEnable %x\n", ThermalConfig->ThermalThrottling.TTLevels.TTEnable)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTState13Enable %x\n", ThermalConfig->ThermalThrottling.TTLevels.TTState13Enable)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTLock %x\n", ThermalConfig->ThermalThrottling.TTLevels.TTLock)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels SuggestedSetting %x\n", ThermalConfig->ThermalThrottling.TTLevels.SuggestedSetting)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels PchCrossThrottling %x\n", ThermalConfig->ThermalThrottling.TTLevels.PchCrossThrottling)); + + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC DmiTsawEn %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.DmiTsawEn)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS0TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS0TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS1TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS1TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS2TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS2TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS3TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS3TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC SuggestedSetting %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T1M %x\n", ThermalConfig->ThermalThrottling.SataTT.P0T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T2M %x\n", ThermalConfig->ThermalThrottling.SataTT.P0T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T3M %x\n", ThermalConfig->ThermalThrottling.SataTT.P0T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0TDisp %x\n", ThermalConfig->ThermalThrottling.SataTT.P0TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0Tinact %x\n", ThermalConfig->ThermalThrottling.SataTT.P0Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0TDispFinit %x\n", ThermalConfig->ThermalThrottling.SataTT.P0TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T1M %x\n", ThermalConfig->ThermalThrottling.SataTT.P1T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T2M %x\n", ThermalConfig->ThermalThrottling.SataTT.P1T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T3M %x\n", ThermalConfig->ThermalThrottling.SataTT.P1T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1TDisp %x\n", ThermalConfig->ThermalThrottling.SataTT.P1TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1Tinact %x\n", ThermalConfig->ThermalThrottling.SataTT.P1Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1TDispFinit %x\n", ThermalConfig->ThermalThrottling.SataTT.P1TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT SuggestedSetting %x\n", ThermalConfig->ThermalThrottling.SataTT.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " MemoryThrottling Enable= %x\n", ThermalConfig->MemoryThrottling.Enable)); + for (i = 0; i < MaxTsGpioPin; i++) { + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PmsyncEnable= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].PmsyncEnable)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting C0TransmitEnable= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].C0TransmitEnable)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PinSelection= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].PinSelection)); + } + DEBUG ((DEBUG_INFO, " PchHotLevel = %x\n", ThermalConfig->PchHotLevel)); + DEBUG ((DEBUG_INFO, " ThermalDeviceEnable %x\n", ThermalConfig->ThermalDeviceEnable)); +} + +/** + Print PCH_GENERAL_CONFIG and serial out. + + @param[in] PchConfig Pointer to a PCH_GENERAL_CONFIG that provides the platform setting + +**/ +VOID +PchPrintGeneralConfig ( + IN CONST PCH_GENERAL_CONFIG *PchConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH General Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SubSystemVendorId= %x\n", PchConfig->SubSystemVendorId)); + DEBUG ((DEBUG_INFO, " SubSystemId= %x\n", PchConfig->SubSystemId)); + DEBUG ((DEBUG_INFO, " Crid= %x\n", PchConfig->Crid)); +} + +/** + Print PCH_LAN_CONFIG and serial out. + + @param[in] LanConfig Pointer to a PCH_LAN_CONFIG that provides the platform setting + +**/ +VOID +PchPrintLanConfig ( + IN CONST PCH_LAN_CONFIG *LanConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LAN Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable= %x\n", LanConfig->Enable)); + DEBUG ((DEBUG_INFO, " K1OffEnable= %x\n", LanConfig->K1OffEnable)); + DEBUG ((DEBUG_INFO, " ClkReqSupported= %d\n", LanConfig->ClkReqSupported)); + DEBUG ((DEBUG_INFO, " ClkReqNumber= %d\n", LanConfig->ClkReqNumber)); +} + + +/** + Print PCH_INTERRUPT_CONFIG and serial out + + @param[in] InterruptConfig Pointer to Interrupt Configuration structure + +**/ +VOID +PchPrintInterruptConfig ( + IN CONST PCH_INTERRUPT_CONFIG *InterruptConfig + ) +{ + UINTN i; + // + // Print interrupt information + // + DEBUG ((DEBUG_INFO, "------------------ PCH Interrupt Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Interrupt assignment:\n")); + DEBUG ((DEBUG_INFO, " Dxx:Fx INTx IRQ\n")); + for (i = 0; i < InterruptConfig->NumOfDevIntConfig; i++) { + DEBUG ((DEBUG_INFO, " D%02d:F%d %d %03d\n", + InterruptConfig->DevIntConfig[i].Device, + InterruptConfig->DevIntConfig[i].Function, + InterruptConfig->DevIntConfig[i].IntX, + InterruptConfig->DevIntConfig[i].Irq)); + } + DEBUG ((DEBUG_INFO, " Legacy PIC interrupt routing:\n")); + DEBUG ((DEBUG_INFO, " PIRQx IRQx\n")); + for (i = 0; i < PCH_MAX_PXRC_CONFIG; i++) { + DEBUG ((DEBUG_INFO, " PIRQ%c -> IRQ%d\n", i + 65, InterruptConfig->PxRcConfig[i])); + } + DEBUG ((DEBUG_INFO, " Other interrupt configuration:\n")); + DEBUG ((DEBUG_INFO, " GpioIrqRoute= %d\n", InterruptConfig->GpioIrqRoute)); + DEBUG ((DEBUG_INFO, " SciIrqSelect= %d\n", InterruptConfig->SciIrqSelect)); + DEBUG ((DEBUG_INFO, " TcoIrqEnable= %d\n", InterruptConfig->TcoIrqEnable)); + DEBUG ((DEBUG_INFO, " TcoIrqSelect= %d\n", InterruptConfig->TcoIrqSelect)); +} + + +/** + Print PCH_FLASH_PROTECTION_CONFIG and serial out. + + @param[in] FlashProtectConfig Pointer to a PCH_FLASH_PROTECTION_CONFIG that provides the platform setting + +**/ +VOID +PchPrintFlashProtectionConfig ( + IN CONST PCH_FLASH_PROTECTION_CONFIG *FlashProtectConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH Flash Protection Config ------------------\n")); + for (i = 0; i < PCH_FLASH_PROTECTED_RANGES; ++i) { + DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].WriteProtectionEnable)); + DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].ReadProtectionEnable)); + DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].ProtectedRangeLimit)); + DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].ProtectedRangeBase)); + } +} + +/** + Print PCH_WDT_CONFIG and serial out. + + @param[in] WdtConfig Pointer to a PCH_WDT_CONFIG that provides the platform setting + +**/ +VOID +PchPrintWdtConfig ( + IN CONST PCH_WDT_CONFIG *WdtConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH WDT Config ------------------\n")); + DEBUG ((DEBUG_INFO, "DisableAndLock= %x\n", WdtConfig->DisableAndLock)); +} + +/** + Print PCH_P2SB_CONFIG and serial out. + + @param[in] P2sbConfig Pointer to a PCH_P2SB_CONFIG that provides the platform setting + +**/ +VOID +PchPrintP2sbConfig ( + IN CONST PCH_P2SB_CONFIG *P2sbConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH P2SB Config ------------------\n")); + DEBUG ((DEBUG_INFO, "SbiUnlock= %x\n", P2sbConfig->SbiUnlock)); + DEBUG ((DEBUG_INFO, "PsfUnlock= %x\n", P2sbConfig->PsfUnlock)); +} + +/** + Print PCH_DCI_CONFIG and serial out. + + @param[in] DciConfig Pointer to a PCH_DCI_CONFIG that provides the platform setting + +**/ +VOID +PchPrintDciConfig ( + IN CONST PCH_DCI_CONFIG *DciConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DCI Config ------------------\n")); + DEBUG ((DEBUG_INFO, "DciEn= %x\n", DciConfig->DciEn)); + DEBUG ((DEBUG_INFO, "DciAutoDetect= %x\n", DciConfig->DciAutoDetect)); +} + +/** + Print PCH_LPC_CONFIG and serial out. + + @param[in] LpcConfig Pointer to a PCH_LPC_CONFIG that provides the platform setting + +**/ +VOID +PchPrintLpcConfig ( + IN CONST PCH_LPC_CONFIG *LpcConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC Config ------------------\n")); + DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding= %x\n", LpcConfig->EnhancePort8xhDecoding)); +} + +/** + Print PCH_SPI_CONFIG and serial out. + + @param[in] SpiConfig Pointer to a PCH_SPI_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSpiConfig ( + IN CONST PCH_SPI_CONFIG *SpiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH SPI Config ------------------\n")); + DEBUG ((DEBUG_INFO, "ShowSpiController= %x\n", SpiConfig->ShowSpiController)); +} + +/** + Print whole PCH_POLICY_PPI and serial out. + + @param[in] PchPolicyPpi The RC Policy PPI instance + +**/ +VOID +PchPrintPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protocol Start ------------------------\n")); + DEBUG ((DEBUG_INFO, " Revision= %x\n", PchPolicyPpi->Revision)); + DEBUG ((DEBUG_INFO, " Port80Route= %x\n", PchPolicyPpi->Port80Route)); + DEBUG ((DEBUG_INFO, " AcpiBase= %x\n", PchPolicyPpi->AcpiBase)); + + PchPrintGeneralConfig (&PchPolicyPpi->PchConfig); + + PchPrintPcieConfig (&PchPolicyPpi->PcieConfig, &PchPolicyPpi->HsioPcieConfig); + + PchPrintPcieConfig2 (&PchPolicyPpi->PcieConfig2); + + PchPrintSataConfig (&PchPolicyPpi->SataConfig, &PchPolicyPpi->HsioSataConfig, PCH_SATA_FIRST_CONTROLLER); + PchPrintSataConfig (&PchPolicyPpi->sSataConfig, &PchPolicyPpi->HsiosSataConfig, PCH_SATA_SECOND_CONTROLLER); + PchPrintUsbConfig (&PchPolicyPpi->UsbConfig); + + PchPrintIoApicConfig (&PchPolicyPpi->IoApicConfig); + + PchPrintHpetConfig (&PchPolicyPpi->HpetConfig); + + PchPrintHdAudioConfig (&PchPolicyPpi->HdAudioConfig); + + PchPrintLanConfig (&PchPolicyPpi->LanConfig); + + PchPrintSmbusConfig (&PchPolicyPpi->SmbusConfig); + + PchPrintLockDownConfig (&PchPolicyPpi->LockDownConfig); + + PchPrintThermalConfig (&PchPolicyPpi->ThermalConfig); + + PchPrintPmConfig (&PchPolicyPpi->PmConfig); + + PchPrintDmiConfig (&PchPolicyPpi->DmiConfig); + + PchPrintSerialIrqConfig (&PchPolicyPpi->SerialIrqConfig); + + + PchPrintFlashProtectionConfig (&PchPolicyPpi->FlashProtectConfig); + + PchPrintWdtConfig (&PchPolicyPpi->WdtConfig); + + PchPrintP2sbConfig (&PchPolicyPpi->P2sbConfig); + + PchPrintDciConfig (&PchPolicyPpi->DciConfig); + + PchPrintLpcConfig (&PchPolicyPpi->LpcConfig); + + PchPrintSpiConfig (&PchPolicyPpi->SpiConfig); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protocol End --------------------------\n")); +DEBUG_CODE_END(); +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.c new file mode 100644 index 0000000000..f5ec0d5fb1 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.c @@ -0,0 +1,587 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyLibrary.h" +#include <Library/PchPmcLib.h> + +/** + mDevIntConfig[] table contains data on INTx and IRQ for each device. + IRQ value for devices which use ITSS INTx->PIRQx mapping need to be set in a way + that for each multifunctional Dxx:Fy same interrupt pins must map to the same IRQ. + Those IRQ values will be used to update ITSS.PIRx register. + In APIC relationship between PIRQs and IRQs is: + PIRQA -> IRQ16 + PIRQB -> IRQ17 + PIRQC -> IRQ18 + PIRQD -> IRQ19 + PIRQE -> IRQ20 + PIRQF -> IRQ21 + PIRQG -> IRQ22 + PIRQH -> IRQ23 + + Devices which use INTx->PIRQy mapping are: cAVS(in PCI mode), SMBus, GbE, TraceHub, PCIe, + SATA, HECI, IDE-R, KT Redirection, xHCI, Thermal Subsystem, Camera IO Host Controller + + PCI Express Root Ports mapping should be programmed only with values as in below table (D27/28/29) + otherwise _PRT methods in ACPI for RootPorts would require additional patching as + PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Mapping + + Configured IRQ values are not used if an OS chooses to be in PIC instead of APIC mode +**/ +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = { +// {31, 0, PchNoInt, 0}, // LPC/eSPI Interface, doesn't use interrupts +// {31, 1, PchNoInt, 0}, // P2SB, doesn't use interrupts +// {31, 2, PchNoInt, 0}, // PMC , doesn't use interrupts + {31, 3, PchIntA, 16}, // cAVS(Audio, Voice, Speach), INTA is default, programmed in PciCfgSpace 3Dh + {31, 4, PchIntA, 16}, // SMBus Controller, no default value, programmed in PciCfgSpace 3Dh +// {31, 5, PchNoInt, 0}, // SPI , doesn't use interrupts + {31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh + {31, 7, PchIntA, 16}, // TraceHub, INTA is default, RO register + {29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh + {29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh + {29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh + {29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh + {29, 4, PchIntA, 16}, // PCI Express Port 13 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {29, 5, PchIntB, 17}, // PCI Express Port 14 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {29, 6, PchIntC, 18}, // PCI Express Port 15 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {29, 7, PchIntD, 19}, // PCI Express Port 16 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {28, 0, PchIntA, 16}, // PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh + {28, 1, PchIntB, 17}, // PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh + {28, 2, PchIntC, 18}, // PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh + {28, 3, PchIntD, 19}, // PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh + {28, 4, PchIntA, 16}, // PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh + {28, 5, PchIntB, 17}, // PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh + {28, 6, PchIntC, 18}, // PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh + {28, 7, PchIntD, 19}, // PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh + {27, 0, PchIntA, 16}, // PCI Express Port 17 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {27, 1, PchIntB, 17}, // PCI Express Port 18 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {27, 2, PchIntC, 18}, // PCI Express Port 19 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {27, 3, PchIntD, 19}, // PCI Express Port 20 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh +// {24, 0, 0, 0}, // Reserved (used by RST PCIe Storage Cycle Router) + {23, 0, PchIntA, 16}, // SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh + {22, 0, PchIntA, 16}, // CSME: HECI #1 + {22, 1, PchIntB, 17}, // CSME: HECI #2 + {22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R) + {22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection + {22, 4, PchIntA, 16}, // CSME: HECI #3 +// {22, 7, PchNoInt, 0}, // CSME: WLAN + {20, 0, PchIntA, 16}, // USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh + {20, 2, PchIntC, 18}, // Thermal Subsystem +// {20, 4, 0, 0}, // TraceHub Phantom (ACPI) Function +// {18, 0, PchNoInt, 0}, // CSME: KVMcc, doesn't use interrupts +// {18, 1, PchNoInt, 0}, // CSME: Clink, doesn't use interrupts +// {18, 2, PchNoInt, 0}, // CSME: PMT, doesn't use interrupts +// {18, 3, 0, 0}, // CSME: CSE UMA +// {18, 4, 0, 0} // CSME: fTPM DMA + {17, 5, PchIntA, 16} // SSATA controller. +#ifdef IE_SUPPORT + , +// {16, 0, PchIntA, 16}, // IE: HECI #1 +// {16, 1, PchIntB, 17}, // IE: HECI #2 +// {16, 2, PchIntC, 18}, // IE: IDE-Redirection (IDE-R) + {16, 3, PchIntD, 19} // IE: Keyboard and Text (KT) Redirection +// {16, 4, PchIntA, 16} // IE: HECI #3 +#endif // IE_SUPPORT +}; + +// +// mLpOnlyDevIntConfig[] table contains data on INTx and IRQ for devices that exist on SPT-LP but not on SPT-H. +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mLpOnlyDevIntConfig[] = { + {25, 1, PchIntB, 33}, // SerialIo I2C Controller #5, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[6] + {25, 2, PchIntC, 34} // SerialIo I2C Controller #4, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[5] +}; +/** + mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped to IRQy). + This information is used by systems which choose to use legacy PIC + interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this table + will be programmed into ITSS.PxRC registers. +**/ +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] = { + 11, // PARC: PIRQA -> IRQ11 + 10, // PBRC: PIRQB -> IRQ10 + 11, // PCRC: PIRQC -> IRQ11 + 11, // PDRC: PIRQD -> IRQ11 + 11, // PERC: PIRQE -> IRQ11 + 11, // PFRC: PIRQF -> IRQ11 + 11, // PGRC: PIRQG -> IRQ11 + 11 // PHRC: PIRQH -> IRQ11 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusRsvdAddresses[] = { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +/** + PchCreatePolicyDefaults creates the default setting of PCH Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] PchPolicyPpi The pointer to get PCH Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchCreatePolicyDefaults ( + OUT PCH_POLICY_PPI **PchPolicyPpi + ) +{ + PCH_POLICY_PPI *PchPolicy; + PCH_SERIES PchSeries; + UINT32 PortIndex; + UINT32 Index; + UINT8 IntConfigTableEntries; + + PchSeries = GetPchSeries (); + + PchPolicy = (PCH_POLICY_PPI *) AllocateZeroPool (sizeof (PCH_POLICY_PPI)); + if (PchPolicy == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + // + // Policy not listed here are set to 0/FALSE as default. + // + + /******************************** + General initialization + ********************************/ + PchPolicy->Revision = PCH_POLICY_REVISION; + PchPolicy->AcpiBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress); + PchPolicy->TempMemBaseAddr = PCH_TEMP_BASE_ADDRESS; + + /******************************** + PCH general configuration + ********************************/ + // + // Default Svid Sdid configuration + // + PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID; + + /******************************** + PCI Express related settings + ********************************/ + + PchPolicy->TempPciBusMin = 2; + PchPolicy->TempPciBusMax = 10; + + PchPolicy->PcieConfig.RpFunctionSwap = TRUE; + + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + PchPolicy->PcieConfig.RootPort[PortIndex].Aspm = PchPcieAspmAutoConfig; + PchPolicy->PcieConfig.RootPort[PortIndex].Enable = TRUE; + PchPolicy->PcieConfig.RootPort[PortIndex].PmSci = TRUE; + PchPolicy->PcieConfig.RootPort[PortIndex].AcsEnabled = TRUE; + + PchPolicy->PcieConfig.RootPort[PortIndex].MaxPayload = PchPcieMaxPayload256; + + PchPolicy->PcieConfig.RootPort[PortIndex].PhysicalSlotNumber = (UINT8) PortIndex; + + PchPolicy->PcieConfig.RootPort[PortIndex].L1Substates = PchPcieL1SubstatesL1_1_2; + + // + // PCIe LTR Configuration. + // + PchPolicy->PcieConfig.RootPort[PortIndex].LtrEnable = TRUE; + if (PchSeries == PchLp) { + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = 0x1003; + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x1003; + } + if (PchSeries == PchH) { + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = 0x0846; + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x0846; + } + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMode = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMultiplier = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideValue = 60; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMode = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMultiplier = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideValue = 60; + + PchPolicy->PcieConfig.RootPort[PortIndex].Uptp = 5; + PchPolicy->PcieConfig.RootPort[PortIndex].Dptp = 7; + } + + for (Index = 0; Index < GetPchMaxPciePortNum (); ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = 6; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = 6; + } + + PchPolicy->PcieConfig2.SwEqCoeffList[0].Cm = 6; + PchPolicy->PcieConfig2.SwEqCoeffList[0].Cp = 8; + PchPolicy->PcieConfig2.SwEqCoeffList[1].Cm = 8; + PchPolicy->PcieConfig2.SwEqCoeffList[1].Cp = 2; + PchPolicy->PcieConfig2.SwEqCoeffList[2].Cm = 10; + PchPolicy->PcieConfig2.SwEqCoeffList[2].Cp = 6; + PchPolicy->PcieConfig2.SwEqCoeffList[3].Cm = 12; + PchPolicy->PcieConfig2.SwEqCoeffList[3].Cp = 8; + PchPolicy->PcieConfig2.SwEqCoeffList[4].Cm = 14; + PchPolicy->PcieConfig2.SwEqCoeffList[4].Cp = 2; + + /******************************** + SATA related settings + ********************************/ + PchPolicy->SataConfig.Enable = TRUE; + PchPolicy->SataConfig.SalpSupport = TRUE; + PchPolicy->SataConfig.SataMode = PchSataModeAhci; + + for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { + PchPolicy->SataConfig.PortSettings[PortIndex].Enable = TRUE; + PchPolicy->SataConfig.PortSettings[PortIndex].DmVal = 15; + PchPolicy->SataConfig.PortSettings[PortIndex].DitoVal = 625; + } + + PchPolicy->SataConfig.Rst.Raid0 = TRUE; + PchPolicy->SataConfig.Rst.Raid1 = TRUE; + PchPolicy->SataConfig.Rst.Raid10 = TRUE; + PchPolicy->SataConfig.Rst.Raid5 = TRUE; + PchPolicy->SataConfig.Rst.Irrt = TRUE; + PchPolicy->SataConfig.Rst.OromUiBanner = TRUE; + PchPolicy->SataConfig.Rst.OromUiDelay = PchSataOromDelay2sec; + PchPolicy->SataConfig.Rst.HddUnlock = TRUE; + PchPolicy->SataConfig.Rst.LedLocate = TRUE; + PchPolicy->SataConfig.Rst.IrrtOnly = TRUE; + PchPolicy->SataConfig.Rst.SmartStorage = TRUE; + + for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = 100; + } + /******************************** + sSATA related settings + ********************************/ + PchPolicy->sSataConfig.Enable = TRUE; + // PchPolicy->sSataConfig.TestMode = FALSE; + // PchPolicy->sSataConfig.LegacyMode = FALSE; + PchPolicy->sSataConfig.SalpSupport = TRUE; + // PchPolicy->sSataConfig.eSATASpeedLimit = FALSE; + PchPolicy->sSataConfig.SataMode = PchSataModeAhci; + // PchPolicy->sSataConfig.SpeedLimit = PchsSataSpeedDefault; + + for (PortIndex = 0; PortIndex < GetPchMaxsSataPortNum (); PortIndex++) { + PchPolicy->sSataConfig.PortSettings[PortIndex].Enable = TRUE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].HotPlug = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].InterlockSw = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].External = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].SpinUp = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].SolidStateDrive = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].DevSlp = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].EnableDitoConfig = FALSE; + PchPolicy->sSataConfig.PortSettings[PortIndex].DmVal = 15; + PchPolicy->sSataConfig.PortSettings[PortIndex].DitoVal = 625; + } + + // PchPolicy->sSataConfig.Rst.RaidAlternateId = FALSE; + PchPolicy->sSataConfig.Rst.Raid0 = TRUE; + PchPolicy->sSataConfig.Rst.Raid1 = TRUE; + PchPolicy->sSataConfig.Rst.Raid10 = TRUE; + PchPolicy->sSataConfig.Rst.Raid5 = TRUE; + PchPolicy->sSataConfig.Rst.Irrt = TRUE; + PchPolicy->sSataConfig.Rst.OromUiBanner = TRUE; + PchPolicy->sSataConfig.Rst.OromUiDelay = PchSataOromDelay2sec; + PchPolicy->sSataConfig.Rst.HddUnlock = TRUE; + PchPolicy->sSataConfig.Rst.LedLocate = TRUE; + PchPolicy->sSataConfig.Rst.IrrtOnly = TRUE; + PchPolicy->sSataConfig.Rst.SmartStorage = TRUE; + + for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + //PchPolicy->sSataConfig.RstPcieStorageRemap[Index].Enable = 0; + //PchPolicy->sSataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = 0; + PchPolicy->sSataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = 100; + } + + /******************************** + USB related configuration + ********************************/ + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) { + PchPolicy->UsbConfig.PortUsb20[PortIndex].Enable = TRUE; + } + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + PchPolicy->UsbConfig.PortUsb30[PortIndex].Enable = TRUE; + } + // + //XHCI Wake On USB Disabled + // + PchPolicy->UsbConfig.XhciWakeOnUsb = FALSE; + // + // USB Port Over Current Pins mapping, please set as per board layout. + // Default is PchUsbOverCurrentPin0(0) + // + PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin4; + PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPin4; + PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPin5; + PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPin5; + PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPin6; + PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPin6; + PchPolicy->UsbConfig.PortUsb20[14].OverCurrentPin = PchUsbOverCurrentPin7; + PchPolicy->UsbConfig.PortUsb20[15].OverCurrentPin = PchUsbOverCurrentPin7; + + PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb30[6].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb30[7].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb30[8].OverCurrentPin = PchUsbOverCurrentPin4; + PchPolicy->UsbConfig.PortUsb30[9].OverCurrentPin = PchUsbOverCurrentPin4; + + // + // Default values of USB2 AFE settings. + // + for (Index = 0; Index < PCH_H_XHCI_MAX_USB2_PORTS; Index++) { + + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Predeemp = 2; + + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Pehalfbit = 1; + } + + // + // Enable/Disable SSIC support in the setup menu + // + for (PortIndex = 0; PortIndex < PCH_XHCI_MAX_SSIC_PORT_COUNT; PortIndex++) { + PchPolicy->UsbConfig.SsicConfig.SsicPort[PortIndex].Enable = FALSE; + } + + // + // xDCI configuration + // + PchPolicy->UsbConfig.XdciConfig.Enable = FALSE; + + + /******************************** + Io Apic configuration + ********************************/ + PchPolicy->IoApicConfig.IoApicId = 0x02; + PchPolicy->IoApicConfig.IoApicEntry24_119 = FALSE; + + /******************************** + HPET Configuration + ********************************/ + PchPolicy->HpetConfig.Enable = TRUE; + PchPolicy->HpetConfig.Base = PCH_HPET_BASE_ADDRESS; + + /******************************** + HD-Audio configuration + ********************************/ + PchPolicy->HdAudioConfig.Enable = PCH_HDAUDIO_AUTO; + PchPolicy->HdAudioConfig.DspEnable = TRUE; + PchPolicy->HdAudioConfig.HdAudioLinkFrequency = PchHdaLinkFreq24MHz; + PchPolicy->HdAudioConfig.IDispLinkFrequency = PchHdaLinkFreq96MHz; + PchPolicy->HdAudioConfig.ResetWaitTimer = 600; // Must be at least 521us (25 frames) + PchPolicy->HdAudioConfig.DspEndpointDmic = PchHdaDmic4chArray; + + /******************************** + Lan configuration + ********************************/ + PchPolicy->LanConfig.Enable = TRUE; + /******************************** + SMBus configuration + ********************************/ + PchPolicy->SmbusConfig.Enable = TRUE; + PchPolicy->SmbusConfig.SmbusIoBase = PcdGet16 (PcdSmbusBaseAddress); + ASSERT (sizeof (mSmbusRsvdAddresses) <= PCH_MAX_SMBUS_RESERVED_ADDRESS); + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = sizeof (mSmbusRsvdAddresses); + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + mSmbusRsvdAddresses, + sizeof (mSmbusRsvdAddresses) + ); + + /******************************** + Lockdown configuration + ********************************/ + PchPolicy->LockDownConfig.GlobalSmi = TRUE; + // + // PCH BIOS Spec Flash Security Recommendations, + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + // will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + // Here we always enable this as a Policy. + // + PchPolicy->LockDownConfig.BiosInterface = TRUE; + PchPolicy->LockDownConfig.RtcLock = TRUE; + + /******************************** + Thermal configuration. + ********************************/ + PchPolicy->ThermalConfig.ThermalDeviceEnable = 0; + PchPolicy->ThermalConfig.TsmicLock = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE; + + /******************************** + MiscPm Configuration + ********************************/ + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.WolOvrWkSts = TRUE; + + PchPolicy->PmConfig.WakeConfig.WolEnableOverride = TRUE; + PchPolicy->PmConfig.WakeConfig.LanWakeFromDeepSx = TRUE; + + PchPolicy->PmConfig.PchSlpS3MinAssert = PchSlpS350ms; + PchPolicy->PmConfig.PchSlpS4MinAssert = PchSlpS44s; + PchPolicy->PmConfig.PchSlpSusMinAssert = PchSlpSus4s; + PchPolicy->PmConfig.PchSlpAMinAssert = PchSlpA2s; + + PchPolicy->PmConfig.PmcReadDisable = TRUE; + PchPolicy->PmConfig.SlpLanLowDc = TRUE; + PchPolicy->PmConfig.PciePllSsc = 0xFF; + + PchPolicy->PmConfig.SlpS0Enable = TRUE; + + PchPolicy->PmConfig.GrPfetDurOnDef = PchPmGrPfetDur5us; + + /******************************** + DMI related settings + ********************************/ + PchPolicy->DmiConfig.DmiAspm = TRUE; + PchPolicy->DmiConfig.DmiStopAndScreamEnable = FALSE; + + /******************************** + Serial IRQ Configuration + ********************************/ + PchPolicy->SerialIrqConfig.SirqEnable = TRUE; + PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode; + PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk; + + + /******************************** + Interrupt Configuration + ********************************/ + IntConfigTableEntries = sizeof (mDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG); + ASSERT (IntConfigTableEntries <= PCH_MAX_DEVICE_INTERRUPT_CONFIG); + PchPolicy->PchInterruptConfig.NumOfDevIntConfig = IntConfigTableEntries; + CopyMem ( + PchPolicy->PchInterruptConfig.DevIntConfig, + mDevIntConfig, + sizeof (mDevIntConfig) + ); + if (GetPchSeries () == PchLp) { + CopyMem ( + &(PchPolicy->PchInterruptConfig.DevIntConfig[IntConfigTableEntries]), + mLpOnlyDevIntConfig, + sizeof (mLpOnlyDevIntConfig) + ); + PchPolicy->PchInterruptConfig.NumOfDevIntConfig += (sizeof (mLpOnlyDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG)); + } + + ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <= PCH_MAX_PXRC_CONFIG); + CopyMem ( + PchPolicy->PchInterruptConfig.PxRcConfig, + mPxRcConfig, + sizeof (mPxRcConfig) + ); + + PchPolicy->PchInterruptConfig.GpioIrqRoute = 14; + PchPolicy->PchInterruptConfig.SciIrqSelect = 9; + PchPolicy->PchInterruptConfig.TcoIrqSelect = 9; + + + /******************************** + Port 61h emulation + ********************************/ + PchPolicy->Port61hSmmConfig.Enable = TRUE; + + + /******************************** + DCI Configuration + ********************************/ + PchPolicy->DciConfig.DciAutoDetect = TRUE; + + /******************************** + LPC Configuration + ********************************/ + PchPolicy->LpcConfig.EnhancePort8xhDecoding = TRUE; + + /******************************** + Power Optimizer related settings + ********************************/ + PchPolicy->SataConfig.PwrOptEnable = TRUE; + PchPolicy->sSataConfig.PwrOptEnable = TRUE; + + + PchPolicy->AdrConfig.PchAdrEn = FORCE_ENABLE; + PchPolicy->AdrConfig.AdrGpioSel = PM_SYNC_GPIO_B; + PchPolicy->AdrConfig.AdrHostPartitionReset = FORCE_DISABLE; + PchPolicy->AdrConfig.AdrTimerEn = FORCE_ENABLE; + PchPolicy->AdrConfig.AdrTimerVal = V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US; + PchPolicy->AdrConfig.AdrMultiplierVal = V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1; + + *PchPolicyPpi = PchPolicy; + return EFI_SUCCESS; +} + +/** + PchInstallPolicyPpi installs PchPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPolicyPpiDesc; + + PchPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (PchPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + PchPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid; + PchPolicyPpiDesc->Ppi = PchPolicyPpi; + + // + // Print whole PCH_POLICY_PPI and serial out. + // + if (PchIsDwrFlow() == FALSE) { + PchPrintPolicyPpi (PchPolicyPpi); + } + + // + // Install PCH Policy PPI + // + Status = PeiServicesInstallPpi (PchPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf new file mode 100644 index 0000000000..fa433c9333 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf @@ -0,0 +1,58 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPchPolicyLib
+ FILE_GUID = BB1AC992-B2CA-4744-84B7-915C185576C5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PchPolicyLib
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ PcdLib
+ PeiServicesLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PchInfoLib
+ PchPmcLib #SERVER_BIOS
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+
+
+[Pcd]
+ gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress #SERVER_BIOS
+ gEfiPchTokenSpaceGuid.PcdSmbusBaseAddress #SERVER_BIOS
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartDebugEnable
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartNumber
+
+
+[Sources]
+ PeiPchPolicyLib.c
+ PeiPchPolicyLibrary.h
+ PchPrintPolicy.c
+ Rvp3PolicyLib.c
+
+
+[Ppis]
+ gPchPlatformPolicyPpiGuid ## PRODUCES # SERVER_BIOS
+
+[Depex]
+ gPchInitPreMemDonePpiGuid
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h new file mode 100644 index 0000000000..9932afdc04 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h @@ -0,0 +1,31 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_PCH_POLICY_LIBRARY_H_ +#define _PEI_PCH_POLICY_LIBRARY_H_ + +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/PeiServicesLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PchInfoLib.h> +#include <Ppi/PchPolicy.h> +#include <PchAccess.h> +#include <Library/PchSerialIoLib.h> +#include <Library/PchPolicyLib.h> + +#define PCH_HPET_BASE_ADDRESS 0xFED00000 + + +#endif // _PEI_PCH_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/Rvp3PolicyLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/Rvp3PolicyLib.c new file mode 100644 index 0000000000..62cc91f821 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/Rvp3PolicyLib.c @@ -0,0 +1,211 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyLibrary.h" + +/* + Apply RVP3 PCH specific default settings + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance +*/ +VOID +EFIAPI +PchRvp3DefaultPolicy ( + IN PCH_POLICY_PPI *PchPolicy + ) +{ + UINTN Index; + + // + // PCIE RP + // + for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) { + PchPolicy->PcieConfig.RootPort[Index].ClkReqDetect = TRUE; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = TRUE; + } + + PchPolicy->PcieConfig.RootPort[0].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[0].ClkReqNumber = 2; + PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtle = 6; + + PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtle = 6; + + PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtle = 6; + + PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtle = 6; + + PchPolicy->PcieConfig.RootPort[4].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[4].ClkReqNumber = 3; + + PchPolicy->PcieConfig.RootPort[5].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[5].ClkReqNumber = 1; + PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtle = 8; + + PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtle = 8; + + PchPolicy->PcieConfig.RootPort[8].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[8].ClkReqNumber = 5; + PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtle = 8; + + PchPolicy->PcieConfig.RootPort[9].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[9].ClkReqNumber = 4; + PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtle = 8; + + PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtle = 8; + + PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtle = 8; + + // + // SATA + // + PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMagEnable = TRUE; + PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMag = 4; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmpEnable = TRUE; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmp = 0x2C; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmpEnable = 0; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmp = 0; + + // + // USB + // + PchPolicy->UsbConfig.PortUsb20[0].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[1].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[2].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[3].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[4].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[5].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[6].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[7].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[8].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Txiset = 5; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[9].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Pehalfbit = 1; + + // OC Map for USB2 Ports + PchPolicy->UsbConfig.PortUsb20[ 0].OverCurrentPin = PchUsbOverCurrentPin0; + PchPolicy->UsbConfig.PortUsb20[ 1].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPinSkip; + + // OC Map for USB3 Ports + PchPolicy->UsbConfig.PortUsb30[0].OverCurrentPin = PchUsbOverCurrentPin0; + PchPolicy->UsbConfig.PortUsb30[1].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPinSkip; + + PchPolicy->UsbConfig.SsicConfig.SsicPort[0].Enable = TRUE; + PchPolicy->UsbConfig.SsicConfig.SsicPort[1].Enable = TRUE; + + // + // IOAPIC + // + PchPolicy->IoApicConfig.BdfValid = 1; + PchPolicy->IoApicConfig.BusNumber = 0xF0; + PchPolicy->IoApicConfig.DeviceNumber = 0x1F; + PchPolicy->IoApicConfig.FunctionNumber = 0; + + // + // LAN + // + PchPolicy->LanConfig.K1OffEnable = TRUE; + PchPolicy->LanConfig.ClkReqSupported = TRUE; + PchPolicy->LanConfig.ClkReqNumber = 3; + + // + // LOCK DOWN + // + PchPolicy->LockDownConfig.SpiEiss = TRUE; + PchPolicy->LockDownConfig.BiosLock = TRUE; + + // + // THERMAL + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = FALSE; + + // + // PM CONFIG + // + PchPolicy->PmConfig.PciClockRun = TRUE; + + // + // DMI + // + PchPolicy->DmiConfig.PwrOptEnable = TRUE; + + + // + // TRACEHUB + // + PchPolicy->PchTraceHubConfig.MemReg0Size = 0x100000; // 1MB + PchPolicy->PchTraceHubConfig.MemReg1Size = 0x100000; // 1MB + +} diff --git a/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..0972343872 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf @@ -0,0 +1,56 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmSpiFlashCommonLib
+ FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ PciLib
+ IoLib
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ SmmServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ MmPciLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec
+
+[Pcd]
+ gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
+ gEfiPchTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+
+[Sources]
+ SpiFlashCommonSmmLib.c
+ SpiFlashCommon.c
+
+[Protocols]
+ gEfiSmmSpiProtocolGuid ## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+ gEfiSmmSpiProtocolGuid
diff --git a/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..9d1e3fb60e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c @@ -0,0 +1,198 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/SpiFlashCommonLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Protocol/Spi.h>
+
+
+EFI_SPI_PROTOCOL *mSpiProtocol;
+
+//
+// FlashAreaBaseAddress and Size for boottime and runtime usage.
+//
+UINTN mFlashAreaBaseAddress = 0;
+UINTN mFlashAreaSize = 0;
+
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // This function is implemented specifically for those platforms
+ // at which the SPI device is memory mapped for read. So this
+ // function just do a memory copy for Spi Flash Read.
+ //
+ CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Length;
+ UINT32 RemainingBytes;
+
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mFlashAreaBaseAddress);
+
+ Offset = Address - mFlashAreaBaseAddress;
+
+ ASSERT ((*NumBytes + Offset) <= mFlashAreaSize);
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+
+ while (RemainingBytes > 0) {
+ if (RemainingBytes > SECTOR_SIZE_4KB) {
+ Length = SECTOR_SIZE_4KB;
+ } else {
+ Length = RemainingBytes;
+ }
+ Status = mSpiProtocol->FlashWrite (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ Length,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ RemainingBytes -= Length;
+ Offset += Length;
+ Buffer += Length;
+ }
+
+ //
+ // Actual number of bytes written
+ //
+ *NumBytes -= RemainingBytes;
+
+ return Status;
+}
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN RemainingBytes;
+
+ ASSERT (NumBytes != NULL);
+ if (NumBytes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mFlashAreaBaseAddress);
+
+ Offset = Address - mFlashAreaBaseAddress;
+
+ ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0);
+ ASSERT ((*NumBytes + Offset) <= mFlashAreaSize);
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+
+ Status = mSpiProtocol->FlashErase (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ (UINT32) RemainingBytes
+ );
+ return Status;
+}
+
diff --git a/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..befff4c8dd --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c @@ -0,0 +1,59 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/SpiFlashCommonLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Protocol/Spi.h>
+
+extern EFI_SPI_PROTOCOL *mSpiProtocol;
+
+extern UINTN mFlashAreaBaseAddress;
+extern UINTN mFlashAreaSize;
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+**/
+EFI_STATUS
+EFIAPI
+SmmSpiFlashCommonLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mFlashAreaBaseAddress = (UINTN)PcdGet32 (PcdFlashAreaBaseAddress);
+ mFlashAreaSize = (UINTN)PcdGet32 (PcdFlashAreaSize);
+
+ //
+ // Locate the SMM SPI protocol.
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gEfiSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Silicon/Intel/LewisburgPkg/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf b/Silicon/Intel/LewisburgPkg/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf new file mode 100644 index 0000000000..3f493a7d4e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf @@ -0,0 +1,34 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BasePchResetCommonLib
+ FILE_GUID = 1E6151B2-6306-4C9C-B9AC-794A13BEBC3F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PchResetCommonLib
+
+[Sources]
+ PchResetCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+ PurleyRcPkg/RcPkg.dec #SERVER_BIOS
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PchCycleDecodingLib
diff --git a/Silicon/Intel/LewisburgPkg/LibraryPrivate/BasePchResetCommonLib/PchResetCommon.c b/Silicon/Intel/LewisburgPkg/LibraryPrivate/BasePchResetCommonLib/PchResetCommon.c new file mode 100644 index 0000000000..7b3c894700 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/LibraryPrivate/BasePchResetCommonLib/PchResetCommon.c @@ -0,0 +1,174 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi/UefiBaseType.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <PchAccess.h> +#include <Library/PchCycleDecodingLib.h> +#include <Library/MmPciBaseLib.h> +#include <IncludePrivate/Library/PchResetCommonLib.h> + + +EFI_STATUS +EFIAPI +PchResetCallback ( + IN PCH_RESET_TYPE PchResetType + ); + +/** + Initialize an Pch Reset ppi/protocol instance. + + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initialized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +PchResetConstructor ( + PCH_RESET_INSTANCE *PchResetInstance + ) +{ + UINTN PmcBaseAddress; + + /// + /// Initialize the Reset protocol instance + /// + PchResetInstance->Signature = PCH_RESET_SIGNATURE; + PchResetInstance->Handle = NULL; + + /// + /// Sanity check to ensure PMC ACPI/PM BASE initialization has occurred previously. + /// + PmcBaseAddress = MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + PchResetInstance->PchPmcBase = PmcBaseAddress; + PchPwrmBaseGet (&(PchResetInstance->PchPwrmBase)); + ASSERT (PchResetInstance->PchPwrmBase != 0); + PchAcpiBaseGet (&(PchResetInstance->PchAcpiBase)); + ASSERT (PchResetInstance->PchAcpiBase != 0); + + + return EFI_SUCCESS; +} + +/** + Execute Pch Reset from the host controller. + @param[in] PchResetInstance Pointer to PchResetInstance to initialize + @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset, + PowerCycleReset, GlobalReset, GlobalResetWithEc + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER If ResetType is invalid. +**/ +EFI_STATUS +PchReset ( + IN PCH_RESET_INSTANCE *PchResetInstance, + IN PCH_RESET_TYPE PchResetType + ) +{ + UINTN PmcBaseAddress; + UINT16 ABase; + UINT8 OutputData; + UINT32 Data32; + UINT16 Data16; + EFI_STATUS Status; + + PmcBaseAddress = PchResetInstance->PchPmcBase; + ABase = PchResetInstance->PchAcpiBase; + switch (PchResetType) { + case ColdReset: + IoWrite8 ((UINTN) R_PCH_RST_CNT, (UINT8) V_PCH_RST_CNT_HARDSTARTSTATE); + OutputData = V_PCH_RST_CNT_FULLRESET; + break; + + case WarmReset: + IoWrite8 ((UINTN) R_PCH_RST_CNT, (UINT8) V_PCH_RST_CNT_SOFTSTARTSTATE); + OutputData = V_PCH_RST_CNT_HARDRESET; + break; + + case ShutdownReset: + /// + /// Firstly, ACPI decode must be enabled + /// + MmioOr8 ( + PmcBaseAddress + R_PCH_PMC_ACPI_CNT, + (UINT8) (B_PCH_PMC_ACPI_CNT_ACPI_EN) + ); + + /// + /// Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5 + /// + IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_GPE0_EN_127_96), 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + Data16 = B_PCH_SMI_STS_PM1_STS_REG; + IoWrite16 ((UINTN) (ABase + R_PCH_SMI_STS), Data16); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 = IoRead32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT)); + + Data32 = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5); + + IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT), Data32); + + Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN; + + IoWrite32 ((UINTN) (ABase + R_PCH_ACPI_PM1_CNT), Data32); + return EFI_SUCCESS; + + case PowerCycleReset: + case GlobalReset: + case GlobalResetWithEc: + /// + /// PCH BIOS Spec Section 4.6 GPIO Reset Requirement + /// + + if ((PchResetType == GlobalReset) || (PchResetType == GlobalResetWithEc)) { + MmioOr32 ( + PmcBaseAddress + R_PCH_PMC_ETR3, + (UINT32) (B_PCH_PMC_ETR3_CF9GR) + ); + } + OutputData = V_PCH_RST_CNT_FULLRESET; + break; + + default: + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_ERROR, "Resetting the platform (%02x)...\n", OutputData)); + + Status = PchResetCallback (PchResetType); + + if ((Status == EFI_SUCCESS) || (Status == EFI_NOT_FOUND)) { + IoWrite8 ((UINTN) R_PCH_RST_CNT, OutputData); + /// + /// Waiting for system reset + /// + CpuDeadLoop (); + } + + return Status; +} diff --git a/Silicon/Intel/LewisburgPkg/PchCommonLib.dsc b/Silicon/Intel/LewisburgPkg/PchCommonLib.dsc new file mode 100644 index 0000000000..c12fe32b7e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/PchCommonLib.dsc @@ -0,0 +1,25 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.common]
+ GpioLib|$(PCH_PKG)/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
+ PchPolicyLib|$(PCH_PKG)/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
+ PchCycleDecodingLib|$(PCH_PKG)/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
+ PchGbeLib|$(PCH_PKG)/Library/PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf
+ PchInfoLib|$(PCH_PKG)/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLib.inf
+ PchP2sbLib|$(PCH_PKG)/Library/PeiDxeSmmPchP2sbLib/PeiDxeSmmPchP2sbLib.inf
+ PchPcrLib|$(PCH_PKG)/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PCH_PKG)/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+ PchResetCommonLib|$(PCH_PKG)/LibraryPrivate/BasePchResetCommonLib/BasePchResetCommonLib.inf
+ PchPmcLib|$(PCH_PKG)/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
diff --git a/Silicon/Intel/LewisburgPkg/PchDxeLib.dsc b/Silicon/Intel/LewisburgPkg/PchDxeLib.dsc new file mode 100644 index 0000000000..d5dc5667c7 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/PchDxeLib.dsc @@ -0,0 +1,19 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+ ResetSystemLib|$(PCH_PKG)/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+ SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
diff --git a/Silicon/Intel/LewisburgPkg/PchPeiLib.dsc b/Silicon/Intel/LewisburgPkg/PchPeiLib.dsc new file mode 100644 index 0000000000..6503f1799a --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/PchPeiLib.dsc @@ -0,0 +1,14 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
diff --git a/Silicon/Intel/LewisburgPkg/PchRcPkg.dec b/Silicon/Intel/LewisburgPkg/PchRcPkg.dec new file mode 100644 index 0000000000..69ec66f1c2 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/PchRcPkg.dec @@ -0,0 +1,232 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PchRcPkg
+ PACKAGE_GUID = 4E97AC4B-F64C-4008-BBDE-01CC3B0BAA6B
+ PACKAGE_VERSION = 0.91
+
+[Includes]
+ Include
+ IncludePrivate
+ AcpiTables/Dsdt
+
+[Ppis]
+ #
+ # PCH
+ #
+ gPchPmcXramOffsetDataPpiGuid = { 0xc1392859, 0x1f65, 0x446e, { 0xa3, 0xf6, 0x85, 0x36, 0xfc, 0xc7, 0xd1, 0xc4 }}
+
+[LibraryClasses]
+
+[LibraryClasses.IA32]
+
+[Guids]
+ gRcPkgTokenSpaceGuid = { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }}
+ gEfiPchTokenSpaceGuid = { 0x89a1b278, 0xa1a1, 0x4df7, { 0xb1, 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 } }
+ gSataControllerDriverGuid = { 0xbb929da9, 0x68f7, 0x4035, { 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 }}
+ gPchInitVariableGuid = { 0xe6c2f70a, 0xb604, 0x4877, { 0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb }}
+ gPchS3ImageGuid = { 0x271dd6f2, 0x54cb, 0x45e6, { 0x85, 0x85, 0x8c, 0x92, 0x3c, 0x1a, 0xc7, 0x6 }}
+ gEfiSmbusArpMapGuid = { 0x707be83e, 0x0bf6, 0x40a5, { 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 }}
+ mPchSataRsteProtocolGuid = { 0x3ea94650, 0xfc5b, 0x11e1, {0xa2, 0x1f, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}}
+ mPchSataRstProtocolGuid = { 0xfc5f2e00, 0xfc68, 0x11e1, {0xa2, 0x1f, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}}
+ gPchInitPeiVariableGuid = { 0xa31b27a4, 0xcae6, 0x48ff, {0x8c, 0x5a, 0x29, 0x42, 0x21, 0xe6, 0xf3, 0x89 }}
+ gChipsetInitInfoHobGuid = { 0xc1392859, 0x1f65, 0x446e, {0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4}}
+ gPchOemSmmGuid = { 0xc0cfaf36, 0x4296, 0x40ba, {0xa9, 0xf1, 0x77, 0x10, 0x9b, 0x91, 0xce, 0x19}}
+ gPchPowerCycleResetGuid = { 0x8d8ee25b, 0x66dd, 0x4ed8, { 0x8a, 0xbd, 0x14, 0x16, 0xe8, 0x8e, 0x1d, 0x24 }}
+ gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
+ gPchGlobalResetWithEcGuid = { 0xd22e6b72, 0x53cd, 0x4158, { 0x83, 0x3f, 0x6f, 0xd8, 0x7e, 0xbe, 0xa9, 0x93 }}
+#S3 add
+ gPchS3CodeInLockBoxGuid = { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}}
+ gPchS3ContextInLockBoxGuid = { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}}
+#S3 add
+ gMeBiosExtensionSetupGuid = { 0x1bad711c, 0xd451, 0x4241, { 0xb1, 0xf3, 0x85, 0x37, 0x81, 0x2e, 0xc, 0x70 } }
+ gAmtForcePushPetPolicyGuid = { 0xacc8e1e4, 0x9f9f, 0x4e40, { 0xa5, 0x7e, 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5 } }
+ gEfiAcpiVariableGuid = { 0xc020489e, 0x6db2, 0x4ef2,{ 0x9a, 0xa5, 0xca, 0x6, 0xfc, 0x11, 0xd3, 0x6a } }
+ gEfiCommonPkgTokenSpaceGuid = { 0x86cf2b1a, 0xb3da, 0x4642, { 0x95, 0xf5, 0xd0, 0x1c, 0x6c, 0x1c, 0x60, 0xb8 }}
+ gSiPolicyHobGuid = { 0xb3903068, 0x7482, 0x4424, { 0xba, 0x4b, 0x40, 0x5f, 0x8f, 0xd7, 0x65, 0x4e }}
+ gEfiPchTokenSpaceGuid = { 0x977c97c1, 0x47e1, 0x4b6b, { 0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b }}
+ gPchPolicyHobGuid = { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}
+ gPchDeviceTableHobGuid = { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}
+ gPchChipsetInitHobGuid = { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
+ gWdtHobGuid = { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0xb7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }}
+ # PCH_SERVER_BIOS_FLAG add
+ gPchPsfErrorHobGuid = { 0x9ee875f4, 0xa463, 0x4b29, { 0x88, 0x79, 0x11, 0x2a, 0x4d, 0x05, 0x47, 0x7f }} #PCH_SERVER_BIOS_FLAG
+
+##
+## PreMem Performance
+##
+ gPerfPchPrePolicyGuid = {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, 0x3E, 0x25, 0xEE, 0x81, 0x92, 0xA4}}
+ gPerfSiValidateGuid = {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, 0xB1, 0x11, 0x33, 0xDE, 0x37, 0xA9}}
+ gPerfPchValidateGuid = {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, 0x29, 0x0B, 0x38, 0xC5, 0x32, 0x25}}
+ gPerfAmtValidateGuid = {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB, 0x3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF}}
+ gPerfCpuValidateGuid = {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, 0xED, 0xFE, 0xF2, 0x23, 0xB2, 0x09}}
+ gPerfMeValidateGuid = {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC, 0x51, 0x0C, 0x31, 0xAF, 0x45, 0xD0}}
+ gPerfSaValidateGuid = {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, 0x09, 0x3E, 0xC5, 0xA5, 0x93, 0x11}}
+ gPerfHeciPreMemGuid = {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC, 0x07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}}
+ gPerfPchPreMemGuid = {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, 0x52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}}
+ gPerfCpuPreMemGuid = {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3, 0xCA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}}
+ gPerfMePreMemGuid = {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF, 0xAB, 0x86, 0x7A, 0x38, 0xCC, 0xF3}}
+ gPerfAmtPreMemGuid = {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1, 0xDD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}}
+ gPerfSaPreMemGuid = {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94, 0x0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}}
+ gPerfEvlGuid = {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, 0x00, 0x47, 0x0A, 0x50, 0x69, 0x40}}
+ gPerfMemGuid = {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, 0x6B, 0x5D, 0x23, 0xC3, 0xAA, 0x3E}}
+ gPlatformGpioConfigGuid = {0xd66acbe3, 0x3293, 0x4ba1, {0xb0, 0x0b, 0xb3, 0x8f, 0x64, 0x8d, 0x8d, 0x5e}}
+
+[Protocols]
+ gEfiSpiProtocolGuid = { 0xf8b84ae6, 0x8465, 0x4f95, { 0x9f, 0xb, 0xea, 0xaa, 0x37, 0xc6, 0x15, 0x5a } }
+ gEfiActiveBiosProtocolGuid = { 0xebbe2d1b, 0x1647, 0x4bda, { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a }}
+ gEfiSerialGpioProtocolGuid = { 0xf52c3858, 0x5ef8, 0x4d41, { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }}
+ gWdtProtocolGuid = { 0xB42B8D12, 0x2ACB, 0x499a, { 0xA9, 0x20, 0xDD, 0x5B, 0xE6, 0xCF, 0x09, 0xB1 }}
+ gPchPlatformPolicyProtocolGuid = { 0x782ee5ae, 0x586b, 0x47c1, { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }}
+ gEfiPchS3SupportProtocolGuid = { 0x2224aee3, 0x8d0b, 0x480a, { 0xb2, 0x72, 0x2a, 0xbe, 0x92, 0xcd, 0x4e, 0x78}}
+ gEfiPchInfoProtocolGuid = { 0x984eb4e9, 0x5a95, 0x41de, {0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0}}
+ gEfiSmmSmbusProtocolGuid = { 0x72e40094, 0x2ee1, 0x497a, { 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc }}
+ gEfiSmmSpiProtocolGuid = {0xbd75fe35, 0xfdce, 0x49d7, {0xa9, 0xdd, 0xb2, 0x6f, 0x1f, 0xc6, 0xb4, 0x37}}
+ gEfiSmmIchnDispatchExProtocolGuid = { 0x3920405b, 0xc897, 0x44da, { 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 }}
+ gEfiSmmIoTrapDispatchProtocolGuid = {0xdb7f536b, 0xede4, 0x4714, {0xa5, 0xc8, 0xe3, 0x46, 0xeb, 0xaa, 0x20, 0x1d}}
+ gPchResetCallbackProtocolGuid = { 0x3a3300ab, 0xc929, 0x487d, {0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0}}
+ gPchResetProtocolGuid = { 0xdb63592c, 0xb8cc, 0x44c8, { 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a}}
+ gEfiGlobalNvsAreaProtocolGuid = {0x74e1e48, 0x8132, 0x47a1, { 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }}
+ gPchSmmIoTrapControlGuid = {0x514D2AFD, 0x2096, 0x4283, {0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }}
+ gEfiPchSetTmcSrcClkProtocolGuid = {0xfbaa2549, 0x53d, 0x4012, 0x86, 0x6c, 0x7a, 0x86, 0xcc, 0x21, 0xae, 0x21}
+ gPchPlatformPolicyProtocolGuid = { 0x782ee5ae, 0x586b, 0x47c1, { 0xa4, 0x1d, 0xce, 0x7f, 0xa0, 0x9c, 0x25, 0x9a }}
+ gPchInfoProtocolGuid = { 0x984eb4e9, 0x5a95, 0x41de, {0xaa, 0xd0, 0x53, 0x66, 0x8c, 0xa5, 0x13, 0xc0}}
+ gPchNvsAreaProtocolGuid = {0x2E058B2B, 0xEDC1, 0x4431, {0x87, 0xD9, 0xC6, 0xC4, 0xEA, 0x10, 0x2B, 0xE3 }}
+ gPchSerialIoUartDebugInfoProtocolGuid = { 0x2fd2b1bd, 0x0387, 0x4ec6, { 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6 }}
+ gHeciProtocolGuid = { 0xcfb33810, 0x6e87, 0x4284, { 0xb2, 0x3, 0xa6, 0x6a, 0xbe, 0x7, 0xf6, 0xe8 } }
+ gPchSerialGpioProtocolGuid = { 0xf52c3858, 0x5ef8, 0x4d41, { 0x83, 0x4e, 0xc3, 0x9e, 0xef, 0x8a, 0x45, 0xa3 }}
+ gEfiLoadPeImageProtocolGuid = { 0x5CB5C776, 0x60D5, 0x45EE, { 0x88, 0x3C, 0x45, 0x27, 0x08, 0xCD, 0x74, 0x3F }}
+ gEfiSmmVariableProtocolGuid = { 0xed32d533, 0x99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 }}
+ gDxePchPlatformResetPolicyProtocolGuid = {0x45ada968, 0xa8c5, 0x4f30, {0xac, 0xd4, 0xf5, 0x13, 0xbc, 0xe5, 0xb0, 0xb3}}
+ gDxePchPlatformPolicyProtocolGuid = { 0x4b0165a9, 0x61d6, 0x4e23, { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 }}
+ gEfiLegacyInterruptProtocolGuid = { 0x31ce593d, 0x108a, 0x485d, { 0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe }}
+ gEfiSmmIchnDispatchProtocolGuid = { 0xc50b323e, 0x9075, 0x4f2a, { 0xac, 0x8e, 0xd2, 0x59, 0x6a, 0x10, 0x85, 0xcc }}
+ gEfiLegacy8259ProtocolGuid = { 0x38321dba, 0x4fe0, 0x4e17, { 0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1 }}
+ gPlatformEmmcInfoProtocolGuid = { 0xf103dd83, 0x3b17, 0x4e1e, { 0x9b, 0x80, 0x5d, 0xcc, 0x9c, 0x59, 0x0b, 0x2f } }
+ gPchEmmcTuningProtocolGuid = { 0x10fe7e3b, 0xdbe5, 0x4cfa, { 0x90, 0x25, 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89 }}
+ gPchTcoSmiDispatchProtocolGuid = {0x9E71D609, 0x6D24, 0x47FD, {0xB5, 0x72, 0x61, 0x40, 0xF8, 0xD9, 0xC2, 0xA4}}
+ gPchPcieSmiDispatchProtocolGuid = {0x3E7D2B56, 0x3F47, 0x42AA, {0x8F, 0x6B, 0x22, 0xF5, 0x19, 0x81, 0x8D, 0xAB}}
+ gPchAcpiSmiDispatchProtocolGuid = {0xD52BB262, 0xF022, 0x49EC, {0x86, 0xD2, 0x7A, 0x29, 0x3A, 0x7A, 0x05, 0x4B}}
+ gPchGpioUnlockSmiDispatchProtocolGuid = {0x83339EF7, 0x9392, 0x4716, {0x8D, 0x3A, 0xD1, 0xFC, 0x67, 0xCD, 0x55, 0xDB}}
+ gPchSmiDispatchProtocolGuid = {0x4566C59F, 0x650B, 0x4B63, {0xB1, 0xEF, 0x4F, 0x36, 0x66, 0x54, 0x4B, 0xEF}}
+ gEfiSmmIchnDispatch2ProtocolGuid = { 0xe0f0cc19, 0x8912, 0x4077, {0xbf, 0x8a, 0x6a, 0x5c, 0x27, 0xa, 0x3e, 0x65}}
+ gEfiSmmIchnDispatch2ExProtocolGuid = { 0x8497455b, 0xb489, 0x4ac7, {0xbd, 0x51, 0x78, 0xdf, 0x4e, 0x1f, 0x1a, 0xcd}}
+ gPchEspiSmiDispatchProtocolGuid = { 0xca236c1b, 0x625c, 0x4753, { 0xb5, 0x53, 0x19, 0x05, 0xfc, 0xec, 0x2e, 0xa7 }}
+ gPchPcieIoTrapProtocolGuid = { 0xd66a1cf, 0x79ad, 0x494b, { 0x97, 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }}
+ gPchSataEfiLoadProtocolGuid = { 0xaee24780, 0x4511, 0x4f23, { 0xa0, 0x28, 0xeb, 0x82, 0x4, 0xd4, 0x82, 0x9c }}
+ gPchsSataEfiLoadProtocolGuid = { 0x8580afee, 0x40ad, 0x4f63, { 0xa5, 0x48, 0x3d, 0x7f, 0x4a, 0x9, 0x86, 0x7d }}
+ gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
+
+[PPIs]
+ gPchPlatformPolicyPpiGuid = { 0xdfe2b897, 0xe8e, 0x4926, { 0xbc, 0x69, 0xe5, 0xed, 0xd3, 0xf9, 0x38, 0xe1 }}
+ gPchInitPreMemDonePpiGuid = { 0xb795d447, 0x7524, 0x4819, { 0xa6, 0x2c, 0xff, 0x6f, 0x46, 0x71, 0xf2, 0xff }}
+ gPeiUsbControllerPpiGuid = { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }}
+ gPchUsbPolicyPpiGuid = { 0xc02b0573, 0x2b4e, 0x4a31, { 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c }}
+ gPchInitPpiGuid = { 0x908c7f8b, 0x5c48, 0x47fb,{ 0x83, 0x57, 0xf5, 0xfd, 0x4e, 0x23, 0x52, 0x76}}
+ gWdtPpiGuid = { 0xF38D1338, 0xAF7A, 0x4FB6, { 0x91, 0xDB, 0x1A, 0x9C, 0x21, 0x83, 0x57, 0x0D }}
+ gPeiSpiPpiGuid = { 0xfbf26154, 0x4e55, 0x4bdc, { 0xaf, 0x7b, 0xd9, 0x18, 0xac, 0x44, 0x3f, 0x61 } }
+ gPchDmiTcVcMapPpiGuid = { 0xed097352, 0x9041, 0x445a, { 0x80, 0xb6, 0xb2, 0x9d, 0x50, 0x9e, 0x88, 0x45 }}
+ gPeiSmbusPolicyPpiGuid = { 0x63b6e435, 0x32bc, 0x49c6, { 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c }}
+ gPchResetCallbackPpiGuid = { 0x17865dc0, 0xb8b, 0x4da8, { 0x8b, 0x42, 0x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d }}
+ gPchPeiInitDonePpiGuid = { 0x1edcbdf9, 0xffc6, 0x4bd4, { 0x94, 0xf6, 0x19, 0x5d, 0x1d, 0xe1, 0x70, 0x56 }}
+ gPchResetPpiGuid = { 0x433e0f9f, 0x5ae, 0x410a, { 0xa0, 0xc3, 0xbf, 0x29, 0x8e, 0xcb, 0x25, 0xac }}
+ gPchHdaVerbTablePpiGuid = { 0x220307a4, 0x3670, 0x42a5, { 0xaa, 0x1, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }}
+ gPchPcieDeviceTablePpiGuid = { 0xaf4a1998, 0x4949, 0x4545, { 0x9c, 0x4c, 0xc1, 0xe7, 0xc0, 0x42, 0xe0, 0x56 }}
+ gPchSmmIoTrapControlGuid = {0x514D2AFD, 0x2096, 0x4283, {0x9D, 0xA6, 0x70, 0x0C, 0xD2, 0x7D, 0xC7, 0xA5 }}
+ gSaPlatformPolicyPpiGuid = { 0x573eaf99, 0xf445, 0x46b5, { 0xa5, 0xd5, 0xbc, 0x4a, 0x93, 0x35, 0x98, 0xf3 } }
+ gPeiSmmControlPpiGuid = { 0x61c68702, 0x4d7e, 0x4f43, { 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }}
+ #SERVER_BIOS gSiPolicyPpiGuid = { 0xaebffa01, 0x7edc, 0x49ff, { 0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70 }}
+ gPchHsioPtssTablePpiGuid = { 0x220307a4, 0x3671, 0x42b5, { 0xaa, 0x02, 0x32, 0x9d, 0xcd, 0x3e, 0x91, 0x6b }}
+ gDirtyWarmResetSignalGuid = { 0x24b9a592, 0x4cfc, 0x4c8f, { 0x86, 0xf4, 0x87, 0x28, 0x2d, 0x7f, 0x9e, 0x9c }}
+ gDirtyWarmResetGuid = { 0xe60fe263, 0xac2b, 0x43d6, { 0xb3, 0xc7, 0x0d, 0x9d, 0xdc, 0x5a, 0x99, 0x1c }}
+
+[PcdsFixedAtBuild]
+ gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress|0x500|UINT16|0x30000003
+ gEfiPchTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x30000005
+ gEfiPchTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x30000001
+ gEfiPchTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x30000002
+ gEfiCommonPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001033
+
+ ## From MdeModulePkg.dec
+ ## Progress Code for S3 Suspend end.
+ # PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+ gEfiPchTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001033
+
+ ## TraceHub Configuration
+ ## PcdTraceHubEnMode: 0 for Disabled, 1 for Internal Debugger, 2 for Host Debugger
+
+ ## TraceHub temporary disabled, until TraceHubInitialize is not working correctly. Sighting 4929727.
+ gEfiPchTokenSpaceGuid.PcdTraceHubEnMode|0x00|UINT8|0x30003001
+
+ ## PcdTraceHubEnFWTrace: 0 for Disabled, 1 for Enabled
+ gEfiPchTokenSpaceGuid.PcdTraceHubEnFwTrace|0x01|UINT8|0x30003002
+ ## PcdTraceHubDest: 0 for Mem, 1 for PTI, 2 for USB3, 3 for BSSB
+ gEfiPchTokenSpaceGuid.PcdTraceHubDest|0x02|UINT8|0x30003003
+ ## PcdTraceHubTempCsrMtbBar: Temporary CSR MTB BAR
+ gEfiPchTokenSpaceGuid.PcdTraceHubTempCsrMtbBar|0xFE100000|UINT32|0x30003004
+
+ gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001
+ gEfiPchTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002
+
+ ##
+ ## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
+ ## value of the struct
+ ## 0x00 EfiGcdAllocateAnySearchBottomUp
+ ## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp
+ ## 0x03 EfiGcdAllocateAnySearchTopDown
+ ## 0x04 EfiGcdAllocateMaxAddressSearchTopDown
+ ##
+ ## below value should not using in this situation
+ ## 0x05 EfiGcdMaxAllocateType : design for max value of struct
+ ## 0x02 EfiGcdAllocateAddress : design for speccification address allocate
+ ##
+ gEfiPchTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
+
+ [PcdsFixedAtBuild,PcdsPatchableInModule]
+ ## From MdeModulePkg.dec
+ ## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to follow ACPI specification.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034
+ ## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x30001035
+ ## Default OEM Revision for ACPI table creation.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001036
+ ## Default Creator ID for ACPI table creation.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037
+ ## Default Creator Revision for ACPI table creation.
+ gEfiPchTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038
+ gEfiPchTokenSpaceGuid.PcdSmbusBaseAddress|0x0780|UINT16|0x00010031
+ gEfiPchTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+ gEfiPchTokenSpaceGuid.PcdWakeOnRTCS5|FALSE|BOOLEAN|0x30000018
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeHour|0|UINT8|0x30000019
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeMinute|0|UINT8|0x30000020
+ gEfiPchTokenSpaceGuid.PcdRtcWakeupTimeSecond|0|UINT8|0x30000021
+ gEfiPchTokenSpaceGuid.PcdPchSataInitReg78Data|0x88880000|UINT32|0x30000007
+ gEfiPchTokenSpaceGuid.PcdPchSataInitReg88Data|0x88338822|UINT32|0x30000009
+
+ ##
+ ## SerialIo Uart Configuration
+ ##
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartDebugEnable|FALSE|BOOLEAN|0x00100001
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartNumber|2|UINT8|0x00100002
+
+ #
+ # PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,
+ # values 0-0x7F will be treated as disable FVI reporting.
+ # FVI structure uses it as SMBIOS OEM type to provide version information.
+ #
+ gEfiPchTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037
|